Trimming Method

Abstract

To shorten a current path to cut a fuse resistor and shorten a current rise time.SOLUTION: In a trimming method that adjusts the electrical characteristics of a circuit to be adjusted provided on a semiconductor substrate by cutting a fuse resistor provided on the semiconductor substrate, when a cutting current is passed through the fuse resistor to cut the fuse resistor, at least one of switching elements provided on the semiconductor substrate is made conductive such that the cutting current is passed through the switching element.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a trimming method.

[0002] A trimming circuit is used to correct the variation in circuit characteristics due to manufacturing variations in semiconductor devices. A trimming circuit having a fuse resistor formed of a polysilicon layer is known (for example, Patent Document 1). In a trimming circuit having a fuse resistor and a read transistor connected in series with each other, and a fusing transistor section provided in parallel with the fuse resistor and the read transistor, a trimming method is known in which a pad is provided at the connection point of the fuse resistor and the read transistor, and a current is passed between the pad and the source of the fusing transistor section to fusing the fuse resistor (for example, Patent Document 2). [Prior art document] [Patent documents] [Patent Document 1] JP 2018-22848 A [Patent Document 2] JP 2007-200387 A Summary of the Invention [Problem to be solved by the invention]

[0003] In the trimming method, it is desirable to reduce the leakage current by completely cutting the fuse resistor. In order to completely cut the fuse resistor, it is desirable to shorten the path of the cutting current that flows to cut the fuse resistor and to shorten the rise time of the cutting current. [Means for solving the problem]

[0004] One aspect of the present invention provides a trimming method. In the trimming method, an electrical characteristic of an adjusted circuit provided on a semiconductor substrate may be adjusted by cutting a fuse resistor provided on the semiconductor substrate. In the trimming method, when a cutting current is applied to the fuse resistor to cut the fuse resistor, at least one of switching elements provided on the semiconductor substrate may be rendered conductive to allow the cutting current to flow through the switching element.

[0005] The fuse resistor may be disposed on one surface of the semiconductor substrate via an insulating film.

[0006] The switching element may be a part of a vertical device. The vertical device may control whether or not a current flows between a first main electrode provided on one surface of a semiconductor substrate and a second main electrode provided on the other surface of the semiconductor substrate. When a blow current is to be passed, the blow current that has flowed into the semiconductor substrate via a fuse resistor may be passed to the first main electrode.

[0007] A control element for controlling the vertical device may be provided on the semiconductor substrate, and the control element may be brought into a non-conducting state when a disconnection current is applied.

[0008] The conductivity type of the semiconductor substrate may be n-type, and the switching element may include a p-type base region formed on one surface side of the semiconductor substrate, an n-type region formed within the base region, a conductive portion formed on the base region between the semiconductor substrate and the n-type region via an insulating film, and a first main electrode in contact with the n-type region, and may include a p-type region formed on the one surface side of the semiconductor substrate away from the p-type base region and electrically connected to a fuse resistor.

[0009] The above summary of the invention does not list all of the necessary features of the present invention. Also, subcombinations of these features may also be inventions. [Brief description of the drawings]

[0010] [Figure 1]1 is a diagram showing a schematic configuration of a trimming circuit 100 to which a trimming method according to an embodiment of the present invention is applied. [Diagram 2] 1 is an example of a circuit diagram to which a trimming method according to an embodiment of the present invention is applied; [Diagram 3] 1 is an example of a circuit diagram to which a trimming method of a comparative example is applied. [Figure 4A] 3 is a cross-sectional view showing an example of a semiconductor device to which the trimming method in FIG. 2 is applied. [Figure 4B] FIG. 4B is an enlarged cross-sectional view of part A in FIG. 4A. [Diagram 5] 4 is a cross-sectional view showing an example of a semiconductor device to which the trimming method of the comparative example in FIG. 3 is applied. [Figure 6] 1 is an example of a flowchart of a trimming method according to an embodiment of the present invention. [Figure 7] FIG. 11 is another circuit diagram to which the trimming method is applied. [Figure 8] FIG. 11 is another circuit diagram to which the trimming method is applied. [Figure 9] 9 is an example of a semiconductor device to which the trimming method in FIG. 8 is applied. [Figure 10] FIG. 11 is a circuit diagram showing another application example of the trimming method. [Figure 11] FIG. 11 is a circuit diagram showing another application example of the trimming method. [Figure 12] FIG. 11 is another circuit diagram to which the trimming method is applied. [Figure 13] FIG. 11 is another circuit diagram to which the trimming method is applied. [Figure 14] FIG. 11 is another circuit diagram to which the trimming method is applied. [Figure 15] FIG. 11 is another circuit diagram to which the trimming method is applied. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0012] 1 is a diagram showing a schematic configuration of a trimming circuit 100 to which a trimming method according to one embodiment of the present invention is applied. The trimming circuit 100 adjusts the electrical characteristics of an adjusted circuit 1. For example, the adjusted circuit 1 includes at least one adjusted element 2 and at least one switching element 3. The adjusted circuit 1 and the adjusted element 2 are provided on the same semiconductor substrate as the trimming circuit 100. The switching element 3 will be described later.

[0013] In one example, the trimming circuit 100 adjusts the resistance value between the internal terminals T1 and T2. A resistor is connected between the internal terminals T1 and T2 as the adjusted element 2. In one example, a plurality of adjusted elements 2 may be connected in series between the internal terminals T1 and T2. The trimming circuit 100 may adjust the resistance value between the internal terminals T1 and T2 by switching between short-circuiting and non-short-circuiting both ends of each adjusted element 2. The number and resistance value of the adjusted elements 2 may be changed as appropriate. However, the adjusted element 2 is not limited to a resistor and may be another passive element or another active element.

[0014] The one or more adjustable elements 2 connected between the internal terminals T1 and T2 may be gate resistors connected to the gate of the switching element 3. The trimming circuit 100 may adjust the value of the gate resistance of the switching element 3 by adjusting the resistance value between the internal terminals T1 and T2. The switching element 3 may be a MOS (Metal-Oxide-Semiconductor type) device such as a vertical MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor). The switching element 3 may be a power semiconductor device. The switching element 3 in this example is a MOSFET. However, the adjustable element 2 and the switching element 3 are not limited to this case. The adjustable element 2 may be an element for adjusting the characteristics of the switching element 3, or an element for adjusting the characteristics of a circuit element different from the switching element 3.

[0015] In this example, the trimming circuit 100 includes a main body section 20 and a transistor section 10. In this example, one main body section 20 and one transistor section 10 form one set. The trimming circuit 100 may include a plurality of sets of main body sections 20 and transistor sections 10. The number of sets of main body sections 20 and transistor sections 10 may be changed as appropriate. As the number of sets of main body sections 20 and transistor sections 10 increases, electrical characteristics such as resistance and current between terminals T1 and T2 can be finely adjusted, and the adjustment accuracy can be improved.

[0016] The transistor section 10 may be a MOS transistor. For example, the transistor section 10 shown in FIG. 1 is an n-channel MOSFET. An adjustable element 2 is provided between a drain 12 and a source 13 of the transistor section 10. That is, the adjustable element 2, whose electrical characteristics such as current are to be adjusted, and the transistor section 10 are connected in parallel. A gate 11 of the transistor section 10 may be electrically connected to an output terminal OUT of the main body section 20. The transistor section 10 is formed on a semiconductor substrate, and a control terminal is connected to the output terminal OUT of the main body section 20. The control terminal may be a gate terminal.

[0017] In this example, when the output terminal OUT of the main body 20 becomes Lo level, i.e., low level, the transistor section 10 turns off. As a result, both ends of the corresponding adjusted element 2 are not short-circuited. On the other hand, when the output terminal OUT of the main body 20 becomes Hi level, i.e., high level, the transistor section 10 turns on. When the transistor section 10 turns on, both ends of the corresponding adjusted element 2 are short-circuited. However, this is not limited to the above case, and the transistor section 10 may be configured so that when the output terminal OUT of the main body 20 becomes Lo level, the transistor section 10 turns on, and when the output terminal OUT of the main body 20 becomes Hi level, the transistor section 10 turns off.

[0018] 2 is an example of a circuit diagram to which the trimming method of one embodiment of the present invention is applied. The trimming method adjusts the electrical characteristics of an adjusted circuit 1 provided on a semiconductor substrate by cutting a fuse resistor 22 provided on the semiconductor substrate.

[0019] The trimming circuit 100 includes a fuse resistor 22, a trimming pad 24, a first diode D1, and an output terminal OUT. The trimming circuit 100 may include a first resistor element R1, a second resistor section 29, a third resistor element R3, and a protection diode ZL. The first resistor element R1 is an example of a first resistor section. The second resistor section 29 in this example may include a second resistor element R2 and a resistor element LVND. The resistor element LVND is a high-resistance element using a transistor. In this example, the second resistor element R2 and the resistor element LVND are connected in series. The third resistor element R3 is an example of a third resistor section. However, the first resistor section, the second resistor section, and the third resistor section are not limited to these cases.

[0020] The trimming circuit 100 is a circuit that outputs to the output terminal OUT a voltage So that corresponds to whether or not the fuse resistor 22 has been cut. The trimming circuit 100 changes the voltage So applied to the output terminal OUT in response to the cutting of the fuse resistor 22, and determines the on / off state of the transistor section 10 as described above. The trimming circuit 100 also changes the voltage So when a virtual cut is performed to generate a state in which the fuse resistor 22 is virtually cut.

[0021] One end of the fuse resistor 22 is connected to the pad 24 at a connection point 28. The other end of the fuse resistor 22 is connected to one end of the first diode D1 at a connection point 27. In this example, the other end of the fuse resistor 22 is connected to the anode of the first diode D1. The output terminal OUT is electrically connected to the connection point 28 between the fuse resistor 22 and the pad 24. In this example, the output terminal OUT is electrically connected to the connection point 28 via a third resistive element R3. The output terminal OUT outputs a voltage according to whether the fuse resistor 22 is cut or not.

[0022] One end of the first resistor element R1 is connected to a connection point 27 between the fuse resistor 22 and the anode of the first diode D1. The other end of the first resistor element R1 is connected to VDD, which is the third potential V3. One end of the second resistor section 29 is connected to a connection point 28 between one end of the fuse resistor 22 and the pad 24. The other end of the second resistor section 29 is connected to GND, which is the fourth potential V4. That is, one end of the fuse resistor 22 is connected to the fourth potential V4 via the second resistor section 29. In this example, the second resistor element R2 is connected to the connection point 28, and the resistor element LVND is connected to the fourth potential V4, but conversely, the resistor element LVND may be connected to the connection point 28, and the second resistor element R2 may be connected to the fourth potential V4.

[0023] In this example, the third potential V3 is higher than the fourth potential V4. In this example, the fourth potential V4 corresponds to the potential of the ground wiring GND (ground potential), and the third potential V3 corresponds to the potential of the high potential wiring VDD. That is, the other end of the fuse resistor 22 may be connected to the high potential wiring VDD via the first resistance element R1. The fourth potential V4 may be a Lo level that is approximately equal to the ground potential, and the third potential V3 may be a Hi level that is approximately equal to the potential of the high potential wiring VDD.

[0024] The other end of the second resistance section 29, particularly the gate and drain of the resistance element LVND, may be connected to the ground wiring GND. The connection point 27 in this example is a point closer to the high potential wiring VDD than the connection point 28. The connection point 27 may be disposed between the fuse resistor 22 and the high potential wiring VDD. The connection point 28 may be disposed between the fuse resistor 22 and the ground wiring GND.

[0025] The protection diode ZL is connected between the other end of the second resistor section 29 and the output terminal OUT. In this example, the anode of the protection diode ZL is connected to the ground wiring GND which is at the fourth potential V4, and the cathode of the protection diode ZL is connected to the output terminal OUT.

[0026] The output terminal OUT is connected to the control terminal of the transistor section 10. In this example, the control terminal is the gate terminal of the transistor section. For the sake of simplicity, one transistor section 10 and one adjusted element 2 are shown in FIG. 2, but a set of a plurality of transistor sections 10 and a plurality of adjusted elements 2 may be provided as shown in FIG. 1. The adjusted element 2 is provided between the drain 12 and source 13 of the transistor section 10.

[0027] In this example, one or more adjusted elements 2 are connected to the gate of the switching element 3 and function as a gate resistor. In this example, one or more switching elements 3 are included in the adjusted circuit 1.

[0028] The fuse resistor 22, the trimming pad 24, the first diode D1, the first resistor element R1, the second resistor section 29, the third resistor element R3, the protection diode ZL, the transistor section 10, and the adjusted circuit 1 may be formed on the same semiconductor substrate. The fuse resistor 22 is, for example, a polysilicon fuse formed by a polysilicon layer. The first diode D1 has a semiconductor region of a second conductivity type in a semiconductor substrate of a first conductivity type. In one example, the first conductivity type is n-type, and the second conductivity type is p-type.

[0029] One end of the first diode D1 may be electrically connected to at least one of one or more switching elements 3 on the same semiconductor substrate as the fuse resistor 22. In this example, one end of the first diode D1 is electrically connected to the switching element 3 included in the adjusted circuit 1. The semiconductor substrate is connected to an external device 50 via a wafer chuck unit 5 arranged on the underside and an external cable 6. In one example, the external device 50 is a wafer tester for performing an electrical characteristic test after the completion of the wafer process. The wafer chuck unit 5 may be a stage that fixes the wafer by vacuum suction. At least a part of the wafer chuck unit 5 is electrically connected to the underside of the semiconductor substrate. The wafer chuck unit 5 can be adjusted to an arbitrary voltage by an external device. Alternatively, it can be electrically disconnected from the power supply of the external device. During normal operation of this semiconductor device, the voltage on the underside of the semiconductor substrate is higher than the VDD potential, and the first diode D1 is in a reverse bias state and no current flows. An external pad is connected to the gate of the switching element 3, and an arbitrary voltage Vg can be applied by the wafer tester.

[0030] The first resistor element R1 is a pull-up resistor for pulling up (voltage dividing) the output terminal OUT to the potential of the high potential wiring VDD when the trimming circuit 100 is not performing trimming, and is also a current limiting resistor for limiting the current flowing through the fuse resistor 22. On the other hand, the second resistor section 29 is a pull-down resistor for pulling down (voltage dividing) the output terminal OUT to the ground potential when the fuse resistor 22 is cut. The second resistor section 29 and the third resistor element R3 are also current limiting resistors for limiting the current flowing through the fuse resistor 22. The resistance values ​​of the first resistor element R1, the second resistor section 29, and the third resistor element R3 are determined based on the voltage S applied to the output terminal OUT when trimming is not performed and the fuse resistor 22 is not cut. O may be adjusted to a level at which the transistor portion 10 turns on.

[0031] [Non-cropped] When the trimming circuit 100 is not performing trimming, the output voltage S O is pulled up (voltage divided) by the high potential wiring VDD. In one example, the voltage applied to the high potential wiring VDD is divided by the first resistor element R1 and the second resistor section 29. For example, a Hi level voltage So (a voltage higher than the threshold voltage of the transistor constituting the transistor section 10) is applied to the output terminal OUT. This turns on the transistor section 10, which is a MOSFET for adjusting current, and both ends of the corresponding adjusted element 2 are maintained in a short-circuited state.

[0032] [Virtual disconnection] The trimming circuit 100 can execute virtual disconnection to check the electrical characteristics of the adjusted circuit 1 after disconnecting the fuse resistor 22. The trimming circuit 100 generates a state in which the fuse resistor 22 is virtually disconnected. When the trimming circuit 100 executes virtual disconnection, the voltage Sp applied to the trimming pad 24 may be adjusted.

[0033] [Normal cutting] In the trimming method of this example, at least one of one or more switching elements 3 provided on a semiconductor substrate is rendered conductive when a cutting current is passed through the fuse resistor 22 to cut the fuse resistor 22. The cutting current refers to a current passed through the fuse resistor 22 to cut the fuse resistor 22 by Joule heat.

[0034] In this example, the switching element 3 is rendered conductive by applying a Hi level (high level) gate voltage Vg equal to or higher than the threshold voltage to the gate electrode of the switching element 3. The applied gate voltage Vg is, for example, 5 V. However, the switching element 3 is not limited to this case, and may be configured such that the switching element 3 is rendered conductive by applying a Lo level (low level) gate voltage Vg equal to or lower than the threshold voltage to the gate electrode of the switching element 3.

[0035] In the trimming method of this example, when a cutting current is passed through the fuse resistor 22 to cut the fuse resistor 22, first, the switching element 3 is made conductive. Next, the wafer chuck unit 5 is made floating. Next, the potential applied to the pad 24 and the potential applied to the first main electrode of the switching element 3 are adjusted so that a forward current flows through the first diode D1. In this example, a first potential V1 is applied to the trimming pad 24, and a second potential V2 is applied to the first main electrode of the switching element 3. The first potential V1 and the second potential V2 are different potentials. In this example, the first potential V1 is higher than the second potential V2. In this example, the first main electrode is the source electrode S.

[0036] In this example, a first potential V1 higher than a third potential V3 applied to the high potential wiring VDD may be applied by an external or internal voltage source to the trimming pad 24. Then, the source electrode which is the first main electrode of the switching element 3 is connected to a second potential V2, for example, a ground potential.

[0037] For example, a voltage of 10 V or more and 30 V or less is applied to pad 24 by an external or internal voltage source. This causes a current to flow through fuse resistor 22, which is then cut off by Joule heat. For example, a voltage is applied to pad 24 by an external voltage source of a wafer tester for inspecting semiconductor devices.

[0038] Since the first diode D1 is connected in the forward direction, a blow current, which is a forward current, flows through the fuse resistor 22 and the first diode D1 to the semiconductor substrate. Then, by making at least one of the switching elements 3 provided on the semiconductor substrate conductive, the blow current flows through the switching element 3. According to this example, a current sufficient to blow the fuse resistor 22 can be passed without being affected by the first resistor element R1 and the second resistor section 29.

[0039] In another example, when the fuse resistor 22 is cut off, the fourth potential V4 (ground potential in this example) to which the second resistance section 29 is connected may be adjusted. In one example, when a voltage for cutting off the fuse resistor 22 is applied to the pad 24, the fourth potential V4 may be increased compared to when no voltage is applied to the pad 24. This makes it possible to suppress a current from flowing from the pad 24 to the second resistance section 29. When a voltage for cutting off the fuse resistor 22 is applied to the pad 24, the fourth ground potential V4 may be made higher than the second potential V2. The fourth potential V4 may be set to the same potential as the high potential wiring VDD. This makes it easier to pass a current through the fuse resistor 22, and the fuse resistor 22 can be easily cut off.

[0040] In the trimming method of this example, at the stage of cutting the fuse resistor 22, a cutting current flows in the order of the pad 24, the fuse resistor 22, the first diode D1, and the switching element 3. That is, the cutting current flowing to cut the fuse resistor 22 flows through the switching element 3 by putting the switching element 3 into a conductive state.

[0041] After trimming, the trimming circuit 100 is in a state where the fuse resistor 22 is cut off. In the state where the fuse resistor 22 is cut off, the second resistor section 29 pulls down the output terminal OUT to the ground potential. A voltage So of Lo level is applied to the output terminal OUT. This turns off the transistor section 10, which is a MOSFET for adjusting current, and both ends of the corresponding adjusted element 2 change to a state where they are not short-circuited.

[0042] FIG. 3 is an example of a circuit diagram to which the trimming method of the comparative example is applied. In the trimming method of the comparative example, when a cutting current is applied to the fuse resistor 22 to cut the fuse resistor, the semiconductor substrate is connected to an external device via a wafer chuck unit 5 and an external cable 6 arranged on the lower surface of the semiconductor substrate. In one example, the external device is a wafer tester for performing an electrical characteristic test after the completion of the wafer process. The wafer chuck unit 5 may be a stage for fixing the wafer by vacuum suction. At least a part of the wafer chuck unit 5 is electrically connected to the lower surface of the semiconductor substrate. The external cable 6 connects the lower surface of the semiconductor substrate on which the trimming circuit 100 and the adjusted circuit 1 are provided to the ground electrode of the external device.

[0043] In the trimming method of the comparative example, at the stage of cutting fuse resistor 22, a cutting current flows in the following order: pad 24, fuse resistor 22, first diode D1, the electrode on the underside of the substrate, wafer chuck portion 5, and external cable 6. In other words, the cutting current flowing to cut fuse resistor 22 passes through wafer chuck portion 5 and external cable 6.

[0044] In the comparative example shown in Fig. 3, the cutting current is influenced by the impedance of the wafer chuck unit 5 and the external cable 6, for example, by parasitic capacitance. Specifically, in the trimming method of the comparative example, the rise of the cutting current at the time of cutting is slower than the rise of the cutting current in the trimming method of the present embodiment shown in Fig. 2. If the rise of the cutting current is slow, only a part of the fuse resistor 22 made of polysilicon may heat up, resulting in insufficient cutting and a large leakage current after trimming. In addition, heat may be transferred to the periphery of the fuse resistor 22 made of polysilicon, which may affect the quality of protective films such as interlayer insulating films.

[0045] FIG. 4A is a cross-sectional view showing an example of a semiconductor device 200 to which the trimming method of the embodiment in FIG. 2 is applied. FIG. 4B is an enlarged cross-sectional view of the A portion of FIG. 4A. The trimming method of the embodiment can be applied to various semiconductor devices 200. The semiconductor device 200 includes an adjusted circuit 1 and a trimming circuit 100. The adjusted circuit 1 and the trimming circuit 100 are provided on the same semiconductor substrate 30. In FIG. 4A and FIG. 4B, for ease of explanation, the first resistor element R1, the second resistor section 29, the third resistor element R3, and the protective diode ZL included in the trimming circuit 100 are shown only in electrical connection relationship by circuit symbols. In addition, in FIG. 4A and FIG. 4B, for ease of explanation, the transistor section 10 of the trimming circuit 100 is omitted and only the main body section 20 is shown.

[0046] The adjusted circuit 1 of this example may include an output stage circuit section 210 formed on the upper surface of the same semiconductor substrate 30. The semiconductor device 200 may include a control circuit section 230. The control circuit section 230 may also be included in the adjusted circuit 1.

[0047] The output stage circuit section 210 may include a plurality of switching elements 3 shown in FIG. 1. In other words, the switching elements 3 may be part of an output transistor that outputs a current to the outside of the semiconductor device 200. The switching elements 3 may be provided on one surface side, i.e., the front surface side, of the semiconductor substrate 30. The output stage circuit section 210 may include a trench gate type power semiconductor device. The output stage circuit section 210 may include a vertical device 7 as an output transistor, which has the switching elements 3 as part of its components.

[0048] The vertical device 7 is a device that controls whether or not a current flows between a first main electrode provided on one surface (upper surface in the figure) of the semiconductor substrate 30 and a second main electrode provided on the other surface (lower surface in the figure) of the semiconductor substrate 30. The vertical device 7 may include a vertical MOSFET or an IGBT. In this example, the vertical device 7 is a vertical MOSFET having a trench gate.

[0049] The semiconductor device 200 may be a power integrated circuit in which an output stage circuit section 210 capable of passing a large current and a control circuit section 230 are mounted on one semiconductor chip. If the electrical characteristics of the semiconductor device 200 are out of the target range after the wafer process is completed, the electrical characteristics can be adjusted to the target range by cutting the polysilicon fuse resistor 22 of the trimming circuit 100 using a wafer tester. The fuse resistor 22 used in the trimming circuit can be cut by laser irradiation or by passing a cutting current, but a laser irradiation device is not required if a cutting current is passed as in this example. A wafer tester that performs an electrical characteristic test after the wafer process is completed can also be used as an external device for the trimming process.

[0050] In this example, the conductivity type of the semiconductor substrate 30 is n-type. The semiconductor substrate 30 includes an n-type drift layer 201. An n+ type layer is formed as a contact layer 202 on the lower surface of the semiconductor substrate 30 by impurity diffusion or the like. A second main electrode 203 is formed on the contact layer 202. The second main electrode 203 is made of a conductive material such as a metal. In this example, the second main electrode 203 is a drain electrode. The lower surface of the main surface of the semiconductor substrate 30 on which the second main electrode 203 is formed is also called the back surface, and the upper surface opposite to the lower surface is also called the front surface. The contact layer 202 functions as a drain layer of the vertical device 7. The second main electrode 203 functions as a drain electrode of the vertical device 7.

[0051] A p-type base region 212 is formed on one surface side of the semiconductor substrate 30. A p+ type region 213 and an n+ type region 214 are formed in the p-type base region 212. These regions are formed by impurity diffusion or the like. A trench gate 211 is formed in the semiconductor substrate 30.

[0052] The trench gate 211 is dug from one surface of the semiconductor substrate. The trench gate 211 penetrates the p-type base region 212 and reaches the n-type drift layer 201. The trench gate 211 includes a conductive portion 215 filled in the trench and an insulating film 216 that electrically isolates the conductive portion 215 from the semiconductor substrate 30. The trench contacts the n+ type region 214, the p-type base region 212, and the n-type drift layer 201. The conductive portion 215 is preferably formed at least on the surface of the p-type base region 212 between the n+ type region 214 and the n-type drift layer 201 via the insulating film 216. The first main electrode 220 is formed so as to contact the p+ type region 213 and the n+ type region 214. The first main electrode 220 is formed of a conductive material. In this example, the first main electrode 220 is a source electrode. An insulating film 222 is formed above the trench gate 211. The insulating film 222 insulates the trench gate 211 from the first main electrode 220.

[0053] The switching element 3 may include an n+ type region 214, a p type base region 212, an n- type drift layer 201, a trench gate 211, and a first main electrode 220. The switching element 3 may be a MOS section 217 of the vertical device 7. The n+ type region 214, the p type base region 212, the n- type drift layer 201, the trench gate 211, and the first main electrode 220 function as a source region, a base region, a drift layer, a gate, and a source electrode, respectively, of the vertical device 7. The MOS section 217 may be a portion including a source region, a base region, a drift layer, a gate, and a source electrode of the vertical device 7, and may not include a drain layer and a drain electrode of the vertical device 7.

[0054] The MOS section 217 may include a planar gate instead of a trench gate. The planar gate is formed on one surface of the semiconductor substrate via an insulating film. Specifically, the planar gate is formed on the surface of the p-type base region 212 sandwiched between the n+ type region 214 and the n- type drift layer 201 via an insulating film.

[0055] In the present invention, "n" indicates an element having electrons as the majority carrier, "p" indicates an element having holes as the majority carrier, "+" indicates a relatively high impurity concentration, and "-" indicates a relatively low impurity concentration.

[0056] When a cutting current is passed through the trimming circuit 100, the trimming circuit 100 makes the MOS unit 217, which is the switching element 3, conductive. That is, a voltage is applied to the conductive portion 215 of the trench gate 211 of the MOS unit 217, and a channel is formed in the p-type base region 212 between the n- type drift layer 201 and the n+ type region 214. When the MOS unit 217 is made conductive, the cutting current that has flowed through the fuse resistor 22 into the semiconductor substrate 30 is passed through the MOS unit 217 to the first main electrode 220. In addition, a plurality of switching elements 3 may be provided. When a cutting current is passed through the trimming circuit 100, all the MOS units 217 of the plurality of power semiconductor devices may be made conductive, or the MOS units of some of the power semiconductor devices may be made conductive. When a cutting current is passed through the trimming circuit 100 to cut the fuse resistor 22, the wafer chuck unit 5 may be made floating.

[0057] The control circuit section 230 may include a CMOS circuit section that combines an n-channel MOS transistor 240 and a p-channel MOS transistor 250 on the front surface side of the semiconductor substrate 30. The n-channel MOS transistor 240 has a p-well region 241 formed in the n-type semiconductor substrate 30. An n+ type source region 242 and a drain region 243 are formed inside the p-well region 241.

[0058] A source electrode 246 is connected to the source region 242, and a drain electrode 247 is connected to the drain region 243. The source electrode 246 and the drain electrode 247 are formed of a conductive material such as a metal. A gate electrode 244 is provided on the front surface of the semiconductor substrate 30 via a gate insulating film 245. A source region 242 is provided on one side of the gate electrode 244, and a drain region 243 is provided on the other side of the gate electrode 244.

[0059] A p-channel MOS transistor 250 has a p-well region 251 formed in an n-type semiconductor substrate 30, and an n-well region 252 inside the p-well region 251. A p+ type source region 253 and a drain region 254 are formed inside the n-well region 252. A source electrode 257 is connected to the source region 253, and a drain electrode 258 is connected to the drain region 254. A gate electrode 255 is provided on the front surface of the semiconductor substrate 30 with a gate insulating film 256 interposed therebetween.

[0060] The control circuit section 230 may be a control element for controlling the vertical device 7. When the cutoff current of this embodiment is passed, the control circuit section 230 may be in a non-conductive state. In this case, by turning off the control circuit section 230 that is not a power semiconductor device, it is possible to prevent a current of a predetermined value or more from passing through the control circuit section 230 and prevent the control circuit section 230 from being damaged.

[0061] In the trimming circuit 100, a first diode D1 and a fuse resistor 22 are formed on a semiconductor substrate 30. The fuse resistor 22 is disposed on the upper surface of the semiconductor substrate 30 via an insulating film 46. The insulating film 46 is partially provided on the semiconductor substrate 30. The insulating film 46 may be a LOCOS oxide film. The fuse resistor 22 is formed of a polysilicon layer 32.

[0062] As shown in FIG. 4B, a first semiconductor region 42 of a second conductivity type is formed on one surface side of the semiconductor substrate 30. In one example, the first semiconductor region 42 is a p-type region formed in the n-type semiconductor substrate 30 by impurity diffusion or the like. The first semiconductor region 42 is formed away from the p-type base region 212. The first semiconductor region 42 is electrically connected to the fuse resistor 22. A PN junction is formed by the first semiconductor region 42 and the semiconductor substrate 30. This PN junction functions as a first diode D1. The first diode D1 may be a vertical diode. In this specification, a vertical diode refers to a diode in which a current flows in the thickness direction of the semiconductor substrate 30. In this example, the anode is disposed on the upper surface side of the semiconductor substrate 30, and the cathode is disposed on the inner side of the semiconductor substrate 30.

[0063] When a cutting current is passed through the fuse resistor 22 to cut the fuse resistor 22, a current flows from the first diode D1, which is a vertical diode, to the switching element 3, which is essentially the MOS portion 217 of a vertical MOSFET. As a result, the p-type region of the first diode D1, the semiconductor substrate 30, and the switching element 3, which is the MOS portion 217 of the vertical device 7, function as a lateral IGBT 218. Specifically, the lateral IGBT 218 includes the first semiconductor region 42 (p-type region), the semiconductor substrate 30 (drift layer 201), the p-type base region 212, and the n+-type region 214 (n-type region) as its components.

[0064] A second semiconductor region 44 of a second conductivity type may be formed by impurity diffusion or the like in a part of the first semiconductor region 42. The second semiconductor region 44 has a higher impurity concentration than the first semiconductor region 42. In one example, the second semiconductor region 44 is a p+ region.

[0065] The contact portion 34 is connected to the second semiconductor region 44 of the second conductivity type. The contact portion 34 may be made of a conductive material. One end of the fuse resistor 22 is connected to a metal wiring 36 via the contact portion 34.

[0066] In a region of the first diode D1 where the second semiconductor region 44 is formed, the insulating film 46 is partially removed, and the second semiconductor region 44 is partially exposed. The second semiconductor region 44 is connected to the metal wiring 36 via the contact portion 34. The metal wiring 36 and the contact portion 34 electrically connect the anode of the first diode D1 (the first semiconductor region 42 and the second semiconductor region 44) and the fuse resistor 22, and function as the connection point 27 shown in FIG. 2. The metal wiring 36 may be connected to the high potential wiring VDD via the first resistor element R1.

[0067] The other end of the fuse resistor 22 is connected to a metal wiring 37 via a contact portion 34. The metal wiring 37 functions as a connection point 28 that connects the fuse resistor 22 to the pad 24 and the second resistance portion 29. The metal wiring 37 may be electrically connected to the output terminal OUT via a third resistance element R3. In addition, the metal wiring 37 may be electrically connected to a ground potential GND via the second resistance portion 29.

[0068] An interlayer insulating film 47 may be formed between the fuse resistor 22, the second semiconductor region 44, and the insulating film 46 and the metal wirings 36, 37. That is, the metal wirings 36 and 37 may be formed on the interlayer insulating film 47. In this case, the contact portion 34 is formed to penetrate an opening in the interlayer insulating film 47.

[0069] In the trimming method of the present embodiment, an external device 50 may be used. The external device 50 applies a gate voltage Vg, a first potential V1, and a second potential V2 to the gate electrode G of the switching element 3 on the semiconductor substrate 30, the pad 24 on the semiconductor substrate 30, and the first main electrode 220 which is the source electrode of the switching element 3, respectively. Specifically, the external device 50 includes a gate voltage application terminal 54, a first potential application terminal 55, and a second potential application terminal 56. The gate voltage application terminal 54 switches whether or not to apply the gate voltage Vg to the gate electrode G of the switching element 3 on the semiconductor substrate 30. The first potential application terminal 55 switches whether or not to apply the first potential V1 to the pad 24 on the semiconductor substrate 30. The second potential application terminal 56 switches whether or not to apply the second potential V2 to the first main electrode 220 which is the source electrode of the switching element 3.

[0070] The external device 50 may be a wafer tester, and in particular may be a tool called a probe card. A probe card is a tool used for electrical testing of a semiconductor device 200 formed on a semiconductor substrate. The probe card functions as a connector that connects electrodes on the semiconductor substrate 30 to a wafer tester, which is a measuring device. A needle of the probe card is brought into contact with each electrode on the semiconductor substrate 30, and a corresponding potential is applied. When a wafer tester is used as the external device 50, a trimming process can be performed according to the result of the wafer test without reconnecting to another external device.

[0071] Fig. 5 is a cross-sectional view showing an example of a semiconductor device 200 to which the trimming method of the comparative example in Fig. 3 is applied. The comparative example shown in Fig. 5 has a different path of a cutting current compared to the embodiment of the present invention shown in Fig. 4A and Fig. 4B. The structure of the semiconductor device 200 itself is similar to the structure shown in Fig. 4A.

[0072] 5, the external device 50 includes a first potential application terminal 55 and a second potential application terminal 56. The first potential application terminal 55 switches whether or not to apply a first potential V1 to the pad 24 on the semiconductor substrate 30. The second potential application terminal 56 switches whether or not to apply a second potential V2 to the wafer chuck unit 5 arranged on the back surface of the semiconductor substrate 30. When a blowing current is passed through the fuse resistor 22 (polysilicon layer 32) to blow the fuse resistor 22, the first potential application terminal 55 applies the first potential V1 to the pad 24 on the semiconductor substrate 30, and the second potential application terminal 56 applies the second potential V2 (ground potential in this comparative example) to the wafer chuck unit 5.

[0073] In the comparative example, the cutting current flows in the order of first potential application terminal 55 of external device 50, pad 24, fuse resistor 22 (polysilicon layer 32), first diode D1, contact layer 202, second main electrode 203, wafer chuck unit 5, external cable 6, and second potential application terminal 56 of external device 50. Therefore, the rise of the cutting current is delayed due to the influence of the impedance of wafer chuck unit 5 and external cable 6, for example, the influence of parasitic capacitance.

[0074] 4A and 4B, when a cutting current is applied to the fuse resistor 22 (polysilicon layer 32) to cut the fuse resistor 22, at least one of the switching elements 3, which are the MOS sections 217 of the vertical device 7 provided on the semiconductor substrate 30, is rendered conductive to allow the cutting current to flow. Thus, the cutting current flows in the order of the first potential application terminal 55 of the external device 50, the pad 24, the fuse resistor (polysilicon layer 32), the first diode D1, the channel of the switching element 3, the first main electrode 220, and the second potential application terminal 56 of the external device 50. Thus, there is no influence of the impedance of the wafer chuck section 5 and the external cable 6, for example, the influence of parasitic capacitance.

[0075] 6 is an example of a flowchart of a trimming method according to an embodiment of the present invention. It is determined whether or not to perform trimming (step S101). Whether or not to perform trimming may be determined based on the result obtained by virtual disconnection. For example, a fuse resistor 22 to be selectively disconnected from among the multiple fuse resistors 22 is determined so that the resistance value or current value between terminals T1 and T2 falls within a target range.

[0076] When trimming is performed (step S101: YES), that is, when a cutting current is passed through the fuse resistor 22 to cut the fuse resistor 22 (step S101: YES), at least one switching element 3 in the output stage circuit section 210 is made conductive (step S102). Specifically, the gate voltage application terminal 54 of the external device 50 applies a gate voltage Vg to the gate electrode G of the switching element 3, thereby making the switching element 3, which is the MOS section 217 of the vertical device 7, conductive. The wafer chuck section 5 is made floating. Depending on the arrangement position of the fuse resistor 22 to be trimmed, one or more switching elements 3 within a predetermined distance from the fuse resistor 22 may be selected from the multiple switching elements 3 and made conductive.

[0077] Then, the voltage between the pad 24 connected to one end of the fuse resistor 22 and the first main electrode 220 of the switching element 3 is adjusted so that a forward current flows through the first diode D1. In this example, a first potential V1 higher than the third potential V3 of the high potential wiring VDD is applied to the pad 24 connected to one end of the fuse resistor 22 (step S103). Meanwhile, a second potential V2 is applied to the first main electrode 220 of the switching element 3 (step S102). As a result, the break current that has flowed from the fuse resistor 22 into the semiconductor substrate 30 is caused to flow to the first main electrode.

[0078] In one example, the first potential application terminal 55 of the external device 50 is switched to a state in which the first potential V1 is applied to the pad 24 on the semiconductor substrate 30. The second potential application terminal 56 of the external device 50 is switched to a state in which the second potential V2 is applied to the first main electrode 220, which is the source electrode of the switching element 3. Note that steps S102, S103, and S104 may be performed simultaneously.

[0079] In this embodiment, the cutting current does not pass through the wafer chuck unit 5 and the external cable 6. Therefore, according to the trimming method of this embodiment, it is possible to suppress a slow rise in the cutting current due to the influence of the impedance of the wafer chuck unit 5 and the external cable 6, for example, the influence of parasitic capacitance. In addition, it is possible to speed up the rise in current when the fuse resistor 22 is cut, without being influenced by the specifications of the wafer chuck unit 5 and the external cable 6. Therefore, the fuse resistor 22 can be cut stably. A wafer tester or the like can also be used as the external device 50, so there is no need to modify the external device 50.

[0080] According to this embodiment, the fuse resistor 22 (polysilicon layer 32) is provided on the upper surface of the semiconductor substrate 30 via an insulating film 46. When a blow current is caused to flow, the switching element 3 provided on the upper surface side of the semiconductor substrate 30 is rendered conductive. Therefore, since the blow current flows between the portions provided on the upper surface of the semiconductor substrate 30, the path through which the blow current flows can be shortened.

[0081] Furthermore, according to this embodiment, a blow current is passed through the switching element 3, which is the MOS section 217 of the vertical device 7, in a conductive state, so that a current large enough to blow the fuse resistor 22 can be passed. When passing a blow current, the MOS sections 217 of a plurality of power semiconductor devices arranged around the fuse resistor to be trimmed may be placed in a conductive state. This allows a larger blow current to be passed compared to passing the blow current through one switching element 3.

[0082] In particular, since the switching element 3 which functions as the MOS portion 217 of the vertical device 7 during operation is diverted to a lateral IGBT or the like during trimming, the operating resistance during trimming can be reduced.

[0083] According to this embodiment, when a cutting current is applied, an existing switching element 3 can be used, and there is no need to provide a separate switching element 3, so that the trimming circuit can be made smaller. In particular, the switching element 3 included in the adjusted circuit 1 can be utilized.

[0084] As in the comparative example, the trimming circuit 100 of this embodiment can realize virtual disconnection for checking the electrical characteristics of the adjusted element after the fuse resistor 22 is disconnected before disconnecting the fuse resistor 22.

[0085] In this example, the trimming pad 24 connected to one end of the fuse resistor 22 is still necessary, but the first main electrode 220 of the switching element 3 can be used as the terminal on the other end side of the fuse resistor 22, and there is no need to provide an external terminal dedicated to trimming. In addition, there is no need to provide a resistance bypass circuit capable of withstanding the large current that melts the fuse resistor 22. Therefore, it is possible to realize a trimming circuit 100 that is both compact and has a virtual blowing function compared to the conventional trimming circuit.

[0086] According to the trimming circuit 100 of this example, even if the fuse resistor 22 is cut off, the pad 24 and the output terminal OUT are electrically connected via the metal wiring 37 and the third resistive element R3. Therefore, the trimming pad 24 can be reused to monitor the voltage at the output terminal OUT. Specifically, even after trimming, the voltage So at the output terminal OUT can be measured. In addition, it is possible to check whether the trimming has caused deterioration (leakage) in the elements, ensuring high reliability in the circuit.

[0087] Fig. 7 is another circuit diagram to which the trimming method is applied. In the trimming circuit 100 shown in Fig. 7, the protection diode ZL is omitted. Also, the second resistance section 29 in Fig. 7 is composed of the second resistance element R2, and the resistance element LVND is omitted. The trimming method of the present invention can be executed in the example shown in Fig. 7 as well.

[0088] Fig. 8 is another circuit diagram to which the trimming method is applied. In the trimming circuit shown in Fig. 8, a trimming pad 24 is connected to a connection point 27 between the fuse resistor 22 and a first resistor element R1, and a first diode D1 is connected to a connection point 28 between the fuse resistor 22 and a second resistor section 29. An output terminal OUT is connected to the connection point 28 between the first diode D1 and the fuse resistor 22 via a third resistor element R3.

[0089] 8, the trimming pads 24 are not provided on either end of the fuse resistor 22, so that an increase in the circuit area can be prevented. However, in the trimming circuit shown in Fig. 8, when the fuse resistor 22 is blown, the pad 24 and the output terminal OUT are electrically separated. Therefore, the trimming pad 24 cannot be reused for monitoring the voltage at the output terminal OUT.

[0090] 8, when a cutting current is passed through the fuse resistor 22 to cut the fuse resistor 22, at least one of the switching elements 3 provided on the semiconductor substrate 30 is rendered conductive so that the cutting current can be passed through the switching element 3. This makes it possible to prevent a delay in the rise of the cutting current when the fuse resistor 22 is cut from being caused by the influence of the impedance of the wafer chuck portion 5 and the external cable 6, for example, the influence of parasitic capacitance.

[0091] 9 is a cross-sectional view showing an example of a semiconductor device to which the trimming method in FIG. 8 is applied. The metal wiring 36 and the contact portion 34 electrically connect the anode of the first diode D1 and the fuse resistor 22, and function as the connection point 28 shown in FIG. 8. The metal wiring 36 also connects the fuse resistor 22 to the second resistor portion 29. The metal wiring 36 may also be electrically connected to the output terminal OUT via the third resistor element R3. The metal wiring 36 may also be electrically connected to the ground potential GND via the second resistor portion 29. Meanwhile, the metal wiring 37 connects the fuse resistor 22 to the first resistor element R1. The metal wiring 37 may also be connected to the high potential wiring VDD via the first resistor element R1.

[0092] Except for the above points, the configuration of the semiconductor device 200 shown in Fig. 9 is the same as that of the semiconductor device shown in Fig. 4A and Fig. 4B. Therefore, repeated explanation will be omitted. An external device 50 may also be used in the semiconductor device 200 shown in Fig. 9. The external device 50 applies a gate voltage, a first potential, and a second potential to the gate electrode G of the switching element 3 on the semiconductor substrate 30, the pad 24 on the semiconductor substrate 30, and the first main electrode 220 which is the source electrode of the switching element 3, respectively.

[0093] 4A and 4B can be applied to the embodiment shown in Fig. 9. Since the cutting current does not pass through the wafer chuck unit 5 and the external cable 6, it is possible to suppress the slow rise of the cutting current caused by the influence of the impedance of the wafer chuck unit 5 and the external cable 6, for example, the influence of parasitic capacitance. In addition, the path through which the cutting current flows can be shortened.

[0094] Fig. 10 is a circuit diagram showing another application example of the trimming method. In the trimming circuit 100 shown in Fig. 10, the third resistor element R3 in the trimming circuit 100 shown in Fig. 8 is omitted. Furthermore, the second resistor section 29 in Fig. 10 is composed of the second resistor element R2, and the resistor element LVND is omitted. The trimming method of the present invention can also be implemented in the example shown in Fig. 10.

[0095] 2, 7, 8, and 10, when a cutting current is passed through the fuse resistor 22 to cut the fuse resistor 22, the switching element 3 included in the adjusted circuit 1 is made conductive to pass the cutting current through the switching element 3. By utilizing the switching element 3 included in the adjusted circuit 1 when passing a cutting current, it is not necessary to provide a separate switching element other than the adjusted circuit 1, and the trimming circuit can be made smaller. However, the present invention is not limited to this case.

[0096] Fig. 11 is a circuit diagram showing another application example of the trimming method. In this example, the switching element 3 is provided as an element separate from the elements included in the adjusted circuit 1. The switching element 3 may be provided on the semiconductor substrate 30 shown in Fig. 4A or Fig. 9. There may be one switching element 3 or multiple switching elements 3. When a blowing current is passed through the fuse resistor 22 to blow the fuse resistor 22, the switching element 3 is set in a conductive state and a blowing current is passed through the switching element 3.

[0097] Specifically, when a cutting current is passed through the fuse resistor 22 to cut the fuse resistor 22, a gate voltage Vg is applied to the gate electrode G of the switching element 3. This puts the switching element 3 into a conductive state. The switching element 3 shown in Fig. 11 may be an element separate from the adjusted circuit 1, and a switching element provided for another purpose may also be used as the switching element 3.

[0098] 11, the cutting current does not pass through the wafer chuck unit 5 and the external cable 6. Therefore, the trimming method of this embodiment can also suppress a slow rise in the cutting current caused by the influence of the impedance of the wafer chuck unit 5 and the external cable 6, for example, the influence of parasitic capacitance. In addition, the path through which the cutting current flows can be shortened.

[0099] FIG. 12 is another circuit diagram to which the trimming method is applied. The trimming circuit 100 of this example includes a plurality of body parts 20. The trimming circuit 100 of this example includes body parts 20-1, 20-2, 20-3, .... In this specification, the kth body part 20 may be referred to as body part 20-k. In addition, in each figure, the reference numerals of each component in the body part 20-k are given the sub-number k. Each body part 20 is provided corresponding to the adjusted element 2. Each body part 20 may be connected to the gate of the transistor part 10 shown in FIG. 1.

[0100] Each of the main body portions 20 has a structure similar to that of any of the main body portions 20 described in Figures 1 to 11. In Figure 12, each of the main body portions 20 has a structure similar to that of the main body portion 20 shown in Figure 2. However, in Figure 12, the third resistor element R3 is omitted.

[0101] The main body 20 in each embodiment may or may not have the third resistor element R3. Also, in Fig. 12, the second resistor element R2 is disposed between the pad 24 and the output terminal OUT. In the main body 20 in each embodiment, the second resistor element R2 may be disposed between the pad 24 and the output terminal OUT as in Fig. 12, or may be disposed between the pad 24 and the resistor element LVND as in Fig. 2.

[0102] In the trimming circuit 100 of this example, the first diode D1 and the switching element 3 are provided in common to the multiple main body parts 20. In other words, each main body part 20 is not provided with an individual first diode D1 and an individual switching element 3. The common first diode D1 is connected to the fuse resistor 22 of each main body part 20. The anode of the first diode D1 of this example is connected to the multiple fuse resistors 22. The cathode side of the first diode D1 is connected to the drain side of the switching element 3.

[0103] 4A or 9, each fuse resistor 22-k may be disposed on the upper surface of the semiconductor substrate 30 via an insulating film 46, and the switching element 3 may be provided on the upper surface of the semiconductor substrate 30. The switching element 3 may be a vertical device that controls whether or not a current flows between a first main electrode 220 provided on the upper surface of the semiconductor substrate 30 and a second main electrode 203 provided on the lower surface of the semiconductor substrate 30.

[0104] When a blow current is to be passed, the switching element 3 may be set in a conductive state, and the blow current that has flowed from the fuse resistor 22-k into the semiconductor substrate 30 may be passed to the first main electrode 220. The switching element 3 may be a switching element 3 included in any of the adjusted circuits 1-k that are adjusted by any of the multiple main body portions 20-k.

[0105] In this example, the fuse resistor 22-k has one end connected to the pad 24-k and the other end connected to the first diode D1. In this example, the one end of the fuse resistor 22-k is connected to the output terminal OUTk and the resistor element LVNDk via the second resistor element R2-1.

[0106] The other end of the fuse resistor 22-k is connected to a first resistor element R1. In this example, the first resistor element R1 is also provided in common to the multiple main bodies 20. One end of the first resistor element R1 is connected to the first diode D1, and the other end is connected to the high potential wiring VDD. In this example, a connection point 27-k is provided for each main body 20-k. The anode of the first diode D1, one end of the first resistor element R1, and the other end of the fuse resistor 22-k are connected to the connection point 27-k.

[0107] The device scale can be reduced by providing the first diode D1 and the switching element 3 in common to the multiple main bodies 20. Also, the device scale can be reduced by providing the first resistor element R1 in common to the multiple main bodies 20.

[0108] In this example, when a cutting current is passed through fuse resistor 22-k to cut fuse resistor 22-k, at least one of one or more switching elements 3 provided in common to multiple main body portions 20 is made conductive, and the cutting current is passed through the switching element 3.

[0109] The fuse resistors 22 to be cut are selected one by one, and a predetermined high potential is applied in sequence to the pads 24-k corresponding to the fuse resistors 22-k to be cut. In each main body 20, the operation of cutting the fuse resistors 22 is the same as the example of FIG. 6. As described above, the high potential is a first potential higher than the voltage applied to the high potential wiring VDD. The pads 24 that are not selected are made floating.

[0110] Also, the ground potential applied to the body portion 20 selected to cut off the fuse resistor 22 may be changed. For example, when cutting off the fuse resistor 22-k, the ground potential applied to the body portion 20-k is increased. The ground potential of the body portion 20-k may be controlled to be the same potential as the potential applied to the pad 24-k. This makes it possible to suppress a current from flowing from the pad 24-k to the second resistor portion 29-k.

[0111] Furthermore, when setting a virtual cut, a voltage for virtual cut may be applied in parallel to each pad 24. That is, each main body portion 20 can be set in a virtual cut state in parallel. Also, some of the main body portions 20 may be selectively set in the virtual cut state.

[0112] Moreover, the resistance values ​​of the first resistor R1 and the second resistor R2 may be sufficiently smaller than the resistance value of the resistor LVND. By increasing the resistance value of the resistor LVND, the current flowing through the main body 20 can be reduced.

[0113] In this example as well, the cutting current does not pass through the wafer chuck unit 5 and the external cable 6. Therefore, the trimming method of this embodiment can also suppress a slow rise in the cutting current caused by the influence of the impedance of the wafer chuck unit 5 and the external cable 6, for example, the influence of parasitic capacitance. In addition, the path through which the cutting current flows can be shortened.

[0114] Fig. 13 is another circuit diagram to which the trimming method is applied. The trimming circuit 100 of this example includes a plurality of main body parts 20. In this example, as in the example of Fig. 12, a first diode D1 and a first resistance element R1 are provided in common to the plurality of main body parts 20. However, in this example, the first diode D1 is connected to a connection point 27-k between each fuse resistor 22-k and the ground potential. Also, the first resistance element R1 is connected between each connection point 27 and the ground potential.

[0115] In this embodiment, the main body 20 outputs a voltage corresponding to the high potential VDD from the output terminal OUT when the fuse resistor 22 is cut off, and outputs a voltage corresponding to the ground potential from the output terminal OUT when the fuse resistor 22 is not cut off.

[0116] In each main body 20, the fuse resistor 22, the first diode D1, and the first resistor element R1 are connected. One end of each fuse resistor 22-k is connected to the pad 24-k, and the other end is connected to the first diode D1 and the first resistor element R1. A second resistor element R2-k is connected to a connection point 28-k between the pad 24-k and the fuse resistor 22-k. One end of the second resistor element R2-k is connected to the connection point 28-k, and the other end is connected to a resistor element LVNDk.

[0117] The resistor element LVNDk has one end connected to the second resistor element R2-k and the other end connected to the high potential wiring VDD. In this example, the connection point between the resistor element LVNDk and the second resistor element R2-k is connected to the output terminal OUTk. A protection diode ZL may be provided between the output terminal OUTk and the ground potential.

[0118] In this example, the device scale can also be reduced by providing the first diode D1 in common to the multiple main bodies 20. Also, the device scale can be reduced by providing the first resistor element R1 in common to the multiple main bodies 20.

[0119] In this example, when a cutting current is passed through fuse resistor 22-k to cut fuse resistor 22-k, at least one of one or more switching elements 3 provided in common to multiple main body portions 20 is made conductive, and the cutting current is passed through the switching element 3.

[0120] In this example, the fuse resistors 22 to be cut are selected one by one, and a predetermined high potential is applied to the pad 24-k corresponding to the fuse resistor 22-k to be cut in order. As described above, the high potential may be a first potential higher than the voltage applied to the high potential wiring VDD. The pads 24 that are not selected are left floating.

[0121] FIG. 14 is another circuit diagram to which the trimming method is applied. In the trimming circuit 100 of this example, the orientation of the anode and cathode of the first diode D1 is different from that of the example of FIG. 12. In addition, in the trimming circuit 100 of this example, the orientation of the drain and source of the switching element 3 is different from that of the example of FIG. 12. In this example, the first potential is applied to the switching element 3 instead of the second potential V2. The second potential V2 is selectively applied to the pad 24-k of the main body 20-k that cuts off the fuse resistor 22-k. Except for these points, the configuration example of FIG. 14 is similar to the configuration shown in FIG. 12. Therefore, detailed explanation will be omitted.

[0122] In the present example, the cathode of the first diode D1 is connected to the fuse resistor 22-k of each of the main bodies 20. One end of each of the fuse resistors 22-k is connected to the pad 24-k, and the other end is connected to the cathode of the first diode D1 via the connection point 27-k.

[0123] In this example, the second potential V2 is selectively applied to the pad 24-k of the main body 20-k that disconnects the fuse resistor 22-k. The second potential V2 is a voltage low enough to allow a forward current to flow from the first diode D1 to the pad 24-k. In other words, the second potential V2 is lower than the first potential V1 applied to the drain electrode of the switching element 3 by more than the sum of the voltage drop due to the dynamic resistance of the switching element 3 functioning as a lateral IGBT and the forward voltage of the first diode D1. For example, the second potential is a potential lower than the ground potential.

[0124] FIG. 15 is another circuit diagram to which the trimming method is applied. In the trimming circuit 100 of this example, the orientation of the anode and cathode of the first diode D1 is different from that of the example of FIG. 13. In addition, in the trimming circuit 100 of this example, the orientation of the drain and source of the switching element 3 is different from that of the example of FIG. 13. In this example, the first potential V1 is applied to the switching element 3 instead of the second potential V2. The second potential V2 is selectively applied to the pad 24-k of the main body 20-k that cuts off the fuse resistor 22-k. Except for these points, the configuration example of FIG. 15 is similar to the configuration shown in FIG. 13. Therefore, detailed explanation will be omitted.

[0125] Each fuse resistor 22-k has one end connected to a pad 24-k and the other end connected to the cathode of the first diode D1 via a connection point 27-k. In this example, a second potential V2 is selectively applied to the pad 24-k of the main body 20-k that disconnects the fuse resistor 22-k. The second potential V1 is a voltage low enough to allow a forward current to flow from the first diode D1 to the pad 24-k. In other words, the second potential V2 is lower than the first potential V1 applied to the drain electrode of the switching element 3 by more than the sum of the voltage drop due to the operating resistance of the switching element 3 functioning as a lateral IGBT and the forward voltage of the first diode D1. For example, the second potential is a potential lower than the ground potential.

[0126] In each embodiment, components described with the same reference numerals may have similar characteristics, functions, and structures. Note that a reference numeral including a subnumber k and a reference numeral not including a subnumber k are considered to be the same reference numeral if the reference numerals other than the subnumber are the same.

[0127] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the claims that such modifications and improvements can also be included in the technical scope of the present invention.

[0128] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically indicated as "before," "prior to," etc., and may be realized in any order unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, it does not mean that it is essential to perform the process in this order. [Explanation of symbols]

[0129] 1...Adjusted circuit, 2...Adjusted element, 3...Switching element, 5...Wafer chuck section, 6...External cable, 7...Vertical device, 10...Transistor section, 11...Gate, 12...Drain, 13...Source, 20...Main body section, 22...Fuse resistor, 24...Pad, 27...Connection point, 28...Connection point, 29...Second resistor section, 30...Semiconductor substrate, 32...Polyester REFERENCE SIGNS LIST, 34....contact portion, 36...metal wiring, 37...metal wiring, 42...first semiconductor region, 44...second semiconductor region, 46...insulation film, 47...interlayer insulation film, 50...external device, 54...gate voltage application terminal, 55...first potential application terminal, 56...second potential application terminal, 100...trimming circuit, 200...semiconductor device, 201...drift layer, 202...contact layer , 203... second main electrode, 210... output stage circuit section, 211... trench gate, 212... p-type base region, 213... p+ type region, 214... n+ type region, 215... conductive section, 216... insulating film, 217... MOS section, 218... lateral IGBT, 220... first main electrode, 222... insulating film, 230... control circuit section, 240... MOS transistor, 241... p-well region, 242 ···Source region, 243···Drain region, 244···Gate electrode, 245···Gate insulating film, 246···Source electrode, 247···Drain electrode, 250···MOS transistor, 251···P-well region, 252···N-well region, 253···Source region, 254···Drain region, 255···Gate electrode, 256···Gate insulating film, 257···Source electrode, 258···Drain electrode

Claims

1. 1. A trimming method for adjusting an electrical characteristic of an adjusted circuit provided on a semiconductor substrate by cutting a fuse resistor provided on the semiconductor substrate, comprising: When a blowing current is applied to the fuse resistor to blow the fuse resistor, at least one of the switching elements provided on the semiconductor substrate is brought into a conductive state, and the blowing current is applied to the switching element; the regulated circuit includes the switching element, When a plurality of fuse resistors are provided, and the respective blowing currents are blown, the respective blowing currents flow through a common switching element. How to trim.

2. 1. A trimming method for adjusting an electrical characteristic of an adjusted circuit provided on a semiconductor substrate by cutting a fuse resistor provided on the semiconductor substrate, comprising: When a blowing current is applied to the fuse resistor to blow the fuse resistor, at least one of the switching elements provided on the semiconductor substrate is brought into a conductive state, and the blowing current is applied to the switching element; the fuse resistor is disposed on one surface of the semiconductor substrate via an insulating film, and is not disposed on the other surface of the semiconductor substrate; the switching element is a part of a vertical device that controls whether or not a current flows between a first main electrode provided on the one surface of the semiconductor substrate and a second main electrode provided on the other surface of the semiconductor substrate, When the cutting current is caused to flow, the cutting current that has flowed into the semiconductor substrate via the fuse resistor is caused to flow to the first main electrode. How to trim.

3. 1. A trimming method for adjusting an electrical characteristic of an adjusted circuit provided on a semiconductor substrate by cutting a fuse resistor provided on the semiconductor substrate, comprising: When a blowing current is applied to the fuse resistor to blow the fuse resistor, at least one of the switching elements provided on the semiconductor substrate is brought into a conductive state, and the blowing current is applied to the switching element; the fuse resistor is disposed on one surface of the semiconductor substrate via an insulating film; The conductivity type of the semiconductor substrate is n-type, The switching element is a p-type base region formed on one surface side of the semiconductor substrate, an n-type region formed in the base region, a conductive portion formed on the base region between the semiconductor substrate and the n-type region via an insulating film, and a first main electrode in contact with the n-type region, a p-type region formed on one surface side of the semiconductor substrate and separated from the p-type base region and electrically connected to the fuse resistor; The break current is passed through a lateral IGBT having components including the p-type region, the semiconductor substrate, the p-type base region, and the n-type region. How to trim.

4. 1. A trimming method for adjusting an electrical characteristic of an adjusted circuit provided on a semiconductor substrate by cutting a fuse resistor provided on the semiconductor substrate, comprising: When a blowing current is applied to the fuse resistor to blow the fuse resistor, at least one of the switching elements provided on the semiconductor substrate is brought into a conductive state, and the blowing current is applied to the switching element; the fuse resistor is disposed on one surface of the semiconductor substrate via an insulating film; the switching element is a part of a vertical device that controls whether or not a current flows between a first main electrode provided on the one surface of the semiconductor substrate and a second main electrode provided on the other surface of the semiconductor substrate, When the cutting current is to be applied, the cutting current that has flowed into the semiconductor substrate via the fuse resistor is applied to the first main electrode; The switching element is a p-type base region formed on one surface side of the semiconductor substrate, an n-type region formed in the base region, a conductive portion formed on the base region between the semiconductor substrate and the n-type region via an insulating film, and a first main electrode in contact with the n-type region, a p-type region formed on one surface side of the semiconductor substrate and separated from the p-type base region and electrically connected to the fuse resistor; The break current is passed through a lateral IGBT having components including the p-type region, the semiconductor substrate, the p-type base region, and the n-type region. How to trim.

5. a control element for controlling the vertical device is provided on the semiconductor substrate; When the cutting current is caused to flow, the control element is made non-conductive. The trimming method according to claim 2 or 4.

6. The vertical device is a MOSFET.

6. The trimming method according to claim 2, 4 or 5.

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