Silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device capable of maintaining ESD resistance even when a field oxide film is removed.SOLUTION: A silicon carbide semiconductor device includes: a silicon carbide semiconductor substrate of a first conductivity type; a first semiconductor layer 2 of the first conductivity type; a second semiconductor layer 6 of a second conductivity type; a first semiconductor region of the first conductivity type; a second semiconductor region 8 of the second conductivity type; a gate insulation film; a gate electrode; a first electrode; a second electrode; and a gate pad section 23. The gate pad section 23 is composed of a gate electrode and a connection section. In a region facing the connection section in a depth direction, there is provided a first region 6a where the second semiconductor region 8 is not provided. In a region facing a corner section of the gate electrode pad in the depth direction, there is provided a second region where the second semiconductor region 8 is not provided. An oxide film 16 being the same as the gate insulation film is provided on surfaces of the second semiconductor region 8, the first region 6a, and the second region.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to silicon carbide semiconductor devices. [Background technology]

[0002] Conventionally, silicon (Si) has been used as a constituent material of power semiconductor devices that control high voltages and large currents. There are several types of power semiconductor devices, such as bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and these are used according to the application.

[0003] For example, bipolar transistors and IGBTs have a higher current density and can handle larger currents than MOSFETs, but they cannot be switched at high speeds. Specifically, bipolar transistors can only be used at switching frequencies of a few kHz, while IGBTs can only be used at switching frequencies of a few tens of kHz. On the other hand, power MOSFETs have a lower current density and are more difficult to use at high currents than bipolar transistors and IGBTs, but they are capable of high-speed switching operations up to a few MHz.

[0004] However, there is a strong demand in the market for power semiconductor devices that combine high current and high speed, and efforts have been made to improve IGBTs and power MOSFETs, with development currently approaching the material limit. From the perspective of power semiconductor devices, semiconductor materials to replace silicon are being considered, and silicon carbide (SiC) is attracting attention as a semiconductor material that can be used to fabricate (manufacture) next-generation power semiconductor devices with excellent low on-voltage, high-speed, and high-temperature characteristics.

[0005] The reason behind this is that SiC is a very chemically stable material, with a wide band gap of 3 eV, making it extremely stable for use as a semiconductor even at high temperatures. In addition, the maximum electric field strength is more than one order of magnitude greater than that of silicon. Since SiC is likely to exceed the material limits of silicon, it is expected to see great growth in future applications for power semiconductors, especially MOSFETs. In particular, it is expected to have a low on-resistance. Vertical SiC-MOSFETs with even lower on-resistance while maintaining high voltage characteristics are anticipated.

[0006] Here, FIG. 9 is a top view showing a gate pad portion of a conventional silicon carbide semiconductor device. A vertical SiC-MOSFET will be described as an example of a conventional silicon carbide semiconductor device. In the vertical SiC-MOSFET, a gate pad portion 123 and a source pad portion are provided on the front surface. The source pad portion is provided around the gate pad portion 123. The gate pad portion 123 is composed of a gate electrode pad 119 connected to the gate electrode, and a connection portion 119a connecting the gate electrode pad 119 and a gate runner. FIG. 10 is a cross-sectional view of the E-E' portion of FIG. 9 of the conventional silicon carbide semiconductor device. FIG. 11 is a cross-sectional view of the F-F' portion of FIG. 9 of the conventional silicon carbide semiconductor device.

[0007] In the gate pad portion 123 of the conventional vertical SiC-MOSFET, n + The front surface of the silicon carbide substrate is - A silicon carbide layer 102, an n-type region (not shown) is deposited, and a lower p + Mold base region 103a, upper p + A p-type base layer 106 is provided on the surface of the p-type base layer 106. ++ A mold contact region 108 is optionally provided.

[0008] In addition, in the gate pad portion 123 of the vertical SiC-MOSFET, a field oxide film 121 having a thickness of about 500 nm is provided in an edge termination region for mitigating an electric field and maintaining a withstand voltage in order to improve ESD (Electrostatic Discharge) resistance. On the field oxide film 121, a HTO (High Temperature Oxide) film 116 having a thickness of about 100 nm is provided.

[0009] Polysilicon 117 is provided on the HTO film 116, an interlayer insulating film 118 made of BPSG and NSG is provided on the polysilicon 117, and a metal film 124 is provided on the interlayer insulating film 118. A contact hole 122a reaching the HTO film 116 is opened in the polysilicon 117, and the contact hole 122a is filled with the interlayer insulating film 118. The polysilicon 117 is electrically insulated from a gate pad portion 123 and a source pad portion by the interlayer insulating film 118.

[0010] Furthermore, a contact hole 122b reaching the polysilicon 117 is opened in the interlayer insulating film 118, electrically connecting the metal film 124 and the polysilicon 117. A contact hole 122c reaching the interlayer insulating film 118 is opened in the metal film 124, and the metal film 124 is electrically insulated from a portion of the gate pad portion 123 and a portion of the source pad portion. The metal film 124 in the portion of the gate pad portion 123 becomes the gate electrode pad 119.

[0011] In addition, a technology is known in which, by increasing the surface area of ​​the entire gate polysilicon layer provided on the first main surface of the semiconductor substrate via an oxide film, even if a large amount of charge is injected into the gate pad due to ESD or the like, the voltage applied to the oxide film below the gate polysilicon layer can be distributed, thereby suppressing dielectric breakdown of the oxide film (for example, see Patent Document 1 below). [Prior art documents] [Patent documents]

[0012] [Patent Document 1] JP 2020-150179 A Summary of the Invention [Problem to be solved by the invention]

[0013] Here, in a trench MOSFET, the field oxide film 121 is selectively formed after the trench is formed. In order to form the field oxide film 121, a mask needs to be formed, which increases the manufacturing cost. For this reason, a vertical SiC-MOSFET in which the field oxide film 121 is removed has been proposed.

[0014] Fig. 12 is a cross-sectional view of the silicon carbide semiconductor device from which the field oxide film has been removed, taken along the line E-E' in Fig. 9. Fig. 13 is a cross-sectional view of the silicon carbide semiconductor device from which the field oxide film has been removed, taken along the line F-F' in Fig. 9. In this case, as shown in Figs. 12 and 13, p ++ An HTO film 116 is provided on the mold contact region 108 .

[0015] However, if the field oxide film 121 is not formed, electric field concentration occurs, which causes a problem of reduced ESD resistance. As a result, when an ESD test is performed on a silicon carbide semiconductor device from which the field oxide film has been removed, destruction may occur in the gate electrode pad 119. In particular, destruction may occur in the corners of the gate electrode pad 119 (part B in FIG. 9 ) and in the contact hole 122b of the connection part 119a where the electric field is concentrated, and in the region from the contact hole 122b to the gate electrode pad 119 (part A in FIG. 9 ).

[0016] In order to solve the above-mentioned problems associated with the conventional techniques, an object of the present invention is to provide a silicon carbide semiconductor device capable of maintaining ESD resistance even when the field oxide film is removed. [Means for solving the problem]

[0017] In order to solve the above-mentioned problems and achieve the object of the present invention, the silicon carbide semiconductor device according to the present invention has the following features. In the silicon carbide semiconductor device, a first semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate is provided on a front surface of a silicon carbide semiconductor substrate of a first conductivity type. A second semiconductor layer of a second conductivity type is selectively provided on a surface layer of the first semiconductor layer opposite to the silicon carbide semiconductor substrate. A first semiconductor region of a first conductivity type is selectively provided on a surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate. A second semiconductor region of a second conductivity type having a higher impurity concentration than the second semiconductor layer is selectively provided on a surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate. A gate electrode is provided via a gate insulating film on at least a part of a surface of the second semiconductor layer sandwiched between the first semiconductor region and the first semiconductor layer. A first electrode is provided on surfaces of the first semiconductor region and the second semiconductor region. A second electrode is provided on a rear surface of the silicon carbide semiconductor substrate. A gate pad section electrically connected to the gate electrode via a gate electrode wiring is provided. The gate pad section is composed of a gate electrode pad and a connection section electrically connecting the gate electrode pad and the gate electrode wiring. A first region in which the second semiconductor region is not provided is located in a region facing the connection section in the depth direction, and a second region in which the second semiconductor region is not provided is located in a region facing a corner of the gate electrode pad in the depth direction. An oxide film identical to the gate insulating film is provided on the surfaces of the second semiconductor region, the first region, and the second region. The same oxide film means an oxide film formed at the same time, includes an oxide film formed at the same time on surfaces with different surface orientations, and corresponds to an oxide film formed at the same time and having a thickness according to the surface orientation.

[0018] In addition, the silicon carbide semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, a width of the first region is greater than or equal to a width of a first polysilicon layer provided in a region opposing the connection portion in the depth direction.

[0019] In addition, in the silicon carbide semiconductor device according to the present invention, a width of the first region is wider than an end of the first polysilicon layer by 20 μm or less.

[0020] In addition, the silicon carbide semiconductor device of the present invention is characterized in that, in the above-mentioned invention, the width of the second region is 10 μm or more and 40 μm or less, centered on an end of the second polysilicon layer provided in a region facing the gate electrode pad in a depth direction.

[0021] In addition, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the first region and the second region have the same conductivity type and the same impurity concentration as the second semiconductor layer.

[0022] In addition, the silicon carbide semiconductor device of the present invention, in the above-mentioned invention, further has a third region, in which the second semiconductor region is not provided, facing a peripheral portion of the gate electrode pad in a depth direction, and the oxide film is also provided on a surface of the third region.

[0023] In addition, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the high-temperature oxide film has a thickness of not less than 50 nm and not more than 150 nm.

[0024] According to the above-mentioned invention, a field oxide film is not provided, and p is formed on the connection part of the gate pad part and the corner of the gate electrode pad. ++ The HTO film is in contact with the p-type base layer (second semiconductor layer of the second conductivity type) in the depth direction at the connection and corner portions. ++ Since the impurity concentration in the p-type base layer is lower than that in the p-type contact region, and the lower the impurity concentration, the wider the depletion layer becomes, the p-type base layer increases the ESD resistance, and the same level of ESD resistance as when a field oxide film is provided can be achieved. In this way, the present invention makes it possible to reduce manufacturing costs while maintaining the ESD resistance without providing a field oxide film. Effect of the Invention

[0025] The silicon carbide semiconductor device according to the present invention has an advantage in that it is possible to maintain ESD resistance even when the field oxide film is removed. [Brief description of the drawings]

[0026] [Figure 1] 1 is a cross-sectional view showing a structure of a silicon carbide semiconductor device according to an embodiment. [Diagram 2] FIG. 2 is a cross-sectional view showing another structure of the silicon carbide semiconductor device according to the embodiment. [Diagram 3] 1 is a top view showing a structure of a silicon carbide semiconductor device according to an embodiment; [Figure 4] 2 is an enlarged view of a gate pad portion of the silicon carbide semiconductor device according to the embodiment; FIG. [Diagram 5] 2 is an enlarged view of a connection portion of a gate electrode pad of the silicon carbide semiconductor device according to the embodiment; FIG. [Figure 6] 6 is a cross-sectional view of the silicon carbide semiconductor device according to the embodiment taken along the line CC' of FIG. 5. [Figure 7] 2 is an enlarged view of a corner of a gate electrode pad of the silicon carbide semiconductor device according to the embodiment; [Figure 8] 8 is a cross-sectional view of the silicon carbide semiconductor device according to the embodiment taken along line DD' of FIG. 7. [Figure 9] FIG. 1 is a top view showing a gate pad portion of a conventional silicon carbide semiconductor device. [Figure 10] 10 is a cross-sectional view of the conventional silicon carbide semiconductor device taken along the line EE' of FIG. [Figure 11] 10 is a cross-sectional view of the conventional silicon carbide semiconductor device taken along the line FF' of FIG. [Figure 12] 10 is a cross-sectional view of the silicon carbide semiconductor device from which the field oxide film has been removed, taken along the line EE' of FIG. 9. [Figure 13] 10 is a cross-sectional view of the silicon carbide semiconductor device from which the field oxide film has been removed, taken along the line F-F' of FIG. 9. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] A preferred embodiment of the silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, in a layer or region prefixed with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - attached to n or p mean that the impurity concentration is higher and lower than that of a layer or region to which they are not attached, respectively. When the notations of n and p including + and - are the same, it indicates that the concentrations are close, but the concentrations are not necessarily the same. In the following description of the embodiment and the accompanying drawings, the same symbols are attached to similar configurations, and duplicated explanations are omitted. In addition, in this specification, in the notation of Miller indices, "-" means a bar attached to the index immediately following it, and a negative index is represented by adding "-" before the index. In addition, the description of "same" or "equivalent" should include within 5% in consideration of variations in manufacturing. In addition, the same oxide film means an oxide film formed at the same time, including oxide films formed simultaneously on surfaces with different surface orientations, and corresponds to an oxide film formed simultaneously and having a thickness according to the surface orientation.

[0028] (Embodiment) The semiconductor device according to the present invention is configured using a wide band gap semiconductor. In the embodiment, a silicon carbide semiconductor device fabricated (manufactured) using, for example, silicon carbide (SiC) as a wide band gap semiconductor will be described by taking a trench-type MOSFET 50 as an example. Fig. 1 is a cross-sectional view showing a structure of the silicon carbide semiconductor device according to the embodiment.

[0029] As shown in Fig. 1, the semiconductor device according to the embodiment includes a semiconductor substrate 40 made of silicon carbide (hereinafter referred to as a silicon carbide substrate (semiconductor substrate (semiconductor chip)) with an active region 20 and an edge termination region 30 surrounding the active region 20. The active region 20 is a region through which current flows in an on-state. The edge termination region 30 is a region that relieves the electric field on the front surface side of the substrate in the drift region and maintains a breakdown voltage.

[0030] The silicon carbide substrate 40 is a n-type semiconductor substrate made of silicon carbide. + Mold support substrate (n + A first conductivity type silicon carbide semiconductor substrate (1) is provided on a front surface of the n-type silicon carbide substrate (1). - Type semiconductor layer (n - The n-type silicon carbide layer (a first semiconductor layer of a first conductivity type) 2 and a p-type semiconductor layer (a p-type base layer, a second semiconductor layer of a second conductivity type) 6 made of silicon carbide are laminated in this order. + The n-type silicon carbide substrate 1 functions as a drain region. - The n-type silicon carbide layer 2 + The surface layer on the opposite side (front surface side of the substrate) to the silicon carbide substrate 1 side is + A p-type base region 3 and an n-type region 5 are selectively provided. + The mold base region 3 is a lower p + Mold base region 3a, upper p + The mold base region 3b is made up of two layers.

[0031] In addition, the edge termination region 30 includes a plurality of p - Low concentration region (here, two, p - type, p -- The JTE structure 32 is provided with adjacent n-type MOSFETs (designated MOSFETs 32a and 32b). + The JTE structure 32 and the n-type semiconductor region 33 are provided. + The step 31 causes the n-type semiconductor region 33 to - The p-type silicon carbide layer 2 is provided at the bottom 31a of the step 31 formed by thinning the thickness of the p-type silicon carbide layer 2. + The n-type base region 3 extends from the active region 20 side to the edge termination region 30. - The p-type silicon carbide layer 2 + The portion other than the n-type base region 3 is a drift region. + Lower n than silicon carbide substrate 1 -The n-type drift layer has an impurity concentration higher than that of the n-type silicon carbide layer 2.

[0032] n - The n-type silicon carbide layer 2 + A p-type base layer 6 is provided on the surface opposite to the silicon carbide substrate 1. The impurity concentration of the p-type base layer 6 is + The impurity concentration of the p-type base region 3 is lower than that of the n-type base region 3. + A p-type source region (a first semiconductor region of a first conductivity type) 7 and ++ A contact region (second semiconductor region of a second conductivity type) 8 is selectively provided on each of the first and second semiconductor regions.

[0033] The p-type base layer 6 is a p + The p-type base layer 6 is provided to cover the n-type base region 3 and the n-type region 5. The p-type base layer 6 extends to the edge termination region 30. In the edge termination region 30, the p-type base layer 6 is formed up to the step 31. + Type base region 3 and n - The insulating layer 1 is provided so as to cover the silicon carbide layer 2 .

[0034] A trench structure is formed in the active region 20 on the front surface side of the silicon carbide substrate 40. Specifically, the trench 15 is formed between the n-type base layer 6 and the p-type base layer 6. + From the surface on the opposite side to the silicon carbide substrate 1 side (the front surface side of the silicon carbide base 40), + The n-type region 5 and the lower p-type source region 7 and the p-type base layer 6 are connected to each other. + A gate insulating film 9 is formed on the bottom and side walls of the trench 15 along the inner wall of the trench 15, and a gate electrode 10 is formed on the inside of the gate insulating film 9 in the trench 15. The gate electrode 10 is formed by the gate insulating film 9 so as to cover the n-type region 5, the p-type region 3a, and the n-type region 5b. + The gate electrode 10 is insulated from the p-type base region 3 and the p-type base layer 6. A part of the gate electrode 10 may protrude from above the trench 15 (the source electrode pad 13 side) towards the source electrode pad 13.

[0035] The interlayer insulating film 11 is provided on the entire front surface side of the silicon carbide substrate 40 so as to cover the gate electrode 10 embedded in the trench 15. The source electrode 12 is connected to the n-type + Type source region 7 and p ++ The source electrode 12 is in contact with the gate electrode 10 by an interlayer insulating film 11. A source electrode pad 13 is provided on the source electrode 12. + A drain electrode 14 is provided on the back surface of the silicon carbide substrate 1 .

[0036] Although FIG. 1 illustrates only one trench MOS structure, more MOS gate structures (insulated gates made of metal-oxide-semiconductor) having trench gate structures may be arranged in parallel.

[0037] Fig. 2 is a cross-sectional view showing another structure of a silicon carbide semiconductor device according to an embodiment. Fig. 2 shows an example of a planar MOSFET 51. As shown in Fig. 2, the semiconductor device according to the embodiment includes an active region 20 and an edge termination region 30 surrounding the periphery of the active region 20 on a silicon carbide substrate 40 made of silicon carbide.

[0038] The silicon carbide substrate 40 is a n-type semiconductor substrate made of silicon carbide. + Mold support substrate (n + A n-type silicon carbide substrate 1 is provided on the front surface of the n-type silicon carbide substrate 1. - Type semiconductor layer (n - The n-type silicon carbide layer 2 and a p-type semiconductor layer (p-type base layer) 6 made of silicon carbide are laminated in this order. + The n-type silicon carbide substrate 1 functions as a drain region. - The n-type silicon carbide layer 2 + The surface layer on the opposite side (front surface side of the substrate) to the silicon carbide substrate 1 side is + An n-type base region 3 and an n-type region 5 are optionally provided.

[0039] In addition, the p-type base layer 6 +The portion on the base region 3 is + Type source region 7 and p ++ A contact region 8 is provided. + Type source region 7 and p ++ The contact regions 8 are in contact with each other. ++ The contact region 8 is an n + The second source region 7 is disposed closer to the edge termination region 30 than the second source region 7 .

[0040] In addition, an n-type well region 4 is provided on the portion of the p-type base layer 6 above the n-type region 5, penetrating the p-type base layer 6 in the depth direction and reaching the n-type region 5. The n-type well region 4 is formed by connecting the n-type region 5, the n - The p-type base layer 6 and the n-type silicon carbide layer 2 form a drift region. + A gate electrode 10 is provided on the surface of a portion sandwiched between the n-type source region 7 and the n-type well region 4, with a gate insulating film 9 interposed therebetween. The gate electrode 10 may be provided on the surface of the n-type well region 4 with the gate insulating film 9 interposed therebetween.

[0041] An interlayer insulating film 11 is provided on the entire front surface side of the silicon carbide substrate so as to cover the gate electrode 10. A source electrode 12 is connected to the n-type semiconductor layer 11 through a contact hole opened in the interlayer insulating film 11. + Type source region 7 and p ++ The source electrode 12 is in contact with the gate electrode 10 by an interlayer insulating film 11. A source electrode pad 13 is provided on the source electrode 12. + A drain electrode 14 is provided on the back surface of the silicon carbide substrate 1 .

[0042] 2 shows only one MOS structure, but more MOS gates (insulated gates made of metal-oxide-semiconductor) may be arranged in parallel. The structure of the edge termination region 30 is the same as that of the trench MOSFET, and therefore will not be described.

[0043] 3 is a top view showing a structure of a silicon carbide semiconductor device according to an embodiment. As shown in FIG. 3, the silicon carbide semiconductor device has a source pad portion 26 and a gate pad portion 23 on the top surface. A source electrode pad 13 is provided on the source pad portion 26. The source electrode pad 13 is electrically connected to the source electrode 12, and the gate pad portion 23 is electrically connected to the gate electrode 10 via a gate runner 25.

[0044] Fig. 4 is an enlarged view of a gate pad portion of the silicon carbide semiconductor device according to the embodiment. As shown in Fig. 4, the gate pad portion 23 is composed of a gate electrode pad 19 and a connection portion 19a (part A in Fig. 3) of the gate electrode pad that electrically connects the gate electrode pad 19 and a gate runner 25. Here, the connection portion 19a is a region between the gate runner 25 and the gate electrode pad 19.

[0045] Fig. 5 is an enlarged view of a connection portion of a gate electrode pad of a silicon carbide semiconductor device according to an embodiment. In Fig. 5, contact holes 22a, 22b, and 22c, which will be described below, are shown. However, contact hole 22a is shown by a single line because it is narrow.

[0046] 6 is a cross-sectional view of the silicon carbide semiconductor device according to the embodiment taken along the line CC' of FIG. 5. In the connection portion 19a of the gate electrode pad of the silicon carbide semiconductor device according to the embodiment, n + The front surface of the silicon carbide substrate is - A silicon carbide layer 2 is deposited on the n-type region (not shown), and a lower p + Mold base region 3a, upper p + A p-type base region 3b is selectively provided, and a p-type base layer 6 is provided on the n-type region. + The mold base region 3a and the upper p + By providing the p-type base region 3b, the displacement current flows easily through this region at the time of turn-off due to its low resistance, and the concentration of the electric field on the HTO film 16 described later can be suppressed. ++6 shows a trench-type MOSFET 50, whereas a planar-type MOSFET 51 has a p + In this case, the lower p + Mold base region 3a, upper p + It has the same effect as the mold base region 3b.

[0047] p ++ An HTO film 16 is formed on the contact region 8 and the first region 6a described later at the same time as the gate insulating film 9 and has a thickness (50 nm to 150 nm) similar to that of the gate insulating film 9. The gate insulating film 9 and the HTO film 16 formed at the same time should have a thickness in the range of 50 nm to 150 nm even if there is a difference in thickness due to the difference in surface orientation. Polysilicon 17 is provided on the HTO film 16, an interlayer insulating film 18 made of BPSG and NSG is provided on the polysilicon 17, and a metal film 24 is provided on the interlayer insulating film 18. A contact hole 22a reaching the HTO film 16 is opened in the polysilicon 17, and the interlayer insulating film 18 fills the contact hole 22a. The interlayer insulating film 18 electrically insulates the polysilicon 17a facing the gate pad portion 23 in the depth direction (from the source electrode 12 to the drain electrode 14) from a portion facing the source pad portion 26 in the depth direction.

[0048] Furthermore, a contact hole 22b reaching the polysilicon 17 is opened in the insulating film 18, electrically connecting the metal film 24 and the polysilicon 17. A contact hole 22c reaching the interlayer insulating film 18 is opened in the metal film 24, and the metal film 24 is electrically insulated from the gate pad portion 23 and the source pad portion 26.

[0049] In the embodiment, as shown in FIG. 6, a field oxide film is not provided, and the p-type base layer 6 and the p ++ A thin HTO film 16 is provided on the surface of the contact region 8. If a field oxide film is not provided, electric field concentration occurs and ESD resistance decreases, so a structure for mitigating the electric field is provided in the area where electric field concentration occurs.

[0050] The electric field concentration occurs at the connection portion 19a of the gate electrode pad. Therefore, the connection portion 19a of the gate electrode pad has p ++ The contact region 8 is pulled out, and the p ++ The connection portion 19a has a first region 6a where the p-type contact region 8 is not provided. Therefore, in the connection portion 19a, the HTO film 16 is in contact with the p-type base layer 6 in the depth direction. In this structure, for example, the width L2 of the polysilicon 17a of the connection portion 19a or more, the p ++ The first region 6a can be used as the p-type base layer 6 without forming the contact region 8. The width L1 of the first region 6a is preferably equal to the width L2 (e.g., 80 μm) of the polysilicon 17a or is wider than the end 17c of the polysilicon 17a by 20 μm or less. For this reason, the width L1 of the first region 6a is preferably 80 μm or more and 120 μm or less. If it is wider than 120 μm, there will be many low-resistance regions, and the HTO film 16 may be destroyed when a displacement current flows at turn-off. If it is narrower than the width L2 of the polysilicon 17a, the depletion layer width is narrow and the ESD resistance cannot be sufficiently increased.

[0051] The first region 6a is p ++ The impurity concentration in the first region 6a is lower than that in the type contact region 8. The lower the impurity concentration, the wider the depletion layer width, so the first region 6a increases the ESD resistance, and it is possible to achieve an ESD resistance equivalent to that in the case where a field oxide film is provided. In this way, in the embodiment, it is possible to reduce manufacturing costs while maintaining the ESD resistance without providing a field oxide film.

[0052] Fig. 7 is an enlarged view of a corner of a gate electrode pad of a silicon carbide semiconductor device according to an embodiment. The corner of the gate electrode pad is the four corners of the gate electrode pad (part B in Fig. 3). Fig. 7 shows contact holes 22a and 22c. However, contact hole 22a is shown by a single line because it is narrow.

[0053] 8 is a cross-sectional view of the silicon carbide semiconductor device according to the embodiment taken along the line DD' of FIG. 7. The corner of the gate electrode pad of the silicon carbide semiconductor device according to the embodiment has n + The front surface of the silicon carbide substrate is - A silicon carbide layer 2 is deposited on the n-type region (not shown), and a lower p + Mold base region 3a, upper p + A p-type base layer 6 is provided on the surface of the p-type base layer 6. ++ 8 shows a trench-type MOSFET 50, whereas a planar-type MOSFET 51 has a p + This becomes one layer of the mold base region 3 (see FIG. 2).

[0054] p ++ An HTO film 16 is provided on the contact region 8 and a second region 6b described later. Polysilicon 17 is provided on the HTO film 16, an interlayer insulating film 18 made of BPSG and NSG is provided on the polysilicon 17, and a metal film 24 is provided on the interlayer insulating film 18. A contact hole 22a reaching the HTO film 16 is opened in the polysilicon 17, and the contact hole 22a is filled with the interlayer insulating film 18. The interlayer insulating film 18 electrically insulates the polysilicon 17 from the polysilicon 17b facing the gate pad portion 23 in the depth direction and from a portion facing the source pad portion 26 in the depth direction.

[0055] A contact hole 22c reaching the interlayer insulating film 18 is opened in the metal film 24, and the metal film 24 is electrically insulated from a portion of the gate pad portion 23 and a portion of the source pad portion 26. The metal film 24 in the portion of the gate pad portion 23 becomes the gate electrode pad 19.

[0056] The corners of the gate electrode pad are areas where electric field concentration occurs. For this reason, the corners of the gate electrode pad have p ++ The contact region 8 is pulled out, and the p ++The gate electrode pad 19 has a second region 6b where the p-type contact region 8 is not provided. Therefore, at the corners of the gate electrode pad, the HTO film 16 is in contact with the p-type base layer 6 in the depth direction. In this structure, for example, the p ++ In this embodiment, the second region 6b is used as the p-type base layer 6 without forming the p-type contact region 8. The width L3 of the second region 6b at the corner of the gate electrode pad is preferably 10 μm to 40 μm from the end 17d of the polysilicon 17b. Even in this case, if it is wider than 40 μm, the low resistance region increases, and there is a risk that the HTO film 16 will be destroyed when a displacement current flows at turn-off. Also, if it is narrower than 10 μm, the depletion layer width is narrow and the ESD resistance cannot be sufficiently increased.

[0057] In the gate electrode pad 19, p ++ The contact region 8 is pulled out, and the p ++ For example, as shown in FIG. 4, the entire outer periphery of the gate electrode pad 19 may include a region where the p ++ The contact region 8 is pulled out, and the p ++ Alternatively, the third region 6c may be provided with no type contact region 8. In this case, for example, the p ++ No type contact region 8 is formed, and the third region 6c serves as a p-type base layer 6. It is preferable that the width L3 of the third region 6c on the periphery of the gate electrode pad is 10 μm or more and 40 μm or less, centered on the end 17d of the polysilicon 17b.

[0058] The second region 6b and the third region 6c are p ++ The impurity concentration in the second region 6b is lower than that in the second contact region 8. The lower the impurity concentration, the wider the depletion layer width, so the second region 6b and the third region 6c increase the ESD resistance, and it is possible to achieve an ESD resistance equivalent to that in the case where a field oxide film is provided. In this way, in the embodiment, it is possible to reduce manufacturing costs while maintaining the ESD resistance without providing a field oxide film.

[0059] (Method of Manufacturing Silicon Carbide Semiconductor Device According to an Embodiment) The method for manufacturing a silicon carbide semiconductor device according to the embodiment can be described as follows. Here, a trench MOSFET with a breakdown voltage of 1200 V is fabricated as an example. First, for example, 2.0×10 19 / cm 3 The n-type dopant of silicon carbide single crystal is doped with nitrogen (N) or other n-type impurities (dopants) to achieve an impurity concentration of + A silicon carbide substrate (semiconductor wafer) 1 is prepared. + The front surface of the n-type silicon carbide substrate 1 may be a (0001) surface having an off angle of about 4 degrees in the <11-20> direction. + The front surface of the silicon carbide substrate 1 is, for example, 1.0×10 16 / cm 3 The impurity concentration of n-type impurities such as nitrogen is - The silicon carbide layer 2 is epitaxially grown to a thickness of, for example, 10 μm.

[0060] Next, photolithography and ion implantation are used to create n - The n-type region 5 is selectively formed in the surface layer of the silicon carbide layer 2. In this ion implantation, for example, 1×10 17 / cm 3 Alternatively, an n-type impurity (dopant) such as nitrogen may be implanted to a concentration of 0.1 to 1.0 n-type.

[0061] Next, p is formed in the surface layer of the n-type region 5 by photolithography and ion implantation. + The outermost p-type base region 3 is selectively formed. + The base region 3 is formed so as to extend to the edge termination region 30. In this ion implantation, a p-type impurity (dopant) such as aluminum (Al) is implanted into the p + The impurity concentration of the base region 3 is 5.0×10 18 / cm 3 The mixture may be injected so that

[0062] Next, n- The surface of the silicon carbide layer 2 is then coated with, for example, 2.0×10 17 / cm 3 A p-type base layer 6 doped with a p-type impurity such as aluminum to have an impurity concentration of 1.3 μm is epitaxially grown to a thickness of, for example, 1.3 μm.

[0063] In the process up to this point, n + A silicon carbide substrate 1 has an n-type - A silicon carbide substrate 40 is fabricated by sequentially stacking a silicon carbide layer 2 and a p-type base layer 6. Next, a set of steps including forming an ion implantation mask by photolithography and etching, ion implantation using the ion implantation mask, and removal of the ion implantation mask is repeated under different ion implantation conditions to form n ions in the surface layer of the p-type base layer 6. + Type source region 7 and p ++ In this case, the first region 6a, the second region 6b, and the third region 6c are provided with p ++ The mold contact region 8 is not formed.

[0064] Next, a step 31 is formed on the surface of the p-type base layer 6 in the edge termination region 30 by photolithography and etching, for example, to a depth of 1.5 μm from the surface of the p-type base layer 6. - A part of the silicon carbide layer 2 is removed to form an n - The n-type silicon carbide layer 2 is exposed. Next, the JTE structure 32 is selectively formed by photolithography and ion implantation. Next, the n-type silicon carbide layer 2 is selectively formed by photolithography and ion implantation. + A mold region 33 is selectively formed.

[0065] Next, a heat treatment (annealing) is performed to form, for example, p + Type base region 3, n + Type source region 7, p ++ type contact region 8, JTE structure 32, n +The type semiconductor region 33 is activated. The temperature of the heat treatment may be, for example, about 1700° C. The time of the heat treatment may be, for example, about 2 minutes. As described above, the ion implantation regions may be activated collectively by one heat treatment, or the heat treatment may be performed each time an ion implantation is performed.

[0066] Next, the surface of the p-type base layer 6 (i.e., n + Type source region 7 and p ++ On the surface of the contact region 8), n + A trench 15 is formed through the p-type source region 7 and the p-type base layer 6 to reach the n-type region 5. The bottom of the trench 15 is + The mold base region 3 is reached.

[0067] Next, n + Type source region 7 and p ++ A gate insulating film 9 is formed along the surface of the contact region 8 and the bottom and sidewalls of the trench 15. The gate insulating film 9 is formed by a method of deposition by chemical reaction such as high temperature oxidation (HTO). ++ The gate insulating film 9 formed on the surface of the mold contact region 8 becomes the HTO film 16 shown in FIGS.

[0068] Next, a polycrystalline silicon layer doped with, for example, phosphorus atoms (P) is formed on the gate insulating film 9. This polycrystalline silicon layer is formed so as to fill the trench 15. This polycrystalline silicon layer is patterned and left inside the trench 15 to form the gate electrode 10. A part of the gate electrode 10 may protrude from above the trench 15 (the source electrode pad 13 side) towards the source electrode pad 13.

[0069] Next, for example, phosphorus glass (PSG) is formed to a thickness of about 1 μm so as to cover the gate insulating film 9 and the gate electrode 10, forming an interlayer insulating film 11. The interlayer insulating film 11 and the gate insulating film 9 are patterned and selectively removed to form contact holes, and n + Type source region 7 and p ++ The mold contact region 8 is exposed. After that, a heat treatment (reflow) is performed to flatten the interlayer insulating film 11.

[0070] Next, a conductive film that will become the source electrode 12 is formed in the contact hole and on the interlayer insulating film 11. This conductive film is selectively removed to leave the source electrode 12 only in, for example, the contact hole.

[0071] Next, the back surface (n + A drain electrode 14 made of, for example, a nickel (Ni) film is formed on the back surface of the n-type silicon carbide substrate 1. Then, a heat treatment is performed at a temperature of, for example, about 970° C. to form an n-type silicon carbide substrate. + The silicon carbide substrate 1 and the drain electrode 14 are connected to each other by an ohmic junction.

[0072] Next, for example, an aluminum film is provided by, for example, a sputtering method so as to have a thickness of, for example, about 5 μm, so as to cover the source electrode 12 and the interlayer insulating film 11. Thereafter, the aluminum film is selectively removed and left so as to cover the active region 20, thereby forming the source electrode pad 13.

[0073] Next, a drain electrode pad is formed by sequentially stacking, for example, titanium (Ti), nickel (Ni) and gold (Au) on the surface of the drain electrode 14. In this manner, the trench MOSFET 50 shown in Fig. 1 is completed. The planar MOSFET 51 shown in Fig. 2 can also be formed in a similar manner.

[0074] As described above, according to the embodiment, a field oxide film is not provided, and p is formed on the connection portion of the gate pad portion and the corners of the gate electrode pad. ++The HTO film is in contact with the p-type base layer in the depth direction at the connection and corners. ++ Since the impurity concentration in the p-type base layer is lower than that in the p-type contact region, and the lower the impurity concentration, the wider the depletion layer width, the p-type base layer increases the ESD resistance, and the same level of ESD resistance as in the case where a field oxide film is provided can be realized. In this way, in the embodiment, it is possible to reduce manufacturing costs while maintaining the ESD resistance without providing a field oxide film.

[0075] The present invention can be modified in various ways without departing from the spirit of the present invention, and in each of the above-mentioned embodiments, for example, the dimensions of each part and the impurity concentration are variously set according to the required specifications, etc. Also, in each of the embodiments of the present invention, the first conductivity type is p-type and the second conductivity type is n-type, but the present invention is similarly valid even if the first conductivity type is n-type and the second conductivity type is p-type. [Industrial Applicability]

[0076] INDUSTRIAL APPLICABILITY As described above, the silicon carbide semiconductor device according to the present invention is useful for power semiconductor devices used in power conversion devices such as inverters, power supply devices for various industrial machines, inverters for electric vehicles, and the like. [Explanation of symbols]

[0077] 1n + Silicon carbide substrate 2, 102 n - mold silicon carbide layer 3 p + Type-based regions 3a, 103a lower p + Type-based regions 3b, 103b upper p + Type-based regions 4. N-type well region 5 n-type region 6, 106 p-type base layer 6a p ++ A first region in which the mold contact region is not provided 6b p++ A second region where the mold contact region is not provided. 6c p ++ A third region in which the mold contact region is not provided. 7 n + Type Source Area 8, 108 p. ++ Mold Contact Area 9 Gate insulating film 10 Gate electrode 11 Interlayer insulating film 12 Source electrode 13 Source electrode pad 14 Drain electrode 15. Trench 16, 116 HTO membrane 17, 117 Polysilicon 17a Polysilicon facing the gate pad in the depth direction 17b Polysilicon facing the gate electrode pad in the depth direction 17c End of polysilicon facing the gate pad in the depth direction 17d: An end of the polysilicon facing the gate electrode pad in the depth direction 18, 118 Interlayer insulating film 19, 119 Gate electrode pad 19a, 119a connection 20 active area 22a, 22b, 22c, 122a, 122b, 122c contact holes 23, 123 Gate pad section 24, 124 Metal film 25 Gate Runner 26 Source pad section 30 Edge Termination Area 31 Steps 32 JTE structure 33n + Semiconductor area 40 Silicon carbide substrate 50 Trench MOSFET 51 Planar MOSFET 121 Field oxide

Claims

1. a first conductivity type silicon carbide semiconductor substrate; a first semiconductor layer of a first conductivity type provided on a front surface of the silicon carbide semiconductor substrate and having a lower impurity concentration than the silicon carbide semiconductor substrate; a second semiconductor layer of a second conductivity type selectively provided on a surface layer of the first semiconductor layer on an opposite side to the silicon carbide semiconductor substrate; a first semiconductor region of a first conductivity type selectively provided in a surface layer of the second semiconductor layer on a side opposite to the silicon carbide semiconductor substrate; a second semiconductor region of a second conductivity type having a higher impurity concentration than the second semiconductor layer, the second semiconductor region being selectively provided in a surface layer of the second semiconductor layer on the opposite side to the silicon carbide semiconductor substrate; a gate electrode provided via a gate insulating film on at least a portion of a surface of the second semiconductor layer sandwiched between the first semiconductor region and the first semiconductor layer; a first electrode provided on a surface of the first semiconductor region and the second semiconductor region; A second electrode provided on a back surface of the silicon carbide semiconductor substrate; a gate pad portion electrically connected to the gate electrode via a gate electrode wiring; Equipped with the gate pad section is composed of a gate electrode pad and a connection section that electrically connects the gate electrode pad and the gate electrode wiring, a first region in which the second semiconductor region is not provided, the first region being opposed to the connection portion in a depth direction; a second region in which the second semiconductor region is not provided, the second region being located in a region opposite to a corner portion of the gate electrode pad in a depth direction; having a gate insulating film formed on surfaces of the second semiconductor region, the first region and the second region;

2. 2 . The silicon carbide semiconductor device according to claim 1 , wherein a width of said first region is equal to or greater than a width of a first polysilicon layer provided in a region facing said connection portion in a depth direction.

3. 3 . The silicon carbide semiconductor device according to claim 2 , wherein a width of the first region is wider than an end of the first polysilicon layer by 20 μm or less.

4. The silicon carbide semiconductor device according to any one of claims 1 to 3, characterized in that a width of the second region is 10 μm or more and 40 μm or less, centered on an end of a second polysilicon layer provided in a region opposite to the gate electrode pad in a depth direction.

5. 5. The silicon carbide semiconductor device according to claim 1, wherein the first region and the second region have the same conductivity type and the same impurity concentration as the second semiconductor layer.

6. 6. The silicon carbide semiconductor device according to claim 1, further comprising a third region, in which the second semiconductor region is not provided, in a region facing a peripheral portion of the gate electrode pad in a depth direction, and the oxide film is also provided on a surface of the third region.

7. 7. The silicon carbide semiconductor device according to claim 1, wherein the oxide film has a thickness of not less than 50 nm and not more than 150 nm.

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