Semiconductor Device

Abstract

To provide a semiconductor device capable of preventing a body diode from turning on even at a large current by suppressing voltage drop in a lateral direction of a gate pad section and suppressing injection of a minority carrier (positive holes).SOLUTION: A semiconductor device includes: a first semiconductor layer 2 of a first conductivity type arranged on a front face of a semiconductor substrate 1 of the first conductivity type; a second semiconductor layer 3 of a second conductivity type; and a first semiconductor region 7 of the first conductivity type. In the semiconductor device, a gate electrode 10 is arranged in an inside of a part of a first trench 18 among a plurality of trenches via a gate insulation film, and a conductive layer 15 is arranged in an inside of a second trench 19 except the first trench among the plurality of trenches.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Conventionally, in power semiconductor elements, vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) with a trench structure have been fabricated (manufactured) to reduce the on-resistance of the elements. In vertical MOSFETs, a trench structure in which the channel is formed perpendicular to the substrate surface can increase the cell density per unit area compared to a planar structure in which the channel is formed parallel to the substrate surface, and therefore the current density per unit area can be increased, which is advantageous from the standpoint of cost.

[0003] The trench gate structure is a three-dimensional structure in which a MOS gate (insulated gate made of metal-oxide-semiconductor) is embedded in a trench formed in a semiconductor substrate made of silicon carbide (hereafter referred to as silicon carbide substrate), and the portion along the sidewall of the trench is used as a channel (inversion layer).For this reason, when comparing elements with the same on-resistance (Ron), the trench gate structure can overwhelmingly reduce the element area (chip area) compared to a planar gate structure in which a MOS gate is provided as a flat plate on a silicon carbide substrate, making it a promising device structure for the future.

[0004] In a trench MOSFET, a trench for a Schottky barrier diode (SBD) is formed between adjacent gate trenches, and a Schottky junction is formed on the side surface of the trench. Fig. 13 is a cross-sectional view showing the configuration of a conventional trench-type silicon carbide semiconductor device with an internal SBD. In Fig. 13, the left side of the omitted dashed line in the center shows the configuration of an active section 21 where an element structure is formed and where a current flows when the device is on, and the right side of the omitted dashed line in the center shows the configuration of a gate pad section 20.

[0005] As shown in Fig. 13, the conventional trench-type silicon carbide semiconductor device includes, in an active portion 21, a trench-type MOS gate (insulated gate made of metal-oxide film-semiconductor) structure and a contact trench 19 in which a trench-type SBD is embedded, on the front surface of an n-type silicon carbide substrate 1. The active portion 21 is a region that carries a current that flows when the substrate is on. Specifically, the n-type silicon carbide substrate 1 has an n-type MOS gate (insulated gate made of metal-oxide film-semiconductor) structure on the front surface of the n-type silicon carbide substrate 1, which is a drain layer. - n-type drift layer 2 - The n-type silicon carbide substrate 1 has a front surface (n - On the side of the n-type drift layer 2, a p-type base layer 6 and + Type source region 7, p + A MOS gate structure consisting of a contact region 8, a gate insulating film 9 and a gate electrode 10 is provided.

[0006] In order to reduce the electric field applied to the gate insulating film 9 at the bottom of the gate trench 18 and the contact trench 19, + A mold base region 3 is provided in the mesa portion. A contact trench 19 is provided in the mesa portion to a depth approximately equal to that of the gate trench 18.

[0007] n + The n-type source region 7 is selectively provided inside the p-type base layer 6 between the adjacent gate trench 18 and contact trench 19. + The n-type source region 7 and the p-type base layer 6 exposed on the inner wall of the contact trench 19 are exposed through a contact hole penetrating the interlayer insulating film 11 in the depth direction. + Type source region 7 and p + A source electrode pad 14 is provided as a front surface electrode through a contact hole so as to contact a source electrode 13 that is in ohmic contact with the type contact region 8 and a Schottky electrode 15 embedded in a contact trench 19. + The n-type source region 7 is in contact with the back surface (n - A drain electrode (not shown) is provided as a back surface electrode on the surface opposite to the drift layer 2.

[0008] The gate pad portion 20 is a portion where a gate electrode pad 17 electrically connected to the gate electrode 10 is provided, and does not have element structures such as a gate trench 18 and a contact trench 19. As shown in Fig. 13, when the device is on, a current S flows from the drain electrode side to the source electrode 13 side of the active portion 21.

[0009] In the case of an SBD built into a trench MOSFET with this structure, the drift region can be shared with the MOSFET, so the chip area can be smaller than the combined chip area of ​​the external SBD and MOSFET. In addition, in the case of an external SBD, the VF (forward voltage) of the SBD is the same as the p-type base layer 6 of the MOSFET and the n - When the built-in voltage of the body diode formed between the gate electrode and the gate drift layer 2 is exceeded, the body diode turns on and the bipolar action of the body diode causes the characteristics to change over time (deterioration with age), reducing reliability.

[0010] On the other hand, with an internal SBD, even if the voltage at the drain of the MOSFET, which is equivalent to the cathode of an external SBD, exceeds the built-in voltage of the body diode, the potential difference near the pn junction that constitutes the body diode is low because the voltage is maintained in the drift region, making it difficult for current to flow through the body diode. As a result, even large currents do not flow through the body diode, making it less likely to deteriorate due to bipolar operation.

[0011] Also, a semiconductor device is known in which, in order to prevent destruction of the gate pad portion, the element portion has a first trench structure having a first buried layer and a plurality of first protective trenches formed deeper than the gate trenches, and the gate pad portion has a second trench structure having a second buried layer made of a metal layer forming a Schottky contact and electrically connected to the source electrode layer (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0012] [Patent Document 1] International Publication No. 2016 / 006696 Summary of the Invention [Problem to be solved by the invention]

[0013] Here, in the gate pad section 20, a p-type region (p + The p-type base region 3 and the p-type base layer 6 are formed. These p-type regions have a larger area than the p-type region of the active portion 21, so a lateral voltage drop occurs due to spreading resistance. - When a pn junction consisting of a type drift layer is forward biased, minority carriers (holes) are injected, and even a relatively small current density flows through the body diode in the gate pad section 20. As such, the body diode in the gate pad section 20 has a problem in that its characteristics change over time due to bipolar operation, decreasing its reliability.

[0014] In order to solve the above-mentioned problems, the present invention aims to provide a semiconductor device that can suppress the lateral voltage drop in the gate pad portion, suppress the injection of minority carriers (holes), and prevent the body diode from turning on even with a large current. [Means for solving the problem]

[0015] In order to solve the above problems and achieve the object of the present invention, the semiconductor device according to the present invention has the following features. The semiconductor device includes a first trench and a second trench extending toward a gate electrode pad in a top view, a source electrode portion at least a part of which is provided above the first trench and the second trench, a gate pad portion including a gate electrode pad, a gate electrode including a first buried portion embedded in the first trench and a protruding portion provided to protrude above the first trench, and a conductive layer including a second buried portion embedded in the second trench. The source electrode portion includes a first source electrode connection portion provided between the protruding portion and the gate electrode pad in a top view, and a second source electrode connection portion sandwiching the protruding portion between the first source electrode connection portion and the gate electrode pad in a top view. The second trench includes a first source connection trench in which the conductive layer is connected to the first source electrode connection portion.

[0016] In addition, in the semiconductor device according to the present invention, the first source connection trench extends below the gate electrode pad.

[0017] In addition, the semiconductor device of the present invention is characterized in that, in the above-mentioned invention, the second trench includes a second source connection trench in which the conductive layer is connected to the second source electrode connection portion.

[0018] In addition, the semiconductor device of the present invention is characterized in that, in the above-mentioned invention, at least a portion of the first source connection trench is arranged opposite the first trench in the direction of the gate electrode pad when viewed from above.

[0019] In addition, in the semiconductor device according to the present invention, in the above-mentioned invention, the protruding portion has a portion extending in a second direction perpendicular to the gate electrode pad direction in a top view.

[0020] In addition, the semiconductor device of the present invention is characterized in that, in the above-mentioned invention, the protrusion is provided from above the first trench toward the outside of the first buried portion in the direction of the gate electrode pad.

[0021] In addition, the semiconductor device of the present invention is characterized in that, in the above-mentioned invention, the second source connection trench is arranged between adjacent first trenches, parallel to the first trenches and spaced apart from the first trenches.

[0022] Moreover, the semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the semiconductor device includes a silicon carbide semiconductor base, the first embedded portion of the gate electrode is in contact with the silicon carbide semiconductor base via a gate insulating film, and the second embedded portion of the conductive layer is in contact with at least a part of the silicon carbide semiconductor base.

[0023] Moreover, in the semiconductor device according to the present invention, in the above-mentioned invention, the silicon carbide semiconductor base includes a drift layer of a first conductivity type, a base layer of a second conductivity type provided above the drift layer, a high-concentration contact region of the second conductivity type having a higher impurity concentration than the base layer and selectively provided on the surface side of the base layer, and a high-concentration source region of the first conductivity type having a higher impurity concentration than the drift layer and selectively provided on the surface side of the base layer.

[0024] In addition, the semiconductor device of the present invention is characterized in that, in the above-mentioned invention, the second buried portion buried inside the second source connection trench is in contact with at least a portion of the high-concentration contact region.

[0025] Moreover, in the semiconductor device according to the present invention, in the above-described invention, the silicon carbide semiconductor substrate includes a high concentration region of a first conductivity type on a surface side of the base layer, the high concentration region having an impurity concentration higher than that of the drift layer, and selectively provided under the first source electrode connection portion.

[0026] In addition, the semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the silicon carbide semiconductor substrate includes an under-trench base layer of a second conductivity type provided under the first trench or the second trench.

[0027] In addition, the semiconductor device of the present invention is characterized in that, in the above-mentioned invention, the source electrode portion includes a source electrode pad, the first source electrode connection portion is a source contact portion that electrically connects the conductive layer of the first source connection trench to the source electrode portion, and the second source electrode connection portion is a source electrode that electrically connects the conductive layer of the second source connection trench to the source electrode portion. Effect of the Invention

[0028] The semiconductor device according to the present invention has the effect of suppressing the lateral voltage drop in the gate pad portion, suppressing the injection of minority carriers (holes), and preventing the body diode from turning on even with a large current. [Brief description of the drawings]

[0029] [Figure 1] 4 is a cross-sectional view taken along the line YY' of FIG. 3 showing the configuration of the silicon carbide semiconductor device in accordance with the first embodiment. [Diagram 2] 4 is a cross-sectional view taken along the line XX' of FIG. 3 showing the configuration of the silicon carbide semiconductor device in accordance with the first embodiment. [Diagram 3] 1 is a top view showing a configuration of a silicon carbide semiconductor device in accordance with a first embodiment. [Figure 4] 4 is an enlarged view of a portion A in FIG. 3 showing the configuration of the silicon carbide semiconductor device in accordance with the first embodiment. [Diagram 5] 4 is a diagram showing current flows in the YY' cross section of the silicon carbide semiconductor device according to the first embodiment of the present invention in FIG. 3. [Figure 6] 1 is a cross-sectional view (part 1) illustrating a schematic state during the manufacture of the silicon carbide semiconductor device according to the first embodiment. FIG. [Figure 7]5 is a cross-sectional view (part 2) illustrating a schematic diagram of a silicon carbide semiconductor device in the middle of its manufacture according to the first embodiment. FIG. [Figure 8] 5A to 5C are cross sectional views (part 3) illustrating schematic configurations of the silicon carbide semiconductor device in the course of manufacturing the silicon carbide semiconductor device according to the first embodiment. [Figure 9] 4 is a cross sectional view (part 4) illustrating a schematic diagram during the manufacture of the silicon carbide semiconductor device according to the first embodiment. FIG. [Figure 10] 5 is a cross sectional view (part 5) illustrating a schematic diagram during the manufacture of the silicon carbide semiconductor device according to the first embodiment. FIG. [Figure 11] 11 is a cross-sectional view showing a configuration of a gate pad portion of a silicon carbide semiconductor device according to a second embodiment. FIG. [Figure 12] 13 is a cross-sectional view showing another configuration of the gate pad portion of the silicon carbide semiconductor device according to the second embodiment. FIG. [Figure 13] FIG. 1 is a cross-sectional view showing the configuration of a conventional SBD-embedded trench-type silicon carbide semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] A preferred embodiment of the semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, in layers and regions marked with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - marked with n or p mean that the impurity concentration is higher and lower than that of layers and regions not marked with them, respectively. When the notations of n and p including + and - are the same, it indicates that the concentrations are close, but does not necessarily mean that the concentrations are the same. In the following description of the embodiments and the accompanying drawings, similar configurations are marked with the same symbols, and duplicated explanations will be omitted.

[0031] (Embodiment 1) The semiconductor device according to the present invention is configured using a wide band gap semiconductor. In the first embodiment, a silicon carbide semiconductor device manufactured using, for example, silicon carbide (SiC) as a wide band gap semiconductor will be described by taking a MOSFET as an example. Fig. 1 is a Y-Y' cross-sectional view of Fig. 3 showing the configuration of the silicon carbide semiconductor device according to the first embodiment. Fig. 2 is an X-X' cross-sectional view of Fig. 3 showing the configuration of the silicon carbide semiconductor device according to the first embodiment. Fig. 3 is a top view showing the configuration of the silicon carbide semiconductor device according to the first embodiment.

[0032] The semiconductor device according to the first embodiment shown in Fig. 1 is a trench-type SiC-MOSFET having a gate trench (first trench) 18 and a contact trench (second trench) 19 on the front surface side of a semiconductor substrate (semiconductor chip) in an active portion 21. The active portion 21 is a region through which a current flows in an on-state. The gate trench 18 is a trench in which a gate electrode 10 is embedded via a gate insulating film 9. The contact trench 19 is a trench in which an SBD having a Schottky junction by a conductive layer 15 described later is embedded.

[0033] Specifically, as shown in FIGS. 1 and 2, the silicon carbide semiconductor device according to the embodiment has an n-type silicon carbide substrate (semiconductor substrate of a first conductivity type) 1 having a first main surface (front surface), for example, a (0001) surface (Si surface) and an n-type silicon carbide substrate (semiconductor substrate of a first conductivity type) 2 having a first main surface (front surface), for example, a (0001) surface (Si surface). - A first conductivity type drift layer (first semiconductor layer) 2 is deposited on the n-type semiconductor layer 1 .

[0034] The n-type silicon carbide substrate 1 is, for example, a silicon carbide single crystal substrate doped with nitrogen (N). - The n-type drift layer 2 is a low-concentration n-type drift layer that has a lower impurity concentration than the n-type silicon carbide substrate 1 and is doped with, for example, nitrogen. - An n-type high concentration region 5 is formed on the surface of the n-type drift layer 2 opposite to the n-type silicon carbide substrate 1. The n-type high concentration region 5 has a lower n concentration than the n-type silicon carbide substrate 1. -The n-type silicon carbide substrate 1 and the n-type high-concentration drift layer 2 are doped with, for example, nitrogen at a higher impurity concentration than the n-type drift layer 2. - The combination of the p-type drift layer 2 and a p-type base layer (a second semiconductor layer of a second conductivity type) 6 described below constitutes a silicon carbide semiconductor substrate.

[0035] A back electrode (not shown) is provided on the second main surface (back surface, that is, the back surface of the silicon carbide semiconductor base) of the n-type silicon carbide substrate 1. The back surface electrode constitutes a drain electrode.

[0036] A trench structure is formed on the first main surface side (p-type base layer 6 side) of the silicon carbide semiconductor substrate. Specifically, the gate trench 18 and the contact trench 19 penetrate the p-type base layer 6 from the surface of the p-type base layer 6 opposite to the n-type silicon carbide substrate 1 side (the first main surface side of the silicon carbide semiconductor substrate). - The gate insulating film 9 is formed on the bottom and side walls of the gate trench 18 along the inner wall of the gate trench 18, and the gate electrode 10 is formed on the inside of the gate insulating film 9 in the gate trench 18. The gate electrode 10 is formed by the gate insulating film 9. - The gate electrode 10 is insulated from the p-type drift layer 2 and the p-type base layer 6. A part of the gate electrode 10 may protrude from above the gate trench 18 (the source electrode pad 14 side) towards the gate electrode pad 17 side.

[0037] In the active portion 21, the contact trenches 19 are arranged in a striped planar layout extending in the X-X' direction between adjacent gate trenches 18, parallel to the gate trenches 18 and spaced apart from the gate trenches 18. For example, when contact trenches 19 are arranged in all mesa portions, the gate trenches 18 and the contact trenches 19 are arranged alternately and repeatedly spaced apart from each other in the Y-Y' direction perpendicular to the X-X' direction. The contact trenches 19 penetrate the p-type base layer 6 from the first main surface side of the silicon carbide semiconductor substrate to form n - The contact trench 19 reaches the type drift layer 2. The depth of the contact trench 19 is approximately equal to the depth of the gate trench 18.

[0038] n - The surface layer of the n-type drift layer 2 on the side opposite to the n-type silicon carbide substrate 1 (the first main surface side of the silicon carbide semiconductor base) is + A mold base region 3 is optionally provided. + The base region 3 is formed under the gate trench 18 and the contact trench 19. + The width of the base region 3 is wider than the width of the gate trench 18 and the contact trench 19. + The base region 3 is doped with aluminum, for example. + The p-type base region 3 is provided apart from the p-type base layer 6. + The high-concentration n-type drift layer 5 is a p + It may be formed to a position deeper than the mold base region 3 .

[0039] n - A p-type base layer 6 is provided on the first main surface side of the base body of the drift layer 2. Inside the p-type base layer 6, an n-type + A p-type source region (a first semiconductor region of a first conductivity type) 7 and + A contact region 8 is optionally provided. + The n-type source region 7 is in contact with the gate trench 18. + Type source region 7 and p + The mold contact regions 8 abut each other.

[0040] Although FIG. 1 illustrates only two trench MOS structures, more trench MOS gate (insulated gate made of metal-oxide-semiconductor) structures may be arranged in parallel.

[0041] The interlayer insulating film 11 is provided on the entire first main surface side of the silicon carbide semiconductor substrate so as to cover the gate electrode 10 embedded in the gate trench 18. In the gate pad portion 20, the interlayer insulating film 11 is provided so as to cover the conductive layer 15 embedded in the contact trench 19. The source electrode (first electrode) 13 is connected to the n-type semiconductor layer 11 through a contact hole opened in the interlayer insulating film 11. + Type source region 7 and p + The source electrode 13 is in contact with the contact region 8. The source electrode 13 is electrically insulated from the gate electrode 10 by an interlayer insulating film 11. A source electrode pad 14 is provided on the source electrode 13. A barrier metal 12 made of a single layer or multilayer of Ti, TiN, or the like is provided between the source electrode 13 and the interlayer insulating film 11 to prevent diffusion of metal atoms from the source electrode 13 to the gate electrode 10 side.

[0042] A conductive layer 15 made of, for example, Ti silicide (TiSi) is provided along the front surface of the silicon carbide semiconductor substrate and the inner wall of the contact trench 19. The conductive layer 15 may be configured by laminating electrodes made of different materials. The conductive layer 15 functions as a front surface electrode together with the source electrode 13. The conductive layer 15 is p-type, and extends from the front surface of the silicon carbide semiconductor substrate to the side wall of the contact trench 19. + It contacts the mold contact region 8 .

[0043] The conductive layer 15 is p-type over the entire surface from the bottom of the contact trench 19 to the corner. + The conductive layer 15 contacts the n-type high concentration region 5 on the side wall of the contact trench 19, and forms a Schottky junction with the n-type high concentration region 5. This forms a Schottky barrier diode consisting of the conductive layer 15 in the contact trench 19 and the n-type high concentration region 5. If the n-type high concentration region 5 is not provided, the side wall of the contact trench 19 will be in contact with the n-type high concentration region 5. - A Schottky junction is formed between the n-type drift layer 2 and the conductive layer 15 in the contact trench 19. - A Schottky barrier diode is formed by the n-type drift layer 2.

[0044] A gate electrode pad 17 electrically connected to the gate electrode 10 is provided in the gate pad section 20. The gate electrode pad 17 is electrically insulated from the conductive layer 15 by the interlayer insulating film 11.

[0045] The contact trench 19 is also provided in the gate pad portion 20. In the gate pad portion 20, the conductive layer 15 is connected to the source electrode 13 in the peripheral portion of the gate pad portion 20. The peripheral portion of the gate pad portion 20 refers to the boundary portion with the active portion 21 of the gate pad portion 20. In addition, for example, a portion B (see FIG. 3) partially lacking the gate electrode 10 may be provided in the central portion of the gate pad portion 20, and a source contact portion 24 that connects the anode electrode of the SBD under the gate electrode pad 17 and the source electrode 13 may be provided inside the portion B.

[0046] 4 is an enlarged view of a portion A in FIG. 3 showing the configuration of the silicon carbide semiconductor device according to the first embodiment. As shown in FIG. 4, an n-type silicon carbide substrate 1 is provided under source contact portion 24 (on the n-type silicon carbide substrate 1 side) for ohmic contact. + It is preferable to provide a mold region 25. In addition, in FIG. + The interval W1 between the base regions 3 is set to a value corresponding to the p + A p-type base region 3 and a p-type layer covering the bottom surface of the gate trench 18 + The width of the gate pad portion 20 is the same as the width W2 between the contact trenches 19 and the type base region 3. However, for example, the width W1 may be narrower than the width W2 by narrowing the width between the contact trenches 19 in the gate pad portion 20. This is because the active portion 21 has a MOS structure, and narrowing the width W2 would narrow the region through which current passes and increase the on-resistance, so the width W2 cannot be narrowed. On the other hand, in the gate pad portion 20, when the SBD is conductive, the pn junction is forward biased, so the depletion layer shrinks, allowing the width W2 to be narrowed.

[0047] Fig. 5 is a diagram showing a current flow when a pn junction is forward biased in the Y-Y' cross section of the silicon carbide semiconductor device according to the first embodiment in Fig. 3. By providing an SBD in the gate pad portion 20 similarly to the active portion 21, an SBD current S1 can be caused to flow also under the gate pad portion 20 as shown in Fig. 5, and this current can suppress the lateral voltage drop under the gate pad portion 20 and suppress the injection of minority carriers (holes).

[0048] (Method of Manufacturing Silicon Carbide Semiconductor Device According to First Embodiment) Next, there will be described a method for manufacturing the silicon carbide semiconductor device according to the first embodiment. Figures 6 to 10 are cross-sectional views that typically show states during the manufacturing process of the silicon carbide semiconductor device according to the first embodiment.

[0049] First, an n-type silicon carbide substrate 1 made of n-type silicon carbide is prepared. Then, an n-type silicon carbide substrate made of silicon carbide is formed on a first main surface of the n-type silicon carbide substrate 1 while being doped with n-type impurities, for example, nitrogen atoms. - The semiconductor layer 2 is then epitaxially grown. The state up to this point is shown in FIG.

[0050] Next, n - An ion implantation mask having predetermined openings is formed on the surface of the type drift layer 2 by photolithography, for example, using an oxide film. Then, p-type impurities such as aluminum are implanted into the openings of the oxide film to form p + A mold base region 3 is formed.

[0051] Next, n - A lower n-type high concentration region, which is a part of n-type high concentration region 5, is formed by doping an n-type impurity such as nitrogen on the surface of drift layer 2. Next, an n-type epitaxial layer is formed.

[0052] Next, a part of the ion implantation mask is removed, and n-type impurities such as nitrogen are ion-implanted into the opening. -An upper n-type high concentration region is provided in part of the surface region of drift layer 2. This upper n-type high concentration region and the lower n-type high concentration region are formed so that at least a part of them are in contact with each other to form n-type high concentration region 5. However, this n-type high concentration region 5 may or may not be formed over the entire surface of the substrate. The state up to this point is shown in Figure 7.

[0053] Next, n - A p-type base layer 6 doped with p-type impurities such as aluminum is formed by epitaxial growth on the surface of the n-type drift layer 2. Next, the p-type base layer 6 and the exposed n-type - An ion implantation mask having a predetermined opening is formed on the surface of the p-type drift layer 2 by photolithography, for example, using an oxide film. An n-type impurity such as phosphorus (P) is ion-implanted into this opening, so that n-type impurities such as phosphorus (P) are implanted into a part of the surface of the p-type base layer 6. + The n-type source region 7 is formed. + The impurity concentration of the n-type source region 7 is set to be higher than the impurity concentration of the n-type high concentration region 5. + The ion implantation mask used for forming the p-type source region 7 is removed, and a new ion implantation mask having a predetermined opening is formed in the same manner, and p-type impurities such as aluminum are ion-implanted into a portion of the surface of the p-type base layer 6 to form a p + A contact region 8 is provided. + The impurity concentration of the contact region 8 is set to be higher than the impurity concentration of the p-type base layer 6. The state up to this point is shown in Fig. 8. Note that the p-type base layer 6 may be formed by ion implantation of p-type impurities such as aluminum, instead of epitaxial growth.

[0054] Next, heat treatment (annealing) is performed in an inert gas atmosphere at about 1700°C, and p + Type base region 3, n + Type source region 7, p + An activation process is performed on the mold contact region 8. As described above, the ion implantation regions may be activated all at once by a single heat treatment, or the heat treatment may be performed each time an ion implantation is performed.

[0055] Next, a trench forming mask having a predetermined opening is formed by photolithography on the surface of the p-type base layer 6. Next, the p-type base layer 6 is penetrated by dry etching to form an n - A gate trench 18 and a contact trench 19 are formed so as to reach the n-type drift layer 2. The bottoms of the gate trench 18 and the contact trench 19 are n-type. - The p-type drift layer 2 + The trench 18 may reach the mold base region 3. The gate trench 18 is formed in the active portion 21, and the contact trench 19 is formed in the active portion 21 and the gate pad portion 20. Next, the mask for forming the trench is removed. The state up to this point is shown in FIG.

[0056] Next, annealing is performed to round the corners of the bottoms and openings of the gate trench 18 and the contact trench 19. Before annealing, isotropic etching may be performed to remove damage to the gate trench 18 and the contact trench 19.

[0057] Next, n + Type source region 7 and p + A gate insulating film 9 is formed along the surface of the contact region 8 and the bottom and sidewalls of the gate trench 18. This gate insulating film 9 may be formed by thermal oxidation through heat treatment at a temperature of about 1000° C. in an oxygen atmosphere. Alternatively, this gate insulating film 9 may be formed by a method of deposition through a chemical reaction such as high temperature oxidation (High Temperature Oxide: HTO).

[0058] Next, a polycrystalline silicon layer doped with, for example, phosphorus atoms is provided on the gate insulating film 9. This polycrystalline silicon layer may be formed so as to fill the inside of the gate trench 18. This polycrystalline silicon layer is patterned by photolithography and left inside the gate trench 18 to form the gate electrode 10.

[0059] Next, n + Type source region 7 and p +A conductive layer 15 is formed along the surface of the mold contact region 8 and the bottom and sidewalls of the contact trench 19. This conductive layer 15 may be made of Ti silicide.

[0060] Next, for example, phosphorus glass is deposited to a thickness of about 1 μm to cover the gate insulating film 9, the gate electrode 10, and the conductive layer 15, forming an interlayer insulating film 11. Next, a barrier metal 12 made of titanium (Ti) or titanium nitride (TiN) is formed to cover the interlayer insulating film 11. The interlayer insulating film 11 and the gate insulating film 9 are patterned by photolithography. + Type source region 7 and p + A contact hole is formed exposing the mold contact region 8. Thereafter, a heat treatment (reflow) is performed to flatten the interlayer insulating film 11.

[0061] Next, a conductive film such as nickel (Ni) that will become the source electrode 13 is provided in the contact hole and on the interlayer insulating film 11. This conductive film is patterned by photolithography to leave the source electrode 13 only in the contact hole. The state up to this point is shown in Figure 10.

[0062] Next, a back electrode (not shown) made of nickel or the like is provided on the second main surface of the n-type silicon carbide semiconductor substrate 1. After that, a heat treatment is performed in an inert gas atmosphere at about 1000° C. to form the n + Type source region 7, p + A source electrode and a back surface electrode are formed in ohmic junction with the n-type contact region and the n-type silicon carbide semiconductor substrate.

[0063] Next, n + An aluminum film having a thickness of about 5 μm is deposited on the first main surface of silicon carbide semiconductor substrate 1 by sputtering, and the aluminum is removed by photolithography so as to cover source electrode 13 and interlayer insulating film 11 of active portion 21, to form source electrode pad 15. Next, a gate electrode pad 17 is formed by a similar method so as to cover interlayer insulating film 11 of gate pad portion 20.

[0064] Next, a drain electrode pad (not shown) is formed on the surface of the back electrode by sequentially stacking, for example, titanium (Ti), nickel and gold (Au). In this manner, the silicon carbide semiconductor device shown in FIGS. 1 and 2 is completed.

[0065] As described above, according to the silicon carbide semiconductor device of the first embodiment, the SBD is provided in the gate pad section as well as in the active section. This allows the SBD current to flow even under the gate pad section, suppresses the lateral voltage drop under the gate pad section, and suppresses the injection of minority carriers (holes). This prevents the body diode from turning on even with a large current.

[0066] (Embodiment 2) Next, the structure of a silicon carbide semiconductor device according to the second embodiment will be described. FIG. 11 is a cross-sectional view showing the configuration of a gate pad portion of the silicon carbide semiconductor device according to the second embodiment. FIG. 12 is a cross-sectional view showing another configuration of the gate pad portion of the silicon carbide semiconductor device according to the second embodiment. The structure of active portion 21 of the silicon carbide semiconductor device according to the second embodiment is similar to that of the first embodiment, and therefore will not be described (see FIG. 1). The silicon carbide semiconductor device according to the second embodiment differs from the silicon carbide semiconductor device according to the first embodiment in that no contact trench 19 is provided in gate pad portion 20, and the p-type region (p + The point is that the p-type base region 3', the p-type base layer 6') are floating.

[0067] The p-type region of the gate pad portion 20 is a p-type region of the source potential (p + The p-type base region 3 is separated by a predetermined distance W3 by the p-type base layer 6 and the n-type high concentration region 5. In this way, by floating the p-type region of the gate pad portion 20, + Type base region 3' and n - This makes it possible to prevent continuous injection of minority carriers into the pn junction formed by the type drift layer 2 when a forward bias is applied.

[0068] In order to prevent a decrease in breakdown voltage when a pn junction is reverse biased due to floating, it is preferable to provide a predetermined distance W3 between the p-type region of the source potential and the p-type region of the gate pad section 20. + It is preferable that W3 is equal to or smaller than the interval W2 (see FIG. 1) between the base regions 3. By making W3 small, the p-type + The depletion layer extending from the base region 3 is easily + When the base region 3' is reached, a punch-through state occurs. + The potential of the base region 3' is p + As we approach the base region 3, p + Since the depletion layer also extends from the n-type base region 3' to the n-type drift region, the breakdown voltage does not decrease.

[0069] Next, a method for manufacturing a silicon carbide semiconductor device according to the second embodiment will be described. The method for manufacturing the active portion 21 is omitted since it is similar to the method for manufacturing a silicon carbide semiconductor device according to the first embodiment. - After forming the n-type drift layer 2, the p + Type base region 3 and p + The mold base region 3' is formed at a predetermined distance W3.

[0070] Next, after forming the p-type base layer 6 by epitaxial growth, the gate pad portion 20 and its periphery are etched in an etching process to selectively remove the p-type base layer 6. The p-type base layer 6 may be removed from the entire gate pad portion 20 as shown in FIG. 11, or only from the periphery of the gate pad portion 20 as shown in FIG. 12. The OUT etching process is a process for removing the p-type base layer 6 from the chip periphery (voltage-resistant structure portion) since the presence of the p-type base layer 6 makes it impossible to form the voltage-resistant structure portion. When the p-type base layer 6 is formed by ion implantation, the p-type base layer 6 may be formed by separating it by a predetermined distance W3 using a mask. The p + The type base region 3' may be formed so as to be connected to the p-base layer 6' as in FIG. 11 and FIG. 12, or may be formed separately from the p-base layer 6' like the active portion.

[0071] As described above, according to the second embodiment, the p-type region of the gate pad is separated from the p-type region of the source potential. This causes the p-type region of the gate pad to be floating, and the p-type region and the n - This prevents continuous minority carrier injection into the pn junction consisting of the type drift layer when forward biased, which prevents the body diode from turning on even with a large current.

[0072] In addition, in the embodiments of the present invention, a trench-type MOSFET has been described as an example, but the present invention is not limited to this and can be applied to semiconductor devices of various configurations, such as MOS-type semiconductor devices such as planar gate MOSFETs and IGBTs. In addition, in the above-mentioned embodiments, the case where silicon carbide is used as the wide band gap semiconductor has been described as an example, but the same effect can be obtained when a wide band gap semiconductor other than silicon carbide, such as gallium nitride (GaN), is used. In addition, in each embodiment, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is similarly valid even if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial Applicability]

[0073] INDUSTRIAL APPLICABILITY As described above, the semiconductor device according to the present invention is useful for power semiconductor devices used in power conversion devices and power supply devices for various industrial machines, and is particularly suitable for semiconductor devices having a trench gate structure. [Explanation of symbols]

[0074] 1. n-type silicon carbide substrate 2n - Mold drift layer 3, 3' p + Type-based regions 5 n-type high concentration region 6, 6' p-type base layer 7 n + Type Source Area 8 p + Mold Contact Area 9 Gate insulating film 10 Gate electrode 11 Interlayer insulating film 12 Barrier metal 13 Source electrode 14 Source electrode pad 15 Conductive layer 16 Field oxide 17 Gate electrode pad 18 Gate trench 19 Contact Trench 20 Gate pad section 21 Active part 24 Source Contact Part 25 n + type area

Claims

1. a first trench and a second trench extending toward a gate electrode pad in a top view; a source electrode portion, at least a portion of which is provided above the first trench and the second trench; a gate pad portion including a gate electrode pad; a gate electrode including a first buried portion buried in the first trench and a protruding portion protruding above the first trench; a conductive layer including a second buried portion buried in the second trench; Equipped with the source electrode portion includes a first source electrode connection portion provided between the protruding portion and the gate electrode pad in a top view, and a second source electrode connection portion sandwiching the protruding portion between the first source electrode connection portion and a second source electrode connection portion in a top view, The second trench includes a first source connection trench in which the conductive layer connects to the first source electrode connection portion.

2. 2. The semiconductor device according to claim 1, wherein the first source connection trench extends beneath the gate electrode pad.

3. 3. The semiconductor device according to claim 1, wherein the second trench includes a second source connection trench in which the conductive layer is connected to the second source electrode connection portion.

4. 4. The semiconductor device according to claim 3, wherein at least a portion of the first source connection trench is disposed opposite to the first trench in a direction toward the gate electrode pad when viewed from above.

5. 5. The semiconductor device according to claim 3, wherein the protruding portion has a portion extending in a second direction perpendicular to a direction of the gate electrode pad in a top view.

6. 6. The semiconductor device according to claim 3, wherein the protruding portion is provided from above the first trench toward an outside of the first buried portion in a direction toward the gate electrode pad.

7. 7. The semiconductor device according to claim 3, wherein the second source connection trench is disposed between adjacent ones of the first trenches, parallel to the first trenches and spaced apart from the first trenches.

8. The semiconductor device includes a silicon carbide semiconductor substrate, the first embedded portion of the gate electrode is in contact with the silicon carbide semiconductor base via a gate insulating film, 8. The semiconductor device according to claim 3, wherein the second embedded portion of the conductive layer is in contact with at least a portion of the silicon carbide semiconductor base.

9. The silicon carbide semiconductor substrate is A drift layer of a first conductivity type; a second conductivity type base layer provided above the drift layer; a high-concentration contact region of a second conductivity type having an impurity concentration higher than that of the base layer, the high-concentration contact region being selectively provided on a surface side of the base layer; a first conductivity type high concentration source region having an impurity concentration higher than that of the drift layer, the high concentration source region being selectively provided on a surface side of the base layer; 9. The semiconductor device according to claim 8, further comprising:

10. 10. The semiconductor device according to claim 9, wherein the second buried portion buried inside the second source connection trench is in contact with at least a part of the high concentration contact region.

11. 11. The semiconductor device according to claim 9, wherein the silicon carbide semiconductor substrate includes a first conductivity type high concentration region on a surface side of the base layer, the high concentration region having a higher impurity concentration than the drift layer selectively provided under the first source electrode connection portion.

12. 12. The semiconductor device according to claim 8, wherein the silicon carbide semiconductor substrate includes an under-trench base layer of a second conductivity type provided under the first trench or the second trench.

13. the source electrode portion includes a source electrode pad, the first source electrode connection portion is a source contact portion that electrically connects the conductive layer of the first source connection trench to the source electrode portion; 13. The semiconductor device according to claim 3, wherein the second source electrode connection portion is a source electrode that electrically connects the conductive layer of the second source connection trench to the source electrode portion.

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