Semiconductor Device

Abstract

To provide a semiconductor device whose on resistance can be reduced.SOLUTION: A vertical semiconductor device including a wide-gap compound semiconductor substrate includes a drift layer. The semiconductor device includes a JFET region provided on the drift layer and exposed on an upper surface. The semiconductor device includes a body region provided on the drift layer, being adjacent to the JFET region, and exposed on an upper surface The semiconductor device includes a source region provided apart from the drift layer and the JFET region by the body region, and exposed on an upper surface. The semiconductor device includes a gate electrode structure. The gate electrode structure is disposed on the upper surface of the JFET region and on the upper surface of the body region in a part separating the JFET region and the source region. Compression stress applied by the gate electrode structure on the upper surface of the JFET region is greater than compression stress applied by the gate electrode structure on the upper surface of the body region.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a vertical semiconductor device having a semiconductor substrate made of a wide-gap compound semiconductor. [Background technology]

[0002] As shown in the example of Patent Document 1, a planar gate vertical semiconductor device using a wide gap compound semiconductor such as GaN is known. In such a semiconductor device, an N-type region (also called a JFET region) is formed on an N-type drift layer. The JFET region is exposed on the upper surface of a semiconductor substrate. A P-type body region is disposed on the drift layer at a position adjacent to the JFET region and exposed on the upper surface of the semiconductor substrate. An N-type source region is disposed at a position exposed on the upper surface of the semiconductor substrate. The source region is separated from the drift layer and the JFET region by the body region. A gate electrode structure is disposed on the upper surface of the JFET region and on the upper surface of the body region at a portion separating the JFET region from the source region.

[0003] A channel is formed on the top surface of the body region facing the gate electrode structure. The current path of the semiconductor device runs from the source region through the channel, JFET region, and drift layer to the drain electrode on the back surface. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 4727426 Summary of the Invention [Problem to be solved by the invention]

[0005] In order to increase the breakdown voltage of a semiconductor device, it is necessary to lower the impurity concentration in the JFET region in order to make it easier to extend the depletion layer, but this increases the resistance of the JFET region and increases the on-resistance of the semiconductor device. [Means for solving the problem]

[0006] This specification discloses a vertical semiconductor device having a semiconductor substrate made of a wide-gap compound semiconductor. The semiconductor device includes a drift layer of a first conductivity type. The semiconductor device includes a JFET region of the first conductivity type that is provided on the drift layer and is disposed at a position exposed on the upper surface of the semiconductor substrate. The semiconductor device includes a body region of a second conductivity type that is provided on the drift layer, adjacent to the JFET region, and disposed at a position exposed on the upper surface of the semiconductor substrate. The semiconductor device includes a source region of the first conductivity type that is separated from the drift layer and the JFET region by the body region and is disposed at a position exposed on the upper surface of the semiconductor substrate. The semiconductor device includes a gate electrode structure having a structure in which a gate insulating film and a gate electrode are laminated in this order. The gate electrode structure is disposed on the upper surface of the JFET region and is disposed on the upper surface of the body region in a portion separating the JFET region from the source region. A compressive stress applied to the upper surface of the JFET region by the gate electrode structure is greater than a compressive stress applied to the upper surface of the body region by the gate electrode structure.

[0007] When compressive stress is applied to the inside of a semiconductor substrate of a wide-gap compound semiconductor, the lattice constant becomes smaller and the band gap becomes narrower. Therefore, a phenomenon occurs in which the impurity level rises relatively and the conduction electrons increase. In the semiconductor device of this specification, the gate electrode structure can apply compressive stress to the upper surface of the JFET region. Since the conduction electrons in the JFET region can be increased, an increase in the on-resistance of the semiconductor device can be suppressed. In addition, the compressive stress applied to the upper surface of the body region in which the channel is formed is smaller than the compressive stress applied to the upper surface of the JFET region. This can suppress the P-type from being compensated in the channel. It is possible to suppress the occurrence of a decrease in threshold voltage and an increase in source-drain leakage current. [Brief description of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view of a main part of a semiconductor device 1 according to a first embodiment. [Diagram 2] FIG. 2 is an enlarged view of the gate insulating film 17 and its vicinity. [Diagram 3] FIG. 11 is a cross-sectional view of a main part of a semiconductor device 201 according to a second embodiment. [Figure 4] FIG. 11 is a cross-sectional view of a main part of a semiconductor device 301 according to a third embodiment. [Diagram 5] FIG. 11 is a cross-sectional view of a main part of a semiconductor device 401 according to a fourth embodiment. [Figure 6] FIG. 11 is a cross-sectional view of a main part of a semiconductor device 501 according to a fifth embodiment. [Figure 7] FIG. 13 is a cross-sectional view of a main part of a semiconductor device 601 according to a sixth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The technical elements disclosed in this specification are listed below. Note that each of the technical elements below is useful independently.

[0010] In an example semiconductor device disclosed in the present specification, the gate insulating film may include a first gate insulating film disposed on an upper surface of the JFET region. The gate insulating film may include a second gate insulating film disposed on an upper surface of the body region in a portion separating the JFET region from the source region. The first gate insulating film and the second gate insulating film may have a specific stress capable of generating a compressive stress on the upper surface of the JFET region and the upper surface of the body region. The magnitude of the specific stress may be larger in the first gate insulating film than in the second gate insulating film.

[0011] According to this configuration, the compressive stress applied to the upper surface of the JFET region can be made larger than the compressive stress applied to the upper surface of the body region, which increases the number of conduction electrons in the JFET region and prevents the P-type from being compensated in the body region.

[0012] In the semiconductor device disclosed in this specification as an example, the first gate insulating film may be thicker than the second gate insulating film.

[0013] The thicker first gate dielectric can have a larger internal stress than the second gate dielectric, and thus the compressive stress applied to the top surface of the JFET region can be larger than the compressive stress applied to the top surface of the body region.

[0014] In an example semiconductor device disclosed in the present specification, the first gate insulating film may be made of a first material. The second gate insulating film may be made of a second material. The first material may have a higher specific stress than the second material.

[0015] With this configuration, the compressive stress applied to the top surface of the JFET region can be made larger than the compressive stress applied to the top surface of the body region.

[0016] In the example semiconductor device disclosed in the present specification, the first material may be a material having a lower impurity concentration than the second material.

[0017] The lower the impurity concentration, the greater the internal stress can be, so the first gate insulating film, which has a lower impurity concentration, can have a greater internal stress than the second gate insulating film.

[0018] In the example semiconductor device disclosed in this specification, the first material and the second material may have different film densities.

[0019] By changing the film density, the internal stress can be made different, so that the first gate insulating film has a larger internal stress than the second gate insulating film.

[0020] In an example semiconductor device disclosed in the present specification, the first gate insulating film may have a laminated structure in which a second insulating film is disposed on the first insulating film. The second gate insulating film may have a single-layer structure in which the first insulating film is disposed. The second insulating film may have a larger specific stress than the first insulating film.

[0021] With this configuration, the compressive stress applied to the top surface of the JFET region can be made larger than the compressive stress applied to the top surface of the body region.

[0022] In the semiconductor device disclosed in the present specification, the second gate insulating film may have a laminated structure in which the second insulating film is disposed on the first insulating film. The first gate insulating film may have a single-layer structure in which the first insulating film is disposed. The stress of the second insulating film may be a stress in a direction opposite to the specific stress.

[0023] With this configuration, the compressive stress applied to the top surface of the JFET region can be made larger than the compressive stress applied to the top surface of the body region.

[0024] In an example of a semiconductor device disclosed in the present specification, the gate electrode may include a first gate electrode disposed above the JFET region and a second gate electrode disposed above a portion of the body region separating the JFET region from the source region. The first gate electrode may have a laminated structure in which a second conductor is disposed on a first conductor. The second gate electrode may have a single-layer structure in which a second conductor is disposed. The first conductor and the second conductor may have a specific stress capable of generating a compressive stress on the upper surface of the JFET region and the upper surface of the body region. The magnitude of the specific stress may be greater for the first conductor than for the second conductor.

[0025] With this configuration, the compressive stress applied to the top surface of the JFET region can be made larger than the compressive stress applied to the top surface of the body region.

[0026] In an example of a semiconductor device disclosed in the present specification, the gate electrode may include a first gate electrode disposed above the JFET region and a second gate electrode disposed above a portion of the body region separating the JFET region from the source region. The second gate electrode may have a laminated structure in which a second conductor is disposed on a first conductor. The first gate electrode may have a single-layer structure in which a second conductor is disposed. The first conductor may have a specific stress capable of generating a compressive stress on an upper surface of the JFET region and an upper surface of the body region. The second conductor may have a stress opposite to the specific stress.

[0027] With this configuration, the compressive stress applied to the top surface of the JFET region can be made larger than the compressive stress applied to the top surface of the body region.

[0028] The material of the semiconductor substrate may be GaN. EXAMPLES

[0029] (Structure of Semiconductor Device 1) 1 shows a cross-sectional view of a main part of a semiconductor device 1 according to the first embodiment. The semiconductor device 1 is a vertical MOSFET having a planar gate structure. The semiconductor device 1 includes a drain electrode 20, a semiconductor substrate 10, a gate electrode structure 16, an interlayer insulating film 19, and a source electrode 21.

[0030] The semiconductor substrate 10 is made of a wide-gap compound semiconductor. In this embodiment, the semiconductor substrate 10 is made of GaN (gallium nitride). + A drain layer 11 of n-type, a drift layer 12 of n-type, a JFET (Junction Field Effect Transistor) region 13 of n-type, a body region 14 of p-type, + The semiconductor substrate 10 has a source region 15 of a type having a drain electrode 20 and a drain layer 11. The drain layer 11 is provided at a position exposed on the back surface of the semiconductor substrate 10, and is in ohmic contact with the drain electrode 20. The drift layer 12 is provided on the drain layer 11, and is arranged between the drain layer 11 and the JFET region 13, and between the drain layer 11 and the body region 14. The drift layer 12 is formed by crystal growth from the surface of the drain layer 11 using an epitaxial growth technique.

[0031] The JFET region 13 is provided on the drift layer 12. The JFET region 13 extends from the surface of the drift layer 12 to the surface 10a of the semiconductor substrate 10 along the thickness direction (+z direction) of the semiconductor substrate 10, and has a form that protrudes from the surface of the drift layer 12. In other words, the JFET region 13 extends from the surface 10a of the semiconductor substrate 10 through the body region 14 to the drift layer 12. In this example, the impurity concentration of the JFET region 13 is equal to the impurity concentration of the drift layer 12.

[0032] The body region 14 is provided on the drift layer 12. The body region 14 is disposed with the JFET region 13 therebetween and is adjacent to a side surface of the JFET region 13. The body region 14 is provided at a position exposed on the front surface 10a of the semiconductor substrate 10 and is in ohmic contact with the source electrode 21.

[0033] The source region 15 is provided on the body region 14. The source region 15 is separated from the drift layer 12 and the JFET region 13 by the body region 14. The source region 15 is provided at a position exposed on the front surface 10a of the semiconductor substrate 10, and is in ohmic contact with the source electrode 21.

[0034] The gate electrode structure 16 has a structure in which a gate insulating film 17 and a gate electrode 18 are laminated in this order. The gate electrode structure 16 is disposed on the upper surface of the JFET region 13, and is also disposed on the upper surface of the body region 14 in a portion separating the JFET region 13 and the source region 15.

[0035] The gate insulating film 17 is silicon oxide. The gate insulating film 17 includes a first gate insulating film 17a and a second gate insulating film 17b. The first gate insulating film 17a is disposed on the upper surface of the JFET region 13. The second gate insulating film 17b is disposed on the upper surface of the body region 14 in a portion separating the JFET region 13 from the source region 15. The thickness T1 of the first gate insulating film 17a is thicker than the thickness T2 of the second gate insulating film 17b. The thickness T1 can be freely set. In this embodiment, when the thickness T1 is 100 nm or more, the effect of applying a compressive force to the upper surface of the JFET region 13 was confirmed. The thickness T1 can be made thick as long as the semiconductor device 1 operates.

[0036] The gate insulating film 17 can be formed by various methods. An example of the formation method will be described. A mask is formed by lithography in a region of the gate insulating film 17 having a thickness T1 corresponding to the first gate insulating film 17a. Then, a region corresponding to the second gate insulating film 17b is thinned by dry etching.

[0037] The gate electrode 18 is made of polysilicon. The gate electrode 18 extends in the depth direction (+y direction) of the paper and is in contact with a gate electrode not shown. The interlayer insulating film 19 is disposed to cover the gate electrode 18. The interlayer insulating film 19 is made of silicon oxide. The source electrode 21 is disposed on the surface 10a of the semiconductor substrate 10. The source electrode 21 is in contact with the source region 15 exposed on the surface 10a. The source electrode 21 is insulated from the gate electrode 18 by the interlayer insulating film 19. In this embodiment, the material of the source electrode 21 is aluminum.

[0038] (Function of gate insulating film 17) A specific stress is generated in the gate insulating film 17 formed on the upper surface of the JFET region 13 and the upper surface of the body region 14. The specific stress is a stress that can generate a compressive stress on the upper surface of the JFET region 13 and the upper surface of the body region 14. Here, a case where the specific stress is a tensile stress will be described.

[0039] FIG. 2 shows an enlarged view of the gate insulating film 17 and its vicinity. In FIG. 2, the interlayer insulating film 19 and the source electrode 21 are omitted. A tensile stress TS1 acts inside the first gate insulating film 17a. A tensile stress TS2 acts inside the second gate insulating film 17b. The tensile stresses TS1 and TS2 are forces that tend to expand the first gate insulating film 17a and the second gate insulating film 17b. Since the thickness T1 of the first gate insulating film 17a is thicker than the thickness T2 of the second gate insulating film 17b, the tensile stress TS1 can be made larger than the tensile stress TS2.

[0040] The tensile stresses TS1 and TS2 are tensile stresses in the direction of a plane parallel to the surface 10a of the semiconductor substrate 10. Therefore, the tensile stress TS1 generates a reaction force RF1 on the surface of the JFET region 13. The reaction force RF1 attracts the surface of the JFET region 13 from both sides, so that a compressive stress can be generated on the surface of the JFET region 13. Similarly, the tensile stress TS2 generates a reaction force RF2 on the surface of the body region 14. The reaction force RF2 attracts the surface of the body region 14 from both sides, so that a compressive stress can be generated on the surface of the body region 14. The tensile stress TS1 is larger than the tensile stress TS2. Therefore, the compressive stress applied to the upper surface of the JFET region 13 can be larger than the compressive stress applied to the upper surface of the body region 14.

[0041] The compressive stress applied to the upper surface of the JFET region 13 and the body region 14 can be evaluated by Raman analysis of a cross section of the semiconductor device 1. Therefore, a state in which the compressive stress applied to the upper surface of the JFET region 13 is greater than the compressive stress applied to the upper surface of the body region 14 can be confirmed by cross-sectional analysis.

[0042] (Operation of Semiconductor Device 1) When the semiconductor device 1 is in use, a positive voltage is applied to the drain electrode 20, and the source electrode 21 is grounded. When a positive voltage higher than the gate threshold voltage is applied to the gate electrode 18, a channel region CH is formed in the body region 14 separating the JFET region 13 and the source region 15, and the semiconductor device 1 is turned on. Electrons flow from the source electrode 21 through the source region 15, the channel region CH, the JFET region 13, the drift layer 12, and the drain layer 11 to the drain electrode 20. This forms a current path CP. When the gate electrode 18 is grounded, the channel region CH disappears, and the semiconductor device 1 is turned off. In this way, the semiconductor device 1 can perform a switching operation based on the voltage applied to the gate electrode 18.

[0043] (assignment) The on-resistance of the semiconductor device 1 is the sum of the resistances of the various parts occurring in the current path CP. That is, the on-resistance is the sum of the resistance of the source region 15, the resistance of the channel region CH, the resistance of the JFET region 13, the resistance of the drift layer 12, and the resistance of the drain layer 11. In order to increase the withstand voltage of the semiconductor device 1, it is necessary to lower the impurity concentration of the JFET region 13 so as to facilitate the extension of the depletion layer. This increases the resistance of the JFET region 13, and therefore increases the on-resistance of the semiconductor device 1.

[0044] To address this issue, it is conceivable to reduce the resistance of the JFET region 13 by making the impurity concentration of a part or the whole of the JFET region 13 higher than that of the drift layer 12. However, when using a GaN material, it is difficult to create different impurity concentrations for the drift layer 12 and the JFET region 13. This is because it is difficult to sufficiently increase the n-type impurity concentration of the JFET region 13 when the JFET region 13 is formed by ion implantation of n-type impurities as counters into the p-type body region 14. In addition, when the body region 14 is stacked on the drift layer 12, a trench reaching the drift layer 12 is processed in the region corresponding to the JFET region 13, and the JFET region 13 is re-epitaxially grown, a high-concentration N-type region is formed at the regrowth interface.

[0045] (effect) When compressive stress is applied to the inside of a semiconductor substrate of GaN, which is a wide-gap compound semiconductor, the lattice constant becomes smaller and the band gap becomes narrower. Therefore, the impurity level rises relatively, and a phenomenon occurs in which the number of conduction electrons increases. In the semiconductor device 1 of this embodiment, the first gate insulating film 17a can apply compressive stress to the upper surface of the JFET region 13. Since the number of conduction electrons in the JFET region 13 can be increased, the resistance of the JFET region 13 can be reduced. As a result, an increase in the on-resistance of the semiconductor device 1 can be suppressed.

[0046] A channel region CH is formed on the upper surface of the body region 14. When a large compressive stress is applied to the channel region CH, the increased number of conduction electrons compensates for the P-type. As a result, the threshold voltage decreases and the source-drain leakage current increases. In the semiconductor device 1 of this embodiment, the compressive stress applied to the upper surface of the body region 14 can be made smaller than the compressive stress applied to the upper surface of the JFET region 13. This makes it possible to suppress the compressive stress applied to the channel region CH, thereby preventing the threshold voltage decrease and the leakage current increase.

[0047] In order to improve the breakdown voltage of the semiconductor device 1, it is better to increase the stretchability of the depletion layer on the drain electrode 20 side of the JFET region 13 rather than the stretchability of the depletion layer on the surface side of the JFET region 13. In other words, it is better to selectively increase the conduction electrons on the surface side of the JFET region 13. In the semiconductor device 1 of this embodiment, a compressive stress is applied to the surface of the JFET region 13 by the first gate insulating film 17a. This makes it possible to selectively increase only the conduction electrons near the surface of the JFET region 13. It becomes possible to improve the breakdown voltage of the semiconductor device 1. EXAMPLES

[0048] 3 shows a cross-sectional view of a main part of a semiconductor device 201 according to Example 2. The semiconductor device 201 of Example 2 differs from Example 1 in the structure of a gate insulating film 217. The same reference numerals are used to designate parts common to the semiconductor device 1 of Example 1 (FIG. 1), and description thereof will be omitted.

[0049] The gate insulating film 217 includes a first gate insulating film 217a and a second gate insulating film 217b. The first gate insulating film 217a is disposed on the upper surface of the JFET region 13. The second gate insulating film 217b is disposed on the upper surface of the body region 14 in a portion separating the JFET region 13 from the source region 15. The first gate insulating film 217a and the second gate insulating film 217b have the same film thickness. The first gate insulating film 217a is formed of a first material. The second gate insulating film 217b is formed of a second material. The first material has a larger tensile stress than the second material.

[0050] The combination of the first and second materials may be various. For example, the first material may be undoped silicon oxide and the second material may be silicon oxide doped with at least one of phosphorus and boron. Undoped silicon oxide has a higher tensile stress than doped silicon oxide.

[0051] Such a gate insulating film 217 can be formed by various methods. One example of the formation method will be described. After forming a non-doped gate insulating film 217, a mask is formed by lithography in a region corresponding to the first gate insulating film 217a. Then, impurities are ion-implanted through the mask into a region corresponding to the second gate insulating film 217b.

[0052] Furthermore, the first material and the second material may have different film densities. For example, the first material may have a lower film density than the second material. An example of the first material is silicon oxide formed by a film formation method that results in a lower film density (e.g., LP-CVD or PVD). An example of the second material is silicon oxide formed by a film formation method that results in a higher film density (e.g., plasma CVD). In general, the lower the film density, the lower the compressive stress. Therefore, relatively speaking, the lower the film density, the higher the tensile stress.

[0053] Such a gate insulating film 217 can be formed by various methods. An example of the formation method will be described. After the first gate insulating film 217a is formed on the entire surface 10a by the LP-CVD method, a mask is formed by lithography in the region corresponding to the first gate insulating film 217a. The gate insulating film in the region corresponding to the second gate insulating film 217b is removed by dry etching. The second gate insulating film 217b is formed by the plasma CVD method. The mask and the gate insulating film formed in the region corresponding to the first gate insulating film 217a are removed.

[0054] (effect) The compressive stress applied to the upper surface of the JFET region 13 by the first gate insulating film 217a can be made larger than the compressive stress applied to the upper surface of the body region 14 by the second gate insulating film 217b. The resistance of the JFET region 13 can be reduced. EXAMPLES

[0055] 4 shows a cross-sectional view of a main part of a semiconductor device 301 according to Example 3. The semiconductor device 301 of Example 3 has a different structure of a gate insulating film 317 from that of Example 1. The same reference numerals are used to designate parts common to the semiconductor device 1 of Example 1 (FIG. 1), and description thereof will be omitted.

[0056] The gate insulating film 317 has a laminated structure of a first insulating film 317L and a second insulating film 317U. The second insulating film 317U has a tensile stress greater than that of the first insulating film 317L. In this embodiment, the first insulating film 317L is silicon oxide, and the second insulating film 317U is silicon nitride.

[0057] The gate insulating film 317 includes a first gate insulating film 317a and a second gate insulating film 317b. The first gate insulating film 317a is disposed on the upper surface of the JFET region 13. The second gate insulating film 317b is disposed on the upper surface of the body region 14 in a portion separating the JFET region 13 from the source region 15. The first gate insulating film 317a includes a laminated structure in which a second insulating film 317U is disposed on a first insulating film 317L. The second gate insulating film 317b includes a single layer structure in which the first insulating film 317L is disposed.

[0058] Such a gate insulating film 317 can be formed by various methods. An example of the formation method will be described. After the first insulating film 317L and the second insulating film 317U are formed over the entire surface 10a, a mask is formed by lithography in the region corresponding to the gate electrode structure 16. The first insulating film 317L and the second insulating film 317U other than the region corresponding to the gate electrode structure 16 are removed by dry etching. The mask is slimmed to expose the region corresponding to the second gate insulating film 317b. The second insulating film 317U in the region corresponding to the second gate insulating film 317b is removed by dry etching.

[0059] (effect) The second insulating film 317U included in the first gate insulating film 317a makes it possible to apply a large compressive stress to the upper surface of the JFET region 13. The resistance of the JFET region 13 can be reduced. EXAMPLES

[0060] 5 shows a cross-sectional view of a main part of a semiconductor device 401 according to Example 4. The semiconductor device 401 of Example 4 has a different structure of a gate insulating film 417 from that of Example 1. The same reference numerals are used to designate parts common to the semiconductor device 1 of Example 1 (FIG. 1), and description thereof will be omitted.

[0061] The gate insulating film 417 has a laminated structure of a first insulating film 417L and a second insulating film 417U. The first insulating film 417L is a film having a tensile stress. The second insulating film 417U is a film having a compressive stress, which is a stress in the opposite direction to the tensile stress. In this embodiment, the first insulating film 417L is silicon oxide, and the second insulating film 417U is silicon nitride.

[0062] The gate insulating film 417 includes a first gate insulating film 417a and a second gate insulating film 417b. The first gate insulating film 417a is disposed on the upper surface of the JFET region 13. The second gate insulating film 417b is disposed on the upper surface of the body region 14 in a portion separating the JFET region 13 from the source region 15. The first gate insulating film 417a has a single-layer structure in which a first insulating film 417L is disposed. The second gate insulating film 417b has a laminated structure in which a second insulating film 417U is disposed on the first insulating film 417L.

[0063] (effect) In the second gate insulating film 417b, the tensile stress of the first insulating film 417L can be relaxed by the compressive stress of the second insulating film 417U. This makes it possible to make the reaction force RF2 acting on the upper surface of the body region 14 smaller than the reaction force RF1 acting on the surface of the JFET region 13. It becomes possible to suppress the compressive stress applied to the channel region CH. EXAMPLES

[0064] 6 shows a cross-sectional view of a main part of a semiconductor device 501 according to the embodiment 5. The semiconductor device 501 of the embodiment 5 has a gate electrode 518 having a different structure from that of the embodiment 1. The same reference numerals are used to designate parts common to the semiconductor device 1 of the embodiment 1 (FIG. 1), and description thereof will be omitted.

[0065] The gate electrode 518 includes a first conductor 518L and a second conductor 518U. The first conductor 518L is a film having a larger tensile stress than the second conductor 518U. In this embodiment, the first conductor 518L is nickel, and the second conductor 518U is polysilicon. The first conductor 518L is disposed above the JFET region 13. The second conductor 518U is disposed above the first conductor 518L and above a portion of the body region 14 that separates the JFET region 13 and the source region 15.

[0066] The gate electrode 518 includes a first gate electrode 518a and a second gate electrode 518b. The first gate electrode 518a is disposed on the upper surface of the JFET region 13. The second gate electrode 518b is disposed on the upper surface of the body region 14 in a portion separating the JFET region 13 from the source region 15. The first gate electrode 518a includes a laminated structure in which a second conductor 518U is disposed on a first conductor 518L. The second gate electrode 518b includes a single-layer structure in which a second conductor 518U is disposed. Such a gate electrode 518 can be formed by various methods. For example, a method similar to that for the gate insulating film 317 described in the third embodiment may be used.

[0067] (effect) The second conductor 518U of the first gate electrode 518a makes it possible to apply a large compressive stress to the upper surface of the JFET region 13. The resistance of the JFET region 13 can be reduced. EXAMPLES

[0068] 7 shows a cross-sectional view of a main part of a semiconductor device 601 according to Example 6. The semiconductor device 601 of Example 6 differs from Example 1 in the structure of a gate electrode 618. The same reference numerals are used to designate parts common to the semiconductor device 1 of Example 1 (FIG. 1), and description thereof will be omitted.

[0069] The gate insulating film 17 is a film having a tensile stress. In this embodiment, the gate insulating film 17 is silicon oxide. The gate electrode 618 includes a first conductor 618L and a second conductor 618U. The second conductor 618U is a conductor having a compressive stress, which is a stress in the opposite direction to the tensile stress. In this embodiment, the first conductor 618L is nickel, and the second conductor 618U is polysilicon.

[0070] The gate electrode 518 also includes a first gate electrode 618a and a second gate electrode 618b. The first gate electrode 618a is disposed on an upper surface of the JFET region 13. The second gate electrode 618b is disposed on an upper surface of the body region 14 in a portion separating the JFET region 13 from the source region 15. The first gate electrode 618a includes a single-layer structure in which a second conductor 518U is disposed. The second gate electrode 518b includes a multilayer structure in which a second conductor 618U is disposed on a first conductor 618L.

[0071] (effect) In the second gate electrode 618b, the compressive stress of the second conductor 618U can relieve the tensile stress of the gate insulating film 17. This makes it possible to make the reaction force RF2 acting on the upper surface of the body region 14 smaller than the reaction force RF1 acting on the surface of the JFET region 13. It becomes possible to suppress the compressive stress applied to the channel region CH.

[0072] Although specific examples of the present invention have been described above in detail, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or drawings can achieve multiple objectives simultaneously, and achieving one of these objectives is itself technically useful.

[0073] (Modification) The techniques described in this specification can be combined in various ways. For example, the technique of making the thickness of the gate insulating film 17 different (Example 1), the technique of making the material of the gate insulating film 217 different (Example 2), the technique of using a laminated structure of the gate insulating films 317 and 417 (Examples 3 and 4), and the technique of using a laminated structure of the gate electrodes 518 and 618 (Examples 5 and 6) can be used in combination of two or more.

[0074] The specific stress generated in the gate insulating film is not limited to tensile stress, and may be any stress that can generate compressive stress in the surface 10a of the semiconductor substrate 10, for example, compressive stress.

[0075] The material of the semiconductor substrate 10 is not limited to GaN, but may be any wide-gap compound semiconductor, such as SiC (silicon carbide), Ga2O3 (gallium oxide), AlGaN (aluminum gallium nitride), AlN (aluminum nitride), InN (indium nitride), InGaN (indium gallium nitride), or a mixed crystal thereof.

[0076] The specific contents of the gate insulating film and the gate electrode materials described in this specification are merely examples, and the present invention is not limited to these combinations.

[0077] The n-type is an example of a first conductivity type. The p-type is an example of a second conductivity type. The tensile stress is an example of a specific stress. [Explanation of symbols]

[0078] 1: Semiconductor device 10: Semiconductor substrate 10a: Surface 11: Drain layer 12: Drift layer 13: JFET region 14: Body region 15: Source region 16: Gate electrode structure 17: Gate insulating film 17a: First gate insulating film 17b: Second gate insulating film 18: Gate electrode

Claims

1. A vertical semiconductor device having a semiconductor substrate made of a wide-gap compound semiconductor, A drift layer of a first conductivity type; a first conductivity type JFET region provided on the drift layer and arranged at a position exposed on an upper surface of the semiconductor substrate; a second conductivity type body region provided on the drift layer, adjacent to the JFET region, and disposed at a position exposed on an upper surface of the semiconductor substrate; a first conductivity type source region that is separated from the drift layer and the JFET region by the body region and that is disposed at a position exposed on an upper surface of the semiconductor substrate; a gate electrode structure having a structure in which a gate insulating film and a gate electrode are laminated in this order, the gate electrode structure being disposed on an upper surface of the JFET region and on an upper surface of the body region in a portion separating the JFET region from the source region; Equipped with The gate insulating film is a first gate insulating film disposed on an upper surface of the JFET region; a second gate insulating film disposed on an upper surface of the body region in a portion separating the JFET region and the source region; It is equipped with the first gate insulating film and the second gate insulating film have a specific stress capable of generating a compressive stress on an upper surface of the JFET region and an upper surface of the body region; the first gate insulating film is formed of a first material; the second gate insulating film is formed of a second material; The first material has a larger specific stress than the second material, the first material and the second material have different film densities; a compressive stress applied by the gate electrode structure to a top surface of the JFET region is greater than a compressive stress applied by the gate electrode structure to a top surface of the body region.

2. A vertical semiconductor device having a semiconductor substrate made of a wide-gap compound semiconductor, A drift layer of a first conductivity type; a first conductivity type JFET region provided on the drift layer and arranged at a position exposed on an upper surface of the semiconductor substrate; a second conductivity type body region provided on the drift layer, adjacent to the JFET region, and disposed at a position exposed on an upper surface of the semiconductor substrate; a first conductivity type source region that is separated from the drift layer and the JFET region by the body region and that is disposed at a position exposed on an upper surface of the semiconductor substrate; a gate electrode structure having a structure in which a gate insulating film and a gate electrode are laminated in this order, the gate electrode structure being disposed on an upper surface of the JFET region and on an upper surface of the body region in a portion separating the JFET region from the source region; Equipped with The gate insulating film is a first gate insulating film disposed on an upper surface of the JFET region; a second gate insulating film disposed on an upper surface of the body region in a portion separating the JFET region and the source region; Equipped with the first gate insulating film and the second gate insulating film have a specific stress capable of generating a compressive stress on an upper surface of the JFET region and an upper surface of the body region; the magnitude of the specific stress is greater in the first gate insulating film than in the second gate insulating film; the second gate insulating film has a laminated structure in which a second insulating film is disposed on a first insulating film, the first gate insulating film has a single-layer structure in which the first insulating film is disposed, the stress of the second insulating film is a stress in a direction opposite to the specific stress, a compressive stress applied to an upper surface of the JFET region by the gate electrode structure is greater than a compressive stress applied to an upper surface of the body region by the gate electrode structure.

3. A vertical semiconductor device having a semiconductor substrate made of a wide-gap compound semiconductor, A drift layer of a first conductivity type; a first conductivity type JFET region provided on the drift layer and arranged at a position exposed on an upper surface of the semiconductor substrate; a second conductivity type body region provided on the drift layer, adjacent to the JFET region, and disposed at a position exposed on an upper surface of the semiconductor substrate; a first conductivity type source region that is separated from the drift layer and the JFET region by the body region and that is disposed at a position exposed on an upper surface of the semiconductor substrate; a gate electrode structure having a structure in which a gate insulating film and a gate electrode are laminated in this order, the gate electrode structure being disposed on an upper surface of the JFET region and on an upper surface of the body region in a portion separating the JFET region from the source region; Equipped with The gate electrode is a first gate electrode disposed above the JFET region; a second gate electrode disposed above the body region in a portion separating the JFET region and the source region; Equipped with the first gate electrode has a laminated structure in which a second conductor is disposed on a first conductor; the second gate electrode has a single layer structure in which the second conductor is disposed; the first conductor and the second conductor have a specific stress capable of generating a compressive stress in a top surface of the JFET region and a top surface of the body region; the magnitude of the specific stress is greater in the first conductor than in the second conductor; a compressive stress applied by the gate electrode structure to a top surface of the JFET region is greater than a compressive stress applied by the gate electrode structure to a top surface of the body region.

4. the first gate insulating film has a laminated structure in which a second insulating film is disposed on a first insulating film, the second gate insulating film has a single-layer structure in which the first insulating film is disposed, The semiconductor device according to claim 1 , wherein the specific stress of said second insulating film is greater than that of said first insulating film.

5. 5. The semiconductor device according to claim 1, wherein the material of the semiconductor substrate is GaN.

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