Multi-component isolation structure for improving image sensor performance - Patents.com

Abstract

PURPOSE: To provide an image sensor including a plurality of photodetectors disposed within a substrate.SOLUTION: Photodetectors are disposed respectively within a plurality of pixel regions. A floating diffusion node is disposed along a front-side surface of a substrate at a middle region of the plurality of pixel regions. A plurality of well regions are disposed within the substrate at corners of the plurality of pixel regions. An isolation structure extends into a back-side surface of the substrate. The isolation structure includes a plurality of elongated isolation components disposed between the adjacent pixel regions, a middle isolation component aligned with the floating diffusion node, and a plurality of peripheral isolation components aligned with the plurality of well regions. The elongated isolation components have a first height, and the middle and peripheral isolation components have a second height less than the first height.SELECTED DRAWING: Figure 19B

Description

[Background technology]

[0001] Many modern electronic devices (e.g., digital cameras, optical imaging devices, etc.) include an image sensor. The image sensor includes an array of pixel regions, each of which includes a photodiode configured to capture and convert an optical signal (e.g., light) into digital data (e.g., a digital image). Complementary metal-oxide-semiconductor (CMOS) image sensors are more commonly used than charge-coupled device (CCD) image sensors because they have many advantages, such as low power consumption, high-speed data processing, and low manufacturing costs. Summary of the Invention [Problem to be solved by the invention]

[0002] The image sensor includes a plurality of pixel regions arranged in an array. Each pixel region includes a photodetector (e.g., photodiode) disposed in a substrate and configured to convert incident radiation (e.g., visible light) into charge carriers. A transfer gate structure is disposed on a front surface of the substrate and configured to control the flow of the converted charge carriers to a floating diffusion node disposed along the front surface. The floating diffusion node is coupled to a plurality of pixel devices (e.g., reset transistor, source follower transistor, etc.) to facilitate digital readout of the converted incident radiation. A plurality of pixel regions can share one floating diffusion node, the floating diffusion node being disposed at the intersection of adjacent pixel regions. For example, in a 2×2 shared pixel layout, the floating diffusion node is disposed at the mid-region of four adjacent photodetectors.

[0003] By utilizing one floating diffusion node for multiple pixel regions, the lateral footprint of the image sensor can be reduced since adjacent pixel regions are placed closer together. However, by reducing the distance between pixel regions, electrical and optical isolation between adjacent photodetectors can be reduced. An example of optical crosstalk is when incident radiation (e.g., light) enters a pixel region at an angle and crosses over an adjacent pixel region. An example of electrical crosstalk is when charge carriers in a photodetector migrate to an adjacent photodetector. To improve electrical and optical isolation, deep trench isolation (DTI) structures are placed in the substrate between adjacent pixel regions. The DTI structures can include a central isolation segment that extends vertically toward the floating diffusion node and outer isolation segments that extend from the central isolation segment and separate adjacent pixel regions.

[0004] To prevent damage to the floating diffusion node, the height of the central isolation segment is less than the height of the outer isolation segments. This reduces damage to the floating diffusion node during the etching process used to form the opening or trench of the DTI structure. Additionally, the well regions are disposed on opposing sides of the floating diffusion node in the substrate. The well regions are disposed on only two sides of the floating diffusion node such that the layout of the image sensor has asymmetric or low-fold rotational symmetry (i.e., two-fold rotational symmetry). Additionally, the well regions have a first doping type (e.g., p-type) that is opposite to the second doping type (e.g., n-type) of the floating diffusion node. The well regions are coupled to a reference voltage (e.g., ground or 0 volts) and are configured to reduce noise throughout the image sensor. The image sensor features can be scaled down to increase the device density of the image sensor. Due to the asymmetric or low-fold rotational symmetry layout of the image sensor, as device features are scaled down, the minimum distance between the floating diffusion node and the well region can be substantially shorter (e.g., less than the length or width of the corresponding photodetector), resulting in junction leakage between the floating diffusion node and the well region. This results in reduced electrical isolation and increased photo response non-uniformity (PRNU) and dark image non-uniformity (DINU) across the image sensor, thereby reducing the overall performance of the image sensor. [Means for solving the problem]

[0005] The present invention provides, in some embodiments, an image sensor including a plurality of photodetectors disposed within a substrate, the photodetectors being disposed within a plurality of pixel regions, a floating diffusion node disposed along a front surface of the substrate at an intermediate region of the plurality of pixel regions, a plurality of well regions disposed within the substrate at corners of the plurality of pixel regions, and an isolation structure extending to a back surface of the substrate, the isolation structure including a plurality of elongated isolation elements disposed between adjacent pixel regions, an intermediate isolation element aligned with the floating diffusion node, and a plurality of peripheral isolation elements aligned with the plurality of well regions, the elongated isolation elements having a first height, and the intermediate and peripheral isolation elements having a second height less than the first height.

[0006] The present invention provides an image sensor in some embodiments, the image sensor includes a plurality of pixel regions disposed in a substrate, a plurality of transfer gate structures disposed on a front surface of the substrate, the transfer gate structures being disposed in the plurality of pixel regions, a floating diffusion node disposed in the substrate at an intersection of the plurality of pixel regions, and a plurality of well regions disposed in the substrate, the well regions being disposed diagonally on corresponding edges of the floating diffusion nodes, and an isolation structure extending on a back surface of the substrate and extending laterally between the plurality of pixel regions, the isolation structure including an intermediate isolation element disposed with the floating diffusion nodes, a plurality of peripheral isolation elements disposed with the plurality of well regions, and a plurality of elongated isolation elements extending laterally between the intermediate isolation element and the peripheral isolation element, the first depth of the elongated isolation element being greater than the second depth of the intermediate isolation element and the peripheral isolation element.

[0007] In some embodiments, the present invention provides a method for forming an image sensor, the method includes forming a plurality of photodetectors in a substrate, the photodetectors being respectively disposed in a plurality of pixel regions, doping the substrate to form floating diffusion nodes at intersections of the plurality of pixel regions and forming a plurality of well regions diagonally on edges of the floating diffusion nodes, forming a hard mask structure on a back surface of the substrate, the hard mask structure including a first hard mask component aligned with the floating diffusion nodes and a second hard mask component aligned with the well regions, performing an etching process on the substrate on which the hard mask structure is disposed to form an isolation structure trench in the substrate, the isolation structure trench including a plurality of first components having a first depth and a plurality of second components having a second depth deeper than the first depth, the first components being aligned with the floating diffusion nodes and the well regions, forming an isolation structure in the isolation structure trench, the isolation structure including a middle isolation component and a plurality of peripheral isolation components having the first depth and a plurality of elongated isolation components having the second depth. Effect of the Invention

[0008] According to the present invention, the image sensor layout has high fold symmetry (e.g., 4-fold rotational symmetry) and increases the minimum distance between the floating diffusion nodes and the well regions. As a result, the device features of the image sensor can be scaled down while simultaneously improving electrical and optical isolation throughout the image sensor. This increases device density and reduces photoresponse nonuniformity (PRNU) and dark image nonuniformity (DINU), thereby improving the overall performance of the image sensor. [Brief description of the drawings]

[0009] Aspects of the invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of illustration.

[0010] [Figure 1A] Shows diagrams of some embodiments of an image sensor including a plurality of well regions and a plurality of pixel regions separated by a separation structure having a plurality of separation components with different heights. [Figure 1B] Shows diagrams of some embodiments of an image sensor including a plurality of well regions and a plurality of pixel regions separated by a separation structure having a plurality of separation components with different heights. [Figure 1C] Shows diagrams of some embodiments of an image sensor including a plurality of well regions and a plurality of pixel regions separated by a separation structure having a plurality of separation components with different heights. [Figure 2A] Shows diagrams of some other embodiments of the image sensors of FIGS. 1A - 1C. [Figure 2B] Shows diagrams of some other embodiments of the image sensors of FIGS. 1A - 1C. [Figure 2C] Shows diagrams of some other embodiments of the image sensors of FIGS. 1A - 1C. [Figure 3A] Shows a cross - sectional view of a further embodiment of the image sensors of FIGS. 1A - 1C. [Figure 3B] Shows a cross - sectional view of a further embodiment of the image sensors of FIGS. 1A - 1C. [Figure 4A] Shows a cross - sectional view of some embodiments of an integrated chip (IC) including a first chip bonded to a second chip and a pixel chip bonded to the second chip, where the pixel chip includes a plurality of pixel regions separated by a separation structure having a plurality of separation components with different heights. [Figure 4B] Shows a cross - sectional view of some embodiments of an integrated chip (IC) including a first chip bonded to a second chip and a pixel chip bonded to the second chip, where the pixel chip includes a plurality of pixel regions separated by a separation structure having a plurality of separation components with different heights. [Diagram 5] 1A-1C illustrate diagrams of several embodiments of methods for forming an image sensor including an isolation structure having multiple isolation components and multiple well regions with symmetrical layouts. [Figure 6] 1A-1C illustrate diagrams of several embodiments of methods for forming an image sensor including an isolation structure having multiple isolation components and multiple well regions with symmetrical layouts. [Figure 7] 1A-1C illustrate diagrams of several embodiments of methods for forming an image sensor including an isolation structure having multiple isolation components and multiple well regions with symmetrical layouts. [Figure 8] 1A-1C illustrate diagrams of several embodiments of methods for forming an image sensor including an isolation structure having multiple isolation components and multiple well regions with symmetrical layouts. [Figure 9] 1A-1C illustrate diagrams of several embodiments of methods for forming an image sensor including an isolation structure having multiple isolation components and multiple well regions with symmetrical layouts. [Figure 10] 1A-1C illustrate diagrams of several embodiments of methods for forming an image sensor including an isolation structure having multiple isolation components and multiple well regions with symmetrical layouts. [Figure 11] 1A-1C illustrate diagrams of several embodiments of methods for forming an image sensor including an isolation structure having multiple isolation components and multiple well regions with symmetrical layouts. [Figure 12] 1A-1C illustrate diagrams of several embodiments of methods for forming an image sensor including an isolation structure having multiple isolation components and multiple well regions with symmetrical layouts. [Figure 13A] 1A-1C illustrate diagrams of several embodiments of methods for forming an image sensor including an isolation structure having multiple isolation components and multiple well regions with symmetrical layouts. [Figure 13B]1A-1C illustrate diagrams of several embodiments of methods for forming an image sensor including an isolation structure having multiple isolation components and multiple well regions with symmetrical layouts. [Figure 13C] 1A-1C illustrate diagrams of several embodiments of methods for forming an image sensor including an isolation structure having multiple isolation components and multiple well regions with symmetrical layouts. [Figure 14A] 1A-1C illustrate diagrams of several embodiments of methods for forming an image sensor including an isolation structure having multiple isolation components and multiple well regions with symmetrical layouts. [Figure 14B] 1A-1C illustrate diagrams of several embodiments of methods for forming an image sensor including an isolation structure having multiple isolation components and multiple well regions with symmetrical layouts. [Figure 14C] 1A-1C illustrate diagrams of several embodiments of methods for forming an image sensor including an isolation structure having multiple isolation components and multiple well regions with symmetrical layouts. [Figure 15A] 1A-1C illustrate diagrams of several embodiments of methods for forming an image sensor including an isolation structure having multiple isolation components and multiple well regions with symmetrical layouts. [Figure 15B] 1A-1C illustrate diagrams of several embodiments of methods for forming an image sensor including an isolation structure having multiple isolation components and multiple well regions with symmetrical layouts. [Figure 15C] 1A-1C illustrate diagrams of several embodiments of methods for forming an image sensor including an isolation structure having multiple isolation components and multiple well regions with symmetrical layouts. [Figure 16A] 1A-1C illustrate diagrams of several embodiments of methods for forming an image sensor including an isolation structure having multiple isolation components and multiple well regions with symmetrical layouts. [Figure 16B] 1A-1C illustrate diagrams of several embodiments of methods for forming an image sensor including an isolation structure having multiple isolation components and multiple well regions with symmetrical layouts. [Figure 16C] 1A-1C illustrate diagrams of several embodiments of methods for forming an image sensor including an isolation structure having multiple isolation components and multiple well regions with symmetrical layouts. [Figure 17A] 1A-1C illustrate diagrams of several embodiments of methods for forming an image sensor including an isolation structure having multiple isolation components and multiple well regions with symmetrical layouts. [Figure 17B] 1A-1C illustrate diagrams of several embodiments of methods for forming an image sensor including an isolation structure having multiple isolation components and multiple well regions with symmetrical layouts. [Figure 17C] 1A-1C illustrate diagrams of several embodiments of methods for forming an image sensor including an isolation structure having multiple isolation components and multiple well regions with symmetrical layouts. [Figure 18A] 1A-1C illustrate diagrams of several embodiments of methods for forming an image sensor including an isolation structure having multiple isolation components and multiple well regions with symmetrical layouts. [Figure 18B] 1A-1C illustrate diagrams of several embodiments of methods for forming an image sensor including an isolation structure having multiple isolation components and multiple well regions with symmetrical layouts. [Figure 18C] 1A-1C illustrate diagrams of several embodiments of methods for forming an image sensor including an isolation structure having multiple isolation components and multiple well regions with symmetrical layouts. [Figure 19A] 1A-1C illustrate diagrams of several embodiments of methods for forming an image sensor including an isolation structure having multiple isolation components and multiple well regions with symmetrical layouts. [Figure 19B] 1A-1C illustrate diagrams of several embodiments of methods for forming an image sensor including an isolation structure having multiple isolation components and multiple well regions with symmetrical layouts. [Figure 20]1 illustrates a flow chart of some embodiments of a method for forming an image sensor including multiple well regions and multiple pixel regions separated by an isolation structure having multiple isolation components. [Figure 21] 5A-5C illustrate cross-sectional views of several alternative embodiments of methods of forming an image sensor including multiple well regions and multiple pixel regions separated by an isolation structure having multiple isolation components. [Figure 22] 5A-5C illustrate cross-sectional views of several alternative embodiments of methods of forming an image sensor including multiple well regions and multiple pixel regions separated by an isolation structure having multiple isolation components. [Diagram 23] 5A-5C illustrate cross-sectional views of several alternative embodiments of methods of forming an image sensor including multiple well regions and multiple pixel regions separated by an isolation structure having multiple isolation components. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The present invention provides many different embodiments or examples for implementing different features of the present invention. To simplify the present invention, specific examples of components and arrangements are described below. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features without the first and second features being in direct contact. Furthermore, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for purposes of simplicity and clarity and does not, in itself, dictate a relationship between the various embodiments and / or configurations discussed.

[0012] Additionally, spatially relative terms such as "below," "downward," "lower," "upward," "above," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein may be similarly interpreted accordingly.

[0013] In various embodiments, the present invention relates to an image sensor having a plurality of well regions arranged around a floating diffusion node and an isolation structure including a plurality of long isolation elements and a plurality of short isolation elements. The image sensor may include a shared pixel layout structure (e.g., a 2×2 shared pixel layout) including a floating diffusion node arranged at an intersection of a plurality of photodetectors. The short isolation elements of the isolation structure include a middle isolation element arranged at the intersection of the shared pixel layout structure and a plurality of peripheral isolation elements arranged at the corners. The long isolation elements are arranged on each side of the shared pixel layout structure and extend laterally between the short isolation elements. Furthermore, the well regions are arranged at the corners of the shared pixel layout structure such that the peripheral isolation elements extend vertically toward the well regions. The well regions include an opposite doping type to the floating diffusion node and are electrically coupled to a reference voltage (e.g., ground or 0 volts). By placing the peripheral isolation components and well regions at the corners of the shared pixel layout structure, the image sensor layout has high fold symmetry (e.g., has four-fold rotational symmetry) and the minimum distance between the floating diffusion nodes and the well regions is increased. As a result, the device features of the image sensor can be scaled down while simultaneously improving electrical and optical isolation throughout the image sensor. This increases device density and reduces photoresponse nonuniformity (PRNU) and dark image nonuniformity (DINU), thereby improving the overall performance of the image sensor.

[0014] Also, the elongated isolation components have a first height, and the intermediate and peripheral isolation components have a second height that is less than the first height. By having the intermediate and peripheral isolation components have the second height, damage to the floating diffusion nodes and well regions is reduced. For example, during manufacturing of an image sensor, an etching process is performed on a substrate to form openings or trenches for the isolation structures. By performing the etching process, the openings in the elongated isolation components are deeper than the openings in the intermediate and peripheral isolation components. This reduces damage to the floating diffusion nodes and / or well regions during the etching process, thereby improving device yield and durability.

[0015] 1A-1C show various views 100a-100c of several embodiments of an image sensor having a plurality of well regions 110 and a plurality of pixel regions 103 separated by an isolation structure 112 including a plurality of isolation elements 114, 116m, 116p. FIG. 1A shows a top view 100a of the image sensor as viewed from the front surface 102f of the substrate 102. FIG. 1B shows a cross-sectional view 100b taken along line A-A' of the top view 100a of FIG. 1A. FIG. 1C shows a cross-sectional view 100c taken along line B-B' of the top view 100a of FIG. 1A. For simplicity and ease of illustration, structures in cross-sectional views 100b, 100c (e.g., interconnect dielectric structure 120) are omitted from top view 100a of FIG. 1A, and image sensor structures or regions in cross-sectional views 100b, 100c (e.g., photodetector 106, isolation components 116m, 116p) are shown as dashed polygons and / or are at least partially transparent in top view 100a of FIG. 1A.

[0016] As shown in the top view 100a of FIG. 1A, the image sensor includes a shared pixel layout structure including a floating diffusion node 108 disposed at the intersection of a plurality of pixel regions 103a-103d. A plurality of photodetectors 106 are disposed within the substrate 102, with each pixel region 103a-103d including an individual photodetector 106. The plurality of pixel regions 103a-103d include a first pixel region 103a, a second pixel region 103b, a third pixel region 103c, and a fourth pixel region 103d, with the first pixel region 103a disposed diagonally opposite the second pixel region 103b. The substrate 102 can include a semiconductor body (e.g., single crystal silicon, CMOS bulk, silicon-germanium, silicon-on-insulator (SOI), etc.). In various embodiments, the substrate 102 has a first doping type (e.g., p-type). The photodetector 106 and the floating diffusion node 108 can have a second doping type (e.g., n-type) opposite to the first doping type. In some embodiments, the first doping type is p-type and the second doping type is n-type, but vice versa. The floating diffusion node 108 is located at the center and / or intersection of the shared pixel layout structure (e.g., at the center and / or intersection of the multiple pixel regions 103a-103d).

[0017] Additionally, a number of well regions 110 are disposed within the substrate 102 and have a first doping type (e.g., p-type). The well regions 110 are disposed at the corners of the shared pixel layout structure such that the well regions 110 are disposed diagonally across the corners or edges of the floating diffusion node 108. The well regions 110 have a first doping type (e.g., p-type) opposite to a second doping type (e.g., n-type) of the floating diffusion node 108 and the photodetector 106.

[0018] A plurality of transfer gate structures 118 are disposed on the substrate 102, and the transfer gate structures 118 are aligned with corresponding photodetectors 106. The photodetectors 106 are configured to absorb incident light (e.g., photons) and generate respective electrical signals corresponding to the incident light. For example, the photodetectors 106 can generate electron-hole pairs from the incident light. In some embodiments, the transfer gate structures 118 are configured to control current flow between the floating diffusion nodes 108 and the corresponding photodetectors 106. For example, the transfer gate structures 118 may be configured to selectively form conductive channels in the substrate 102 between the floating diffusion nodes 108 and adjacent photodetectors 106 to transfer charge stored in the photodetectors 106 to the floating diffusion nodes 108.

[0019] The isolation structure 112 is disposed on the substrate 102 and is disposed between adjacent photodetectors 106. In some embodiments, the isolation structure 112 includes a plurality of elongated isolation elements 114 and a plurality of short isolation elements 116m, 116p. In various embodiments, the plurality of short isolation elements 116m, 116p includes a middle isolation element 116m disposed at an intersection and a plurality of peripheral isolation elements 116p aligned with the plurality of well regions 110. In some embodiments, the elongated isolation element 114 may be referred to as a first isolation element, the peripheral isolation element 116p may be referred to as a second isolation element, and the middle isolation element 116m may be referred to as a central second isolation element or a middle second isolation element. In various embodiments, the long isolation elements 114 have a first height (e.g., h1 in FIG. 1C) and the short isolation elements 116m, 116p have a second height (e.g., h2 in FIGS. 1B and 1C) that is less than the first height (see, e.g., FIG. 1C). The isolation structures 112 laterally surround each pixel region 103 and are configured to improve optical and electrical isolation across the image sensor.

[0020] The well regions 110 are located at the corners of the shared pixel layout structure, which makes the layout of the shared pixel layout structure highly symmetric (e.g., has at least four-fold rotational symmetry) and increases the minimum distance between the well regions 110 and the floating diffusion node 108. As a result, the well regions 110 can improve electrical isolation between adjacent pixel regions (e.g., between pixel regions in adjacent shared pixel layout structures) across the substrate 102 while mitigating junction leakage between the floating diffusion node 108 and the well regions 110. This facilitates scaling down the device features of the image sensor while simultaneously improving electrical and optical isolation across the image sensor. In a further embodiment, the shared pixel layout structure of FIG. 1A has at least four-fold rotational symmetry with respect to the floating diffusion node 108, which makes the interaction of incident radiation uniform across the image sensor. As a result, the overall performance of the image sensor is improved due to reduced photo response non-uniformity (PRNU) and dark image non-uniformity (DINU) across the image sensor.

[0021] In various embodiments, the length and width of the intermediate isolation piece 116m is greater than the length and width of the floating diffusion node 108. In further embodiments, the length and width of the intermediate isolation piece 116m is greater than the length and width of each peripheral isolation piece 116p.

[0022] As shown in cross-sectional views 100b and 100c of FIGS. 1B-1C taken along lines A-A' and B-B', respectively, of FIG. 1A, the interconnect structure 104 covers the front surface 102f of the substrate 102. In some embodiments, the interconnect structure 104 includes a plurality of conductive vias 122 and a plurality of conductive wires 124 disposed within the interconnect dielectric structure 120. In some embodiments, the plurality of conductive vias 122 includes a plurality of conductive ground vias directly overlying and coupled to the well region 110, the conductive ground vias being configured to directly electrically couple the well region 110 to ground (e.g., 0 volts). Furthermore, the plurality of transfer gate structures 118 can include a transfer gate electrode and a transfer gate dielectric disposed between the substrate 102 and the transfer gate electrode. The transfer gate electrode can be or include, for example, aluminum, titanium, tantalum, polysilicon, another conductive material, or any combination thereof. The transfer gate dielectric may be or include, for example, silicon dioxide, a high-k dielectric material (eg, aluminum oxide, hafnium oxide), another dielectric material, or any combination thereof.

[0023] In various embodiments, the intermediate isolation component 116m and the peripheral isolation component 116p extend continuously from the back surface 102b of the substrate 102 toward the front surface 102f. The intermediate isolation component 116m is disposed below the floating diffusion node 108 and is separated from the front surface 102f by a first distance d1. In some embodiments, the first distance d1 is equal to the height of the floating diffusion node 108, so that the upper surface of the intermediate isolation component 116m contacts the bottom of the floating diffusion node 108. In further embodiments, the peripheral isolation component 116p is disposed below the corresponding well region 110 and is separated from the front surface 102f by the first distance d1. The intermediate isolation component 116m is disposed between the first pixel region 103a and the second pixel region 103b. In addition, an etch stop layer 126 is disposed on the front surface 102f of the substrate 102. In some embodiments, the etch stop layer 126 is disposed along the upper surface of the elongated isolation component 114.

[0024] In some embodiments, the plurality of long isolation elements 114 have a first height h1, and the plurality of short isolation elements 116m, 116p have a second height h2 that is less than the first height h1. By having the first height h1 greater than the second height h2, the long isolation elements 114 improve optical and electrical isolation between adjacent pixel regions 103. Also, by having the second height h2 of the short isolation elements 116m, 116p relatively small, damage to doped regions (e.g., floating diffusion nodes 108, well regions 110, etc.) of the image sensor is reduced while at the same time promoting electrical and optical isolation between the pixel regions 103. For example, during fabrication of the image sensor, an etching process can be performed on the back surface 102b of the substrate 102 to form an opening for the isolation structure 112. By performing the etching process, the opening for the long isolation element 114 is deeper than the opening for the short isolation elements 116m, 116p. This reduces damage to the floating diffusion node 108 and / or well region 110 during the etching process. As such, an image sensor including long isolation elements 114 and short isolation elements 116m, 116p having different heights can provide improved optical and electrical isolation throughout the image sensor while improving device stability and durability.

[0025] 2A-2C illustrate various 200a-200c embodiments of an image sensor having a plurality of well regions 110 and a plurality of pixel regions 103 separated by an isolation structure 112 including a plurality of isolation elements 114, 116m, 116p. FIG. 2A illustrates a top view 200a of the image sensor as viewed from the front surface 102f of the substrate 102. FIG. 2B illustrates a cross-sectional view 200b taken along line A-A' of the top view 200a of FIG. 2A. FIG. 2C illustrates a cross-sectional view 200c taken along line B-B' of the top view 200a of FIG. 2A. For simplicity and ease of illustration, structures in cross-sectional views 200b, 200c (e.g., interconnect dielectric structure 120) are omitted from top view 200a of FIG. 2A, and image sensor structures or regions in cross-sectional views 200b, 200c (e.g., photodetector 106, isolation components 116m, 116p) are indicated by dashed polygons and / or are at least partially transparent in top view 200a of FIG. 2A.

[0026] The image sensor includes an interconnect structure 104 disposed on a front surface 102f of the substrate 102. A plurality of pixel regions 103 are disposed across the substrate 102. Each pixel region 103 includes a photodetector 106 disposed within the substrate 102. An isolation structure 112 extends to a back surface 102b of the substrate 102 and laterally surrounds each photodetector 106. The isolation structure 112 is configured to provide isolation between adjacent pixel regions 103. In some embodiments, the isolation structure 112 includes a plurality of elongated isolation members 114, a middle isolation member 116m, and a plurality of peripheral isolation members 116p. The substrate 102 may be or include, for example, silicon, single crystal silicon, epitaxial silicon, germanium, silicon germanium, a III-V material (e.g., gallium nitride, etc.), another semiconductor material, etc. In some embodiments, the substrate 102 has a first doping type (e.g., p-type).

[0027] The interconnect structure 104 includes an interconnect dielectric structure 120, a plurality of conductive vias 122, and a plurality of conductive wires 124. The interconnect dielectric structure 120 may be or include, for example, one or more dielectric layers each including silicon dioxide, a low-k dielectric material, silicon nitride, silicon carbide, another dielectric material, or any combination thereof. As used herein, a low-k dielectric material is a dielectric material having a relative dielectric constant of less than 3.9. The conductive vias 122 and the conductive wires 124 may be or include, for example, aluminum, copper, ruthenium, tungsten, another conductive material, or any combination thereof.

[0028] The photodetector 106 is disposed within the substrate 102 and includes a second doping type (e.g., n-type) opposite to the first doping type (e.g., p-type). In some embodiments, the doping concentration of the photodetector 106 is about 5×10 11 From 5×10 14 atom / cm 3 or any other suitable range of values. In various embodiments, the image sensor includes a shared pixel layout structure including a plurality of pixel regions 103a-103d arranged around a floating diffusion node 108. The floating diffusion node 108 is disposed within the substrate 102 and includes a second doping type (e.g., n-type). In some embodiments, the doping concentration of the floating diffusion node 108 is about 10 13 From 10 16 atom / cm 3 or within any other suitable range of values. In a further embodiment, the doping concentration of the photodetector 106 is lower than the doping concentration of the floating diffusion node 108. The intermediate isolation piece 116m extends continuously from the back surface 102b of the substrate 102 towards the floating diffusion node 108.

[0029] A number of well regions 110 are disposed in the front surface 102f of the substrate 102. In some embodiments, the well regions 110 have a first doping type (e.g., p-type) and are about 10 13 ~10 16 atom / cm3 or any other suitable range of values. In various embodiments, the doping concentration of the well region 110 is equal to the doping concentration of the floating diffusion node 108. In further embodiments, the well region 110 is disposed at a corner or edge of the shared pixel layout structure, each diagonally disposed to a corresponding edge of the floating diffusion node 108. In some embodiments, the well region 110 is electrically coupled directly to a reference voltage, e.g., ground (e.g., 0 volts), and configured to bias the substrate 102 with the reference voltage. In further embodiments, the well region 110 is referred to as a ground well region. The placement of the well region 110 at a corner or edge of the shared pixel layout structure results in a highly symmetrical image sensor layout (e.g., having at least four-fold rotational symmetry with respect to a central region of the plurality of pixel regions 103a-103d), thereby reducing photo response non-uniformity (PRNU) and dark image non-uniformity (DINU) across the image sensor. Furthermore, by placing the well regions 110 at the corners or edges of the shared pixel layout structure, the minimum distance between the well regions 110 and the floating diffusion nodes 108 is increased, thereby reducing junction leakage across the image sensor.

[0030] The plurality of transfer gate structures 118 may be disposed on the substrate 102 and disposed with the corresponding photodetectors 106. The transfer gate structures 118 are configured to control current flow between the floating diffusion nodes 108 and the corresponding photodetectors 106. Furthermore, the plurality of transfer gate structures 118 may include a transfer gate electrode and a transfer gate dielectric disposed between the substrate 102 and the transfer gate electrode. In some embodiments, as shown in the cross-sectional view 200b of FIG. 2B, the transfer gate structures 118 each include a gate body 118a disposed on the front surface 102f of the substrate 102 and a gate protrusion 118b extending to the front surface 102f. In such embodiments, the transfer gate structures 118 are configured as vertical gate structures, which may enhance the ability of the transfer gate structures 118 to control current flow between the floating diffusion nodes 108 and the photodetectors 106.

[0031] In various embodiments, the intermediate isolation components 116m are disposed at the intersections of the pixel regions 103a-103d, and the peripheral isolation components 116p are disposed at the corners or edges of the shared pixel layout structure. The peripheral isolation components 116p extend continuously from the back surface 102b of the substrate 102 toward the well region 110. The elongated isolation components 114 extend continuously laterally between adjacent peripheral isolation components 116p and directly contact both the intermediate isolation components 116m and the peripheral isolation components 116p. The elongated isolation components 114 have a first height h1, and the intermediate isolation components 116m and the peripheral isolation components 116p have a second height h2 that is less than the first height h1. The first height h1 being greater than the second height h2 improves isolation between adjacent pixel regions 103 without damaging doped regions (e.g., floating diffusion nodes 108, well regions 110, etc.) of the image sensor.

[0032] In some embodiments, the isolation structures 112 include a dielectric material (e.g., silicon dioxide, aluminum oxide, silicon carbide, silicon nitride, etc.), a conductive material (e.g., copper, aluminum, titanium nitride, tungsten, etc.), other materials, or any combination thereof. In further embodiments, the isolation structures 112 may include a liner layer and a trench fill structure (not shown), where the trench fill structure extends to the back surface 102b of the substrate 102, and the liner layer is disposed between the trench fill structure and the front surface of the substrate 102. In such embodiments, the liner layer may include a dielectric material (e.g., silicon dioxide, aluminum oxide, silicon nitride, etc.), and the trench fill structure may include a metallic material (e.g., aluminum, copper, tungsten, etc.). In various embodiments, the isolation structures 112 made of a metallic material may further improve optical isolation across the image sensor by reducing optical crosstalk between adjacent pixel regions.

[0033] As shown in cross-sectional view 200b of FIG. 2B, the gate protrusions 118b of adjacent transfer gate structures 118 are disposed between the floating diffusion node 108 and the adjacent well region 110. In various embodiments, the intermediate isolation piece 116m directly contacts the floating diffusion node 108 and the peripheral isolation piece 116p directly contacts the corresponding well region 110. In further embodiments, as shown in cross-sectional view 200c of FIG. 2C, the first width w1 of the intermediate isolation piece 116m is equal to the second width w2 of the floating diffusion node 108. In some embodiments, the elongated isolation pieces are disposed on opposite sides of and contact the floating diffusion node 108.

[0034] 3A and 3B show cross-sectional views 300a and 300b of some embodiments of an image sensor corresponding to some other embodiments of the image sensor of FIGS. 1A-1C, in which the floating diffusion node 108 and the well region 110 are vertically separated from the intermediate and peripheral isolation components 116m, 116p. In some embodiments, the cross-sectional views 300a and 300b of FIGS. 3A and 3B are taken along lines A-A' and B-B', respectively, of the top view 100a of FIG. 1A. In various embodiments, the contact etch stop layer (CESL) 302 extends continuously along the front surface 102f of the substrate 102. In some embodiments, the contact etch stop layer (CESL) 302 extends continuously from the top of the well region 110 to the sidewall of the transfer gate structure 118.

[0035] 4A and 4B show cross-sectional views 400a and 400b of some embodiments of an integrated chip (IC) including a pixel chip 406 having multiple well regions 110 and multiple pixel regions 103 separated by an isolation structure 112 including multiple isolation components 114, 116m, 116p. In some embodiments, the cross-sectional views 400a and 400b of Figures 4A and 4B are taken along lines A-A' and B-B' of the top view 100a of Figure 1A.

[0036] As shown in FIG. 4A, an integrated circuit (IC) includes a first chip 402, a second chip 404, and a pixel chip 406. The pixel chip 406 includes an image sensor of the present invention (e.g., the image sensor of FIG. 1A-FIG. 1C, the image sensor of FIG. 2A-FIG. 2C, or the image sensor of FIG. 3A-FIG. 3B). For example, the pixel chip 406 includes a plurality of pixel regions 103, a plurality of photodetectors 106, an isolation structure 112, a floating diffusion node 108, a well region 110, etc. It should be understood that the first chip 402, the second chip 404, and a portion of the interconnect structure 104 are omitted from the cross-sectional view 400b of FIG. 4B for ease of illustration.

[0037] The first chip 402 includes a first substrate 408, a first interconnect structure 410, and a first plurality of semiconductor devices 412 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)). In various embodiments, the first interconnect structure 410 includes a dielectric structure 414, a plurality of conductive wires 416, and a plurality of conductive vias 418. The first interconnect structure 410 is configured to electrically couple the first plurality of semiconductor devices 412 to other semiconductor devices and / or structures (e.g., devices and / or structures of the second chip 404 and / or the pixel chip 406). In some embodiments, the first chip 402 may be configured as an application-specific integrated circuit (ASIC).

[0038] The second chip 404 includes a backside bonding structure 420, a second substrate 422, a second interconnect structure 430, and a second plurality of semiconductor devices 428 (e.g., MOSFETs). The second interconnect structure 430 may include a dielectric structure 414, a plurality of conductive wires 416, and a plurality of conductive vias 418. The second interconnect structure 430 is configured to electrically couple the second plurality of semiconductor devices 428 to other semiconductor devices and / or structures (e.g., devices and / or structures of the first chip 402 and / or pixel chip 406). The backside bonding structure 420 is disposed on a backside 422b of the second substrate 422, and the second interconnect structure 430 is disposed on a frontside 422f of the second substrate 422. In some embodiments, the backside bonding structure 420 includes a bonding dielectric structure 424 and a conductive wire 416. In various embodiments, a plurality of through-substrate vias (TSVs) 426 extend continuously from the backside bonding structure 420 through the second substrate 422 to the second interconnect structure 430. The plurality of through-substrate vias (TSVs) 426 electrically couple the backside bonding structure 420 to the second interconnect structure 430. In various embodiments, the second plurality of semiconductor devices 428 may include, for example, one or more reset transistors, one or more source follower transistors, other suitable pixel devices, or any combination thereof. In such embodiments, the second plurality of semiconductor devices 428 may be configured to provide a digital readout of the plurality of photodetectors 106.

[0039] In various embodiments, a plurality of optical filters 432 are disposed on the back surface 102b of the substrate 102. The optical filters 432 directly cover the photodetectors 106. The grating structure 434 directly covers the isolation structure 112 and is configured to reduce optical crosstalk between the photodetectors 106. Further, a plurality of microlenses 436 are disposed above the optical filters 432. The microlenses 436 are configured to direct incident electromagnetic radiation towards the photodetectors 106.

[0040] 5-19B illustrate various views 500-1900b of several embodiments of a method for forming an image sensor including an isolation structure having multiple isolation components and multiple well regions with symmetrical layouts. Although the various views 500-1900b illustrated in FIGS. 5-19B are described with respect to the method, the structures illustrated in FIGS. 5-19B are not limited to the method and may exist independently of the method. Additionally, although FIGS. 5-19B are described as a series of operations, the order of these operations may be changed in alternative embodiments, and the disclosed methods are applicable to other structures. In alternative embodiments, some of the operations illustrated and / or described may be omitted in whole or in part.

[0041] As shown in the cross-sectional view 500 of FIG. 5, a plurality of photodetectors 106 are formed in a substrate 102. The substrate 102 may be or include, for example, silicon, single crystal silicon, epitaxial silicon, germanium, silicon germanium, III-V materials (e.g., gallium nitride, etc.), other semiconductor materials, etc., and may have a first doping type (e.g., p-type). In some embodiments, the process of forming the photodetectors 106 includes selectively forming a masking layer (not shown) on the front surface 102f of the substrate 102, performing a selective ion implantation process on the substrate 102 with the masking layer disposed thereon, thereby implanting one or more dopants in the substrate 102, and performing a removal process to remove the masking layer. Each photodetector 106 is disposed in a corresponding pixel region 103, for example, the first pixel region 103a and the second pixel region 103b each include a photodetector 106. In various embodiments, the photodetector 106 includes a second doping type (e.g., n-type) opposite to the first doping type (e.g., p-type). In some embodiments, the doping concentration of the photodetector 106 is higher than the doping concentration of an area adjacent to the substrate 102 and / or surrounding areas.

[0042] As shown in cross-sectional view 600 of FIG. 6, the floating diffusion node 108 and the plurality of well regions 110 are formed in the substrate 102. In some embodiments, the floating diffusion node 108 includes a second doping type (e.g., n-type) and the well region 110 includes a first doping type (p-type). In various embodiments, the doping concentration of the floating diffusion node 108 and the doping concentration of the well region 110 are both higher than the doping concentration of the photodetector 106. In further embodiments, the well region 110 is also referred to as a ground well region. In further embodiments, the floating diffusion node 108 and the plurality of well regions 110 can each be formed by a separate doping process that includes forming a masking layer (not shown) over the substrate 102, providing the masking layer and performing an ion implantation process to implant one or more dopants into the substrate 102, and performing a removal process to remove the masking layer. Furthermore, the floating diffusion node 108, well region 110, and photodetector 106 may be formed such that the doped regions described above have the same layout as shown and / or described in top view 100a of FIG. 1A or top view 200a of FIG. 2A.

[0043] As shown in cross-sectional view 700 of FIG. 7, a plurality of transfer gate structures 118 are formed on the front surface 102f of the substrate 102. In some embodiments, the transfer gate structures 118 each include a transfer gate electrode disposed on the substrate 102 and a transfer gate dielectric disposed between the transfer gate electrode and the substrate 102. In various embodiments, a process for forming the transfer gate structures 118 includes depositing a transfer gate dielectric on the substrate 102 (e.g., by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.), depositing a transfer gate electrode on the transfer gate dielectric (e.g., by PVD, CVD, sputtering, electroplating, etc.), and performing a patterning process on the transfer gate electrode and the transfer gate dielectric. In various embodiments, the transfer gate structures 118 are formed such that each transfer gate structure includes a gate body overlying a gate protrusion, and the gate protrusion extends continuously from the gate body to the front surface 102f of the substrate 102, as shown and / or described in Figures 2A-2C.

[0044] As shown in cross-sectional view 800 of FIG. 8, the interconnect structure 104 is formed on the front surface 102f of the substrate 102. The interconnect structure 104 includes a contact etch stop layer (CESL) 302, an interconnect dielectric structure 120, a plurality of conductive vias 122, and a plurality of conductive wires 124. In various embodiments, the contact etch stop layer (CESL) 302 and the interconnect dielectric structure 120 can be formed by one or more deposition processes, such as a PVD process, a CVD process, an ALD process, other suitable growth or deposition process, or any combination thereof. In further embodiments, the plurality of conductive vias 122 and the plurality of conductive wires 124 can be formed by one or more deposition processes, one or more patterning processes, one or more planarization processes, other suitable fabrication processes, or any combination thereof.

[0045] 9, a second chip 404 is provided bonded to the interconnect structure 104. In various embodiments, the second chip 404 includes a second interconnect structure 430 disposed along a front surface 422f of the second substrate 422 and a second plurality of semiconductor devices 428 disposed within and / or on the second substrate 422. In various embodiments, the second chip 404 is bonded to the interconnect structure 104 by a eutectic bonding process, a fusion bonding process, a hybrid bonding process, or other suitable bonding process.

[0046] 10, the backside bonding structure 420 and the plurality of through-substrate vias (TSVs) 426 are formed on and / or in the second substrate 422. In some embodiments, the backside bonding structure 420 and the plurality of through-substrate vias (TSVs) can be formed by one or more deposition processes, one or more patterning processes, one or more planarization processes, one or more ion implantation processes, other suitable manufacturing processes, or any combination thereof.

[0047] As shown in cross-sectional view 1100 of Figure 11, a first chip 402 bonded to a second chip 404 is provided. In some embodiments, the first chip 402 includes a first substrate 408, a first interconnect structure 410, and a first plurality of semiconductor devices 412 disposed within and / or on the first substrate 408. In various embodiments, the first chip 402 is bonded to the second chip 404 by a eutectic bonding process, a fusion bonding process, a hybrid bonding process, or other suitable bonding process.

[0048] 12, the substrate 102 is subjected to a thinning process to reduce the initial thickness Ti of the substrate 102 to a thickness Ts. In various embodiments, the thinning process includes performing a mechanical grinding process, a chemical mechanical planarization (CMP) process, an etching process, other thinning processes, or any combination thereof.

[0049] As shown in top view 1300a of FIG. 13A and cross-sectional views 1300b-1300c of FIGS. 13B-13C taken along lines A-A' and B-B', respectively, in the top view 1300a, in some embodiments, a hard mask structure 1302 is formed on the back surface 102b of the substrate 102. It should be noted that for ease of illustration, the first chip (402 in FIG. 12), the second chip (404 in FIG. 12), and a portion of the interconnect structure (104 in FIG. 12) are omitted from other subsequent views in the method of FIGS. 13A-13B and 5-19B. In various embodiments, the hard mask structure 1302 includes a plurality of components, where a first hard mask component is aligned over the floating diffusion node 108 and a plurality of peripheral hard mask components are aligned with corresponding well regions 110. In some embodiments, the first hard mask components are larger than each individual peripheral hard mask component.

[0050] As shown in top view 1400a of FIG. 14A and cross-sectional views 1400b-1400c of FIG. 14B-14C taken along lines A-A' and B-B', respectively, in top view 1400a, in some embodiments, an upper dielectric structure 1402 is formed over hard mask structure 1302. In some embodiments, upper dielectric structure 1402 includes a first dielectric layer 1404, a second dielectric layer 1406, and a third dielectric layer 1408.

[0051] As shown in top view 1500a of FIG. 15A and cross-sectional views 1500b-1500c of FIG. 15B-15C taken along lines A-A' and B-B', respectively, in top view 1500a, in some embodiments, photoresist 1502 is formed over upper dielectric structure 1402. In various embodiments, photoresist 1502 is formed to include sidewalls that define a plurality of openings 1504 over upper dielectric structure 1402. In various embodiments, a width of one or more of openings 1504 is smaller than a width of a corresponding lower hardmask component of hardmask structure 1302, as shown in cross-sectional view 1500b of FIG. 15B.

[0052] As shown in top view 1600a of FIG. 16A and cross-sectional views 1600b-1600c of FIGS. 16B-16C taken along lines A-A' and B-B', respectively, in the top view 1600a, in some embodiments, an etching process is performed on the substrate 102 to form an isolation structure trench including a plurality of first parts 1602 having a first depth dp1 and a plurality of second parts 1604 having a second depth dp2. In various embodiments, the substrate 102 etches faster than the hard mask structure 1302 during the etching process, such that the first depth dp1 is less than the second depth dp2. In some embodiments, the etch rate ratio of the substrate 102 to the hard mask structure 1302 is within a range of about 2:1 to 15:1, or other suitable values. In further embodiments, the thickness of the hard mask structure 1302 can be determined based on the etch rate ratio of the substrate 102 to the hard mask structure 1302 during the etching process used to form the isolation structure trench. In various embodiments, the etching process may be a dry etch process, a wet etch process, or a combination thereof. The hard mask structure 1302 etches slower than the substrate 102 during the etching process, thereby reducing the depth of the first part 1602 of the isolation structure trench by the hard mask structure 1302. This makes the first depth dp1 somewhat shallower than the second depth dp2, thereby preventing damage to the floating diffusion node 108 and / or the well region 110 during the etching process.

[0053] As shown in top view 1700a of Figure 17A and cross-sectional views 1700b-1700c of Figures 17B-17C taken along lines A-A' and B-B', respectively, in top view 1700a, in some embodiments, trench fill material 1702 is formed on and / or in substrate 102. In various embodiments, trench fill material 1702 is formed by a CVD process, a PVD process, an ALD process, a sputtering process, an electroplating process, or other suitable growth or deposition process.

[0054] As shown in top view 1800a of FIG. 18A and cross-sectional views 1800b-1800c of FIGS. 18B-18C taken along lines A-A' and B-B' in top view 1800a, respectively, in some embodiments, the trench fill material (1702 in FIGS. 17A-17C) is subjected to a planarization process to define an isolation structure 112 including a plurality of long isolation elements 114, a middle isolation element 116m, and a plurality of peripheral isolation elements 116p. In various embodiments, the plurality of short isolation elements 116m, 116p includes a middle isolation element 116m disposed at an intersection of pixel regions 103a-103d and a plurality of peripheral isolation elements 116p disposed in alignment with the plurality of well regions 110. In various embodiments, by placing a hard mask structure (1302 in FIGS. 17A-17C) before forming a photoresist (1502 in FIGS. 17A-17C), the elongated isolation components 114, the intermediate isolation components 116m, and the peripheral isolation components 116p of the isolation structure 112 can be formed in a single photolithography process, thereby reducing overlap and error problems and reducing damage to the floating diffusion nodes 108 and well regions 110.

[0055] As shown in top view 1900a of FIG. 19A and cross-sectional view 1900b of FIG. 19B taken along line A-A' in top view 1900a, in some embodiments, a grating structure 434, a plurality of light filters 432, and a plurality of microlenses 436 are formed on the back surface 102b of the substrate 102. For ease of illustration, the light filters 432, the grating structure 434, and the microlenses 436 are shown on the pixel regions 103a-103d in FIG. 19A and omitted from other regions on the substrate 102. The grating structure 434 can be formed by depositing a grating material directly over the isolation structure 112, on the substrate 102, and patterning the grating material to form the grating structure 434. The light filters 432 can be formed by depositing and patterning color filter layers corresponding to the plurality of light filters 432. In various embodiments, the microlenses 436 can be formed by depositing a microlens material over the light filter 432 and patterning the microlens material to form a plurality of microlenses 436 .

[0056] FIG. 20 illustrates some embodiments of a method 2000 for forming an image sensor including a plurality of well regions and a plurality of pixel regions separated by an isolation structure having a plurality of isolation components. Although the method 2000 is illustrated and / or described as a series of operations or events, it should be noted that the method is not limited to the order or operations shown. Thus, in some embodiments, operations may be performed in an order different from the order shown and / or may be performed simultaneously. Furthermore, in some embodiments, an illustrated operation or event may be subdivided into multiple acts or events, which may be performed at separate times or simultaneously with other operations or sub-operations. In some embodiments, some illustrated operations or events may be omitted and other unillustrated operations or events may be included.

[0057] In an operation 2002, a plurality of photodetectors are formed in a substrate. The photodetectors are arranged in a plurality of pixel regions. Figure 5 illustrates a cross-sectional view 500 corresponding to some embodiments of operation 2002.

[0058] In operation 2004, floating diffusion nodes are formed at intersections of the pixel regions and well regions are formed at corners of the pixel regions. Figure 6 illustrates a cross-sectional view 600 corresponding to some embodiments of operation 2004.

[0059] In an operation 2006, a plurality of transfer gate structures are formed on the front side of the substrate. Figure 7 illustrates a cross-sectional view 700 corresponding to some embodiments of operation 2006.

[0060] In an operation 2008, an interconnect structure is formed on the front side of the substrate. Figure 8 illustrates a cross-sectional view 800 corresponding to some embodiments of operation 2008.

[0061] In operation 2010, the first chip and the second chip are bonded to the interconnect structure. Figures 9-11 show cross-sectional views 900-1100 corresponding to some embodiments of operation 2010.

[0062] In an operation 2012, the substrate is subjected to a thinning process. Figure 12 illustrates a cross-sectional view 1200 corresponding to some embodiments of operation 2012.

[0063] In operation 2014, a hardmask structure is formed on the backside of the substrate. The hardmask structure includes hardmask components aligned with the floating diffusion nodes and well regions. Figures 13A-13C show various views corresponding to some embodiments of operation 2014.

[0064] In an operation 2016, a photoresist is formed over the hard mask structure. The photoresist overlies the hard mask structure and includes sidewalls that define openings that periphery surround a plurality of pixel regions. Figures 15A-15C show various views corresponding to some embodiments of operation 2016.

[0065] In operation 2018, an etching process is performed on the substrate to form an isolation structure trench including a plurality of first parts having a first depth in the substrate and a plurality of second parts having a second depth deeper than the first depth. The first parts are aligned with the hard mask parts. Figures 16A-16C show various views corresponding to some embodiments of operation 2018.

[0066] In an operation 2020, an isolation structure is formed in the isolation structure trench, the isolation structure including a plurality of elongated isolation pieces, a middle isolation piece, and a plurality of peripheral isolation pieces. The elongated isolation pieces have a first height, and the middle and peripheral isolation pieces have a second height that is less than the first height. Figures 17A-17C and 18A-18C show various views corresponding to some embodiments of operation 2020.

[0067] In an operation 2022, a plurality of optical filters is formed on the back surface, and a plurality of microlenses is formed on the plurality of optical filters. Figures 19A-19B show various views corresponding to some embodiments of operation 2022.

[0068] It should be noted that in some embodiments, the method of Figures 5-19B can instead proceed from Figures 5-8 to Figures 12-19B (i.e., skipping Figures 9-11). In such embodiments, the first chip (402, Figure 12) and the second chip (404, Figure 12) can be omitted, and the thinning process of Figure 12 can be performed immediately after forming the interconnect structure (104, Figure 8) on the substrate (102, Figure 8).

[0069] 21-23, cross-sectional views 2100-2300 illustrate alternative operations that can be performed in place of those of FIGS. 13A-13C and 14A-14C. In one embodiment, the method of FIGS. 5-19B can proceed alternatively from FIGS. 5-12 to FIG. 21, and then from FIG. 21 to FIG. 15A-19B (i.e., skipping the operations of FIGS. 13A-13C and 14A-14C). In another embodiment, the method of FIGS. 5-19B can proceed alternatively from FIGS. 5-12 to FIG. 22, and then from FIG. 22 to FIG. 15A-19B (i.e., skipping the operations of FIGS. 13A-13C and 14A-14C). In yet another embodiment, the method of Figures 5-19B may proceed alternatively from Figures 5-12 to Figure 23, and then proceed alternatively from Figure 23 to Figures 15A-19B (i.e., skipping the actions of Figures 13A-13C and Figures 14A-14C).

[0070] As shown in cross-sectional view 2100 of FIG. 21, a hard mask structure 1302 and an upper dielectric structure 1402 are formed on the back surface 102b of the substrate 102. In various embodiments, the hard mask structure 1302 includes a multi-layer stack of hard mask layers. For example, the hard mask structure 1302 can include a first hard mask layer 2102, a second hard mask layer 2104, and a third hard mask layer 2106. The first hard mask layer 2102 is disposed on the substrate 102, the second hard mask layer 2104 is disposed on the first hard mask layer 2102, and the third hard mask layer 2106 is disposed on the second hard mask layer 2104. In various embodiments, the first, second, and third hard mask layers 2102-2106 include the same material (e.g., oxide, nitride, etc.). In further embodiments, the first hard mask layer 2102 includes a first material (e.g., silicon dioxide), the second hard mask layer 2104 includes a second material (e.g., silicon nitride), and the third hard mask layer 2106 includes a third material (e.g., silicon carbide), and the first material, the second material, and the third material are different from each other. The hard mask structure 1302 is composed of a multi-layer stack, so that the etching rate of the hard mask structure 1302 can be appropriately set in the etching process of Figures 16A-16C so that the first part (1602 in Figures 16A-16C) has a first depth dp1. In various embodiments, the hard mask structure 1302 includes hard mask parts (e.g., as shown in top view 1300a of Figure 13A) that cover the floating diffusion node 108 and the well region 110, respectively.

[0071] As shown in the cross-sectional view 2200 of FIG. 22, a hard mask structure 1302 and an upper dielectric structure 1402 are formed on the back surface 102b of the substrate 102. In some embodiments, the hard mask structure 1302 includes a single hard mask layer. Furthermore, the upper dielectric structure 1402 includes a first dielectric layer 1404, a second dielectric layer 1406, and a third dielectric layer 1408, and the hard mask structure 1302 is embedded in the first dielectric layer 1404 and vertically offset from the back surface 102b of the substrate 102. In various embodiments, the hard mask structure 1302 includes hard mask parts (e.g., as shown in the top view 1300a of FIG. 13A) that cover the floating diffusion node 108 and the well region 110, respectively.

[0072] As shown in cross-sectional view 2300 of FIG. 23, a hard mask structure 1302 and an upper dielectric structure 1402 are formed on the back surface 102b of the substrate 102. In various embodiments, the hard mask structure 1302 includes a multi-layer stack of hard mask layers. For example, the hard mask structure 1302 can include a first hard mask layer 2302 and a second hard mask layer 2304. In various embodiments, the first and second hard mask layers 2302-2304 include the same material (e.g., an oxide, a nitride, etc.). In further embodiments, the first hard mask layer 2302 includes a first material (e.g., silicon dioxide) and the second hard mask layer 2304 includes a second material different from the first material (e.g., silicon nitride). The hard mask structure 1302 is configured as a multi-layer stack, so that the etching rate of the hard mask structure 1302 can be appropriately set in the etching process of FIGS. 16A-16C so that the first component (1602 in FIGS. 16A-16C) has a first depth dp1. In various embodiments, the hard mask structure 1302 includes hard mask components (e.g., as shown in top view 1300a in FIG. 13A) covering the floating diffusion node 108 and the well region 110, respectively. Furthermore, the upper dielectric structure 1402 includes a first dielectric layer 1404, a second dielectric layer 1406, and a third dielectric layer 1408, and the hard mask structure 1302 is embedded in the first dielectric layer 1404 and vertically offset to the back surface 102b of the substrate 102.

[0073] Thus, in some embodiments, the present invention relates to an image sensor including a plurality of pixel regions disposed within a substrate, a floating diffusion node disposed at an intersection of the plurality of pixel regions, and a plurality of well regions disposed diagonally around the edges of the floating diffusion node. Additionally, an isolation structure is disposed within the substrate and includes a plurality of elongated isolation elements, a middle isolation element disposed at the intersection, and a peripheral isolation element aligned with the well regions. The elongated isolation elements have a first height, and the middle and peripheral isolation elements have a second height less than the first height.

[0074] In some embodiments, the present invention provides an image sensor. The image sensor includes a plurality of photodetectors disposed in a substrate, the photodetectors being disposed in a plurality of pixel regions, respectively. The image sensor also includes a floating diffusion node disposed along a front surface of the substrate in a middle region of the plurality of pixel regions, a plurality of well regions disposed in the substrate at corners of the plurality of pixel regions, and an isolation structure extending to a back surface of the substrate, the isolation structure including a plurality of elongated isolation pieces disposed between adjacent pixel regions, a middle isolation piece aligned with the floating diffusion node, and a plurality of peripheral isolation pieces aligned with the plurality of well regions, the elongated isolation pieces having a first height, and the middle and peripheral isolation pieces having a second height less than the first height. In one embodiment, the well regions are each separated from the floating diffusion node by a corresponding one of the plurality of photodetectors. In one embodiment, the image sensor further includes a plurality of conductive ground vias directly overlying and electrically coupled to the well regions. In one embodiment, the isolation structure, the floating diffusion node, and the plurality of well regions have at least four-fold rotational symmetry. In one embodiment, when viewed from a top view, the intermediate isolation component and the peripheral isolation component each have a cross shape, and when viewed from a cross-sectional view, the intermediate isolation component and the peripheral isolation component each have a rectangle. In one embodiment, the well region has a first doping type, the photodetector has a second doping type, and the floating diffusion node has a second doping type, the first doping type being opposite to the second doping type, and the doping concentration of the floating diffusion node and the well region is higher than the doping concentration of the photodetector. In one embodiment, the image sensor further includes a plurality of gate structures covering the pixel region, and a minimum distance between the floating diffusion node and a nearest well region of the plurality of well regions is greater than a width of an individual gate structure in the plurality of gate structures. In one embodiment, each of the plurality of gate structures includes a gate body disposed at a front surface and a gate protrusion extending to the front surface, and the gate protrusion is disposed laterally directly between the floating diffusion node and the plurality of well regions.In one embodiment, the distance between the front surface of the substrate and the intermediate isolation component is greater than the height of the floating diffusion node. In one embodiment, the width and length of the intermediate isolation component are greater than the width and length of each of the peripheral isolation components in the plurality of peripheral isolation components.

[0075] In some embodiments, the present invention provides an image sensor. The image sensor includes a plurality of pixel regions disposed in a substrate, a plurality of transfer gate structures disposed on a front surface of the substrate, the transfer gate structures being disposed in the plurality of pixel regions, a floating diffusion node disposed in the substrate at an intersection of the plurality of pixel regions, and a plurality of well regions disposed in the substrate, the well regions being located diagonally from corresponding edges of the floating diffusion nodes, and an isolation structure extending on a back surface of the substrate and extending laterally between the plurality of pixel regions, the isolation structure including an intermediate isolation element disposed with the floating diffusion nodes, a plurality of peripheral isolation elements disposed with the well regions, and a plurality of elongated isolation elements extending laterally between the intermediate isolation element and the peripheral isolation element, the first depth of the elongated isolation element being greater than the second depth of the intermediate and peripheral isolation elements. In one embodiment, the minimum distance between the floating diffusion node and the well region is greater than the diagonal length of the floating diffusion node. In one embodiment, the image sensor further includes an etch stop layer disposed on the front side of the substrate, the elongated isolation element directly contacting the etch stop layer, and the intermediate and peripheral isolation elements being vertically offset from the etch stop layer. In one embodiment, the length of the intermediate isolation element is equal to the length of the floating diffusion node, and the width of the intermediate isolation element is equal to the width of the floating diffusion node. In one embodiment, a first elongated isolation element of the plurality of elongated isolation elements includes a first sidewall aligned with a sidewall of a first peripheral isolation element of the plurality of peripheral isolation elements, and the first elongated isolation element includes a second sidewall aligned with the sidewall of the intermediate isolation element and perpendicular to the first sidewall.

[0076] In some embodiments, the present invention provides a method of forming an image sensor, the method including: forming a plurality of photodetectors in a substrate, the photodetectors being respectively disposed in a plurality of pixel regions; doping the substrate to form floating diffusion nodes at intersections of the plurality of pixel regions and forming a plurality of well regions diagonally on edges of the floating diffusion nodes; forming a hard mask structure on a back surface of the substrate, the hard mask structure including a first hard mask component aligned with the floating diffusion nodes and a plurality of second hard mask components aligned with the well regions; performing an etching process on the substrate on which the hard mask structure is disposed to form an isolation structure trench in the substrate, the isolation structure trench including a plurality of first components having a first depth and a plurality of second components having a second depth deeper than the first depth, the first components being aligned with the floating diffusion nodes and the well regions; forming an isolation structure in the isolation structure trench, the isolation structure including a middle isolation component and a plurality of peripheral isolation components having the first depth and a plurality of elongated isolation components having the second depth. In one embodiment, forming the isolation structure includes depositing a trench fill layer in the isolation structure trench, the trench fill layer contacting a sidewall of the hard mask structure, and performing a planarization process on the trench fill layer and the hard mask structure. In one embodiment, a width of the first hard mask element is greater than a width of the second hard mask element. In one embodiment, the second hard mask elements are laterally offset from the first hard mask element by respective corresponding photodetectors of the plurality of photodetectors. In one embodiment, the hard mask structure includes a first hard mask layer and a second hard mask layer covering the first hard mask layer.

[0077] The above outlines features of some embodiments to allow those skilled in the art to better understand aspects of the present invention. It should be appreciated by those skilled in the art that other processes and structures can be designed or modified based on the present invention to carry out the same purpose and / or achieve the same advantages of the embodiments described herein. It should also be appreciated by those skilled in the art that such equivalent structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present invention. [Industrial Applicability]

[0078] The present invention provides a new image sensor and method of forming the image sensor. [Explanation of symbols]

[0079] 100a, 200a, 1300a, 1400a, 1500a, 1600a, 1700a, 1800a, 1900a Top view 100b, 100c, 200b, 200c, 300a, 300b, 400a, 400b, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300b, 1300c, 1400b, 1400c, 1500b, 1500c, 1600b, 1600c, 1700b, 1700c, 1800b, 1800c, 1900b, 2100, 2200, 2300 Cross section 102 Substrate 102b, 422b back side 102f, 422f front 103 Pixel Area 103a first pixel region 103b second pixel region 103c third pixel region 103d 4th pixel area 104 Interconnect Structure 106 Photodetector 108 Floating Diffusion Nodes 110 Well Area 112 Separation structure 114 Separation parts / Long separation parts 116m Separation Parts / Short Separation Parts / Middle Separation Parts 116p Separation parts / Short separation parts / Peripheral separation parts 118 Transfer Gate Structure 118a Gate body 118b Gate protrusion 120 Interconnecting Dielectric Structures 122, 418 Conductive Vias 124, 416 Conductive Wire 126 Etch stop layer 302 Contact Etch Stop Layer (CESL) 402 First Chip 404 2nd Chip 406 pixel chip 408 First Board 410 First interconnect structure 412, 428 Semiconductor devices 414 Dielectric Structure 420 Back joint structure 422 Second board 424 Bonded Dielectric Structure 426 Through Substrate Via (TSV) 430 Second interconnect structure 432 Optical Filter 434 Lattice structure 436 Micro Lens 1302 Hard mask structure 1402 Upper dielectric structure 1404 First dielectric layer 1406 Second dielectric layer 1408 Third Dielectric Layer 1502 Photoresist 1504 Aperture 1602 1st part 1604 2nd part 1702 Trench filling material 2000 methods 2002, 2004, 2006, 2008, 2010, 2012, 2014, 2016, 2018, 2020, 2022 operation 2102, 2302 First hard mask layer 2104, 2304 Second hard mask layer 2106 3rd hard mask layer d1 First distance dp1 First depth dp2 Second depth h1 First height h2 Second height Ti, Ts thickness w1 1st width w2 Second width

Claims

1. a plurality of photodetectors disposed within the substrate, each photodetector being disposed within a respective one of a plurality of pixel regions; a floating diffusion node disposed along a front surface of the substrate in an intermediate region of the plurality of pixel regions; a plurality of well regions disposed in the substrate at corners of the plurality of pixel regions; an isolation structure extending to a backside of the substrate; the isolation structure includes a plurality of elongated isolation elements disposed between adjacent pixel regions, a middle isolation element aligned with a floating diffusion node, and a plurality of peripheral isolation elements aligned with the plurality of well regions, the elongated isolation elements having a first height, and the middle and peripheral isolation elements having a second height less than the first height; a length of the intermediate isolation piece substantially equal to a length of the floating diffusion node; a width of the intermediate isolation piece substantially equal to a width of the floating diffusion node; The isolation structure, the floating diffusion node, and the plurality of well regions have at least four-fold rotational symmetry.

2. 2. The image sensor of claim 1, wherein each of the well regions is separated from the floating diffusion node by a corresponding one of the plurality of photodetectors.

3. 2. The image sensor of claim 1, wherein when viewed from a top view, the intermediate isolation piece and the peripheral isolation piece each have a cross shape, and when viewed from a cross-sectional view, the intermediate isolation piece and the peripheral isolation piece each have a rectangular shape.

4. further comprising a plurality of gate structures covering the pixel region; 2. The image sensor of claim 1, wherein a minimum distance between the floating diffusion node and a nearest one of the plurality of well regions is greater than a width of an individual gate structure in the plurality of gate structures.

5. 2. The image sensor of claim 1, wherein a distance between the front surface of the substrate and the intermediate isolation component is greater than a height of the floating diffusion node.

6. A plurality of pixel regions disposed within a substrate; a plurality of transfer gate structures disposed on a front surface of the substrate, each of the transfer gate structures being disposed within one of the pixel regions; a floating diffusion node disposed in the substrate at an intersection of the plurality of pixel regions; a plurality of well regions disposed within a substrate, each well region being diagonally disposed about a corresponding edge of the floating diffusion node; an isolation structure extending on a back surface of the substrate and extending laterally between the plurality of pixel regions; the isolation structure includes an intermediate isolation element disposed with the floating diffusion node, a plurality of peripheral isolation elements disposed with the well region, and a plurality of elongated isolation elements extending laterally between the intermediate isolation element and the peripheral isolation elements, a first depth of the elongated isolation elements being greater than a second depth of the intermediate and peripheral isolation elements; a length of the intermediate isolation piece substantially equal to a length of the floating diffusion node; an intermediate isolation member having a width substantially equal to a width of the floating diffusion node, and the isolation structure, the floating diffusion node, and the plurality of well regions have at least four-fold rotational symmetry.

7. 7. The image sensor of claim 6, wherein a minimum distance between the floating diffusion node and a well region is greater than a diagonal length of the floating diffusion node.

8. forming a plurality of photodetectors in a substrate, the photodetectors being disposed within a plurality of pixel regions, respectively; doping the substrate to form floating diffusion nodes at intersections of the pixel regions and to form a plurality of well regions diagonally adjacent edges of the floating diffusion nodes; forming a hard mask structure on a back surface of the substrate, the hard mask structure including a first hard mask part aligned with the floating diffusion node and a plurality of second hard mask parts aligned with the well region; performing an etching process on the substrate on which the hard mask structure is disposed to form an isolation structure trench in the substrate, the isolation structure trench including a plurality of first components having a first depth and a plurality of second components having a second depth deeper than the first depth, the first components being aligned with the floating diffusion node and the well region, and the second components being positioned between adjacent pixel regions; forming an isolation structure in the isolation structure trench, the isolation structure including intermediate and peripheral isolation elements having a first depth and a plurality of elongated isolation elements having a second depth; Including, a length of the intermediate isolation piece substantially equal to a length of the floating diffusion node; a width of the intermediate isolation piece substantially equal to a width of the floating diffusion node; The method of forming an image sensor, wherein the isolation structure, the floating diffusion node, and the plurality of well regions have at least four-fold rotational symmetry.

9. forming the isolation structure depositing a trench fill layer in the isolation structure trench, the trench fill layer contacting a sidewall of the hard mask structure; performing a planarization process on the trench fill layer and the hard mask structure; 9. The method of claim 8, comprising:

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