CMOS circuits

Abstract

To provide a CMOS circuit that is highly resistant to single events.SOLUTION: A CMOS circuit includes a logical operation circuit obtained by combining a first conductivity type first transistor formed on a first conductivity type substrate and having at least a first well of a second conductivity type different from the first conductivity type with a second conductivity type second transistor having a first conductivity type second well, a first conductivity type third transistor having a second well connected to a gate terminal, and a second conductivity type fourth transistor the gate terminal of which is connected to the first well.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to CMOS circuits. [Background technology]

[0002] Conventionally, semiconductor integrated circuits such as CMOS (Complementary Metal Oxide Semiconductor) type LSI (Large Scale Integration), ASIC (Application Specific Integrated Circuit), FPGA (Field-Programmable Gate Array), GPU (Graphics Processing Unit), etc., have been used in various devices and equipment. In a CMOS type semiconductor integrated circuit, a function that performs a required operation is realized by forming a circuit by connecting a plurality of circuit elements such as transistors formed on a semiconductor substrate (e.g., a silicon substrate).

[0003] For example, CMOS type semiconductor integrated circuits used in outer space, such as artificial satellites orbiting the earth, are used in an environment where radiation such as high-energy charged particles is incident. It is also known that CMOS type semiconductor integrated circuits used on the ground are also affected by radiation such as neutrons. It is known that radiation incident on a CMOS type semiconductor integrated circuit can cause circuit elements formed on a semiconductor substrate to malfunction. More specifically, it is known that when a high-energy charged particle is incident on a CMOS type semiconductor integrated circuit, for example, a fluctuation in potential (so-called Single Event Transient: SET) or storage of erroneous data due to the propagation of a signal affected by the fluctuation in potential (so-called Single Event Upset: SEU) occurs.

[0004] Conventionally, various technologies have been disclosed for taking measures against single events such as single event transients and single event upsets (see Patent Document 1 and Non-Patent Document 1). For example, Patent Document 1 discloses that a circuit element is configured with a dual structure (vertical stacking structure) to prevent a malfunction caused by a single event generated by a high-energy charged particle from propagating to a downstream stage. For example, Non-Patent Document 1 discloses a technology relating to the design (structure) of an embedded circuit element that has increased resistance (robustness) against single event errors (soft errors). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2004-048170 A [Non-patent literature]

[0006] [Non-Patent Document 1] S. Mitra, N. Seifert, M. Zhang, Q. Shi, KSKim, “Robust system design with built-in soft-error resilience”, IEEE Computer Society, vol.38, no.2, pp.43-52, Feb.2005, doi:10.1109 / MC.2005.70. Summary of the Invention [Problem to be solved by the invention]

[0007] However, the technology disclosed in Patent Document 1 is effective only when circuit elements are formed on a semiconductor substrate with an SOI (Silicon on Insulator) structure. A semiconductor substrate with an SOI structure has an insulating layer provided inside the substrate, and is therefore more expensive than, for example, a single crystal silicon substrate (so-called a bulk substrate). Furthermore, in recent years, the manufacturing process of a CMOS type semiconductor integrated circuit has become finer. For this reason, it is no longer possible to expect a countermeasure effect against a single event from a circuit element to which a conventional technology is applied, as the manufacturing process becomes finer. This is because, in the conventional technology, a countermeasure against a single event is taken by providing a spatial distance between each component constituting the circuit element, but when the manufacturing process becomes finer, the circuit elements formed on the semiconductor substrate become smaller, and it becomes impossible to ensure a necessary distance between each component, and the countermeasure effect against a single event by the conventional technology is nullified.

[0008] The present invention has been made based on the above-mentioned problem recognition, and has an object to provide a CMOS circuit that is highly resistant to single events. [Means for solving the problem]

[0009] In order to achieve the above object, a CMOS circuit according to one embodiment of the present invention is a CMOS circuit formed on a substrate of a first conductivity type, and including: a logic operation circuit in which at least a first transistor of the first conductivity type having a first well of a second conductivity type different from the first conductivity type and a second transistor of the second conductivity type having a second well of the first conductivity type are combined; a third transistor of the first conductivity type having a gate terminal connected to the second well; and a fourth transistor of the second conductivity type having a gate terminal connected to the first well. Effect of the Invention

[0010] According to one aspect of the present invention, it is possible to increase the tolerance to single events in a CMOS circuit. [Brief description of the drawings]

[0011] [Figure 1] 1 is a diagram showing an example of the configuration of a CMOS circuit according to a first embodiment; [Diagram 2] 4 is a timing chart showing an example of a normal operation of the CMOS circuit according to the first embodiment. [Diagram 3] 2 is a diagram illustrating an example of a state in which high-energy charged particles are incident on the CMOS circuit according to the first embodiment. FIG. [Figure 4] 4 is a timing chart showing an example of an operation when a single event occurs due to a high-energy charged particle incident on the CMOS circuit according to the first embodiment. [Diagram 5] 4 is a diagram illustrating another example of how high-energy charged particles are incident on the CMOS circuit according to the first embodiment. FIG. [Figure 6] 10 is a timing chart showing another example of the operation when a single event occurs due to a high-energy charged particle incident on the CMOS circuit according to the first embodiment. [Figure 7] FIG. 4 is a diagram showing another example of the configuration of the CMOS circuit according to the first embodiment. [Figure 8] FIG. 4 is a diagram showing another example of the configuration of the CMOS circuit according to the first embodiment. [Figure 9] FIG. 4 is a diagram showing another example of the configuration of the CMOS circuit according to the first embodiment. [Figure 10] FIG. 11 is a diagram showing an example of the configuration of a CMOS circuit according to a second embodiment. [Figure 11] FIG. 13 is a diagram showing an example of the configuration of a CMOS circuit according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, with reference to the drawings, an embodiment of a CMOS (Complementary Metal Oxide Semiconductor) circuit of the present invention will be described. The CMOS circuit of the embodiment is a single logic operation circuit that performs a logic operation, such as a logical negation circuit (NOT circuit or inverter circuit), a logical sum circuit (OR circuit), a logical product circuit (AND circuit), a negative logical sum circuit (NOR circuit), a negative logical product circuit (NAND circuit), an exclusive logical sum circuit (EXOR circuit), or an exclusive negative logical sum circuit (EXNOR circuit). The CMOS circuit of the embodiment can be configured to transmit data (signal level) such as a buffer circuit or a transmission gate circuit, or to hold data (signal level) such as a latch circuit or a flip-flop circuit, by combining a plurality of single logic operation circuits. Furthermore, the CMOS circuit of the embodiment can be configured to store (memorize) data (signal level) such as an SRAM (Static Random Access Memory), by combining a plurality of single logic operation circuits, flip-flop circuits, transmission gate circuits, etc.

[0013] First Embodiment In the following description, for ease of explanation, a logical negation circuit (hereinafter referred to as an "inverter circuit"), which is a logical operation circuit with the simplest configuration, will be described as an example of the CMOS circuit of the first embodiment.

[0014] [Inverter circuit configuration] Fig. 1 is a diagram showing an example of the configuration of a CMOS circuit (inverter circuit) according to the first embodiment. The inverter circuit 1 includes a P-channel MOS transistor P1, an N-channel MOS transistor N1, a P-channel MOS transistor P2, and an N-channel MOS transistor N2. The inverter circuit 1 shown in Fig. 1 is an example in which each transistor is formed on a P-type single crystal semiconductor substrate (bulk substrate).

[0015] In the inverter circuit 1, the configuration of the P-channel MOS transistor P1 and the N-channel MOS transistor N1 is the configuration of a basic logical NOT circuit (inverter circuit) in a general logical operation circuit. In the following description, the inverter circuit with the basic configuration using the P-channel MOS transistor P1 and the N-channel MOS transistor N1 is called a "NOT basic circuit Bc1" to distinguish it from the inverter circuit 1 of the first embodiment.

[0016] The P-channel MOS transistor P1 has a gate terminal connected to the input terminal IN of the inverter circuit 1, a source terminal connected to the drain terminal of the P-channel MOS transistor P2, and a drain terminal connected to the drain terminal of the N-channel MOS transistor N1. The N-channel MOS transistor N1 has a gate terminal connected to the input terminal IN of the inverter circuit 1, a source terminal connected to the drain terminal of the N-channel MOS transistor N2, and a drain terminal connected to the drain terminal of the P-channel MOS transistor P1. The node where the drain terminal of the P-channel MOS transistor P1 and the drain terminal of the N-channel MOS transistor N1 are connected is the output terminal OUT of the inverter circuit 1.

[0017] In the inverter circuit 1, the P-channel MOS transistor P2 is disposed on the source terminal side of the P-channel MOS transistor P1, with the source terminal connected to a power supply VDD (potential fixed to the power supply) and the drain terminal connected to the source terminal of the P-channel MOS transistor P1. The gate terminal of the P-channel MOS transistor P2 is connected to the P-well Pw of the N-channel MOS transistor N1 (body of the N-channel MOS transistor N1 in FIG. 1). The N-channel MOS transistor N2 is disposed on the source terminal side of the N-channel MOS transistor N1, with the source terminal connected to the ground GND (potential fixed to the ground) and the drain terminal connected to the source terminal of the N-channel MOS transistor N1. The gate terminal of the N-channel MOS transistor N2 is connected to the N-well Nw of the P-channel MOS transistor P1 (body of the P-channel MOS transistor P1 in FIG. 1). The gate terminals of the P-channel MOS transistor P2 and the N-channel MOS transistor N2 may be connected to the corresponding wells, for example, by well contacts.

[0018] In the inverter circuit 1, the configuration of the P-channel MOS transistor P2 and the N-channel MOS transistor N2 may be said to be a power supply circuit of the NOT basic circuit Bc1. In the following description, the configuration of the P-channel MOS transistor P2 and the N-channel MOS transistor N2 is also referred to as a "power supply circuit."

[0019] The P-type single crystal semiconductor substrate is an example of a "first conductive type substrate" in the claims. The P-channel MOS transistor P1 is an example of a "first transistor" in the claims, and the N-channel MOS transistor N1 is an example of a "second transistor" in the claims. The N-well Nw is an example of a "first well" in the claims, and the P-well Pw is an example of a "second well" in the claims. The P-type and P-channel are examples of a "first conductive type" in the claims, and the N-type and N-channel are examples of a "second conductive type" in the claims. The NOT basic circuit Bc1 is an example of a "logical operation circuit" in the claims. The P-channel MOS transistor P2 is an example of a "third transistor" in the claims, and the N-channel MOS transistor N2 is an example of a "fourth transistor" in the claims.

[0020] [Operation of inverter circuit] The operation timing of the inverter circuit 1 will be described below. First, normal operation of the inverter circuit 1 will be described. FIG. 2 is a timing chart showing an example of normal operation of the CMOS circuit (inverter circuit 1) according to the first embodiment. FIG. 2 is a timing chart showing a normal state in which high-energy charged particles of radiation are not incident on the inverter circuit 1. In the following description, the "High" level of each signal in the inverter circuit 1 is the level of the power supply VDD (hereinafter referred to as the "VDD level"), and the "Low" level is the level of the ground GND (hereinafter referred to as the "GND level").

[0021] FIG. 2 shows the timing at which the signals at the input terminal IN, output terminal OUT, N-well Nw, and P-well Pw change and their signal levels when an input signal whose signal level changes between the VDD level and the GND level at a predetermined time interval is input to the input terminal IN of the inverter circuit 1.

[0022] In normal operation of the inverter circuit 1, the N-well Nw is at the VDD level, and the P-well Pw is at the GND level. In other words, the power supply circuit formed by the P-channel MOS transistor P2 and the N-channel MOS transistor N2 of the inverter circuit 1 is always on. Therefore, in normal operation of the inverter circuit 1, the input signal input to the input terminal IN is inverted with a timing delayed by a predetermined delay time in the NOT basic circuit Bc1, and is output to the output terminal OUT.

[0023] In this way, in normal operation of the inverter circuit 1, the signal output by the NOT basic circuit Bc1 is output as an output signal to the output terminal OUT. In other words, in normal operation of the inverter circuit 1, the input signal input to the input terminal IN of the inverter circuit 1 is inverted and output to the output terminal OUT, just like a general logical NOT circuit.

[0024] Next, the operation of the inverter circuit 1 when high-energy charged particles of radiation are incident on it will be described. FIG. 3 is a diagram showing an example of how high-energy charged particles are incident on the CMOS circuit (inverter circuit 1) according to the first embodiment. FIG. 3 shows a case where a high-energy charged particle E of radiation R is incident on an N-channel MOS transistor N1 of a NOT basic circuit Bc1 constituting the inverter circuit 1. Due to the incident charged particle E, a single event transient corresponding to the charge of the incident charged particle E also occurs in the inverter circuit 1. It is known that the incident charged particle E has a greater effect on a transistor in an off state than on a transistor in an on state.

[0025] Fig. 4 is a timing chart showing an example of the operation when a single event occurs due to a high-energy charged particle incident on the CMOS circuit (inverter circuit 1) according to the first embodiment. Fig. 4 is a timing chart showing the operation when a charged particle E is incident on the inverter circuit 1 when an input signal of GND level is input to the input terminal IN of the inverter circuit 1.

[0026] When a charged particle E is incident on the N-channel MOS transistor N1 of the NOT basic circuit Bc1 at timing t1 when a GND level input signal is input to the input terminal IN of the inverter circuit 1, the potential of the N-channel MOS transistor N1 in the off state changes transiently according to the charge of the incident charged particle E. This causes a momentary pulse of the GND level, as shown by the dashed line in Figure 4, to appear at the output node of the NOT basic circuit Bc1, that is, the output terminal OUT. This is a single event transient.

[0027] The right side of FIG. 4 shows the period during which the single event transient occurred in an enlarged manner, and shows the detailed timing and the signal level. With the occurrence of the single event transient, for example, the potential level of the N-well Nw drops, and the potential level of the P-well Pw rises. The right side of FIG. 4 shows an example in which the potential level of the N-well Nw drops to the GND level, and the potential level of the P-well Pw rises to a level between the VDD level and the GND level. The difference in the amount of fluctuation in the potential level in each well shown on the right side of FIG. 4 is an example based on the assumption that the potential level of the N-well Nw fluctuates more than that of the P-well Pw because the semiconductor substrate forming the CMOS circuit is a P-type single crystal semiconductor substrate, and the amount of fluctuation in the potential level in each well is considered to change depending on, for example, the charge of the charged particle E.

[0028] Then, the N-channel MOS transistor N2 is turned off due to the drop in the potential level of the N-well Nw, and the P-channel MOS transistor P2 is turned off due to the rise in the potential level of the P-well Pw. That is, the power supply circuit is turned off. On the right side of FIG. 4, the power supply circuit is turned off from timing t1 to timing t2. As a result, the N-channel MOS transistor N2 is not affected by the potential levels of the P-well Pw and the N-well Nw, which fluctuate due to the charge of the incident charged particle E, and the NOT basic circuit Bc1 does not output a signal including a single event transient to the output node (output terminal OUT). In other words, in the inverter circuit 1, the power supply circuit is turned off to eliminate the influence of the fluctuation in the potential level of the well due to the charge of the incident charged particle E, or to reduce the single event transient included in the signal output to the output node by the NOT basic circuit Bc1. FIG. 4 shows an example in which the single event transient is reduced and output to the output terminal OUT by a solid line.

[0029] 5 is a diagram showing another example of how high-energy charged particles are incident on the CMOS circuit (inverter circuit 1) according to the first embodiment. Fig. 5 shows a case where a high-energy charged particle E of radiation R is incident on a P-channel MOS transistor P1 of a NOT basic circuit Bc1 constituting the inverter circuit 1.

[0030] Fig. 6 is a timing chart showing another example of the operation when a single event occurs due to a high-energy charged particle incident on the CMOS circuit (inverter circuit 1) according to the first embodiment. Fig. 6 is a timing chart showing the operation when a charged particle E is incident on the inverter circuit 1 when an input signal of VDD level is input to the input terminal IN of the inverter circuit 1.

[0031] When a charged particle E is incident on the P-channel MOS transistor P1 of the NOT basic circuit Bc1 at timing t3 when a VDD-level input signal is being input to the input terminal IN of the inverter circuit 1, the potential of the P-channel MOS transistor P1, which is in the off state, fluctuates, and a momentary pulse of the VDD level as shown by the dashed line in FIG. 6 appears as a single event transient.

[0032] The right side of FIG. 6 also shows the period during which the single event transient occurred in an enlarged manner, and shows the timing and the signal level in more detail. When the single event transient occurs, the power supply circuit is turned off, as in the case where a charged particle E is incident on the N-channel MOS transistor N1 when a GND level input signal is input to the input terminal IN of the inverter circuit 1 shown in FIG. 4. On the right side of FIG. 6, the power supply circuit is in the off state from timing t3 to timing t4. As a result, the P-channel MOS transistor P1 is not affected by the potential levels of the P-well Pw and the N-well Nw, which vary depending on the charge of the incident charged particle E, and the NOT basic circuit Bc1 does not output a signal including the single event transient to the output node (output terminal OUT). In FIG. 6, a solid line shows an example in which the single event transient is reduced and output to the output terminal OUT.

[0033] In this way, in the inverter circuit 1, the incident charged particle E causes the P-channel MOS transistor P2 and the N-channel MOS transistor N2 connected as the power supply circuit of the NOT basic circuit Bc1 to be turned off by fluctuating the potential level of the well. As a result, the inverter circuit 1 prevents a signal including a single event transient generated in any of the transistors in the off state of the NOT basic circuit Bc1 from being output to the output node (output terminal OUT). In other words, the inverter circuit 1 eliminates or reduces the single event transient output to the output terminal OUT by the power supply circuit turned off by the incident charged particle E. As a result, the inverter circuit 1 does not propagate the single event transient generated inside the inverter circuit 1 to, for example, another CMOS circuit connected in the rear stage of the inverter circuit 1. As a result, in a CMOS type semiconductor integrated circuit including the inverter circuit 1, it is possible to prevent a single event upset in which erroneous data is stored due to the propagation of a signal including the generated single event transient. In other words, it is possible to increase the resistance to a single event generated by the incident charged particle E to the CMOS circuit.

[0034] [Other CMOS circuit configurations] In the above description, the inverter circuit 1 has been described as an example of the CMOS circuit of the first embodiment. However, the CMOS circuit of the first embodiment may have another configuration different from the inverter circuit 1. Hereinafter, an example of the configuration of a CMOS circuit other than the inverter circuit 1 in the CMOS circuit of the first embodiment will be described. FIGS. 7 to 9 are diagrams showing another example of the configuration of the CMOS circuit according to the first embodiment.

[0035] Fig. 7 shows an example of a buffer circuit in which two NOT circuits are connected in series. The buffer circuit 2 includes a P-channel MOS transistor P1-1, a P-channel MOS transistor P1-2, an N-channel MOS transistor N1-1, an N-channel MOS transistor N1-2, a P-channel MOS transistor P2, and an N-channel MOS transistor N2. The buffer circuit 2 shown in Fig. 7 is an example in which each transistor is formed on a P-type single crystal semiconductor substrate.

[0036] In the buffer circuit 2, the configuration of the P-channel MOS transistor P1-1, the P-channel MOS transistor P1-2, the N-channel MOS transistor N1-1, and the N-channel MOS transistor N1-2 is the configuration of a basic buffer circuit in a general logic operation circuit (hereinafter referred to as "buffer basic circuit Bc2"). In the buffer circuit 2, the P-channel MOS transistor P1-1 and the N-channel MOS transistor N1-1 form a first-stage logical NOT circuit (inverter circuit), and the P-channel MOS transistor P1-2 and the N-channel MOS transistor N1-2 form a second-stage logical NOT circuit (inverter circuit). In the buffer circuit 2, the configurations of the first-stage inverter circuit and the second-stage inverter circuit are similar to the NOT basic circuit Bc1 in the inverter circuit 1.

[0037] In the buffer circuit 2, the P-channel MOS transistor P2 is also disposed on the source terminal side of the P-channel MOS transistor P1-1 and the P-channel MOS transistor P1-2, with the source terminal connected to the power supply VDD and the gate terminal connected to a P-well Pw (the body of the N-channel MOS transistor N1-1 in FIG. 7) common to the N-channel MOS transistor N1-1 and the N-channel MOS transistor N1-2. The drain terminal of the P-channel MOS transistor P2 is connected to the source terminals of the P-channel MOS transistor P1-1 and the P-channel MOS transistor P1-2. In other words, the buffer circuit 2 includes a single P-channel MOS transistor P2 common to the P-channel MOS transistor P1-1 and the P-channel MOS transistor P1-2. The N-channel MOS transistor N2 is disposed on the source terminal side of the N-channel MOS transistor N1-1 and the N-channel MOS transistor N1-2, with the source terminal connected to the ground GND and the gate terminal connected to an N-well Nw (the body of the P-channel MOS transistor P1-1 in FIG. 7) common to the P-channel MOS transistor P1-1 and the P-channel MOS transistor P1-2. The drain terminal of the N-channel MOS transistor N2 is connected to the source terminals of the N-channel MOS transistor N1-1 and the N-channel MOS transistor N1-2. That is, the buffer circuit 2 includes one N-channel MOS transistor N2 common to the N-channel MOS transistor N1-1 and the N-channel MOS transistor N1-2. The gate terminals of the P-channel MOS transistor P2 and the N-channel MOS transistor N2 may be connected to the well common to the corresponding MOS transistors by, for example, a well contact.

[0038] The P-channel MOS transistor P1-1 and the P-channel MOS transistor P1-2 are an example of the "plurality of first transistors" in the claims, and the N-channel MOS transistor N1-1 and the N-channel MOS transistor N1-2 are an example of the "plurality of second transistors" in the claims. The buffer basic circuit Bc2 is an example of the "logical operation circuit" in the claims.

[0039] In the buffer circuit 2, in normal operation, an output signal corresponding to an input signal input to the input terminal IN of the buffer circuit 2 is transmitted (output) to the output terminal OUT, similarly to a general buffer circuit. That is, in the buffer circuit 2, an input signal input to the input terminal IN of the buffer circuit 2 is inverted by a first-stage inverter circuit and output to an internal node Io, and the signal at the internal node Io is further inverted by a second-stage inverter circuit, and an output signal having the same logic level as the input signal input to the input terminal IN is transmitted (output) to the output terminal OUT. In the buffer circuit 2, similarly to the inverter circuit 1, a power supply circuit consisting of a P-channel MOS transistor P2 and an N-channel MOS transistor N2 is turned off in response to the incident high-energy charged particle E, and a signal including a single event transient generated in any of the transistors in the off state provided in the buffer basic circuit Bc2 is prevented or reduced from being transmitted (output) to the output terminal OUT.

[0040] Moreover, the buffer circuit 2 includes one P-channel MOS transistor P2 and one N-channel MOS transistor N2. That is, the buffer circuit 2 includes one common power supply circuit for the first-stage inverter circuit and the second-stage inverter circuit. This allows the buffer circuit 2 to have a smaller circuit size than when the first-stage inverter circuit and the second-stage inverter circuit each include a corresponding P-channel MOS transistor P2 and N-channel MOS transistor N2.

[0041] 8 is an example of a two-input NAND circuit. The NAND circuit 3 includes a P-channel MOS transistor P1A, a P-channel MOS transistor P1B, an N-channel MOS transistor N1A, an N-channel MOS transistor N1B, a P-channel MOS transistor P2, and an N-channel MOS transistor N2. The NAND circuit 3 shown in FIG. 8 is an example in which each transistor is formed on a P-type single crystal semiconductor substrate.

[0042] In the NAND circuit 3, the configuration of P-channel MOS transistor P1A, P-channel MOS transistor P1B, N-channel MOS transistor N1A, and N-channel MOS transistor N1B is the same as that of a basic NAND circuit (NAND circuit: hereinafter referred to as "NAND basic circuit Bc3") in a typical logical operation circuit.

[0043] In the NAND circuit 3, the P-channel MOS transistor P2 is also disposed on the source terminal side of the P-channel MOS transistor P1A and the P-channel MOS transistor P1B, with the source terminal connected to the power supply VDD and the gate terminal connected to a P-well Pw (the body of the N-channel MOS transistor N1A in FIG. 8) common to the N-channel MOS transistor N1A and the N-channel MOS transistor N1B. The drain terminal of the P-channel MOS transistor P2 is connected to the source terminals of the P-channel MOS transistor P1A and the P-channel MOS transistor P1B. The N-channel MOS transistor N2 is disposed on the source terminal side of the N-channel MOS transistor N1B, with the source terminal connected to the ground GND and the gate terminal connected to an N-well Nw (the body of the P-channel MOS transistor P1A in FIG. 8) common to the P-channel MOS transistor P1A and the P-channel MOS transistor P1B. The drain terminal of the N-channel MOS transistor N2 is connected to the source terminal of the N-channel MOS transistor N1B. That is, the NAND circuit 3 also includes a single P-channel MOS transistor P2 shared by the P-channel MOS transistor P1A and the P-channel MOS transistor P1B, and an N-channel MOS transistor N2 shared by the N-channel MOS transistor N1A and the N-channel MOS transistor N1B.

[0044] The P-channel MOS transistor P1A and the P-channel MOS transistor P1B are an example of the "plurality of first transistors" in the claims, and the N-channel MOS transistor N1A and the N-channel MOS transistor N1B are an example of the "plurality of second transistors" in the claims. The NAND basic circuit Bc3 is an example of the "logical operation circuit" in the claims.

[0045] In the normal operation of the NAND circuit 3, as in a general NAND circuit, an output signal of a logic level corresponding to the logic level of the input signal input to the input terminal INA and the input terminal INB of the NAND circuit 3 is output to the output terminal OUT. In the NAND circuit 3, as in the inverter circuit 1, a power circuit consisting of a P-channel MOS transistor P2 and an N-channel MOS transistor N2 is turned off in response to the incident high-energy charged particle E, eliminating or reducing the output of a signal including a single event transient generated in any of the off-state transistors of the NAND basic circuit Bc3 to the output terminal OUT. Moreover, the NAND circuit 3 can also reduce the circuit size by providing one each of the P-channel MOS transistor P2 and the N-channel MOS transistor N2.

[0046] 9 is an example of a two-input NOR circuit. The NOR circuit 4 includes a P-channel MOS transistor P1A, a P-channel MOS transistor P1B, an N-channel MOS transistor N1A, an N-channel MOS transistor N1B, a P-channel MOS transistor P2, and an N-channel MOS transistor N2. The NOR circuit 4 shown in FIG. 9 is an example in which each transistor is formed on a P-type single crystal semiconductor substrate.

[0047] In the NOR circuit 4, the configuration of P-channel MOS transistor P1A, P-channel MOS transistor P1B, N-channel MOS transistor N1A, and N-channel MOS transistor N1B is the configuration of a basic NOR circuit (NOR circuit: hereinafter referred to as "NOR basic circuit Bc4") in a typical logical operation circuit.

[0048] In the NOR circuit 4, the P-channel MOS transistor P2 is disposed on the source terminal side of the P-channel MOS transistor P1B, with the source terminal connected to the power supply VDD and the gate terminal connected to a P-well Pw (the body of the N-channel MOS transistor N1A in FIG. 9) common to the N-channel MOS transistor N1A and the N-channel MOS transistor N1B. The drain terminal of the P-channel MOS transistor P2 is connected to the source terminal of the P-channel MOS transistor P1B. The N-channel MOS transistor N2 is disposed on the source terminal side of the N-channel MOS transistor N1A and the N-channel MOS transistor N1B, with the source terminal connected to the ground GND and the gate terminal connected to an N-well Nw (the body of the P-channel MOS transistor P1A in FIG. 9) common to the P-channel MOS transistor P1A and the P-channel MOS transistor P1B. The drain terminal of the N-channel MOS transistor N2 is connected to the source terminals of the N-channel MOS transistor N1A and the N-channel MOS transistor N1B. That is, the NOR circuit 4 also includes a single P-channel MOS transistor P2 shared by the P-channel MOS transistor P1A and the P-channel MOS transistor P1B, and an N-channel MOS transistor N2 shared by the N-channel MOS transistor N1A and the N-channel MOS transistor N1B.

[0049] The P-channel MOS transistor P1A and the P-channel MOS transistor P1B are an example of the "plurality of first transistors" in the claims, and the N-channel MOS transistor N1A and the N-channel MOS transistor N1B are an example of the "plurality of second transistors" in the claims. The NOR basic circuit Bc4 is an example of the "logical operation circuit" in the claims.

[0050] In the normal operation of the NOR circuit 4, as in a general NOR circuit, an output signal of a logic level corresponding to the logic level of the input signal input to the input terminal INA and the input terminal INB of the NOR circuit 4 is output to the output terminal OUT. In the NOR circuit 4, as in the inverter circuit 1, a power supply circuit composed of a P-channel MOS transistor P2 and an N-channel MOS transistor N2 is turned off in response to the incident high-energy charged particle E, eliminating or reducing the output of a signal including a single event transient generated in any of the off-state transistors of the NOR basic circuit Bc4 to the output terminal OUT. Moreover, the NOR circuit 4 can also reduce the circuit size by providing one each of the P-channel MOS transistor P2 and the N-channel MOS transistor N2.

[0051] The operation of each CMOS circuit shown in FIG. 7 to FIG. 9 when eliminating or reducing a single event transient can be easily understood by considering it as the operation when a high-energy charged particle is incident on the inverter circuit 1 shown in FIG. 3 to FIG. 6. Therefore, detailed description of the operation of each CMOS circuit shown in FIG. 7 to FIG. 9 when eliminating or reducing a single event transient is omitted. Furthermore, as described above, various configurations of the CMOS circuit are conceivable in addition to the CMOS circuits shown in FIG. 7 to FIG. 9. For example, it is conceivable to configure a D-type flip-flop circuit by combining a plurality of inverter circuits 1 and transmission gate circuits (so-called transmission gates). In this case, each CMOS circuit constituting the D-type flip-flop circuit may be provided with a P-channel MOS transistor P2 and an N-channel MOS transistor N2, or a configuration including one P-channel MOS transistor P2 and one N-channel MOS transistor N2 shared in the entire D-type flip-flop circuit (for example, a configuration equivalent to the configuration in which the NOT basic circuit Bc1 in the inverter circuit 1 is configured as a D-type flip-flop circuit) may be used. Furthermore, as described above, the CMOS circuit may be configured as a memory that stores data (signal level) by combining a plurality of independent logic operation circuits, flip-flop circuits, transmission gate circuits, etc., such as an SRAM. These configurations may be configured to be equivalent to the inverter circuit 1 shown in FIG. 1 and the CMOS circuits (buffer circuit 2, NAND circuit 3, NOR circuit 4) shown in FIGS. 7 to 9. The operation of these circuits can be easily understood by considering them as the operation of the inverter circuit 1 shown in FIGS. 3 to 6 when a high-energy charged particle is incident thereon. Therefore, detailed explanations of various possible configurations and operations of the CMOS circuit will be omitted.

[0052] As described above, the CMOS circuit of the first embodiment includes a P-channel MOS transistor P2 whose gate terminal is connected to the P-well Pw of the N-channel MOS transistor N1, and an N-channel MOS transistor N2 whose gate terminal is connected to the N-well Nw of the P-channel MOS transistor P1, as a power supply circuit of the logic operation circuit of the basic configuration. With this configuration, the CMOS circuit of the first embodiment eliminates or reduces the output (transmission) of a signal including a single event transient generated in the logic operation circuit in response to the incident charged particle E to the output terminal. As a result, the CMOS circuit of the first embodiment can prevent a single event transient generated inside the CMOS circuit from being propagated to, for example, another CMOS circuit connected in the rear stage of the CMOS circuit. Furthermore, the CMOS circuit of the first embodiment can prevent a single event upset in which a signal including a single event transient generated inside the CMOS circuit is propagated and erroneous data is stored. In other words, the CMOS circuit of the first embodiment can realize a CMOS circuit with improved resistance to the incidence of the charged particle E.

[0053] As a result, the semiconductor integrated circuit having the function realized by the CMOS circuit of the first embodiment can reduce the possibility of malfunction even when used in an environment where high-energy charged particles E are incident, such as outer space. In other words, by realizing the function with the CMOS circuit of the first embodiment, a highly reliable semiconductor integrated circuit can be realized that is less likely to malfunction due to the influence of the usage environment. Therefore, the semiconductor integrated circuit having the function realized by the CMOS circuit of the first embodiment can obtain the same effect even when used in environments where high reliability is required, such as for example, industrial equipment, automotive use, and medical use, other than outer space.

[0054] In the CMOS circuit of the first embodiment, a P-channel MOS transistor P2, whose source terminal is connected to a power supply VDD, is arranged on the source terminal side of the P-channel MOS transistor P1, and an N-channel MOS transistor N2, whose source terminal is connected to a ground GND, is arranged on the source terminal side of the N-channel MOS transistor N1. However, the arrangement and connection of the P-channel MOS transistor P2 and the N-channel MOS transistor N2 in the CMOS circuit may be configured in other ways.

[0055] <Second embodiment> Hereinafter, a CMOS circuit according to the second embodiment will be described. In the following description, for ease of explanation, a logical negation circuit (inverter circuit), which is a logical operation circuit with the simplest configuration, will be described as an example of the CMOS circuit according to the second embodiment.

[0056] [Inverter circuit configuration] Fig. 10 is a diagram showing an example of the configuration of a CMOS circuit (inverter circuit) according to the second embodiment. The inverter circuit 1A includes a P-channel MOS transistor P1, an N-channel MOS transistor N1, a P-channel MOS transistor P2, and an N-channel MOS transistor N2. The inverter circuit 1A shown in Fig. 10 is an example in which each transistor is formed on a P-type single crystal semiconductor substrate.

[0057] In the inverter circuit 1A, the configuration of the P-channel MOS transistor P1 and the N-channel MOS transistor N1 is a NOT basic circuit Bc1. In the inverter circuit 1A, the P-channel MOS transistor P2 is disposed on the source terminal side of the N-channel MOS transistor N1, with the source terminal connected to the ground GND, the gate terminal connected to the P-well Pw (the body of the N-channel MOS transistor N1 in FIG. 10) of the N-channel MOS transistor N1, and the drain terminal connected to the source terminal of the N-channel MOS transistor N1. The N-channel MOS transistor N2 is disposed on the source terminal side of the P-channel MOS transistor P1, with the source terminal connected to the power supply VDD, the gate terminal connected to the N-well Nw (the body of the P-channel MOS transistor P1 in FIG. 10) of the P-channel MOS transistor P1, and the drain terminal connected to the source terminal of the P-channel MOS transistor P1. The gate terminals of the P-channel MOS transistor P2 and the N-channel MOS transistor N2 may be connected to the corresponding wells by, for example, well contacts.

[0058] Also in the inverter circuit 1A, the configuration of the P-channel MOS transistor P2 and the N-channel MOS transistor N2 can be said to be a power supply circuit for the NOT basic circuit Bc1.

[0059] Even during normal operation of the inverter circuit 1A, the N-well Nw is at the VDD level and the P-well Pw is at the GND level, so that the power supply circuit of the inverter circuit 1A is always on. Therefore, even during normal operation of the inverter circuit 1A, the input signal input to the input terminal IN is inverted with a timing delayed by a predetermined delay time in the NOT basic circuit Bc1 and output to the output terminal OUT.

[0060] On the other hand, in the inverter circuit 1A, when a high-energy charged particle E is incident, a single event transient occurs in any of the transistors in the inverter circuit 1A in the off state according to the charge of the incident charged particle E. For this reason, in the inverter circuit 1A, the potential level of the N-well Nw drops and the potential level of the P-well Pw rises for the same reason as described in the first embodiment. As a result, in the inverter circuit 1A, the P-channel MOS transistor P2 and the N-channel MOS transistor N2, that is, the power supply circuit, are turned off due to the fluctuation of the corresponding wells. As a result, in the inverter circuit 1A, as in the inverter circuit 1 of the first embodiment, the transistors in the off state are not affected by the potential levels of the P-well Pw and the N-well Nw that fluctuate due to the charge of the incident high-energy charged particle E, and the NOT basic circuit Bc1 eliminates or reduces the output of a signal including a single event transient to the output node (output terminal OUT).

[0061] As described above, the CMOS circuit of the second embodiment, like the CMOS circuit of the first embodiment, includes a P-channel MOS transistor P2 whose gate terminal is connected to the P-well Pw of the N-channel MOS transistor N1, and an N-channel MOS transistor N2 whose gate terminal is connected to the N-well Nw of the P-channel MOS transistor P1, as a power supply circuit of a logic operation circuit of a basic configuration. With this configuration, like the CMOS circuit of the first embodiment, the CMOS circuit of the second embodiment also eliminates or reduces the output (transmission) of a signal including a single event transient generated in the logic operation circuit in response to the incident charged particle E to the output terminal. As a result, like the CMOS circuit of the first embodiment, the CMOS circuit of the second embodiment can realize a CMOS circuit with improved resistance to the incidence of the charged particle E.

[0062] Moreover, in the CMOS circuit of the second embodiment, the transistors connected as power supply circuits to the transistors constituting the logical operation circuit of the basic configuration are transistors of different conductivity types. More specifically, in the inverter circuit 1A, the transistor connected as power supply circuits to the P-channel MOS transistor P1 constituting the NOT basic circuit Bc1 is the N-channel MOS transistor N2 of different conductivity types, and the transistor connected as power supply circuits to the N-channel MOS transistor N1 constituting the NOT basic circuit Bc1 is the P-channel MOS transistor P2 of different conductivity types. Therefore, in the CMOS circuit of the second embodiment, it is possible to increase the resistance to the parasitic bipolar effect that may occur when adjacent transistors operate simultaneously.

[0063] <Third embodiment> Hereinafter, a CMOS circuit according to the third embodiment will be described. In the following description, for ease of explanation, a logical negation circuit (inverter circuit), which is a logical operation circuit with the simplest configuration, will be described as an example of the CMOS circuit according to the third embodiment.

[0064] [Inverter circuit configuration] Fig. 11 is a diagram showing an example of the configuration of a CMOS circuit (inverter circuit) according to the third embodiment. The inverter circuit 1B includes a P-channel MOS transistor P1, an N-channel MOS transistor N1, a P-channel MOS transistor P2, and an N-channel MOS transistor N2. The inverter circuit 1B shown in Fig. 11 is an example in which each transistor is formed on a P-type single crystal semiconductor substrate.

[0065] In the inverter circuit 1B, the P-channel MOS transistor P1 has a gate terminal connected to the input terminal IN of the inverter circuit 1, a source terminal connected to a power supply VDD, and a drain terminal connected to the source terminal of the P-channel MOS transistor P2. The N-channel MOS transistor N1 has a gate terminal connected to the input terminal IN of the inverter circuit 1, a source terminal connected to ground GND, and a drain terminal connected to the source terminal of the N-channel MOS transistor N2.

[0066] In the inverter circuit 1B, the P-channel MOS transistor P2 is disposed on the drain terminal side of the P-channel MOS transistor P1, and the source terminal is connected to the drain terminal of the P-channel MOS transistor P1, and the drain terminal is connected to the drain terminal of the N-channel MOS transistor N2. The gate terminal of the P-channel MOS transistor P2 is connected to the P-well Pw of the N-channel MOS transistor N1 (the body of the N-channel MOS transistor N1 in FIG. 11). The N-channel MOS transistor N2 is disposed on the drain terminal side of the N-channel MOS transistor N1, and the source terminal is connected to the drain terminal of the N-channel MOS transistor N1, and the drain terminal is connected to the drain terminal of the P-channel MOS transistor P2. The gate terminal of the N-channel MOS transistor N2 is connected to the N-well Nw of the P-channel MOS transistor P1 (the body of the P-channel MOS transistor P1 in FIG. 11). The gate terminals of the P-channel MOS transistor P2 and the N-channel MOS transistor N2 may be connected to the corresponding wells by, for example, well contacts.

[0067] In the inverter circuit 1B, a node where the drain terminal of the P-channel MOS transistor P2 and the drain terminal of the N-channel MOS transistor N2 are connected is the output terminal OUT of the inverter circuit 1B. In the inverter circuit 1B, the configuration of the P-channel MOS transistor P1 and the N-channel MOS transistor N1 is the NOT basic circuit Bc1. In the inverter circuit 1B, the configuration of the P-channel MOS transistor P2 and the N-channel MOS transistor N2 is the transmission circuit of the NOT basic circuit Bc1 rather than the power circuit of the NOT basic circuit Bc1. However, in the inverter circuit 1B, the transmission circuit configured with the P-channel MOS transistor P2 and the N-channel MOS transistor N2 also operates in the same manner as the power circuit configured with the P-channel MOS transistor P2 and the N-channel MOS transistor N2 in the inverter circuit 1 of the first embodiment and the inverter circuit 1A of the second embodiment.

[0068] That is, even in normal operation of the inverter circuit 1B, the N-well Nw is at the VDD level and the P-well Pw is at the GND level, so that the transmission circuit included in the inverter circuit 1B is always in the ON state. Therefore, even in normal operation of the inverter circuit 1B, the input signal input to the input terminal IN is inverted with a timing delayed by a predetermined delay time in the NOT basic circuit Bc1 and output to the output terminal OUT.

[0069] On the other hand, in the inverter circuit 1B, when a high-energy charged particle E is incident, a single event transient occurs in any of the transistors in the inverter circuit 1B in the off state according to the charge of the incident charged particle E. For this reason, in the inverter circuit 1B, the potential level of the N-well Nw drops and the potential level of the P-well Pw rises for the same reason as described in the first embodiment. As a result, in the inverter circuit 1B, the P-channel MOS transistor P2 and the N-channel MOS transistor N2, that is, the transmission circuit, are turned off due to the fluctuation of the corresponding well. As a result, in the inverter circuit 1B, like the inverter circuit 1 of the first embodiment and the inverter circuit 1A of the second embodiment, the transistors in the off state are not affected by the potential levels of the P-well Pw and the N-well Nw that fluctuate due to the charge of the incident high-energy charged particle E, and the NOT basic circuit Bc1 eliminates or reduces the output of a signal including a single event transient to the output node (output terminal OUT).

[0070] As described above, the CMOS circuit of the third embodiment includes a P-channel MOS transistor P2 whose gate terminal is connected to the P-well Pw of the N-channel MOS transistor N1, and an N-channel MOS transistor N2 whose gate terminal is connected to the N-well Nw of the P-channel MOS transistor P1, as a transmission circuit of the logic operation circuit of the basic configuration. With this configuration, the CMOS circuit of the third embodiment, like the CMOS circuit of the first embodiment and the CMOS circuit of the second embodiment, eliminates or reduces the output (transmission) of a signal including a single event transient generated in the logic operation circuit in response to the incident charged particle E to the output terminal. As a result, the CMOS circuit of the third embodiment can realize a CMOS circuit with improved resistance to the incidence of the charged particle E, like the CMOS circuit of the first embodiment and the CMOS circuit of the second embodiment.

[0071] As described above, according to the CMOS circuit of each embodiment, the logic operation circuit of the basic configuration includes a P-channel MOS transistor P2 whose gate terminal is connected to the P-well Pw of the N-channel MOS transistor N1, and an N-channel MOS transistor N2 whose gate terminal is connected to the N-well Nw of the P-channel MOS transistor P1. As a result, in the CMOS circuit of each embodiment, even if a single event transient occurs in the logic operation circuit due to incidence of high-energy charged particles of radiation from the usage environment, it is possible to eliminate or reduce the output (transmission) of a signal including the generated single event transient to the output node (output terminal OUT). As a result, a semiconductor integrated circuit having the function realized by the CMOS circuit of each embodiment can reduce the possibility of malfunction and obtain high reliability even when used in an environment where high-energy charged particles are incident.

[0072] In each of the above-mentioned embodiments, an example in which the transistors included in the CMOS circuit are formed on a P-type single crystal semiconductor substrate (bulk substrate) has been described. However, in addition to the P-type single crystal substrate, there are various other structures of semiconductor substrates, such as an N-type single crystal substrate and a P-type or N-type SOI structure substrate. The configuration and operation of the CMOS circuit in this case may be equivalent to the configuration and operation of the CMOS circuit formed on the above-mentioned P-type single crystal semiconductor substrate. Therefore, detailed description of the configuration and operation of the CMOS circuit formed on a semiconductor substrate other than the P-type single crystal semiconductor substrate will be omitted.

[0073] The above describes the form for carrying out the present invention using an embodiment, but the present invention is not limited to such an embodiment, and various modifications and substitutions can be made within the scope that does not deviate from the gist of the present invention. [Explanation of symbols]

[0074] 1, 1A, 1B... Inverter circuit 2. Buffer circuit 3. NAND circuit 4. NOR circuit P1, P1-1, P1-2, P1A, P1B, P2...P-channel MOS transistors N1, N1-1, N1-2, N1A, N1B, N2...N-channel MOS transistors Pw...P well Nw...N-well Bc1...NOT basic circuit Bc2... Buffer basic circuit Bc3...NAND basic circuit Bc4...NOR basic circuit Io...Internal Node

Claims

1. a logic operation circuit formed on a substrate of a first conductivity type, and including at least a first transistor of the first conductivity type having a first well of a second conductivity type different from the first conductivity type, and a second transistor of the second conductivity type having a second well of the first conductivity type; a third transistor of the first conductivity type having a gate terminal connected to the second well; a fourth transistor of the second conductivity type having a gate terminal connected to the first well; A CMOS circuit comprising:

2. a gate terminal of the third transistor is connected to the second well of the second transistor; a gate terminal of the fourth transistor is connected to the first well of the first transistor; 2. The CMOS circuit of claim 1.

3. the third transistor has a source terminal fixed to a power supply potential and a drain terminal connected to the source terminal of the first transistor; The fourth transistor has a source terminal fixed to a ground potential and a drain terminal connected to the source terminal of the second transistor.

3. The CMOS circuit of claim 2.

4. the third transistor has a source terminal fixed to a ground potential and a drain terminal connected to the source terminal of the second transistor; the fourth transistor has a source terminal fixed to a power supply potential and a drain terminal connected to the source terminal of the first transistor; 3. The CMOS circuit of claim 2.

5. the first transistor has a source terminal fixed to a power supply potential; the third transistor has a source terminal connected to the drain terminal of the first transistor; the second transistor has a source terminal fixed to a ground potential; the fourth transistor has a source terminal connected to the drain terminal of the second transistor; a drain terminal of the third transistor and a drain terminal of the fourth transistor are connected to an output terminal of a logic operation circuit; 3. The CMOS circuit of claim 2.

6. the logic operation circuit is a logic operation circuit in which a plurality of the first transistors and a plurality of the second transistors are combined, The third transistor and the fourth transistor are provided one by one. A CMOS circuit according to any one of claims 1 to 5.

7. the transistor of the first conductivity type is a P-channel MOS transistor, The second conductivity type transistor is an N-channel MOS transistor.

7. A CMOS circuit according to any one of claims 1 to 6.

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