Sensing and ranging systems

Abstract

A system for imaging image data measures the distance to an object without adding a distance measurement sensor.　This sensing system comprises a light-emitting unit, a prescribed number of pixels, and a counting unit. In this solid-state imaging element, the light-emitting unit emits emission light in synchronization with a light-emitting control signal having a higher frequency than a prescribed vertical synchronizing signal. In addition, the prescribed number of pixels respectively generate pulse signals by photoelectric conversion. In addition, the counting unit counts the number of pulse signals in synchronization with each of the light emission control signal and the vertical synchronizing signal.

Description

[Technical field]

[0001] The present technology relates to a sensing system, and more particularly to a sensing system and a distance measuring system that count the number of pulses. [Background technology]

[0002] In recent years, a device called SPAD (Single Photon Avalanche Diode) has been developed and researched to capture very weak optical signals and realize optical communication, distance measurement, photon counting, etc. This SPAD is an avalanche photodiode with high sensitivity that can detect a single photon. For example, a solid-state imaging element has been proposed in which pixels that generate pulse signals using SPADs and a counter that counts the number of these pulse signals within an exposure period are arranged (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2019 / 150785 Summary of the Invention [Problem to be solved by the invention]

[0004] In the above-mentioned conventional technology, a high-sensitivity SPAD is used to detect weak light, thereby improving image quality when capturing images in a dark environment. However, the above-mentioned solid-state imaging element cannot measure the distance to an object in the captured image. If a distance measuring sensor using infrared rays or a laser is added to measure the distance, the power consumption and cost of the system will increase, which is not desirable.

[0005] This technology was developed in light of these circumstances, and aims to measure the distance to an object in a system that captures image data without adding a distance measuring sensor. [Means for solving the problem]

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect of the present technology is a sensing system including a light emitting unit that irradiates irradiation light in synchronization with a light emission control signal having a higher frequency than a predetermined vertical synchronization signal, a predetermined number of pixels that each generate a pulse signal by photoelectric conversion, and a counting unit that counts the number of the pulse signals in synchronization with each of the light emission control signal and the vertical synchronization signal, thereby providing an effect of performing imaging of image data and distance measurement.

[0007] In the first aspect, the counting unit may include a first counter that counts the pulse signals in synchronization with the light emission control signal, and a second counter that counts the pulse signals in synchronization with the vertical synchronization signal, thereby providing an effect that distance measurement is performed based on the count values ​​of the counters.

[0008] In addition, in the first aspect, the counting unit may include a first counter that sequentially counts the pulse signals in synchronization with the light emission control signal and counts the pulse signals in synchronization with the vertical synchronization signal, and a second counter that counts the pulse signals in synchronization with the vertical synchronization signal, thereby providing an effect of reducing the number of counters.

[0009] In addition, in the first aspect, the pixel array unit in which the predetermined number of pixels are arranged may be divided into a plurality of pixel blocks, the counting unit may be provided for each of the pixel blocks, and the first counter may count the logical sum of the pulse signals from each of the pixels in the pixel block, thereby providing an effect of measuring the distance for each pixel block.

[0010] In addition, in the first aspect, four of the first counters and five of the second counters may be arranged for each pixel block, thereby providing an effect that a distance is measured based on four count values.

[0011] In the first aspect, eight of the first counters and one of the second counters may be arranged for each pixel block, thereby providing an effect of widening the range of distances that can be measured.

[0012] In addition, in the first aspect, the pixel array unit in which the predetermined number of pixels are arranged may be divided into a plurality of pixel blocks, each of the plurality of pixel blocks may be divided into a plurality of areas, the counting unit may be provided in association with each of the plurality of areas, and the first counter may count the logical sum of the pulse signals from each of the pixels in the corresponding area, thereby providing an effect that the distance is measured from the count value for each area.

[0013] In the first aspect, nine of the pixels may be arranged in each of the plurality of areas, thereby providing an effect that the logical sum of pulse signals for nine pixels is counted.

[0014] In the first aspect, four of the pixels may be arranged in each of the plurality of areas, thereby providing an effect that the logical sum of pulse signals for four pixels is counted.

[0015] In the first aspect, four areas may be arranged in the pixel block, thereby providing an effect that the distance is measured from the respective count values ​​of the two areas.

[0016] In the first aspect, two areas may be arranged in the pixel block, thereby providing an effect that the distance is measured from the respective count values ​​of the four areas.

[0017] In addition, in the first aspect, the first counter may count the logical sum of the pulse signals of a set number of the pixels in the pixel block, thereby bringing about an effect that the data size of the count value is changed.

[0018] In addition, in the first aspect, the counting unit may include a predetermined number of counters that sequentially count the pulse signals in synchronization with the light emission control signal and the pulse signals in synchronization with the vertical synchronization signal, thereby providing an effect of reducing the number of counters.

[0019] In the first aspect, the counting unit may include nine of the counters. This provides an effect that the distance is measured from the nine count values.

[0020] In the first aspect, the counting unit may include four of the counters. This provides an effect that the distance is measured from the four count values.

[0021] In addition, in the first aspect, a pixel driving unit may be further provided that supplies an enable signal in which a plurality of setting values ​​are sequentially set as a phase difference with respect to the light emission control signal, and the counter may supply the pulse signal in synchronization with the enable signal. This provides an effect of improving distance measurement accuracy.

[0022] A second aspect of the present technology is a distance measuring system including a light emitting unit that emits irradiation light in synchronization with a light emission control signal having a frequency higher than a predetermined vertical synchronization signal, a predetermined number of pixels that each generate a pulse signal by photoelectric conversion, a counting unit that counts the number of the pulse signals in synchronization with each of the light emission control signal and the vertical synchronization signal, and a distance measuring unit that measures the distance to an object based on the counted value of the counting unit. This provides the effect of capturing image data and performing distance measurement based on the counted value.

[0023] In addition, a third aspect of the present technology is a sensing system including a light emitting unit that emits irradiation light based on a light emission control signal, a plurality of pixels each generating a pulse signal by photoelectric conversion, and a counting unit that counts the number of pulse signals of the plurality of pixels, the counting unit including a plurality of counters, and an output destination control circuit that is connected between the plurality of pixels and the plurality of counters and receives a plurality of pulse signals output from the plurality of pixels and distributes the plurality of pulse signals to any of a plurality of counters, the plurality of pixels being provided on a first chip, and the output control circuit and the counting unit being provided on a second chip. This provides an effect that imaging of image data and distance measurement are performed in the sensing system having a stacked structure. [Brief description of the drawings]

[0024] [Figure 1] 1 is a block diagram showing an example configuration of a distance measuring system according to a first embodiment of the present technology. [Diagram 2] 1 is a diagram showing an example of a layered structure of a solid-state imaging element according to a first embodiment of the present technology. [Diagram 3] 1 is a block diagram showing a configuration example of a solid-state imaging element according to a first embodiment of the present technology. [Figure 4] 1 is a block diagram showing an example of a configuration of a pixel block according to a first embodiment of the present technology. [Diagram 5] 1 is a circuit diagram showing a configuration example of a pixel according to a first embodiment of the present technology. [Figure 6] 1 is a cross-sectional view showing a configuration example of a pixel according to a first embodiment of the present technology. [Figure 7] 2 is a circuit diagram showing a configuration example of an output destination control circuit according to the first embodiment of the present technology. FIG. [Figure 8] 3 is a diagram showing an example of a correspondence relationship between circuits provided on a pixel chip and a circuit chip according to the first embodiment of the present technology; FIG. [Figure 9] 4 is a diagram for explaining an operation of a counter according to the first embodiment of the present technology. FIG. [Figure 10]4 is a timing chart showing an example of an operation in a distance measurement mode of the solid-state imaging element according to the first embodiment of the present technology. [Figure 11] 4 is a timing chart showing an example of an operation in an imaging mode of the solid-state imaging element according to the first embodiment of the present technology. [Figure 12] 1 is an example of an overall view of a distance measuring system according to a first embodiment of the present technology. [Figure 13] 5 is a flowchart showing an example of the operation of the distance measuring system in the first embodiment of the present technology. [Figure 14] 13 is a block diagram showing an example of the configuration of a pixel block according to a second embodiment of the present technology. FIG. [Figure 15] 13 is a circuit diagram showing a configuration example of an output destination control circuit according to a second embodiment of the present technology. FIG. [Figure 16] 13 is a diagram showing an example of a correspondence relationship between circuits provided on a pixel chip and a circuit chip according to a second embodiment of the present technology. FIG. [Figure 17] 13 is a diagram for explaining an operation of a counter according to the second embodiment of the present technology. FIG. [Figure 18] 13 is a circuit diagram showing a configuration example of an output destination control circuit according to a third embodiment of the present technology. FIG. [Figure 19] 13 is a diagram showing an example of a correspondence relationship between circuits provided on a pixel chip and a circuit chip according to a third embodiment of the present technology. FIG. [Figure 20] 13 is a diagram for explaining an operation of a counter according to the third embodiment of the present technology. FIG. [Figure 21] 13 is a circuit diagram showing a configuration example of an output destination control circuit according to a fourth embodiment of the present technology. FIG. [Figure 22] 13 is a diagram showing an example of a correspondence relationship between circuits provided on a pixel chip and a circuit chip according to a fourth embodiment of the present technology. FIG. [Figure 23] 13 is a diagram for explaining an operation of a counter according to the fourth embodiment of the present technology. FIG. [Figure 24]FIG. 13 is a diagram showing an example of a circuit provided in a pixel block according to a fifth embodiment of the present technology. [Diagram 25] FIG. 23 is a diagram showing an example of a circuit provided in a pixel block according to a sixth embodiment of the present technology. [Figure 26] FIG. 23 is a block diagram showing a configuration example of a 0-degree area according to a sixth embodiment of the present technology. [Figure 27] 13 is a circuit diagram showing a configuration example of an output destination control circuit according to a sixth embodiment of the present technology. FIG. [Figure 28] FIG. 23 is a diagram showing an example of a circuit provided in a pixel block according to a seventh embodiment of the present technology. [Figure 29] 23 is a timing chart showing an example of an operation in a distance measurement mode of a solid-state imaging element according to the seventh embodiment of the present technology. [Diagram 30] FIG. 23 is a diagram showing an example of a circuit provided in a pixel block according to an eighth embodiment of the present technology. [Diagram 31] 13 is a circuit diagram showing a configuration example of an output destination control circuit according to an eighth embodiment of the present technology. FIG. [Diagram 32] 23 is a timing chart showing an example of an operation in a distance measurement mode of a solid-state imaging element according to the eighth embodiment of the present technology. [Diagram 33] FIG. 23 is a diagram showing an example of a circuit provided in a pixel block according to a ninth embodiment of the present technology. [Diagram 34] FIG. 23 is a diagram showing an example of a circuit provided in a pixel block according to a tenth embodiment of the present technology. [Diagram 35] 23 is a circuit diagram showing a configuration example of an output destination control circuit according to a tenth embodiment of the present technology. FIG. [Diagram 36] 23 is a diagram for explaining an operation of a pixel driving section according to a tenth embodiment of the present technology. FIG. [Figure 37] 1 is a block diagram showing a schematic configuration example of a vehicle control system; [Figure 38] FIG. 4 is an explanatory diagram showing an example of an installation position of an imaging unit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] Hereinafter, modes for carrying out the present technology (hereinafter, referred to as embodiments) will be described. The description will be made in the following order. 1. First embodiment (example of counting in synchronization with a light emission control signal and a vertical synchronization signal) 2. Second embodiment (example in which one counter counts in synchronization with a light emission control signal and a vertical synchronization signal) 3. Third embodiment (example in which all counters count in synchronization with the light emission control signal and the vertical synchronization signal) 4. Fourth embodiment (example in which eight counters count in synchronization with a light emission control signal and a vertical synchronization signal) 5. Fifth embodiment (example of dividing into multiple areas and counting in synchronization with light emission control signals and vertical synchronization signals) 6. Sixth embodiment (example of reducing the number of pixels in an area and counting in synchronization with a light emission control signal and a vertical synchronization signal) 7. Seventh embodiment (example of reducing the number of areas and counting in synchronization with the light emission control signal and the vertical synchronization signal) 8. Eighth embodiment (example of switching the phase difference and counting in synchronization with the light emission control signal and the vertical synchronization signal) 9. Ninth embodiment (example in which the phase difference is fixed and counting is performed in synchronization with the light emission control signal and the vertical synchronization signal) 10. Tenth embodiment (example of switching the number of pixels to be counted and counting in synchronization with the light emission control signal and vertical synchronization signal) 11. Mobile application examples

[0026] <1. First embodiment> [Example of distance measurement system configuration] 1 is a block diagram showing an example of a configuration of a distance measuring system 100 according to a first embodiment of the present technology. The distance measuring system 100 is for capturing image data and measuring distance. The distance measuring system 100 includes a light emitting unit 110, a driver 120, a controller 130, a solid-state imaging element 200, a processor 140, and an application processor 150.

[0027] Each of the elements in the distance measuring system 100 may be arranged in one electronic device or distributed across multiple devices. In the case of distributing the elements across multiple devices, for example, the light emitting unit 110, the driver 120, the controller 130, the solid-state imaging element 200, and the processor 140 are arranged in an imaging device, and the application processor 150 is arranged in an image processing device.

[0028] The light emitting unit 110 emits light in accordance with a light emission control signal LCLK from the driver 120, and irradiates irradiation light. For example, near-infrared light is used as the irradiation light.

[0029] The driver 120 generates a predetermined periodic signal as a light emission control signal LCLK under the control of the controller 130 , and supplies the signal to the light emitting unit 110 .

[0030] The controller 130 operates the driver 120 and the processor 140 in synchronization. Here, the distance measurement system has a plurality of modes including a distance measurement mode for measuring the distance to an object and an imaging mode for capturing image data. In the distance measurement mode, the controller 130 causes the driver 120 to generate a light emission control signal LCLK, and also causes the processor 140 to generate a signal identical to the light emission control signal LCLK as a light emission control signal LCLK'. On the other hand, in the imaging mode, the controller 130 stops the driver 120 and causes the processor 140 to generate a vertical synchronization signal VSYNC.

[0031] Here, the frequency of the vertical synchronization signal VSYNC is, for example, 30 Hertz (Hz) or 60 Hertz (Hz). On the other hand, the frequency of the light emission control signal LCLK is higher than that of the vertical synchronization signal VSYNC, for example, 10 to 20 Megahertz (MHz).

[0032] The processor 140 controls the solid-state imaging element 200 and the application processor 150. In the distance measurement mode, the processor 140 generates a light emission control signal LCLK' and supplies it to the solid-state imaging element 200, and receives a depth map from the solid-state imaging element 200. On the other hand, in the imaging mode, the processor 140 generates a vertical synchronization signal VSYNC and supplies it to the solid-state imaging element 200, and receives image data from the solid-state imaging element 200. Then, the processor 140 supplies the depth map and image data to the application processor 150.

[0033] The application processor 150 performs predetermined processing such as image recognition processing based on image data and a depth map.

[0034] The solid-state imaging element 200 generates image data or a depth map by photoelectric conversion. In a distance measurement mode, the solid-state imaging element 200 photoelectrically converts reflected light relative to irradiated light in synchronization with a light emission control signal LCLK' to generate a depth map. Meanwhile, in an imaging mode, the solid-state imaging element 200 photoelectrically converts incident light in synchronization with a vertical synchronization signal VSYNC to generate image data. The solid-state imaging element 200 supplies the image data and the depth map to the processor 140. Note that a system including the solid-state imaging element 200 is an example of a sensing system described in the claims.

[0035] Note that the solid-state imaging device 200 may have some or all of the functions of the processor 140 and the application processor 150 .

[0036] [Example of the configuration of a solid-state imaging element] 2 is a diagram showing an example of a stacked structure of a solid-state imaging element 200 in the first embodiment of the present technology. This solid-state imaging element 200 includes a circuit chip 202 and a pixel chip 201 stacked on the circuit chip 202. These chips are electrically connected through a connection portion such as a via. In addition to the via, the chips can also be connected by Cu-Cu bonding or bumps. They can also be connected by other methods (such as magnetic coupling). Although two chips are stacked, three or more layers can also be stacked.

[0037] 3 is a block diagram showing a configuration example of a solid-state imaging element 200 according to the first embodiment of the present technology. The solid-state imaging element 200 includes a pixel driving section 210, a vertical scanning circuit 220, a pixel array section 230, a column buffer 240, a signal processing circuit 250, and an output section 260. A plurality of pixels are arranged in a two-dimensional lattice in the pixel array section 230. The pixel array section 230 is divided into a plurality of pixel blocks 300.

[0038] The pixel driving section 210 drives the pixel blocks in the pixel array section 230 in synchronization with the light emission control signal LCLK', and causes the pixel blocks to count the number of pulses.

[0039] The vertical scanning circuit 220 sequentially selects rows of pixels in synchronization with a vertical synchronization signal VSYNC, and outputs the count values ​​to a column buffer 240 .

[0040] The column buffer 240 holds the count value for each pixel.

[0041] The signal processing circuit 250 performs a predetermined signal processing on the data in which the count values ​​are arranged. For example, in the distance measurement mode, the signal processing circuit 250 calculates the distance for each pixel block 300 based on the count value, and generates a depth map in which the distance data is arranged. In the imaging mode, the signal processing circuit 250 generates image data in which the count values ​​for each pixel are arranged as pixel data, and performs various image processing on the image data. Then, the signal processing circuit 250 supplies the depth map and image data to the processor 140.

[0042] [Pixel block configuration example] 4 is a block diagram showing an example of a configuration of a pixel block 300 according to the first embodiment of the present technology. The pixel block 300 includes a pixel 310, pixels 321 to 328, an output destination control circuit 370, counters 331 to 343, and switches 351 to 363.

[0043] The pixel 310 generates a pulse signal using a SPAD. The pixel 310 supplies a pulse signal P1 to an output destination control circuit 370 and a counter 335. The configuration of the pixels 321 to 328 is the same as that of the pixel 310. These nine pixels are arranged, for example, in 3 rows and 3 columns. Furthermore, in the pixel array section 230, a vertical signal line 309 is wired for each column. The vertical signal line in the nth column (n is an integer) is designated as 309-n.

[0044] The pixel 321 generates a pulse signal P2 and supplies it to the output destination control circuit 370 and the counter 336. The pixel 322 generates a pulse signal P3 and supplies it to the output destination control circuit 370 and the counter 337. The pixel 323 generates a pulse signal P4 and supplies it to the output destination control circuit 370 and the counter 338. The pixel 324 generates a pulse signal P5 and supplies it to the output destination control circuit 370 and the counter 339.

[0045] In addition, the pixel 325 generates a pulse signal P6 and supplies it to the output destination control circuit 370 and the counter 340. The pixel 326 generates a pulse signal P7 and supplies it to the output destination control circuit 370 and the counter 341. The pixel 327 generates a pulse signal P8 and supplies it to the output destination control circuit 370 and the counter 342. The pixel 328 generates a pulse signal P9 and supplies it to the output destination control circuit 370 and the counter 343.

[0046] The output destination control circuit 370 controls the output destination of the pulse signals P1 to P9. In the distance measurement mode, the output destination control circuit 370 generates a signal of the logical sum of the pulse signals P1 to P9 in synchronization with the enable signals EN1 to EN4 from the pixel driving unit 210, and inputs the signal to the counters 331 to 334. The signal to the counter 331 is the input signal CIN1, and the signal to the counter 332 is the input signal CIN2. The signal to the counter 333 is the input signal CIN3, and the signal to the counter 334 is the input signal CIN4. On the other hand, in the imaging mode, no signal is output from the output destination control circuit 370 to the counters.

[0047] The counter 331 counts the number of input signals CIN1. Because this input signal CIN1 is the logical sum of the pulse signals of each pixel in the pixel block 300, the count value indicates the number of photons incident on the pixel block 300. The counter 331 outputs the count value to the switch 351 as CNT1.

[0048] The counters 332 to 334 have the same configuration as the counter 331. The counters 332 to 334 output the count values ​​of the input signals CIN2 to CIN4 to the switches 352 to 354 as CNT2 to CNT4.

[0049] The counter 335 counts the number of pulse signals P1. The counter 335 outputs the count value as CNT5 to the switch 355. The counters 336 to 343 have the same configuration as the counter 335. The counters 336 to 343 output the count values ​​of the pulse signals P2 to P9 to the switches 356 to 363 as CNT6 to 13.

[0050] Further, reset signals RST1 to RST13 are input to the counters 331 to 343 from the vertical scanning circuit 220. The count values ​​of the counters are initialized by the reset signals. Note that the pixel driving unit 210 can supply the reset signals instead of the vertical scanning circuit 220.

[0051] The switch 351 outputs the count value CNT1 to the column buffer 240 via the vertical signal line 309-n in accordance with the selection signal SELn from the vertical scanning circuit 220. The configuration of the switches 352 to 363 is similar to that of the switch 351. The switches 353, 355, 358, and 361 output the count value to the column buffer 240 via the vertical signal line 309-n in accordance with, for example, the selection signal SELn. The switches 352, 356, 359, and 362 output the count value to the column buffer 240 via the vertical signal line 309-(n+1) in accordance with, for example, the selection signal SEL(n+1). The switches 354, 357, 360, and 363 output the count value to the column buffer 240 via the vertical signal line 309-(n+2) in accordance with, for example, the selection signal SEL(n+2).

[0052] Although nine pixels are arranged in the pixel block 300, the number of pixels in the pixel block 300 is not limited to nine pixels and may be four pixels as described below. Although a counter is provided for each pixel, a counter can also be provided for each column. In this case, the vertical scanning circuit 220 selects the rows in sequence, and the counter group counts the pulse signals from the selected row.

[0053] [Pixel configuration example] 5 is a circuit diagram showing an example of a configuration of a pixel 310 according to the first embodiment of the present technology. The pixel 310 includes a SPAD 311, a resistor 312, and an inverter 313.

[0054] The SPAD 311 generates a photocurrent by photoelectric conversion and avalanche amplifies the photocurrent. The resistor 312 and the SPAD 311 are connected in series between a power supply terminal and a ground terminal.

[0055] The inverter 313 inverts the potential at the connection point between the resistor 312 and the SPAD 311, and outputs the inverted potential to the output destination control circuit 370 as a pulse signal P1.

[0056] Also, for example, the SPAD 311 is provided on the pixel chip 201, and the resistor 312 and inverter 313 and subsequent circuits (such as the output destination control circuit 370) are provided on the circuit chip 202. Note that the entire pixel 310 can also be provided on the pixel chip 201.

[0057] 6 is a cross-sectional view showing a configuration example of a pixel 310 in the first embodiment of the present technology. As shown in the figure, light collected by a microlens 105 is input to each layer in the pixel 310. The configuration of the area other than the microlens 105 is similar to that described in, for example, paragraphs 0024 to 0053 of JP 2018-88488 A.

[0058] [Example of output control circuit configuration] 7 is a circuit diagram showing an example of the configuration of the output destination control circuit 370 according to the first embodiment of the present technology. The output destination control circuit 370 includes OR (logical sum) gates 371-374 and AND (logical multiplication) gates 381-384.

[0059] The OR gate 371 outputs the logical sum of the pulse signals P1 to P9 to the AND gate 381. The OR gate 372 outputs the logical sum of the pulse signals P1 to P9 to the AND gate 382. The OR gate 373 outputs the logical sum of the pulse signals P1 to P9 to the AND gate 383. The OR gate 374 outputs the logical sum of the pulse signals P1 to P9 to the AND gate 384. If the pulse signals P1 to P9 are output almost simultaneously, the OR gate 371 will produce one signal after the logical sum, resulting in miscounting. For this reason, the number of inputs to the OR gate 371 may be reduced by wiring to only even numbers (such as P2 and P4), only odd numbers (such as P1 and P3), or by 1 / 3 pixels. The same applies to OR gates such as the OR gate 372.

[0060] The AND gate 381 outputs the logical product of the signal from the OR gate 371 and the enable signal EN1 from the pixel driving unit 210 to the counter 331 as the input signal CIN1. The AND gate 382 outputs the logical product of the signal from the OR gate 372 and the enable signal EN2 from the pixel driving unit 210 to the counter 332 as the input signal CIN2. The AND gate 383 outputs the logical product of the signal from the OR gate 373 and the enable signal EN3 from the pixel driving unit 210 to the counter 333 as the input signal CIN3. The AND gate 384 outputs the logical product of the signal from the OR gate 374 and the enable signal EN4 from the pixel driving unit 210 to the counter 334 as the input signal CIN4.

[0061] Here, the enable signal EN1 is the same signal as the light emission control signal LCLK. The enable signal EN2 is a signal whose phase is shifted by 90 degrees from the light emission control signal LCLK. The enable signal EN3 is a signal whose phase is shifted by 180 degrees from the light emission control signal LCLK. The enable signal EN4 is a signal whose phase is shifted by 270 degrees from the light emission control signal LCLK. In other words, the enable signals EN1 to EN4 are signals whose phase differences with the light emission control signal LCLK are 0 degrees, 90 degrees, 180 degrees, and 270 degrees.

[0062] With the configuration illustrated in the figure, the counter 331 can count the number of pulses (in other words, the number of photons) in the pixel block 300 in synchronization with the enable signal EN1 having a phase difference of 0 degrees. Furthermore, the counter 332 can count the number of pulses in the pixel block 300 in synchronization with the enable signal EN2 having a phase difference of 90 degrees. The counter 333 can count the number of pulses in the pixel block 300 in synchronization with the enable signal EN3 having a phase difference of 180 degrees. The counter 334 can count the number of pulses in the pixel block 300 in synchronization with the enable signal EN3 having a phase difference of 270 degrees.

[0063] The signal processing circuit 250 calculates the distance based on the count values ​​CNT1 to CNT4 of the counters 331 to 334, for example, using the following formula. d=(c / 4πf)×tan -1 ×{(CNT2-CNT4) / (CNT1-CNT3)}…Formula 1 In the above formula, d is the distance, for example, in meters (m). c is the speed of light, for example, in meters per second (m / s). tan -1 is the inverse function of the tangent function. The value of (CNT2-CNT4) / (CNT1-CNT3) indicates the phase difference between the irradiated light and the reflected light. π indicates the ratio of the circumference of a circle to its diameter. Furthermore, f is the frequency of the irradiated light, and its unit is, for example, megahertz (MHz).

[0064] This distance measurement method, which calculates distance based on the flight time of light, is called the ToF (Time of Flight) method.

[0065] 8 is a diagram showing an example of a correspondence relationship between circuits provided in the pixel chip 201 and the circuit chip 202 in the first embodiment of the present technology. As illustrated in the figure, SPADs for nine pixels are arranged in the pixel chip 201 for each pixel block 300. Also, 13 counters are arranged in the circuit chip 202 for each pixel block 300. Note that in the figure, circuits other than the counters in the circuit chip 202 (such as the output destination control circuit 370) are omitted.

[0066] Four of the 13 counters count the number of pulses in pixel block 300 in synchronization with enable signals with phase differences of 0 degrees, 90 degrees, 180 degrees, and 270 degrees. In the figure, the value in parentheses below the counter indicates the phase difference of the corresponding enable signal. The remaining nine counters count the number of pulses of a corresponding pixel in synchronization with the vertical synchronization signal VSYNC.

[0067] 9 is a diagram for explaining the operation of the counters in the first embodiment of the present technology. Counters #1 to #4 in the drawing represent counters 331 to 334. Counters #5 to #13 represent counters 335 to 343.

[0068] In the distance measurement mode, counters #1 to #4 count the number of pulses in the pixel block 300 in synchronization with enable signals EN1 to EN4 having phase differences of 0 degrees, 90 degrees, 180 degrees, and 270 degrees. Meanwhile, counters #5 to #13 stop counting.

[0069] In the imaging mode, the counters #5 to #13 count the number of pulses of the corresponding pixels in synchronization with the vertical synchronization signal VSYNC, while the counters #1 to #4 stop counting.

[0070] [Example of operation of solid-state imaging device] 10 is a timing chart showing an example of the operation of the solid-state imaging device 200 in the distance measurement mode according to the first embodiment of the present technology. It is assumed that the distance measurement mode is set at timing T0. The processor 140 stops supplying the vertical synchronization signal VSYNC. The vertical scanning circuit 220 supplies a reset signal RST to the counters 331 to 334 to initialize the count values.

[0071] Also, at timing T1, the driver 120 starts supplying the light emission control signal LCLK, and the light emitting unit 110 emits light in synchronization with the signal. Also, at timing T1, the pixel driving unit 210 starts supplying the enable signal EN1, which has a phase difference of 0 degrees with respect to the light emission control signal LCLK. Then, at timing T2, the pixel driving unit 210 starts supplying the enable signal EN2, which has a phase difference of 90 degrees. At timing T3, the pixel driving unit 210 starts supplying the enable signal EN3, which has a phase difference of 180 degrees. At timing T4, the pixel driving unit 210 starts supplying the enable signal EN4, which has a phase difference of 270 degrees.

[0072] After a certain period of time has elapsed, the vertical scanning circuit 220 outputs the count values ​​in response to a selection signal. The signal processing circuit 250 calculates the distance for each pixel block 300 using Equation 1 based on the count values.

[0073] 11 is a timing chart showing an example of the operation of the imaging mode of the solid-state imaging element 200 according to the first embodiment of the present technology. It is assumed that the imaging mode is set at timing T10. The processor 140 starts supplying the vertical synchronization signal VSYNC at timing T11 or later.

[0074] Furthermore, the driver 120 stops supplying the light emission control signal LCLK, and the pixel driving unit 210 stops supplying the enable signals EN1 to EN4. The vertical scanning circuit 220 supplies the reset signal RST to the counters 335 to 343 to initialize the count values. Then, during the exposure period from timing T12 to T13 synchronized with the vertical synchronization signal VSYNC, the vertical scanning circuit 220 stops supplying the reset signal RST. During this period, the counters 335 to 343 count the number of pulses, and the vertical scanning circuit 220 outputs the count values ​​in response to a selection signal. The signal processing circuit 250 generates image data in which these count values ​​are arranged.

[0075] 12 is an example of an overall diagram of a distance measuring system 100 according to the first embodiment of the present technology. In a pixel block 300, circuits other than the pixel 310 and pixels 321 to 328 are disposed in a counter unit 330.

[0076] The light emitting unit 110 emits light in synchronization with a light emission control signal LCLK, which has a higher frequency than the vertical synchronization signal VSYNC. Each of the pixels, such as the pixel 310, generates a pulse signal by photoelectric conversion.

[0077] In the distance measurement mode, the output destination control circuit 370 supplies the logical sum of the pulse signals in the pixel block 300 to the counters 331 to 334 in synchronization with the enable signals EN1 to EN4. The counters 331 to 334 count the logical sum signal. As described above, the enable signal is a signal with a predetermined phase difference (0 degrees or 90 degrees) with respect to the light emission control signal LCLK, so the count values ​​of the counters 331 to 334 are values ​​obtained by counting the number of pulses in synchronization with the light emission control signal LCLK. The counters 331 to 334 are an example of a first counter described in the claims.

[0078] On the other hand, in the imaging mode, the counters 335 to 343 count the number of pulse signals of the corresponding pixels in synchronization with the vertical synchronization signal VSYNC. Note that the counters 335 to 343 are an example of a second counter set forth in the claims.

[0079] As illustrated in the figure, the counting unit 330 is provided with counters 335 to 343 that perform counting in synchronization with a vertical synchronization signal VSYNC, and counters 331 to 334 that perform counting in synchronization with a light emission control signal LCLK. This allows the solid-state imaging element 200 to perform distance measurement using the ToF method in addition to capturing image data. Also, since the solid-state imaging element 200 itself can perform distance measurement, there is no need to add a distance measurement sensor that uses infrared rays or a laser. Therefore, the power consumption and cost of the distance measurement system 100 can be reduced compared to the case where a distance measurement sensor is added separately.

[0080] 13 is a flowchart showing an example of the operation of the distance measuring system 100 in the first embodiment of the present technology. This operation is started, for example, when an application for performing distance measuring and imaging is executed.

[0081] The distance measurement system 100 transitions to a distance measurement mode, and the light emitting unit 110 emits irradiation light in synchronization with the light emission control signal LCLK (step S901). The counters 331 to 334 count the number of pulses in synchronization with the light emission control signal LCLK (step S902). The signal processing circuit 250 then measures the distance based on the count value and generates a depth map (step S903).

[0082] Next, the ranging system 100 transitions to an imaging mode, and the solid-state imaging element 200 switches to the counters 335 to 343 to count the number of pulses within an exposure period synchronized with a vertical synchronization signal (step S904). The signal processing circuit 250 performs image processing such as face recognition based on the image data in which the count values ​​are arranged (step S905). After step S905, the ranging system 100 ends its operation.

[0083] Although the solid-state imaging device 200 performs imaging (step S904) after distance measurement (step S903), distance measurement may be performed after imaging. Also, distance measurement and imaging may be performed simultaneously.

[0084] In this way, according to the first embodiment of the present technology, the counting unit 330 counts the number of pulses in synchronization with each of the light emission control signal and the vertical synchronization signal, so that distance measurement can be performed while capturing image data in synchronization with the vertical synchronization signal at the pixel.

[0085] <2. Second embodiment> In the first embodiment described above, the counters 331 to 334 for distance measurement and the counters 335 to 343 for imaging are provided for every 9 pixels, but as the number of pixels increases, the number of counters required increases, resulting in an increase in the circuit size. The solid-state imaging element 200 of the second embodiment differs from the first embodiment in that the number of counters is reduced by using some of the counters for imaging also for distance measurement.

[0086] 14 is a block diagram showing an example of a configuration of a pixel block 300 according to a second embodiment of the present technology. The pixel block 300 according to the second embodiment differs from the pixel block 300 according to the first embodiment in that the counters 340 to 343 and the switches 360 to 363 are not provided.

[0087] Moreover, the output destination control circuit 370 of the second embodiment supplies input signals CIN1 to CIN9 to the counters 331 to 339. Moreover, the switches 351, 354, and 357 output the count value via a vertical signal line 309-n. The switches 352, 355, and 358 output the count value via a vertical signal line 309-(n+1). The switches 353, 356, and 359 output the count value via a vertical signal line 309-(n+2).

[0088] 15 is a circuit diagram showing a configuration example of an output destination control circuit 370 according to the second embodiment of the present technology. The output destination control circuit 370 according to the second embodiment differs from the first embodiment in that it further includes selectors 391 to 394.

[0089] Moreover, the AND gate 381 in the second embodiment supplies the logical product to a selector 391, and the AND gate 382 supplies the logical product to a selector 392. The AND gate 383 supplies the logical product to a selector 393, and the AND gate 384 supplies the logical product to a selector 394.

[0090] The selector 391 selects either the pulse signal P1 or the signal from the AND gate 381 in accordance with a control signal CTRL1, and supplies the selected signal to the counter 331 as an input signal CIN1.

[0091] Moreover, the pulse signal P2 is input directly to the counter 332 as the input signal CIN2.

[0092] The selector 392 selects either the pulse signal P3 or the signal from the AND gate 382 in accordance with a control signal CTRL2, and supplies the selected signal to the counter 333 as an input signal CIN3.

[0093] Moreover, the pulse signal P4 is input as it is to the counter 334 as the input signal CIN4. The pulse signals P5 and P6 are input as they are to the counters 335 and 336 as the input signals CIN5 and CIN6.

[0094] The selector 393 selects either the pulse signal P7 or the signal from the AND gate 383 in accordance with a control signal CTRL3, and supplies the selected signal to the counter 337 as an input signal CIN7.

[0095] Moreover, the pulse signal P8 is input directly to the counter 338 as the input signal CIN8.

[0096] The selector 394 selects either the pulse signal P9 or the signal from the AND gate 384 in accordance with a control signal CTRL4, and supplies the selected signal to the counter 339 as an input signal CIN9.

[0097] The above-mentioned control signals CTRL1 to CTRL4 are supplied, for example, from the pixel driving unit 210. In the distance measurement mode, the pixel driving unit 210 controls the selectors 391 to 394 by the control signals CTRL1 to CTRL4 to select signals from the AND gates 381 to 384. This allows the counters 331, 333, 337, and 339 to count the number of pulses in synchronization with the enable signals EN1 to EN4 having phase differences of 0 degrees, 90 degrees, 180 degrees, and 270 degrees. Then, the signal processing circuit 250 performs distance measurement based on these count values.

[0098] On the other hand, in the imaging mode, the pixel driving unit 210 controls the selectors 391 to 394 by the control signals CTRL1 to CTRL4 to select the pulse signals P1, P3, P7, and P9. As a result, the counters 331, 333, 337, and 339, together with the remaining counters, count the number of pulses of the corresponding pixels in synchronization with the vertical synchronization signal.

[0099] 16 is a diagram showing an example of a correspondence relationship between circuits provided on the pixel chip 201 and the circuit chip 202 according to the second embodiment of the present technology. As shown in the diagram, for each pixel block 300, SPADs for nine pixels are arranged on the pixel chip 201. In addition, for each pixel block 300, nine counters are arranged on the circuit chip 202.

[0100] In the distance measurement mode, the top left, top right, bottom left and bottom right counters among the nine counters count the number of pulses in synchronization with enable signals EN1 to EN4 having phase differences of 0 degrees, 90 degrees, 180 degrees and 270 degrees, respectively. On the other hand, in the imaging mode, each of the nine counters counts the number of pulses of the corresponding pixel in synchronization with the vertical synchronization signal.

[0101] Although the four counters used for distance measurement are arranged at the top left, top right, bottom left and bottom right, the arrangement is not limited to this.

[0102] 17 is a diagram for explaining the operation of the counters in the second embodiment of the present technology. Counters #1 to #9 in the diagram represent counters 331 to 339.

[0103] In the distance measurement mode, counters #1, #3, #7, and #9 count the number of pulses in the pixel block 300 in synchronization with enable signals EN1 to EN4 (in other words, light emission control signal LCLK) having phase differences of 0 degrees, 90 degrees, 180 degrees, and 270 degrees. Meanwhile, the remaining counters stop counting.

[0104] In the imaging mode, the counters #1 to #9 count the number of pulses of the corresponding pixels in synchronization with the vertical synchronization signal VSYNC.

[0105] As shown in the figure, counters #1, #3, #7, and #9 sequentially count the number of pulses in the pixel block 300 in synchronization with the light emission control signal LCLK, and then count the number of pulses in synchronization with the vertical synchronization signal VSYNC. The remaining counters #2, #4, #5, #6, and #8 count the number of pulses in synchronization with the vertical synchronization signal VSYNC. In other words, four of the nine counters used for imaging are also used for distance measurement. This allows the number of counters to be reduced compared to the first embodiment in which nine counters for imaging and four counters for distance measurement are provided separately.

[0106] Note that counters #1, #3, #7 and #9 are examples of a first counter described in the claims, and counters #2, #4, #5, #6 and #8 are examples of a second counter described in the claims.

[0107] In this way, in the second embodiment of the present technology, the four counters sequentially count the number of pulses in synchronization with the light emission control signal and the vertical synchronization signal. This eliminates the need to provide separate counters for imaging and distance measurement, allowing the number of counters to be reduced.

[0108] <3. Third embodiment> In the second embodiment described above, the four counters count the number of pulses in synchronization with the enable signal having a phase difference of 0 degrees to 270 degrees, but in this configuration, the range of distances that can be measured may be insufficient. The solid-state imaging device 200 of the third embodiment differs from the second embodiment in that the range of phase differences is widened to expand the range of distances that can be measured.

[0109] 18 is a circuit diagram showing a configuration example of an output destination control circuit 370 according to a third embodiment of the present technology. The output destination control circuit 370 according to the third embodiment differs from the second embodiment in that it further includes OR gates 375 to 379, AND gates 385 to 389, and selectors 395 to 399.

[0110] The connections between the OR gates 375 to 379 , the AND gates 385 to 389 , and the selectors 395 to 399 are similar to those of the OR gate 371 , the AND gate 381 , and the selector 391 .

[0111] Enable signals EN5 to EN9 are input to the AND gates 385 to 389. Control signals CTRL5 to CRTRL9 are input to the selectors 395 to 399. The selectors 391 to 399 select either the pulse signals P1 to P9 or the signals from the AND gates 381 to 389, and supply them to the counters 331 to 339 as input signals CIN1 to CIN9.

[0112] The phase differences of the enable signals EN1 to EN9 are set to, for example, 0 degrees, 360 degrees, 90 degrees, 450 degrees, 720 degrees, 630 degrees, 270 degrees, 540 degrees, and 180 degrees. By setting the phase difference of the enable signals to be between 0 degrees and 720 degrees, the range of distances that the signal processing circuit 250 can measure can be expanded compared to when the phase difference is between 0 degrees and 270 degrees.

[0113] In the distance measurement mode, the signal processing circuit 250 obtains a rough distance based on a phase difference of, for example, 0 to 720 degrees, and then obtains a precise distance based on a phase difference of, for example, 0 to 540 degrees. In this way, by gradually narrowing the range of the phase difference, the accuracy of the distance can be gradually improved.

[0114] 19 is a diagram showing an example of a correspondence relationship between circuits provided on the pixel chip 201 and the circuit chip 202 according to the third embodiment of the present technology. As illustrated in the figure, SPADs for nine pixels are arranged on the pixel chip 201 for each pixel block 300. In addition, nine counters are arranged on the circuit chip 202 for each pixel block 300.

[0115] In distance measurement mode, of the nine counters, the top left, top right, bottom left and bottom right counters count the number of pulses in synchronization with enable signals with phase differences of 0 degrees, 90 degrees, 180 degrees and 270 degrees. The center counter counts the number of pulses in synchronization with enable signals with phase differences of 720 degrees. The center counters on the top, bottom, left and right count the number of pulses in synchronization with enable signals with phase differences of 360 degrees, 540 degrees, 450 degrees and 630 degrees.

[0116] 20 is a diagram for explaining the operation of the counter in the third embodiment of the present technology. In the distance measurement mode, the counters #1 to #9 count the number of pulses in the pixel block 300 in synchronization with the enable signals with phase differences of 0 degrees, 360 degrees, 90 degrees, 450 degrees, 720 degrees, 630 degrees, 270 degrees, 540 degrees, and 180 degrees.

[0117] In the imaging mode, the counters #1 to #9 count the number of pulses of the corresponding pixels in synchronization with the vertical synchronization signal VSYNC.

[0118] In this way, according to the third embodiment of the present technology, nine counters count the number of pulses in synchronization with nine enable signals having different phase differences, thereby enabling the measurable distance range to be expanded compared to the case where counting is performed in synchronization with four enable signals.

[0119] <4. Fourth embodiment> In the above-mentioned third embodiment, nine counters count the number of pulses in synchronization with an enable signal, but in this configuration, the amount of data used for distance measurement increases, which may increase the amount of processing by the signal processing circuit 250. The solid-state imaging device 200 of the fourth embodiment differs from the third embodiment in that the number of counters used for distance measurement is reduced.

[0120] 21 is a circuit diagram showing a configuration example of an output destination control circuit 370 according to a fourth embodiment of the present technology. The output destination control circuit 370 according to the fourth embodiment differs from the third embodiment in that the OR gate 375, the AND gate 385, and the selector 395 are eliminated. In addition, the pulse signal P5 is directly supplied to the counter 335 as the input signal CIN5.

[0121] 22 is a diagram showing an example of a correspondence relationship between circuits provided in a pixel chip 201 and a circuit chip 202 according to a fourth embodiment of the present technology. The pixel block 300 according to the fourth embodiment differs from the third embodiment in that the central counter does not count in the distance measurement mode.

[0122] 23 is a diagram for explaining the operation of the counters in the fourth embodiment of the present technology. In the distance measurement mode, eight counters other than counter #5 count the number of pulses in synchronization with an enable signal. In other words, the number of counters used for distance measurement is reduced from nine to eight. This reduces the number of data used for distance measurement, and reduces the amount of processing by the signal processing circuit 250. Note that the counters other than counter #5 are an example of a first counter described in the claims, and counter #5 is an example of a second counter described in the claims.

[0123] In this way, according to the fourth embodiment of the present technology, eight counters count the number of pulses in synchronization with the enable signal, thereby reducing the number of data used for ranging compared to the case where nine counters count in synchronization with the enable signal.

[0124] <5. Fifth embodiment> In the first embodiment described above, only one counter synchronized with an enable signal with a phase difference of 0 degrees is provided for each pixel block, but this configuration may cause the quality of the signal from the counter to be insufficient. The solid-state imaging device 200 of the fifth embodiment differs from the first embodiment in that it improves signal quality by providing two or more counters synchronized with the same enable signal.

[0125] FIG. 24 is a diagram showing an example of a circuit provided in a pixel block 300 in the fifth embodiment of the present technology. The pixel block 300 is divided into a plurality of areas. For example, the pixel block 300 is divided into a 0 degree area 410, a 90 degree area 420, a 180 degree area 430, and a 270 degree area 440. In the 0 degree area 410, nine counters such as a counter 411 are arranged in 3 rows x 3 columns. In the 90 degree area 420, nine counters such as a counter 421 are arranged in 3 rows x 3 columns. In the 180 degree area 430, nine counters such as a counter 431 are arranged in 3 rows x 3 columns. In the 270 degree area 440, nine counters such as a counter 441 are arranged in 3 rows x 3 columns. The number of pixels in each area is the same as the number of counters (i.e., 9).

[0126] In the 0 degree area 410, the upper left, upper right, lower left and lower right counters count the number of pulses in the 0 degree area 410 in synchronization with an enable signal with a phase difference of 0 degrees. In the 90 degree area 420, the upper left, upper right, lower left and lower right counters count the number of pulses in the 90 degree area 420 in synchronization with an enable signal with a phase difference of 90 degrees. In the 180 degree area 430, the upper left, upper right, lower left and lower right counters count the number of pulses in the 180 degree area 430 in synchronization with an enable signal with a phase difference of 180 degrees. In the 270 degree area 440, the upper left, upper right, lower left and lower right counters count the number of pulses in the 270 degree area 440 in synchronization with an enable signal with a phase difference of 270 degrees.

[0127] An output destination control circuit 370 is arranged in each of the 0 degree area 410, the 90 degree area 420, the 180 degree area 430, and the 270 degree area 440. In the figure, the output destination control circuit 370 is omitted. The configuration of the output destination control circuit 370 in the fifth embodiment is similar to that in the second embodiment illustrated in Figure 15. However, the same enable signal is input to the four counters.

[0128] As shown in the figure, four count values ​​are generated for each pixel block 300 by counting in synchronization with enable signals having the same phase difference. The signal processing circuit 250 calculates the sum or average of these four count values ​​and performs distance measurement using the calculation result. By calculating the sum or average of the four count values, it is possible to reduce signal noise and improve signal quality.

[0129] The counters at the top left, top right, bottom left, and bottom right of each area are an example of the first counter described in the claims, and the other counters are an example of the second counter described in the claims. In addition, the number of areas in each pixel block 300 is not limited to four, and the number of pixels in each area is not limited to nine.

[0130] In this way, according to the fifth embodiment of the present technology, four counters that count in synchronization with enable signals having the same phase difference are arranged for each pixel block 300, so that signal noise can be reduced by calculating the sum or average of these count values.

[0131] <6. Sixth embodiment> In the above-mentioned fifth embodiment, nine pixels are arranged for each area, but in this configuration, the number of pixels in the pixel block 300 is 36, which may cause the resolution of the depth map to be insufficient. The solid-state imaging element 200 of the sixth embodiment differs from the fifth embodiment in that the number of pixels for each area is reduced and the resolution of the depth map is improved.

[0132] 25 is a diagram showing an example of a circuit provided in a pixel block 300 in a sixth embodiment of the present technology. The pixel block 300 in the sixth embodiment differs from the fifth embodiment in that the number of pixels per area is four. The four pixels are arranged in two rows and two columns. In addition, a counter that counts the number of pulses in synchronization with an enable signal is arranged in the upper left for each area.

[0133] As shown in the figure, the number of pixels per area is reduced to four pixels, thereby improving the resolution of the depth map compared to the fifth embodiment in which the number of pixels per area is nine pixels.

[0134] 26 is a block diagram showing an example of a configuration of a 0-degree area 410 according to the sixth embodiment of the present technology. The pixels 310, 321 to 323, and a counting unit 330 are arranged in the 0-degree area 410. The counting unit 330 includes an output destination control circuit 370, counters 411 to 414, and switches 351 to 354.

[0135] The pixels 310, 321 to 323 output pulse signals P1 to P4 to an output destination control circuit 370. The output destination control circuit 370 supplies input signals CIN1 to CIN4 to counters 411 to 414. The counters 411 to 414 supply count values ​​CNT1 to CNT4 to switches 351 to 354. The switches 351 and 353 supply the count values ​​to a vertical signal line 309-n, and the switches 352 and 354 supply the count values ​​to a vertical signal line 309-(n+1).

[0136] The configurations of the 90 degree area 420 , the 180 degree area 430 and the 270 degree area 440 are similar to that of the 0 degree area 410 .

[0137] 27 is a circuit diagram showing a configuration example of an output destination control circuit 370 in the sixth embodiment of the present technology. An OR gate 371, an AND gate 381, and a selector 391 are arranged in this output destination control circuit 370. The connection configuration of the OR gate 371, the AND gate 381, and the selector 391 in the sixth embodiment is the same as that in FIG. 15 of the second embodiment, except that the output destination is a counter 411.

[0138] Moreover, the pulse signals P2 to P4 are directly supplied to the counters 412 to 414 as the input signals CIN2 to CIN4.

[0139] The counter 411 is an example of a first counter as defined in the claims, and the counters 412 to 414 are an example of a second counter as defined in the claims.

[0140] In this way, according to the sixth embodiment of the present technology, the number of pixels per area is reduced to four pixels, thereby enabling the resolution of the depth map to be improved compared to when the number of pixels per area is nine pixels.

[0141] <7. Seventh embodiment> In the sixth embodiment described above, four areas are arranged for each pixel block, but in this configuration, the number of pixels in the pixel block 300 is 16, which may cause the resolution of the depth map to be insufficient. The solid-state imaging device 200 of the seventh embodiment differs from the sixth embodiment in that the number of areas is reduced and the resolution of the depth map is improved.

[0142] 28 is a diagram showing an example of a circuit provided in a pixel block in the seventh embodiment of the present technology. The pixel block 300 in the seventh embodiment is different from the sixth embodiment in that the number of areas is two. For example, a 0 degree area 410 and a 180 degree area 430 are provided in the pixel block 300. By reducing the number of areas in the pixel block 300 from four to two, the size of the pixel block 300 can be reduced. This can improve the resolution of the depth map.

[0143] 29 is a timing chart showing an example of the operation of the solid-state imaging device 200 in the seventh embodiment of the present technology in the distance measurement mode. It is assumed that the distance measurement mode is set at timing T0. The processor 140 stops supplying the vertical synchronization signal VSYNC. The vertical scanning circuit 220 supplies a reset signal RST to the counters 331 to 334 to initialize the count values.

[0144] Also, at timing T1, driver 120 starts supplying a light emission control signal LCLK, and light emitting unit 110 emits light in synchronization with this signal. Also, at timing T1, pixel driving unit 210 starts supplying enable signal EN1, which has a phase difference of 0 degrees with respect to light emission control signal LCLK. Then, at timing T2, pixel driving unit 210 starts supplying enable signal EN2, which has a phase difference of 180 degrees.

[0145] After a certain period of time has elapsed, the vertical scanning circuit 220 outputs the count values ​​in response to a selection signal. The signal processing circuit 250 calculates the distance for each pixel block 300 based on the count values.

[0146] In this way, according to the seventh embodiment of the present technology, the number of areas for each pixel block 300 is reduced to two, so that the resolution of the depth map can be improved compared to when the number of areas is four.

[0147] <8. Eighth embodiment> In the seventh embodiment described above, the counter counts the number of pulses in synchronization with enable signals with phase differences of 0 and 180 degrees, but because enable signals of 90 and 270 degrees are not used, the distance measurement accuracy decreases and the measurable distance range becomes narrow. The solid-state imaging device 200 of the eighth embodiment differs from the seventh embodiment in that the counter counts the number of pulses in synchronization with enable signals with phase differences of 90 and 270 degrees in addition to enable signals with phase differences of 0 and 180 degrees.

[0148] 30 is a diagram showing an example of a circuit provided in a pixel block 300 in an eighth embodiment of the present technology. The pixel block 300 in the eighth embodiment is different from the seventh embodiment in that it is not divided into a plurality of areas, but has counters 411 to 414 arranged therein. Furthermore, four pixels are arranged in the pixel block 300. In the figure, circuits other than the counters (such as an output destination control circuit 370) are omitted.

[0149] In the distance measurement mode, counters 411 and 414 count the number of pulses in synchronization with the enable signals of 0 degrees and 180 degrees, and counters 412 and 413 count the number of pulses in synchronization with the enable signals of 90 degrees and 270 degrees.

[0150] 31 is a circuit diagram showing a configuration example of an output destination control circuit 370 according to an eighth embodiment of the present technology. The output destination control circuit 370 according to the eighth embodiment includes OR gates 371 to 374, AND gates 381 to 384, and selectors 391 to 394.

[0151] The connection configuration of the OR gates 371 to 374, the AND gates 381 to 384, and the selectors 391 to 394 is similar to that of the OR gate 371, the AND gate 381, and the selector 391 in the second embodiment.

[0152] Enable signals EN1 to EN4 are input to the AND gates 381 to 384. Control signals CTRL1 to CTRL4 are input to the selectors 391 to 394. The selectors 391 to 394 also select either the pulse signals P1 to P4 or the signals from the AND gates 381 to 384, and supply them to the counters 411 to 414 as input signals CIN1 to CIN4.

[0153] 32 is a timing chart showing an example of the operation of the solid-state imaging device 200 in the eighth embodiment of the present technology in the distance measurement mode. It is assumed that the distance measurement mode is set at timing T0. The processor 140 stops supplying the vertical synchronization signal VSYNC. The vertical scanning circuit 220 supplies a reset signal RST to the counters 331 to 334 to initialize the count values.

[0154] Also, at timing T1, driver 120 starts supplying a light emission control signal LCLK, and light emitting unit 110 emits light in synchronization with that signal. Also, at timing T1, pixel driving unit 210 starts supplying enable signals EN1 and EN4, which have a phase difference of 0 degrees with respect to light emission control signal LCLK. Then, at timing T2, pixel driving unit 210 starts supplying enable signals EN2 and EN3, which have a phase difference of 90 degrees.

[0155] After a certain period of time has elapsed, the vertical scanning circuit 220 outputs the count values ​​in response to a selection signal, and the signal processing circuit 250 holds the count values.

[0156] Next, at timing T3, vertical scanning circuit 220 supplies reset signal RST to counters 331 to 334 to initialize the count values. At timing T4, pixel driving unit 210 starts supplying enable signals EN1 and EN4 that have a phase difference of 180 degrees with respect to light emission control signal LCLK. Then, at timing T5, pixel driving unit 210 starts supplying enable signals EN2 and EN3 that have a phase difference of 270 degrees.

[0157] After a certain period of time has elapsed, the vertical scanning circuit 220 outputs the count value in response to a selection signal. The signal processing circuit 250 calculates the distance for each pixel block 300 based on the held count value and the output count value.

[0158] As illustrated in the figure, the pixel driving unit 210 supplies an enable signal in which a plurality of set values ​​(such as 90 degrees and 270 degrees) are sequentially set as phase differences. By switching the phase difference in this way, the counter can count the number of pulses in synchronization with enable signals with phase differences of 90 degrees and 270 degrees, in addition to enable signals with phase differences of 0 degrees and 180 degrees. Since the number of phase differences is increased, the accuracy of distance measurement can be improved and the range of distances that can be measured can be expanded.

[0159] Although all four counters are performing counting in the distance measurement mode, it is also possible for only two counters (such as counters 411 and 412) to perform counting in the distance measurement mode. By reducing the number of counters operating in the distance measurement mode, it is possible to reduce power consumption.

[0160] In this way, according to the eighth embodiment of the present technology, the pixel driving unit 210 sets each of the multiple setting values ​​to the phase difference in sequence, so that the number of phase differences can be increased. This improves the distance measurement accuracy and expands the measurable distance range.

[0161] <9. Ninth embodiment> In the above-mentioned eighth embodiment, the pixel driving unit 210 switches the phase difference, but in this configuration, the distance measurement interval becomes longer than when the phase difference is fixed, and the frame rate of the depth map decreases. The solid-state imaging device 200 of the ninth embodiment differs from the eighth embodiment in that the phase difference is fixed to improve the frame rate of the depth map.

[0162] 33 is a diagram showing an example of a circuit provided in a pixel block 300 according to the ninth embodiment of the present technology. In the pixel block 300 according to the ninth embodiment, counters 411 to 414 are arranged in the same manner as in the eighth embodiment.

[0163] However, in the ranging mode, the phase difference between the enable signals EN1 to EN4 is fixed. For example, the counter 411 counts the number of pulses in synchronization with the enable signal EN1 of 0 degrees, and the counter 412 counts the number of pulses in synchronization with the enable signal EN2 of 90 degrees. The counter 413 counts the number of pulses in synchronization with the enable signal EN3 of 180 degrees, and the counter 414 counts the number of pulses in synchronization with the enable signal EN4 of 270 degrees. Since the phase difference is fixed, the frame rate of the depth map is improved compared to the eighth embodiment.

[0164] In this way, according to the ninth embodiment of the present technology, the pixel driving unit 210 fixes the phase difference of the enable signal, thereby improving the frame rate of the depth map compared to the case where the phase difference is switched.

[0165] <10. Tenth embodiment> In the above-mentioned ninth embodiment, the counter counts the number of pulses in units of four pixels in the distance measurement mode, but as the number of pixels to be counted increases, the maximum count value becomes larger and the data size of the count value becomes larger. The solid-state imaging device 200 of the tenth embodiment differs from the ninth embodiment in that the number of pixels to be counted can be switched between four pixels and two pixels, making the data size variable.

[0166] 34 is a diagram showing an example of a circuit provided in a pixel block in the tenth embodiment of the present technology. In the pixel block 300 in the tenth embodiment, for example, a 0 degree area 410 and a 180 degree area 430 are provided. In addition, four pixels and an output destination control circuit 370 are provided for each area. In the distance measurement mode, one of the four counters in the area counts the number of pulses in synchronization with an enable signal. In the imaging mode, each of the four counters counts the number of pulses in synchronization with a vertical synchronization signal.

[0167] 35 is a circuit diagram showing an example of a configuration of an output destination control circuit 370 according to the tenth embodiment of the present technology. The output destination control circuit 370 according to the tenth embodiment includes OR gates 371, 372, and 380, AND gates 381 and 382, ​​and a selector 391.

[0168] The OR gate 371 supplies the logical sum of the pulse signals P1 and P2 to the AND gate 381. The OR gate 372 supplies the logical sum of the pulse signals P3 and P4 to the AND gate 382.

[0169] The AND gate 381 supplies the logical product of the signal from the OR gate 371 and the enable signal EN1a to the OR gate 380. The AND gate 382 supplies the logical product of the signal from the OR gate 372 and the enable signal EN1b to the OR gate 380.

[0170] The OR gate 380 outputs the logical sum of the signals from the AND gates 381 and 382 to the selector 391 .

[0171] The selector 391 selects either the pulse signal P1 or the signal from the OR gate 380 in accordance with a control signal CTRL, and supplies the selected signal to the counter 411 as an input signal CIN1.

[0172] Moreover, the pulse signals P2 to P4 are directly supplied to the counters 412 to 414 as the input signals CIN2 to CIN4.

[0173] The counter 411 is an example of a first counter as defined in the claims, and the counters 412 to 414 are an example of a second counter as defined in the claims.

[0174] 36 is a diagram for explaining the operation of the pixel driving unit 210 in the tenth embodiment of the present technology. The control in the figure corresponds to the 0 degree area 410. In the tenth embodiment, the distance measurement mode is set to either a four-pixel addition mode or a two-pixel addition mode. The four-pixel addition mode is a mode in which the number of pixels targeted for counting the pulse signal is four, and the two-pixel addition mode is a mode in which the number of pixels targeted for counting the pulse signal is two.

[0175] In the four-pixel addition mode, the pixel driving unit 210 supplies a signal with a phase difference of 0 degrees as the enable signals EN1a and EN1b. In the two-pixel addition mode, the pixel driving unit 210 supplies a signal with a phase difference of 0 degrees as one of the enable signals EN1a and EN1b. The other of the enable signals EN1a and EN1b is not supplied. In the imaging mode, no enable signal is supplied. Note that the control of the 180-degree area 430 is similar to that of the 0-degree area 410 illustrated in the same figure, except that the phase difference is set to 180 degrees.

[0176] Furthermore, in the distance measurement mode, the pixel driving unit 210 sets the control signal CTRL to "0" to cause the selector 391 to select the signal from the OR gate 380. On the other hand, in the imaging mode, the pixel driving unit 210 sets the control signal CTRL to "1" to cause the selector 391 to select the pulse signal P1.

[0177] 35 and 36, output destination control circuit 370 outputs the logical sum of the pulse signals of a set number (four or two) of the four pixels in pixel block 300, and counter 411 counts the logical sum. This makes it possible to switch the number of pixels to be counted between four and two, and change the data size of the count value.

[0178] It should be noted that pixel driving section 210 switches the number of pixels to be counted between four pixels and two pixels, but is not limited to this configuration, and can also be switched to, for example, one pixel or three pixels.

[0179] In this way, according to the tenth embodiment of the present technology, the counter 411 counts the logical sum of the pulse signals of a set number of pixels among the four pixels in the pixel block 300, so that the data size of the count value can be changed.

[0180] <11. Application examples for mobile devices> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, etc.

[0181] FIG. 37 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a moving object control system to which the technology according to the present disclosure can be applied.

[0182] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 37, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also, as functional configurations of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053 are illustrated.

[0183] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0184] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as head lamps, back lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves or signals of various switches transmitted from a portable device that replaces a key may be input to the body system control unit 12020. The body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, and the like of the vehicle.

[0185] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for a person, a car, an obstacle, a sign, or characters on a road surface, based on the received image.

[0186] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0187] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing.

[0188] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the outside-of-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0189] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on the driver's operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0190] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0191] The audio / video output unit 12052 transmits at least one output signal of audio and image to an output device capable of visually or audibly notifying information to passengers in the vehicle or the outside of the vehicle. In the example of Fig. 37, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as the output device. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.

[0192] FIG. 38 is a diagram showing an example of the installation position of the imaging unit 12031.

[0193] In FIG. 38, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0194] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin is mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

[0195] 38 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.

[0196] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of a plurality of imaging elements, or may be an imaging element having pixels for detecting a phase difference.

[0197] For example, the microcomputer 12051 can extract, as a preceding vehicle, a three-dimensional object that is the closest three-dimensional object on the travel path of the vehicle 12100 and travels at a predetermined speed (for example, 0 km / h or more) in approximately the same direction as the vehicle 12100, by calculating the distance to each three-dimensional object in the imaging ranges 12111 to 12114 and the change over time of this distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. Furthermore, the microcomputer 12051 can set a vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving that travels autonomously without relying on the driver's operation.

[0198] For example, the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0199] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured images of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

[0200] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the imaging unit 12031 among the configurations described above. Specifically, the solid-state imaging element 200 in FIG. 3 can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, distance measurement can be performed without adding a sensor, thereby reducing the power consumption and cost of the vehicle control system.

[0201] The above-mentioned embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specified in the claims correspond to each other. Similarly, the matters specified in the claims and the matters in the embodiment of the present technology having the same name correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist of the technology.

[0202] The processing procedures described in the above embodiments may be regarded as a method having a series of these procedures, or as a program for causing a computer to execute the series of procedures or a recording medium for storing the program. For example, a CD (Compact Disc), an MD (MiniDisc), a DVD (Digital Versatile Disc), a memory card, a Blu-ray (registered trademark) Disc, etc. may be used as this recording medium.

[0203] It should be noted that the effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0204] The present technology can also be configured as follows. (1) a light-emitting unit that emits light in synchronization with a light-emitting control signal having a frequency higher than that of a predetermined vertical synchronization signal; A predetermined number of pixels each generating a pulse signal by photoelectric conversion; a counter that counts the number of the pulse signals in synchronization with each of the light emission control signal and the vertical synchronization signal; A sensing system comprising: (2) The counting unit is a first counter that counts the pulse signals in synchronization with the light emission control signal; a second counter that counts the pulse signals in synchronization with the vertical synchronization signal; The sensing system according to (1) above, comprising: (3) The counting unit is a first counter that sequentially counts the pulse signals in synchronization with the light emission control signal and counts the pulse signals in synchronization with the vertical synchronization signal; a second counter that counts the pulse signals in synchronization with the vertical synchronization signal; The sensing system according to (1) above, comprising: (4) the pixel array portion in which the predetermined number of pixels are arranged is divided into a plurality of pixel blocks; the counting unit is provided for each of the pixel blocks, The first counter counts the logical sum of the pulse signals from each of the pixels in the pixel block. The sensing system described in (3) above. (5) The sensing system according to (4), wherein four of the first counters and five of the second counters are arranged for each pixel block. (6) The sensing system according to (4), wherein eight of the first counters and one of the second counters are arranged for each pixel block. (7) The pixel array unit in which the predetermined number of pixels are arranged is divided into a plurality of pixel blocks, Each of the plurality of pixel blocks is divided into a plurality of areas, The counting unit is provided in association with each of the plurality of areas, The first counter counts the logical sum of the pulse signals from each of the pixels in the corresponding area. The sensing system described in (3) above. (8) Nine of the pixels are arranged in each of the plurality of areas. The sensing system described in (7) above. (9) Four of the pixels are arranged in each of the plurality of areas. The sensing system described in (7) above. (10) Within the pixel block, four areas are arranged. A sensing system according to any one of (7) to (9). (11) Two areas are arranged within the pixel block. A sensing system according to any one of (7) to (9). (12) The first counter counts the logical sum of the pulse signals of a set number of pixels among the pixels in the pixel block. A sensing system according to any one of (7) to (9). (13) The counting unit includes a predetermined number of counters that sequentially perform a process of counting the pulse signals in synchronization with the light emission control signal and a process of counting the pulse signals in synchronization with the vertical synchronization signal. The sensing system described in (1) above. (14) The counting unit includes nine of the counters. The sensing system according to (13) above. (15) The counting unit includes four of the counters. The sensing system according to (13) above. (16) A pixel driving unit that supplies an enable signal to which a plurality of setting values ​​are sequentially set as a phase difference with respect to the light emission control signal, The counter supplies the pulse signal in synchronization with the enable signal. A sensing system according to any one of (13) to (15). (17) a light-emitting unit that emits light in synchronization with a light-emitting control signal having a frequency higher than that of a predetermined vertical synchronization signal; A predetermined number of pixels each generating a pulse signal by photoelectric conversion; a counter that counts the number of the pulse signals in synchronization with each of the light emission control signal and the vertical synchronization signal; a distance measuring unit that measures a distance to an object based on a count value of the counting unit; A ranging system comprising: (18) a light emitting unit that emits irradiation light based on a light emission control signal; A plurality of pixels each generating a pulse signal by photoelectric conversion; A counting unit that counts the number of pulse signals of the plurality of pixels; Equipped with the counting unit includes a plurality of counters; and an output destination control circuit connected between the plurality of pixels and the plurality of counters, receiving a plurality of pulse signals output from the plurality of pixels, and distributing the plurality of pulse signals to any of a plurality of counters; The plurality of pixels are provided on a first chip, The output control circuit and the counter unit are provided on a second chip. Sensing system. [Explanation of symbols]

[0205] 100 Distance Measuring System 105 Micro Lens 110 Light emitting part 120 Driver 130 Controller 140 processors 150 Application Processors 200 Solid-state image sensor 201 Pixel Chip 202 Circuit Chip 210 Pixel driving unit 220 Vertical scanning circuit 230 Pixel array section 240 Column Buffer 250 Signal Processing Circuit 260 Output section 300 pixel block 310, 321-328 pixels 311 SPAD 312 Resistance 313 Inverter 330 Counting Department 331~343, 411~414, 421, 431, 441 Counter 351~363 Switch 370 Output destination control circuit 371~380 OR gate 381~389 AND gate 391~399 Selector 410 0 degree area 420 90 degree area 430 180 degree area 440 270 degree area 12031 Imaging unit

Claims

1. a light emitting unit that irradiates irradiation light in synchronization with a light emission control signal having a frequency higher than a predetermined vertical synchronization signal; A predetermined number of pixels each generating a pulse signal by photoelectric conversion; a counter that counts the number of the pulse signals in synchronization with each of the light emission control signal and the vertical synchronization signal; a signal processing circuit for measuring a distance to an object based on the count value of the counting unit; A driver that generates the light emission control signal and supplies it to the light emitting unit; a controller that stops the driver when an imaging mode is set and causes the driver to generate the light emission control signal when a distance measurement mode is set; Equipped with The counting unit is a first counter that sequentially counts the pulse signals in synchronization with the light emission control signal and counts the pulse signals in synchronization with the vertical synchronization signal; a second counter that counts the pulse signals in synchronization with the vertical synchronization signal; Equipped with The pixel array unit in which the predetermined number of pixels are arranged is divided into a plurality of pixel blocks, Each of the plurality of pixel blocks is divided into a plurality of areas, The counting unit is provided in association with each of the plurality of areas, The first counter counts the logical sum of the pulse signals from each of the pixels in a corresponding area; the plurality of areas includes a first area and a second area; two or more of the first counters are arranged in the first area, the first counters counting the logical sum in synchronization with a first enable signal, the phase difference of which with respect to the light emission control signal is set to a predetermined value; two or more of the first counters are arranged in the second area, the first counters counting the logical sum in synchronization with a second enable signal having a phase difference different from the predetermined value; The signal processing circuit calculates statistics of the count values ​​of the first counter for each of the phase differences and measures the distance based on the statistics. Ranging system.

2. Nine of the pixels are arranged in each of the plurality of areas.

2. The ranging system according to claim 1.

3. Four of the pixels are arranged in each of the plurality of areas.

2. The ranging system according to claim 1.

4. Within the pixel block, four areas are arranged.

2. The ranging system according to claim 1.

5. A light emitting unit that irradiates irradiation light based on a light emission control signal having a frequency higher than that of a predetermined vertical synchronization signal; A plurality of pixels each generating a pulse signal by photoelectric conversion; A counting unit that counts the number of pulse signals of the plurality of pixels; a signal processing circuit for measuring a distance to an object based on the count value of the counting unit; A driver that generates the light emission control signal and supplies it to the light emitting unit; a controller that stops the driver when an imaging mode is set and causes the driver to generate the light emission control signal when a distance measurement mode is set; Equipped with the counting unit includes a plurality of counters; and an output destination control circuit connected between the plurality of pixels and the plurality of counters, receiving a plurality of pulse signals output from the plurality of pixels, and distributing the plurality of pulse signals to any of a plurality of counters; The plurality of pixels are provided on a first chip, the output control circuit, the signal processing circuit, and the counter are provided in a second chip; The counting unit is a first counter that sequentially counts the pulse signals in synchronization with the light emission control signal and counts the pulse signals in synchronization with the vertical synchronization signal; a second counter that counts the pulse signals in synchronization with the vertical synchronization signal; Equipped with The pixel array unit in which the predetermined number of pixels are arranged is divided into a plurality of pixel blocks, Each of the plurality of pixel blocks is divided into a plurality of areas, The counting unit is provided in association with each of the plurality of areas, The first counter counts the logical sum of the pulse signals from each of the pixels in a corresponding area; the plurality of areas includes a first area and a second area; two or more of the first counters are arranged in the first area, the first counters counting the logical sum in synchronization with a first enable signal, the phase difference of which with respect to the light emission control signal is set to a predetermined value; two or more of the first counters are arranged in the second area, the first counters counting the logical sum in synchronization with a second enable signal having a phase difference different from the predetermined value; The signal processing circuit calculates statistics of the count values ​​of the first counter for each of the phase differences and measures the distance based on the statistics. Ranging system.

Images