Solid-state imaging device and imaging apparatus

Abstract

The present invention makes it possible to maintain dynamic range even in low light. A solid-state imaging device (200) is provided with a plurality of detecting pixels (300) each of which outputs a change in the brightness of incident light, a detecting circuit (305) which outputs an event signal on the basis of the change in brightness output from each of the detecting pixels, and a first common line (3101) connecting the plurality of detecting pixels together, wherein: each of the detecting pixels is provided with a photoelectric conversion element (311), a logarithmic conversion circuit (312, 313) which converts a photoelectric current flowing out from the photoelectric conversion element into a voltage signal corresponding to the logarithmic value of the photoelectric current, a first circuit (340) which outputs the change in brightness of the incident light incident on the photoelectric conversion element on the basis of the voltage signal output from the logarithmic conversion circuit, a first transistor (317) connected between the photoelectric conversion element and the logarithmic conversion circuit, and a second transistor (318) connected between the photoelectric conversion element and the first common line; and the detecting circuit is provided with a second circuit (500) which outputs the event signal on the basis of the change in brightness output from each detecting pixel.

Description

[Technical field]

[0001] The present disclosure relates to a solid-state imaging device and an imaging apparatus. [Background technology]

[0002] Conventionally, in imaging devices and the like, a synchronous solid-state imaging device is used that captures image data (frames) in synchronization with a synchronous signal such as a vertical synchronous signal. In this general synchronous solid-state imaging device, image data can only be acquired at every synchronous signal period (e.g., 1 / 60 seconds), making it difficult to respond to cases where faster processing is required in fields related to traffic, robots, and the like. Therefore, an asynchronous solid-state imaging device has been proposed that detects, for each pixel address, the fact that the amount of change in the luminance of that pixel exceeds a threshold as an address event (see, for example, Patent Document 1). A solid-state imaging device that detects an address event for each pixel in this way is also called an EVS (Event-based Vision Sensor) or a DVS (Dynamic Vision Sensor). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 5244587 Summary of the Invention [Problem to be solved by the invention]

[0004] In the above-mentioned asynchronous solid-state imaging device, the transistors constituting the address event detection circuit operate in the subthreshold region, so the dynamic range at low illuminance depends heavily on the ratio (S / N) of the thermal noise (N) of the transistor to the photocurrent (S). In particular, when pixels are miniaturized to reduce size and improve resolution, the photocurrent per pixel decreases, lowering the S / N ratio and making the dynamic range at low illuminance very narrow. This can result in problems such as a decrease in sensitivity to the occurrence of address events and an increase in false detections.

[0005] In view of this, the present disclosure proposes a solid-state imaging device and an imaging apparatus that make it possible to ensure a dynamic range even in low illuminance conditions. [Means for solving the problem]

[0006] In order to solve the above problems, a solid-state imaging device of one embodiment according to the present disclosure includes a plurality of detection pixels each outputting a luminance change of incident light, a detection circuit outputting an event signal based on the luminance change output from each of the detection pixels, and a first common line connecting the plurality of detection pixels, each of the detection pixels including a photoelectric conversion element, a logarithmic conversion circuit converting a photocurrent flowing out of the photoelectric conversion element into a voltage signal corresponding to the logarithmic value of the photocurrent, a first circuit outputting a luminance change of incident light incident on the photoelectric conversion element based on the voltage signal output from the logarithmic conversion circuit, a first transistor connected between the photoelectric conversion element and the logarithmic conversion circuit, and a second transistor connected between the photoelectric conversion element and the first common line, and the detection circuit includes a second circuit outputting the event signal based on the luminance change output from each of the detection pixels. [Brief description of the drawings]

[0007] [Figure 1] 1 is a block diagram showing an example of the configuration of an imaging device according to a first embodiment. [Diagram 2] 1 is a diagram illustrating an example of a layered structure of a solid-state imaging device according to a first embodiment. [Diagram 3]2 is an example of a plan view of the photosensor chip according to the first embodiment. [Figure 4] 1 is an example of a plan view of a detection chip according to a first embodiment. [Diagram 5] 3 is an example of a plan view of an address event detection unit according to the first embodiment. [Figure 6] 2 is a circuit diagram showing a configuration example of a logarithmic response unit according to the first embodiment. FIG. [Figure 7] 4 is a circuit diagram showing another configuration example of the logarithmic response unit according to the first embodiment. FIG. [Figure 8] 2 is a block diagram showing an example of the configuration of a detection block according to the first embodiment. FIG. [Figure 9] FIG. 2 is a circuit diagram illustrating a configuration example of a differentiator according to the first embodiment. [Figure 10] 3 is a circuit diagram showing a configuration example of a comparison section according to the first embodiment. FIG. [Figure 11] 2 is a circuit diagram showing a configuration example of a differentiator, a selector, and a comparator according to the first embodiment. FIG. [Figure 12] 4 is a timing chart showing an example of control of the row driving circuit according to the first embodiment. [Figure 13] 2 is a block diagram showing an example of the configuration of a detection pixel and a detection circuit according to the first embodiment. FIG. [Figure 14] 5 is a flowchart showing an example of the operation of the solid-state imaging device according to the first embodiment. [Figure 15] 11 is a block diagram showing a configuration example of a detection pixel and a detection circuit in a modified example of the first embodiment of the present technology. FIG. [Figure 16] 13 is a timing chart showing an example of control of a row drive circuit in a modified example of the first embodiment of the present technology. [Figure 17] 2 is a circuit diagram showing a schematic configuration example of a shared block according to the first embodiment. FIG. [Figure 18] FIG. 2 is a plan view showing an example of the layout of a shared block according to the first embodiment. [Figure 19]5 is a timing chart showing an example of control of a switching transistor in each of a high-resolution mode and a binning mode according to the first embodiment. [Figure 20] 5 is a flowchart showing an operation example of the imaging device according to the first embodiment. [Figure 21] FIG. 11 is a circuit diagram illustrating a schematic configuration example of a shared block according to a second embodiment. [Figure 22] FIG. 11 is a plan view showing an example of the layout of a shared block according to the second embodiment. [Figure 23] 10 is a timing chart showing an example of control of a switching transistor in each of a high-resolution mode and a binning mode according to the second embodiment. [Figure 24] FIG. 13 is a circuit diagram illustrating a schematic configuration example of a shared block according to a third embodiment. [Diagram 25] 13 is a timing chart showing an example of control of a switching transistor in each of a high-resolution mode and a binning mode according to the third embodiment. [Figure 26] FIG. 13 is a circuit diagram illustrating a schematic configuration example of a shared block according to a fourth embodiment. [Figure 27] FIG. 13 is a circuit diagram illustrating a schematic configuration example of a shared block according to a modified example of the fourth embodiment. [Figure 28] FIG. 13 is a circuit diagram showing a schematic configuration example of a readout circuit according to a fourth embodiment. [Figure 29] FIG. 13 is an example of a plan view of a detection chip according to a fourth embodiment. [Diagram 30] 13 is a flowchart showing an example of an operation performed by switching between an object detection mode and a grayscale image readout mode according to the fourth embodiment. [Diagram 31] FIG. 13 is a circuit diagram illustrating a schematic configuration example of a shared block according to a fifth embodiment. [Diagram 32] FIG. 13 is a circuit diagram illustrating a schematic configuration example of a shared block according to a modified example of the fifth embodiment. [Diagram 33] FIG. 13 is an example of a plan view of a detection chip according to a sixth embodiment. [Diagram 34]1 is a block diagram showing an example of a schematic configuration of a vehicle control system; [Diagram 35] 4 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit; FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, an embodiment of the present disclosure will be described in detail with reference to the drawings. In the following embodiments, the same components are designated by the same reference numerals, and duplicated descriptions will be omitted.

[0009] The present disclosure will be described in the following order. 1. First embodiment 1.1 Configuration example of imaging device 1.2 Example of a solid-state imaging device configuration 1.3 Example of logarithmic response section 1.3.1 Modifications of the logarithmic response section 1.4 Example of detection block configuration 1.4.1 Example of differentiator, selector and comparator configuration 1.5 Row driver circuit control example 1.6 Example of detection pixel and detection circuit configuration 1.6.1 Example of operation of a solid-state imaging device 1.7 Modifications of the detection pixel and detection circuit 1.7.1 Example of control of row driving circuit according to modified example 1.8 Example of shared block configuration 1.9 Shared block layout example 1.10 Example of operation 1.10.1 Timing chart 1.10.2 Flowchart 1.11 Actions and Effects 2. Second embodiment 2.1 Example of shared block configuration 2.2 Example of shared block layout 2.3 Operation example (timing chart) 2.4 Actions and Effects 3. Third embodiment 3.1 Example of shared block configuration 3.2 Operation example (timing chart) 3.3 Actions and Effects 4. Fourth embodiment 4.1 Example of shared block configuration 4.1.1 Shared Block Variants 4.2 Example of readout circuit configuration 4.3 Example of detection chip configuration 4.4 Example of operation 4.5 Actions and Effects 5. Fifth embodiment 5.1 Example of shared block configuration 5.1.1 Shared Block Variants 5.2 Example of operation 6. Sixth embodiment 7. Application examples for mobile objects

[0010] 1. First embodiment First, the first embodiment will be described in detail with reference to the drawings.

[0011] 1.1 Configuration example of imaging device 1 is a block diagram showing an example of a configuration of an imaging device 100 according to a first embodiment of the present disclosure. The imaging device 100 includes an optical unit 110, a solid-state imaging device 200, a recording unit 120, and a control unit 130. The imaging device 100 is assumed to be a camera mounted on an industrial robot, an in-vehicle camera, or the like.

[0012] The optical unit 110 collects the incident light and guides it to the solid-state imaging device 200. The solid-state imaging device 200 photoelectrically converts the incident light to generate image data. The solid-state imaging device 200 performs predetermined signal processing, such as image recognition processing, on the generated image data, and outputs the processed data to the recording unit 120 via a signal line 209.

[0013] The recording unit 120 is configured with, for example, a flash memory, and records data output from the solid-state imaging device 200 and data output from the control unit 130.

[0014] The control unit 130 is configured with an information processing device such as an application processor, and controls the solid-state imaging device 200 to output image data.

[0015] 1.2 Example of a solid-state imaging device configuration (Stack structure example) 2 is a diagram showing an example of a stacked structure of a solid-state imaging device 200 according to this embodiment. This solid-state imaging device 200 includes a detection chip 202 and a light-receiving chip 201 stacked on the detection chip 202. These chips are electrically connected through a connection portion such as a via. Note that, other than the via, the chips can also be connected by Cu-Cu bonding or bumps. For example, the light-receiving chip 201 may be an example of a first chip in the claims, and the detection chip 202 may be an example of a second chip in the claims.

[0016] (Photo-detector chip layout example) 3 is an example of a plan view of the light-receiving chip 201 according to this embodiment. The light-receiving chip 201 is provided with a light-receiving section 220 and via arrangement sections 211, 212, and 213.

[0017] Vias to be connected to the detection chip 202 are arranged in the via arrangement sections 211, 212, and 213. In the light receiving section 220, a plurality of shared blocks 221 are arranged in a two-dimensional lattice pattern.

[0018] One or more logarithmic response units 310 are arranged in each shared block 221. For example, four logarithmic response units 310 are arranged in two rows and two columns in each shared block 221. These four logarithmic response units 310 share a circuit on the detection chip 202. Details of the shared circuit will be described later. The number of logarithmic response units 310 in the shared block 221 is not limited to four. A part or all of the circuit configuration in each logarithmic response unit 310, except for the photoelectric conversion element 311, may be disposed on the detection chip 202 side.

[0019] The logarithmic response unit 310 converts the photocurrent flowing out from the photoelectric conversion element 311 into a voltage signal corresponding to the logarithmic value. A pixel address consisting of a row address and a column address is assigned to each of the logarithmic response units 310. Note that the pixel in this disclosure may be a configuration based on the photoelectric conversion element 311 described later, and in this embodiment, may be a configuration corresponding to, for example, the detection pixel 300 described later.

[0020] (Example of layout of detection chip) 4 is an example of a plan view of the detection chip 202 according to this embodiment. The detection chip 202 is provided with via arrangement units 231, 232, and 233, a signal processing circuit 240, a row driving circuit 251, a column driving circuit 252, and an address event detection unit 260. Vias connected to the photosensor chip 201 are arranged in the via arrangement units 231, 232, and 233.

[0021] The address event detection section 260 detects the presence or absence of an address event for each logarithmic response section 310, and generates a detection signal indicating the detection result.

[0022] The row drive circuit 251 selects a row address and causes the address event detection section 260 to output a detection signal corresponding to the row address.

[0023] The column driving circuit 252 selects a column address and causes the address event detection section 260 to output a detection signal corresponding to the selected column address.

[0024] The signal processing circuit 240 performs a predetermined signal processing on the detection signal from the address event detection unit 260. The signal processing circuit 240 arranges the detection signals as pixel signals in a two-dimensional lattice pattern and generates image data having 2 bits of information for each pixel. The signal processing circuit 240 then performs signal processing such as image recognition processing on the image data.

[0025] (Example of layout of detection chip) 5 is an example of a plan view of the address event detection section 260 according to this embodiment. A plurality of detection blocks 320 are arranged in this address event detection section 260. The detection blocks 320 are arranged for each shared block 221 on the photosensor chip 201. When the number of shared blocks 221 is N (N is an integer), N detection blocks 320 are arranged. Each detection block 320 is connected to a corresponding shared block 221.

[0026] 1.3 Example of logarithmic response section 6 is a circuit diagram showing a basic configuration example of the logarithmic response unit according to this embodiment. The logarithmic response unit 310 includes a photoelectric conversion element 311, nMOS (n-channel Metal Oxide Semiconductor) transistors 312 and 313, and a pMOS (p-channel MOS) transistor 314. Of these, the two nMOS transistors 312 and 313, for example, constitute a logarithmic conversion circuit that converts the photocurrent flowing out of the photoelectric conversion element 311 into a voltage signal corresponding to the logarithmic value. The pMOS transistor 314 operates as a load MOS transistor for this logarithmic conversion circuit. The photoelectric conversion element 311 and the nMOS transistors 312 and 313 may be arranged in the light receiving chip 201, for example, and the pMOS transistor 314 may be arranged in the detection chip 202.

[0027] The source of the nMOS transistor 312 is connected to the cathode of the photoelectric conversion element 311, and the drain is connected to a power supply terminal. The pMOS transistor 314 and the nMOS transistor 313 are connected in series between the power supply terminal and the ground terminal. The connection point of the pMOS transistor 314 and the nMOS transistor 313 is connected to the gate of the nMOS transistor 312 and the input terminal of the detection block 320. A predetermined bias voltage Vbias1 is applied to the gate of the pMOS transistor 314.

[0028] The drains of nMOS transistors 312 and 313 are connected to the power supply side, and such a circuit is called a source follower. These two source followers connected in a loop convert the photocurrent from the photoelectric conversion element 311 into a voltage signal corresponding to its logarithmic value. In addition, pMOS transistor 314 supplies a constant current to nMOS transistor 313.

[0029] Furthermore, the ground of the light receiving chip 201 and the ground of the detection chip 202 are separated from each other to prevent interference.

[0030] 1.3.1 Modifications of the logarithmic response section In FIG. 6, the source follower type logarithmic response unit 310 has been described, but the configuration is not limited to this. FIG. 7 is a circuit diagram showing a basic configuration example of a logarithmic response unit according to a modified example of this embodiment. As shown in FIG. 7, the logarithmic response unit 310A has a so-called gain boost type circuit configuration in which, for example, an nMOS transistor 315 connected in series between an nMOS transistor 312 and a power supply line and an nMOS transistor 316 connected in series between an nMOS transistor 313 and a pMOS transistor 314 are added to the source follower type circuit configuration exemplified in FIG. 6. The four nMOS transistors 312, 313, 315, and 316 constitute a logarithmic conversion circuit that converts, for example, a photocurrent flowing out from a photoelectric conversion element 311 into a voltage signal corresponding to its logarithmic value.

[0031] In this way, even when gain boost type logarithmic response unit 310A is used, it is possible to convert the photocurrent from photoelectric conversion element 311 into a voltage signal whose logarithmic value corresponds to the amount of charge.

[0032] 1.4 Example of detection block configuration 8 is a block diagram showing an example of a configuration of the detection block 320 according to this embodiment. The detection block 320 includes a plurality of buffers 330, a plurality of differentiators 340, a selection section 400, a comparison section 500, and a transfer circuit 360. The buffers 330 and the differentiators 340 are arranged for each logarithmic response section 310 in the shared block 221. For example, when the shared block 221 includes four logarithmic response sections 310, four buffers 330 and four differentiators 340 are arranged.

[0033] The buffer 330 outputs a voltage signal from the corresponding logarithmic response unit 310 to the differentiator 340. The buffer 330 can improve the driving force for driving the subsequent stage. In addition, the buffer 330 can ensure isolation of noise caused by the switching operation of the subsequent stage.

[0034] The differentiator 340 obtains the amount of change in the voltage signal, i.e., the change in luminance of light incident on the photoelectric conversion element 311, as a differential signal. This differentiator 340 receives the voltage signal from the corresponding logarithmic response unit 310 via the buffer 330, and obtains the amount of change in the voltage signal by differentiation. Then, the differentiator 340 supplies the differential signal to the selection unit 400. The m-th (m is an integer from 1 to M) differential signal Sin in the detection block 320 is set as Sinm. This differentiator 340 may correspond to, for example, the first circuit in the claims.

[0035] The selection section 400 selects one of the M differential signals in accordance with a selection signal from the row drive circuit 251. The selection section 400 includes selectors 410 and 420.

[0036] M number of differential signals Sin are input to the selector 410. The selector 410 selects one of these differential signals Sin in accordance with a selection signal, and supplies it as Sout+ to the comparison unit 500. M number of differential signals Sin are also input to the selector 420. The selector 420 selects one of these differential signals Sin in accordance with the selection signal, and supplies it as Sout- to the comparison unit 500.

[0037] The comparison unit 500 compares the differential signal (i.e., the amount of change) selected by the selection unit 400 with a predetermined threshold. The comparison unit 500 supplies a signal indicating the comparison result as a detection signal to the transfer circuit 360. The comparison unit 500 may correspond to, for example, the second circuit in the claims.

[0038] The transfer circuit 360 transfers the detection signal to the signal processing circuit 240 in accordance with the column driving signal from the column driving circuit 252 .

[0039] (Example of differentiator configuration) 9 is a circuit diagram showing an example of the configuration of the differentiator 340 according to this embodiment. The differentiator 340 includes capacitors 341 and 343, an inverter 342, and a switch 344.

[0040] One end of the capacitor 341 is connected to the output terminal of the buffer 330, and the other end is connected to the input terminal of the inverter 342. The capacitor 343 is connected in parallel to the inverter 342. The switch 344 opens and closes a path connecting both ends of the capacitor 343 in accordance with a row drive signal.

[0041] The inverter 342 inverts the voltage signal input via the capacitor 341. The inverter 342 outputs the inverted signal to the selection unit 400.

[0042] When the switch 344 is turned on, a voltage signal V init is input, and the opposite side becomes a virtual ground terminal. For convenience, the potential of this virtual ground terminal is set to zero. At this time, the potential Q stored in the capacitor 341 init If the capacitance of capacitor 341 is C1, then this is expressed by the following equation (1): On the other hand, both ends of capacitor 343 are short-circuited, so that the stored charge therein is zero. Q init =C1×V init (1)

[0043] Next, switch 344 is turned off, and the voltage on the buffer 330 side of capacitor 341 changes to V after If we consider the case where the charge Q stored in the capacitor 341 becomes after is expressed by the following equation (2). Q after =C1×V after (2)

[0044] On the other hand, the charge Q2 stored in the capacitor 343 increases the output voltage to V out Then, it is expressed by the following equation (3). Q2=-C2×V out (3)

[0045] At this time, the total charge amount of capacitors 341 and 343 does not change, so the following equation (4) holds. Q init =Q after +Q2 ···(4)

[0046] By substituting equations (1) to (3) into equation (4) and rearranging it, the following equation (5) is obtained. V out =-(C1 / C2)×(V after -V init ) ···(5)

[0047] Equation (5) represents the subtraction operation of the voltage signal, and the gain of the subtraction result is C1 / C2. Since it is usually desired to maximize the gain, it is preferable to design C1 large and C2 small. On the other hand, if C2 is too small, kTC noise increases and noise characteristics may deteriorate, so the reduction in the capacitance of C2 is limited to a range in which noise can be tolerated. In addition, since a differentiator 340 is mounted for each pixel, there are area restrictions on the capacitances C1 and C2. Taking these into consideration, for example, C1 is set to a value of 20 to 200 femtofarads (fF), and C2 is set to a value of 1 to 20 femtofarads (fF).

[0048] (Example of comparison section configuration) 10 is a circuit diagram showing an example of the configuration of the comparing section 500 according to this embodiment. The comparing section 500 includes comparators 510 and 520.

[0049] The comparator 510 compares the differential signal Sout+ from the selector 410 with a predetermined upper threshold Vrefp. The comparator 510 supplies the comparison result to the transfer circuit 360 as a detection signal DET+. The detection signal DET+ indicates the presence or absence of an on-event. Here, an on-event means that the amount of change in luminance has exceeded a predetermined upper threshold.

[0050] The comparator 520 compares the differential signal Sout- from the selector 420 with a lower threshold Vrefn that is lower than the upper threshold Vrefp. The comparator 520 supplies the comparison result to the transfer circuit 360 as a detection signal DET-. The detection signal DET- indicates the presence or absence of an off-event. Here, an off-event means that the amount of change in luminance has fallen below a predetermined lower threshold. The comparison unit 500 detects the presence or absence of both an on-event and an off-event, but can also detect only one of them.

[0051] For example, the comparator 510 may be an example of a first comparator as recited in the claims, and the comparator 520 may be an example of a second comparator as recited in the claims. Also, for example, the upper threshold value may be an example of a first threshold value as recited in the claims, and the lower threshold value may be an example of a second threshold value as recited in the claims.

[0052] 1.4.1 Example of differentiator, selector and comparator configuration FIG. 11 is a circuit diagram showing an example of the configuration of the differentiator 340, the selector 410, and the comparator 510 in the detection block 320 according to the present embodiment.

[0053] The differentiator 340 includes capacitors 341 and 343, pMOS transistors 345 and 346, and an nMOS transistor 347. The pMOS transistor 345 and the nMOS transistor 347 are connected in series between a power supply terminal and a ground terminal, with the pMOS transistor 345 on the power supply side. A capacitor 341 is inserted between the gates of the pMOS transistor 345 and the nMOS transistor 347 and the buffer 330. The connection point of the pMOS transistor 345 and the nMOS transistor 347 is connected to the selector 410. With this connection configuration, the pMOS transistor 345 and the nMOS transistor 347 function as an inverter 342.

[0054] In addition, a capacitor 343 and a pMOS transistor 346 are connected in parallel between the connection point of the pMOS transistor 345 and the nMOS transistor 347 and the capacitor 341. The pMOS transistor 346 functions as a switch 344.

[0055] Further, a plurality of pMOS transistors 411 are arranged in the selector 410. The pMOS transistor 411 is arranged for each differentiator 340.

[0056] Each pMOS transistor 411 is inserted between the corresponding differentiator 340 and the comparator 510. A selection signal SEL is input to each gate of the pMOS transistor 411. The selection signal SEL of the m-th pMOS transistor 411 is designated as SELm. These selection signals SEL allow the row driving circuit 251 to control any one of the M pMOS transistors 411 to an ON state and the remaining to an OFF state. Then, the differentiated signal Sout+ is output as a selected signal to the comparator 510 via the pMOS transistor 411 in the ON state. The circuit configuration of the selector 420 is the same as that of the selector 410.

[0057] The comparator 510 includes a pMOS transistor 511 and an nMOS transistor 512. The pMOS transistor 511 and the nMOS transistor 512 are connected in series between a power supply terminal and a ground terminal. The differentiated signal Sout+ is input to the gate of the pMOS transistor 511, and the voltage of the upper limit threshold Vrefp is input to the gate of the nMOS transistor 512. A detection signal DET+ is output from the connection point of the pMOS transistor 511 and the nMOS transistor 512. The circuit configuration of the comparator 520 is the same as that of the comparator 510.

[0058] In addition, the circuit configurations of the differentiator 340, the selector 410, and the comparator 510 are not limited to those illustrated in Fig. 11 as long as they have the functions described with reference to Fig. 8. For example, nMOS transistors and pMOS transistors can be interchanged.

[0059] 1.5 Row driver circuit control example 12 is a timing chart showing an example of control of the row driving circuit 251 according to this embodiment. At timing T0, the row driving circuit 251 selects the first row by the row driving signal L1 and drives the differentiator 340 of that row. The capacitor 343 in the differentiator 340 of the first row is initialized by this row driving signal L1. In addition, the row driving circuit 251 selects the upper left corner of the 2 rows x 2 columns in the shared block 221 for a certain period of time by the selection signal SEL1, and drives the selection unit 400. As a result, the presence or absence of an address event in the odd-numbered columns of the first row is detected.

[0060] Next, at timing T1, the row drive circuit 251 drives the differentiator 340 in the first row again by the row drive signal L1. The row drive circuit 251 also selects the top right corner of the 2 rows x 2 columns in the shared block 221 for a certain period by the selection signal SEL2. This allows the presence or absence of an address event in the even columns of the first row to be detected.

[0061] At timing T2, the row drive circuit 251 drives the differentiator 340 in the second row by the row drive signal L2. The capacitor 343 in the differentiator 340 in the second row is initialized by this row drive signal L2. In addition, the row drive circuit 251 selects the bottom left of the 2 rows x 2 columns in the shared block 221 for a certain period of time by the selection signal SEL3. This allows the presence or absence of an address event in the odd columns of the second row to be detected.

[0062] Next, at timing T3, the row drive circuit 251 drives the differentiator 340 in the second row again by the row drive signal L2. The row drive circuit 251 also selects the lower right corner of the 2 rows x 2 columns in the shared block 221 for a certain period by the selection signal SEL4. This allows the presence or absence of an address event in the even columns of the second row to be detected.

[0063] Similarly, the row driving circuit 251 sequentially selects rows in which the logarithmic response units 310 are arranged, and drives the selected rows with a row driving signal. Furthermore, each time the row driving circuit 251 selects a row, it sequentially selects each of the detection pixels 300 in the shared block 221 of the selected row with a selection signal. For example, if 2 rows x 2 columns of detection pixels 300 are arranged in the shared block 221, each time a row is selected, odd and even columns in that row are selected in sequence.

[0064] The row driving circuit 251 can also sequentially select the rows in which the shared blocks 221 are arranged (in other words, two rows of the logarithmic response units 310). In this case, each time a row is selected, four detection pixels in the shared blocks 221 of that row are selected in sequence.

[0065] 1.6 Example of detection pixel and detection circuit configuration 13 is a block diagram showing an example of the configuration of a detection pixel 300 and a detection circuit 305 according to this embodiment. Of the detection block 320 shared by a plurality of logarithmic response units 310 in the shared block 221, a circuit consisting of a selection unit 400, a comparison unit 500, and a transfer circuit 360 is defined as a detection circuit 305. Also, a circuit consisting of the logarithmic response unit 310, a buffer 330, and a differentiator 340 is defined as a detection pixel 300. As illustrated in the figure, the detection circuit 305 is shared by a plurality of detection pixels 300.

[0066] Each of the detection pixels 300 that share the detection circuit 305 generates a voltage signal corresponding to the logarithmic value of the photocurrent. Then, each of the detection pixels 300 outputs a differential signal Sin indicating the amount of change in the voltage signal in accordance with the row drive signal to the detection circuit 305. In each of the detection pixels 300, the voltage signal corresponding to the logarithmic value is generated by the logarithmic response unit 310, and the differential signal is generated by the differentiator 340.

[0067] Selection signals such as selection signals SEL1 and SEL2 are commonly input to the selectors 410 and 420 in the detection circuit 305. The detection circuit 305 selects a differential signal (i.e., an amount of change) of a detection pixel indicated by the selection signal from among the multiple detection pixels 300, and detects whether the amount of change exceeds a predetermined threshold. Then, the detection circuit 305 transfers the detection signal to the signal processing circuit 240 in accordance with the column drive signal. In the detection circuit 305, the differential signal is selected by the selection unit 400, and the comparison with the threshold is performed by the comparison unit 500. The detection signal is also transferred by the transfer circuit 360.

[0068] In a typical DVS, the comparison unit 500 and the transfer circuit 360 are arranged for each detection pixel together with the logarithmic response unit 310, the buffer 330, and the differentiator 340. In contrast, in the above-described configuration in which the detection circuit 305 including the comparison unit 500 and the transfer circuit 360 is shared by a plurality of detection pixels 300, the circuit scale of the solid-state imaging device 200 can be reduced compared to a case in which the detection circuit 305 is not shared. This facilitates miniaturization of pixels.

[0069] In particular, when a stacked structure is adopted, in a typical configuration in which the detection circuit 305 is not shared, the circuit scale of the detection chip 202 is larger than that of the light receiving chip 201. For this reason, the circuit on the detection chip 202 side limits the pixel density, making it difficult to miniaturize the pixels. However, by having multiple detection pixels 300 share the detection circuit 305, the circuit scale of the detection chip 202 can be reduced, making it easy to miniaturize the pixels.

[0070] Although the buffer 330 is arranged for each detection pixel 300, the present invention is not limited to this configuration, and a configuration without the buffer 330 may also be used.

[0071] In addition, the photoelectric conversion element 311 and the nMOS transistors 312 and 313 of the logarithmic response unit 310 are arranged on the light receiving chip 201, and the pMOS transistor 314 and subsequent transistors are arranged on the detection chip 202, but this configuration is not limited to this. For example, only the photoelectric conversion element 311 can be arranged on the light receiving chip 201, and the rest can be arranged on the detection chip 202. In addition, only the logarithmic response unit 310 can be arranged on the light receiving chip 201, and the buffer 330 and subsequent transistors can be arranged on the detection chip 202. In addition, the logarithmic response unit 310 and the buffer 330 can be arranged on the light receiving chip 201, and the differentiator 340 and subsequent transistors can be arranged on the detection chip 202. In addition, the logarithmic response unit 310, the buffer 330, and the differentiator 340 can be arranged on the light receiving chip 201, and the detection circuit 305 and subsequent transistors can be arranged on the detection chip 202. In addition, up to the selection unit 400 can be arranged on the light receiving chip 201, and the comparison unit 500 and subsequent transistors can be arranged on the detection chip 202.

[0072] 1.6.1 Example of operation of a solid-state imaging device 14 is a flowchart showing an example of the operation of the solid-state imaging device 200 according to this embodiment. This operation is started, for example, when a predetermined application for detecting the presence or absence of an address event is executed.

[0073] The row driving circuit 251 selects any one of the rows (step S901). Then, in the selected row, the row driving circuit 251 selects and drives any one of the detection pixels 300 in each shared block 221 (step S902). The detection circuit 305 detects the presence or absence of an address event in the selected detection pixel 300 (step S903). After step S903, the solid-state imaging device 200 repeatedly executes steps S901 and onward.

[0074] In this manner, in this embodiment, the detection circuit 305 for detecting the presence or absence of an address event is shared by a plurality of detection pixels 300, so that the circuit size can be reduced compared to a case in which the detection circuit 305 is not shared. This makes it easier to miniaturize the detection pixels 300.

[0075] 1.7 Modifications of the detection pixel and detection circuit In the above-described first embodiment, the solid-state imaging device 200 selects the detection pixels 300 one by one and simultaneously detects an on-event and an off-event for the detection pixels. However, the solid-state imaging device 200 can also select two detection pixels and detect an on-event for one of them and an off-event for the other. The solid-state imaging device 200 of this modification of the first embodiment differs from the first embodiment in that it detects an on-event for one of the two detection pixels and detects an off-event for the other.

[0076] 15 is a block diagram showing an example of the configuration of the detection pixel 300 and the detection circuit 305 in a modification of the present embodiment. The detection circuit 305 in this modification of the first embodiment differs from the first embodiment in that a selection signal such as selection signals SEL1p and SEL2p is input to the selector 410, and a selection signal such as selection signals SEL1n and SEL2n is input to the selector 420. In the modification of the first embodiment, two detection pixels 300 are selected, and the selector 410 selects one of the differential signals according to the selection signals SEL1p and SEL2p. At the same time, the selector 420 selects the other differential signal according to the selection signals SEL1n and SEL2n.

[0077] 1.7.1 Example of control of row driving circuit according to modified example 16 is a timing chart showing an example of control of the row driving circuit 251 in the modified example of this embodiment. It is assumed that two detection pixels, a detection pixel 300 that outputs a differential signal Sin1 and a detection pixel 300 that outputs a differential signal Sin2, are selected at timings T0 to T2. At timings T0 to T1, the row driving circuit 251 sets the selection signals SEL1p and SEL2n to a high level and the selection signals SEL2p and SEL1n to a low level. As a result, an ON event is detected for the pixel corresponding to the differential signal Sin1, and an OFF event is detected for the pixel corresponding to the differential signal Sin2.

[0078] Then, in the period from timing T1 to T2, the row driving circuit 251 sets the selection signals SEL1p and SEL2n to a low level and sets the selection signals SEL2p and SEL1n to a high level, thereby detecting an ON event for the pixel corresponding to the differentiated signal Sin2 and detecting an OFF event for the pixel corresponding to the differentiated signal Sin1.

[0079] In this way, according to the modified example of this embodiment, an ON event is detected for one of the two detection pixels and an OFF event is detected for the other, so that an ON event and an OFF event can be detected at the same time and in parallel in space.

[0080] 1.8 Example of shared block configuration Next, a more detailed configuration example of each shared block 221 in the above description will be described in detail below with reference to the drawings. In the following description, the logarithmic response unit 310 is quoted as an example of a gain boost type logarithmic response unit 310A illustrated in FIG. 7, but is not limited thereto, and various circuits that generate a voltage signal according to the logarithmic value of the photocurrent, such as the source follower type logarithmic response unit 310 illustrated in FIG. 6, may be used. In the following description, a case in which one shared block 221 includes a total of four logarithmic response units 310A in two rows and two columns is illustrated, but is not limited thereto, and each shared block 221 may include one or more logarithmic response units 310A.

[0081] FIG. 17 is a circuit diagram showing a schematic configuration example of a shared block according to the present embodiment. As shown in FIG. 17, each shared block 221 includes four logarithmic response units 310A1 to 310A4. Each of the logarithmic response units 310A1 to 310A4 (hereinafter, when the logarithmic response units 310A1 to 310A4 are not distinguished from each other, the reference numerals are referred to as 310An) has a configuration in which two switching transistors 317 and 318 are added to the basic configuration of the logarithmic response unit 310A illustrated in FIG. 6. Each of the two switching transistors 317 and 318 may be an nMOS transistor or a pMOS transistor. For example, the switching transistor 317 may be an example of a first transistor in the claims, and the switching transistor 318 may be an example of a second transistor in the claims.

[0082] The switching transistor 317 is connected, for example, between the cathode of the photoelectric conversion element 311 and the drain of the nMOS transistor 312 and the gate of the nMOS transistor 313, and controls the flow of the photocurrent flowing out of the photoelectric conversion element 311 into the logarithmic conversion circuit.

[0083] The switching transistor 318 is connected, for example, between the cathode of the photoelectric conversion element 311 and a common line 3101. The cathodes of the photoelectric conversion elements 311 in all the logarithmic response units 310An included in the same shared block 221 are connected to the common line 3101 via the switching transistor 318. For example, the common line 3101 may be an example of a first common line in the claims.

[0084] In the above configuration, by turning on the switching transistors 318 in two or more of the logarithmic response units 310An included in one shared block 221, turning on the switching transistor 317 in one of the two or more logarithmic response units 310An (referred to as logarithmic response unit 310A1), and turning off the switching transistors 317 in the other logarithmic response units 310An, it is possible to concentrate the photocurrent flowing out from the photoelectric conversion element 311 of the logarithmic response unit 310A1 and the photocurrent flowing out from the photoelectric conversion element 311 of the logarithmic response unit 310An whose switching transistor 317 is turned off, into the logarithmic conversion circuit of the logarithmic response unit 310A1. In other words, it is possible to collect photocurrent flowing out from the photoelectric conversion element 311 of the logarithmic response unit 310An in which the switching transistor 317 is in the off state and the switching transistor 318 is in the on state in the logarithmic conversion circuit of the logarithmic response unit 310An in which both the switching transistors 317 and 318 are in the on state.

[0085] In this way, by configuring the photocurrents flowing out from the multiple photoelectric conversion elements 311 to be collected in one logarithmic conversion circuit, it is possible to secure a larger amount of photocurrent, thereby widening the dynamic range in photocurrent detection. As a result, it is possible to secure a sufficiently wide dynamic range even under low illuminance conditions.

[0086] On the other hand, when sufficient illuminance is obtained, by turning off the switching transistor 318 and turning on the switching transistor 317 in all or a necessary and sufficient number of logarithmic response units 310An, it is possible to operate each of these all or a necessary and sufficient number of logarithmic response units 310An as a single address event detection pixel, thereby making it possible to detect address events with high resolution and reduce operating power.

[0087] 1.9 Shared block layout example Next, a layout example of the shared block 221 illustrated in Fig. 17 will be described. Fig. 18 is a plan view showing a layout example of the shared block according to this embodiment. For convenience of explanation, Fig. 18 shows a schematic layout example of the element formation surface side of the semiconductor substrate on which the photoelectric conversion element 311 is formed, and a schematic layout example of a part of the wiring layer formed on the element formation surface. For clarification, Fig. 18 also shows the arrangement of each nMOS transistor 312, 313, 315, and 316 and switching transistors 317 and 318 with the position of the gate electrode. Furthermore, Fig. 18 shows an outline of a current path formed in a binning mode described later by a thick arrow.

[0088] Here, in this embodiment, there are at least two definitions of one pixel. One is a pixel on a layout that is a repeated pattern in the design of the light receiving section 220, and the other is a pixel on a circuit that operates as one detection pixel 300. Each of these pixels on a circuit is configured to include one logarithmic response unit 310An. In the following description, the pixel on the layout is referred to as a layout pixel, and the pixel on the circuit is referred to as a circuit pixel. In addition, the configuration of the detection pixel 300 that is arranged in the light receiving section 220 is all or a part of the logarithmic response unit 310An, so here, the logarithmic response unit 310An will be described as a circuit pixel.

[0089] (Layout pixels) 18, the pixel area in which one layout pixel 10 is arranged in the light receiving chip 201 is partitioned by pixel separation parts 12 extending in the row and column directions. Each layout pixel 10 includes a photoelectric conversion element 311 arranged substantially in the center, a plurality of nMOS transistors 312, 313, 315, and 316 and switching transistors 317 and 318 arranged along the outer periphery of the pixel area, in other words, arranged so as to surround the photoelectric conversion element 311 from at least two directions (three directions in FIG. 18), and a contact 314c for forming a connection with a pMOS transistor 314 arranged on the detection chip 202 side.

[0090] 18, for example, the nMOS transistors 312 and 315 in the left column in each logarithmic response unit 310An illustrated in FIG. 17 are arranged to the left of the photoelectric conversion element 311, and the nMOS transistors 313 and 316 in the right column are arranged to the right of the photoelectric conversion element 311. In addition, the two switching transistors 317 and 318 are arranged, for example, above or below the photoelectric conversion element 311. In this way, by adopting a highly symmetrical layout in which the photoelectric conversion element 311 is sandwiched between two nMOS transistors, it is possible to improve the process accuracy and yield during manufacturing.

[0091] Furthermore, the two switching transistors 317 and 318 are arranged, for example, below the photoelectric conversion element 311 in the odd-numbered rows, and above the photoelectric conversion element 311 in the even-numbered rows. That is, the layout pixels 10 in the even-numbered rows have a layout obtained by upside-down flipping of the layout pixels 10 in the odd-numbered rows. With such a layout, it is possible to use the pattern of one layout pixel 10 for all layout pixels 10, and therefore it is also possible to facilitate the layout design of the light receiving section 220.

[0092] Furthermore, by flipping the layout pixels 10 upside down between odd and even rows, it is possible to place the switching transistors 317 and 318 of the logarithmic response unit 310An that constitutes one shared block 221 close to each other, which makes it possible to simplify the layout design of the common line 3101 and shorten the wiring length of the common line 3101.

[0093] (Circuit pixel) On the other hand, on the circuit, a photoelectric conversion element 311 in a certain layout pixel 10, two nMOS transistors 312 and 315 arranged on the left side of this photoelectric conversion element 311, and two nMOS transistors 313 and 316 arranged on the right side of the photoelectric conversion element 311 in the layout pixel 10 adjacent to the left of this layout pixel 10 constitute one circuit pixel (here, a logarithmic response unit 310An). That is, in the circuit pixel on the layout (here, the logarithmic response unit 310An), a logarithmic conversion circuit constituted by four nMOS transistors 312, 313, 315, and 316 has a configuration spanning the pixel separation unit 12.

[0094] In this way, by configuring a logarithmic conversion circuit in one logarithmic response unit 310An between adjacent layout pixels 10, it is possible to shorten the wiring length of the logarithmic conversion circuit, i.e., the length of the wiring connecting the nMOS transistors 312, 313, 315, and 316 that configure the logarithmic conversion circuit, while maintaining the symmetry of the layout pixel 10. This makes it possible to reduce the time constant formed by the wiring that configures the logarithmic conversion circuit and improve the response speed of the logarithmic conversion circuit.

[0095] 1.10 Example of operation Next, an operation example of the imaging device 100 according to this embodiment will be described. As described above, in this embodiment, by controlling the on / off of the switching transistors 317 and 318, it is possible to switch between a mode in which one logarithmic response unit 310 (which may be the logarithmic response unit 310A) operates as one pixel (hereinafter referred to as a high-resolution mode) and a mode in which two or more logarithmic response units 310 in the shared block 221 operate as one pixel (hereinafter referred to as a binning mode). It is also possible to realize a mode in which some shared blocks 221 are driven in the high-resolution mode and the remaining shared blocks 221 are driven in the binning mode (hereinafter referred to as a ROI mode). For example, the binning mode and the ROI mode may be an example of the first mode in the claims, and the high-resolution mode may be an example of the second mode in the claims. The binning mode may be an example of the third mode in the claims, and the ROI mode may be an example of the fourth mode in the claims.

[0096] 1.10.1 Timing chart Fig. 19 is a timing chart showing an example of control of the switching transistor in each of the high resolution mode and the binning mode according to this embodiment. As shown in Fig. 19, in the high resolution mode shown in the section T10 to T11, in each of the logarithmic response units 310A1 to 310A4, the switching transistor 317 is turned on and the switching transistor 318 is turned off. This forms a current path through which the photocurrent flowing out from the photoelectric conversion element 311 of each of the logarithmic response units 310A1 to 310A4 flows into the respective logarithmic conversion circuits.

[0097] In contrast, in the binning mode shown in sections T11 to T12, both switching transistors 317 and 318 of logarithmic response unit 310A1 are turned on. Meanwhile, in logarithmic response units 310A2 to 310A4, switching transistor 317 is turned off and switching transistor 318 is turned on. This forms a current path through which photocurrent flowing out from photoelectric conversion element 311 of each of logarithmic response units 310A1 to 310A4 flows into the logarithmic conversion circuit of logarithmic response unit 310A1.

[0098] 1.10.2 Flowchart Next, an operation example of the imaging device 100 will be described. FIG. 20 is a flowchart showing an operation example of the imaging device according to this embodiment, which is a flow chart showing an operation example of switching between a mode in which all pixels operate in a binning mode (hereinafter referred to as an all-pixel binning mode), a mode in which all pixels operate in a high-resolution mode (hereinafter referred to as an all-pixel high-resolution mode), and an ROI mode. Note that in this description, a case in which the control unit 130 (see FIG. 1) in the imaging device 100 controls the operation mode of the solid-state imaging device 200 is illustrated, but is not limited thereto, and for example, the signal processing circuit 240 in the solid-state imaging device 200 may be configured to control the operation mode. Also, the operation illustrated in FIG. 20 may be ended by, for example, an interrupt operation to the control unit 130 or the solid-state imaging device 200.

[0099] As shown in FIG. 20, in this operation, after startup, the control unit 130 sets, for example, the full-pixel binning mode as the operation mode of the solid-state imaging device 200 (step S101). In the full-pixel binning mode, as described above, all the shared blocks 221 of the light receiving unit 220 are driven in the binning mode. In this case, for example, in the example shown in FIG. 17, the switching transistors 317 of all the logarithmic response units 310A1 to 310A4 in each shared block 221 are turned on, the switching transistor 318 of the logarithmic response unit 310A1 is turned on, and the switching transistors 318 of the logarithmic response units 310A2 to 310A4 are turned off. Thereby, a current path is formed through which the photocurrent flowing out from the photoelectric conversion elements 311 of all the logarithmic response units 310A1 to 310A4 flows into the logarithmic conversion circuit of the logarithmic response unit 310A1.

[0100] Next, the control unit 130 determines whether an object is detected in the full pixel binning mode (step S102), and continues the full pixel binning mode until an object is detected (NO in step S102). The detection and determination of an object may be performed based on, for example, whether an address event (on event and / or off event) is detected in any shared block, or whether an area in which an address event is detected has a certain area or number of pixels (for example, a preset threshold or more). In addition, the detection of an object does not need to be determined in one frame, but may be determined in several consecutive frames. Note that one frame may be, for example, image data configured with address information (which may include a timestamp) of pixels in which an address event is detected within a predetermined period. In addition, the detection of an object may be performed by processing such as object recognition for image data.

[0101] If an object is detected (YES in step S102), the control unit 130 determines, for example, whether the detected object is a wide-area object or whether there are multiple objects (step S103). Note that a wide-area may be, for example, a range that occupies a preset ratio (for example, 20% of the area or number of pixels) or more of the light receiving unit 220.

[0102] When a non-wide area object is detected (NO in step S103), the control unit 130 sets, for example, the operation mode of the solid-state imaging device 200 to the ROI mode (step S104). In the ROI mode, for example, a part of the light receiving unit 220 including the area where the object is detected is driven in the high resolution mode, and the other area is driven in the binning mode.

[0103] Next, the control unit 130 determines whether or not an object is detected (step S105), and if an object is not detected (NO in step S105), the process returns to step S101 and resets the full-pixel binning mode to the solid-state imaging device 200. If an object is detected (YES in step S105), the control unit 130 determines, for example, whether the detected object is a wide-range object or multiple objects (step S106), as in step S103, and if the object is not a wide-range object (NO in step S106), the process returns to step S105 and continues the ROI mode.

[0104] When a wide-range object is detected in step S103 or step S106 (YES in step S103 / S106), the control unit 130 sets, for example, the all-pixel high resolution mode as the operation mode of the solid-state imaging device 200 (step S107). In the all-pixel high resolution mode, as described above, all the shared blocks 221 of the light receiving unit 220 are driven in the high resolution mode. In this case, for example, in the example shown in FIG. 17, the switching transistors 317 of all the logarithmic response units 310A1-310A4 in each shared block 221 are turned off, and the switching transistors 318 are turned on. This forms an individual current path through which the photocurrent flowing out from the photoelectric conversion element 311 of each logarithmic response unit 310A1-310A4 flows into its own logarithmic conversion circuit.

[0105] Next, the control unit 130 judges whether an object is detected (step S108). If an object is not detected (NO in step S108), the control unit 130 returns to step S101 and resets the full pixel binning mode to the solid-state imaging device 200. If an object is detected (YES in step S108), the control unit 130 judges, for example, whether the detected object is a wide-area object or multiple objects (step S109) in the same manner as in step S103, and if it is a wide-area object (YES in step S109), the control unit 130 returns to step S108 and continues the full pixel high resolution mode. On the other hand, if the detected object is not a wide-area object or multiple objects (NO in step S109), the control unit 130 proceeds to step S104, sets the operation mode of the solid-state imaging device 200 to the ROI mode, and executes the subsequent operations.

[0106] 1.11 Actions and Effects As described above, according to this embodiment, by configuring the photocurrents flowing out from the multiple photoelectric conversion elements 311 to be collected in one logarithmic conversion circuit, it is possible to secure a larger amount of photocurrent, and therefore to widen the dynamic range in photocurrent detection. As a result, it is possible to secure a sufficiently wide dynamic range even under low illuminance conditions.

[0107] On the other hand, when sufficient illuminance is obtained, by turning off the switching transistor 318 and turning on the switching transistor 317 in all or a necessary and sufficient number of logarithmic response units 310An, it is possible to operate each of these all or a necessary and sufficient number of logarithmic response units 310An as a single address event detection pixel, thereby making it possible to detect address events with high resolution and reduce operating power.

[0108] In addition, during binning mode, by constantly keeping the switching transistors 318 of the shared logarithmic response units 310An (for example, all logarithmic response units 310An in the shared block 221) on, a current path is always formed from each of the logarithmic response units 310A2 to 310An to the logarithmic conversion circuit of the logarithmic response unit 310A1. This makes it possible for multiple detection pixels 300 to share a single logarithmic conversion circuit without having to have a charge storage unit such as a floating diffusion region, as in a CMOS type image sensor.

[0109] 2. Second embodiment Next, the second embodiment will be described in detail with reference to the drawings. In this embodiment, another configuration of the shared block 221 described in the first embodiment with reference to FIG. 17 will be described by way of example.

[0110] As described with reference to FIGS. 17 and 18, in the first embodiment, the photocurrent flowing out from the photoelectric conversion element 311 of the logarithmic response units 310A2 to 310A4 in which the switching transistor 318 is turned off in the binning mode flows into the logarithmic conversion circuit of the logarithmic response unit 310A1 through the common line 3101, the switching transistor 317 of the logarithmic response unit 310A1, the cathode of the photoelectric conversion element 311, and the switching transistor 318. Therefore, in the first embodiment, it is necessary to design the potential from the switching transistor 317 of the logarithmic response unit 310A1 through the cathode of the photoelectric conversion element 311 to the switching transistor 318 so that the photocurrent flowing out from the photoelectric conversion element 311 of the logarithmic response units 310A2 to 310A4 smoothly flows into the logarithmic conversion circuit of the logarithmic response unit 310A1. Therefore, in the second embodiment, a shared block capable of significantly relaxing constraints on potential design will be described by way of an example.

[0111] Note that the configurations and operations of the imaging device and solid-state imaging device according to this embodiment may be similar to those of the imaging device 100 and solid-state imaging device 200 according to the above-described first embodiment, and therefore detailed description thereof will be omitted here. However, in this embodiment, the shared block 221 according to the first embodiment is replaced with a shared block 621 described later.

[0112] 2.1 Example of shared block configuration FIG. 21 is a circuit diagram showing a schematic configuration example of a shared block according to this embodiment. The logarithmic response unit 310Bn exemplified below is an example of a logarithmic response unit based on the gain boost type logarithmic response unit 310A exemplified in FIG. 7, but is not limited thereto. For example, the logarithmic response unit 310B can be configured based on various circuits that generate a voltage signal according to the logarithmic value of the photocurrent, such as the source follower type logarithmic response unit 310 exemplified in FIG. 6. In addition, in the following description, a case in which one shared block 621 includes a total of four logarithmic response units 310Bn of 2 rows x 2 columns is exemplified, but is not limited thereto. Each shared block 621 may include one or more logarithmic response units 310Bn.

[0113] As shown in FIG. 21, the logarithmic response units 310B1 to 310B4 according to this embodiment (in this description, when the logarithmic response units 310B1 to 310B4 are not distinguished from each other, the reference numerals thereof are designated as 310Bn) have a configuration similar to that of the logarithmic response unit 310An described in the first embodiment with reference to FIG. 17, with a switching transistor 319 added thereto. The source of the switching transistor 319 is connected to, for example, the drain of the switching transistor 318, and the drain is connected to, for example, the drain of the switching transistor 317, the source of the nMOS transistor 312, and the gate of the nMOS transistor 313. For example, the switching transistor 319 may be an example of a third transistor in the claims. Also, for example, a node connecting the drain of the switching transistor 317, the source of the nMOS transistor 312, and the gate of the nMOS transistor 313 may be an example of a second node in the claims, and the drain of the switching transistor 318 may be an example of a second node in the claims.

[0114] 2.2 Example of shared block layout Next, a layout example of the shared block 621 illustrated in FIG. 21 will be described. FIG. 22 is a plan view showing a layout example of the shared block according to this embodiment. For convenience of explanation, FIG. 22 shows a schematic layout example of the element formation surface side of the semiconductor substrate on which the photoelectric conversion element 311 is formed, and a schematic layout example of a part of the wiring layer formed on the element formation surface. In addition, in FIG. 22, the arrangement of each nMOS transistor 312, 313, 315, and 316 and the switching transistors 317 to 319 is shown with the position of the gate electrode for clarification. Furthermore, in FIG. 22, the outline of the current path formed in the binning mode described later is shown by a thick arrow. For example, the nMOS transistor 312 may be an example of a fourth transistor in the claims, the nMOS transistor 313 may be an example of a fifth transistor in the claims, the nMOS transistor 315 may be an example of a sixth transistor in the claims, and the nMOS transistor 316 may be an example of a seventh transistor in the claims.

[0115] 22, each layout pixel 20 according to this embodiment has a similar configuration to the layout pixel 10 described in the first embodiment with reference to Fig. 18, except that a switching transistor 319 is added to the same side of the photoelectric conversion element 311 as the switching transistor 317. With this layout, it is possible to shorten the wiring from the common line 3101 to the switching transistor 319.

[0116] 2.3 Operation example (timing chart) Next, an operation example of the logarithmic response unit 310Bn will be described. Fig. 23 is a timing chart showing an example of control of the switching transistor in each of the high resolution mode and the binning mode according to this embodiment. As shown in Fig. 23, in the high resolution mode shown in the section T20 to T21, in each of the logarithmic response units 310B1 to 310B4, the switching transistors 317 and 319 are turned off, and the switching transistor 318 is turned on. This forms a current path through which the photocurrent flowing out from the photoelectric conversion element 311 of each of the logarithmic response units 310B1 to 310B4 flows into the respective logarithmic conversion circuits.

[0117] In contrast, in the binning mode shown in sections T21 to T22, switching transistor 317 of logarithmic response unit 310B1 is turned on, switching transistor 318 is turned off, and switching transistor 319 is turned on. On the other hand, in logarithmic response units 310B2 to 310B4, switching transistor 317 is turned off, switching transistor 318 is turned on, and switching transistor 319 is turned off. This forms a current path through which photocurrent flowing out from photoelectric conversion element 311 of each of logarithmic response units 310B1 to 310B4 flows into the logarithmic conversion circuit of logarithmic response unit 310B1.

[0118] 2.4 Actions and Effects As described above, according to this embodiment, in the binning mode, a current path is formed in which the photocurrent flowing in via the common line 3101 flows into the logarithmic conversion circuit of the logarithmic response unit 310B1 via the switching transistor 319 of the logarithmic response unit 310B1, without passing through the switching transistor 318 of the logarithmic response unit 310B1, the cathode of the photoelectric conversion element 311, and the switching transistor 317. This makes it possible to significantly relax constraints on the potential design from the switching transistor 318 to the switching transistor 317.

[0119] The other configurations, operations, and effects may be similar to those of the above-described embodiment, and therefore detailed description thereof will be omitted here.

[0120] 3. Third embodiment Next, a third embodiment will be described in detail with reference to the drawings. In this embodiment, still another configuration of the shared block 221 described in the first embodiment with reference to FIG. 17 will be described by way of example.

[0121] Note that the configurations and operations of the imaging device and solid-state imaging device according to this embodiment may be similar to those of the imaging device 100 and solid-state imaging device 200 according to the first embodiment described above, and therefore detailed description thereof will be omitted here. However, in this embodiment, the shared block 221 according to the first embodiment is replaced with a shared block 721 described later.

[0122] 3.1 Example of shared block configuration Fig. 24 is a circuit diagram showing a schematic configuration example of a shared block according to this embodiment. The logarithmic response unit 310Cn exemplified below is an example of a logarithmic response unit based on the gain boost type logarithmic response unit 310A exemplified in Fig. 7, but is not limited thereto. For example, the logarithmic response unit 310B can be configured based on various circuits that generate a voltage signal according to the logarithmic value of the photocurrent, such as the source follower type logarithmic response unit 310 exemplified in Fig. 6. In addition, in the following description, a case in which one shared block 721 includes a total of four logarithmic response units 310Cn of 2 rows x 2 columns is exemplified, but is not limited thereto. Each shared block 721 may include one or more logarithmic response units 310Cn.

[0123] 24, logarithmic response units 310C1-310C4 according to this embodiment (in this description, when the logarithmic response units 310C1-310C4 are not distinguished from one another, they are referred to as 310Cn) have a configuration similar to that of logarithmic response unit 310Bn described in the second embodiment using FIG. 21, except that switching transistor 319 is omitted. In logarithmic response unit 310Cn, the drain of switching transistor 317 is connected to the source of nMOS transistor 312, the source of switching transistor 317 is connected to the gate of nMOS transistor 313 and the cathode of photoelectric conversion element 311, and the drain of switching transistor 318 is connected to the source of switching transistor 317, the gate of nMOS transistor 313, and the cathode of photoelectric conversion element 311.

[0124] 3.2 Operation example (timing chart) Next, an operation example of the logarithmic response unit 310Cn will be described. Fig. 25 is a timing chart showing an example of control of the switching transistor in each of the high resolution mode and the binning mode according to this embodiment. As shown in Fig. 25, in the high resolution mode shown in the section T30 to T31, in each of the logarithmic response units 310C1 to 310B4, the switching transistor 317 is turned on and the switching transistor 318 is turned off. This forms a current path through which the photocurrent flowing out from the photoelectric conversion element 311 of each of the logarithmic response units 310C1 to 310C4 flows into the respective logarithmic conversion circuits.

[0125] In contrast, in the binning mode shown in sections T31 to T32, the switching transistors 317 and 318 of the logarithmic response unit 310C1 are both turned on. Meanwhile, in the logarithmic response units 310C2 to 310C4, the switching transistor 317 is turned off and the switching transistor 318 is turned on. This forms a current path through which the photocurrent flowing out from the photoelectric conversion element 311 of each of the logarithmic response units 310C1 to 310C4 flows into the logarithmic conversion circuit of the logarithmic response unit 310C1.

[0126] 3.3 Actions and Effects As described above, according to this embodiment, compared to, for example, the second embodiment, it is possible to omit the switching transistor 319, and therefore it is possible to reduce the area occupied by the logarithmic response unit 310Cn in the pixel area. This makes it possible to increase the area of ​​the light receiving surface of the photoelectric conversion element 311, and therefore it is possible to improve the sensitivity and expand the dynamic range of the solid-state imaging device 200. Furthermore, since the switching transistor 319 is omitted, it is also possible to further reduce the driving current.

[0127] The other configurations, operations, and effects may be similar to those of the above-described embodiment, and therefore detailed description thereof will be omitted here.

[0128] 4. Fourth embodiment In the above-described embodiment, the solid-state imaging device 200 outputs frame data (corresponding to image data) consisting of detection signals indicating the presence or absence of an address event for each pixel. In contrast, in the fourth embodiment, an example will be described in which the solid-state imaging device 200 can output image data (hereinafter also referred to as gradation image data) consisting of pixel signals corresponding to the exposure amount for each pixel, in addition to image data consisting of detection signals for each pixel.

[0129] Note that the configuration and operation of the imaging device and solid-state imaging device according to this embodiment may be similar to the configuration and operation of the imaging device 100 and solid-state imaging device 200 according to the above-described first embodiment, and therefore detailed description thereof will be omitted here. However, in this embodiment, the shared block 221 according to the first embodiment is replaced with a shared block 821 described later, and the detection chip 202 is replaced with a detection chip 802 described later.

[0130] 4.1 Example of shared block configuration Fig. 26 is a circuit diagram showing a schematic configuration example of a shared block according to this embodiment. The shared block 821 exemplified below is based on the shared block 221 exemplified in Fig. 17, but is not limited thereto, and may be based on, for example, the shared block 621 according to the second embodiment or the shared block 721 according to the third embodiment.

[0131] As shown in Figure 26, the shared block 821 of this embodiment has a configuration similar to that of the shared block 221 described using Figure 17 in the first embodiment, and has a configuration in which a readout circuit 370 for reading out pixel signals is connected to a common line 3101.

[0132] 4.1.1 Shared Block Variants Moreover, the shared block 821 according to this embodiment can be based on, for example, the shared block 621 described in the second embodiment with reference to Fig. 21. Even in this case, as shown in Fig. 27, the shared block 821 has a configuration similar to that of the shared block 621 described with reference to Fig. 21, in which a readout circuit 370 for reading out pixel signals is connected to a common line 3101.

[0133] 4.2 Example of readout circuit configuration 28 is a circuit diagram showing a schematic configuration example of a readout circuit according to this embodiment. As shown in FIG. 28, a readout circuit 370 according to this embodiment includes a reset transistor 373, an amplifier transistor 375, and a selection transistor 376.

[0134] The readout circuit 370 operates together with the photoelectric conversion element 311 and the switching transistor 318 of the logarithmic response unit 310An to function as a gradation pixel 810 that generates a pixel signal according to the amount of received light. That is, in this embodiment, the switching transistor 318 of each logarithmic response unit 310An also functions as a transfer transistor in the gradation pixel 810. In addition, a node to which the drain of the switching transistor 318, the source of the reset transistor 373, and the gate of the amplification transistor 375 are connected functions as a floating diffusion region (FD) 374 having a current-voltage conversion function that converts the accumulated charge into a voltage according to the amount of the charge.

[0135] The drain of the reset transistor 373 and the drain of the amplification transistor 375 are connected to, for example, a power supply voltage VDD. However, the drain of the reset transistor 373 may be connected to, for example, a reset voltage different from the power supply voltage VDD. The source of the amplification transistor 375 is connected to the drain of the selection transistor 376, and the source of the selection transistor 376 is connected to a vertical signal line VSL for inputting an analog pixel signal to a column ADC (Analog to Digital Converter) 270 described later.

[0136] When reading out a pixel signal, a high-level transfer signal TRG is applied from the row drive circuit 251 to the gate of the switching transistor 318. This turns on the switching transistor 318, and the charge accumulated in the cathode of the photoelectric conversion element 311 is transferred to the floating diffusion region 374 via the switching transistor 318. As a result, a pixel signal having a voltage value according to the amount of charge accumulated in the floating diffusion region 374 appears at the source of the amplification transistor 375. Then, by setting the selection signal SEL applied from the row drive circuit 251 to the gate of the selection transistor 376 at a high level, the pixel signal that appeared at the source of the amplification transistor 375 appears on the vertical signal line VSL.

[0137] Furthermore, when discharging the charge accumulated in the floating diffusion region 374 to reset the floating diffusion region 374, a high-level reset signal RST is applied from the row drive circuit 251 to the gate of the reset transistor 373. This causes the charge accumulated in the floating diffusion region 374 to be discharged to the power supply side via the reset transistor 373 (FD reset). At that time, by also turning on the switching transistor 318 during the same period, it is also possible to discharge the charge accumulated in the cathode of the photoelectric conversion element 311 to the power supply side (PD reset).

[0138] In each shared block 821, the number of photoelectric conversion elements 311 simultaneously connected to the readout circuit 370 when reading out gradation image data, i.e., the number of switching transistors 318 (transfer transistors) turned on during the same period, is not limited to 1 and may be multiple. For example, in each shared block 821, when reading out high-resolution gradation image data, the switching transistors 318 may be connected to the readout circuit 370 in sequence in a time-division manner, and when reading out by expanding the dynamic range at low illuminance or the like (during binning), two or more switching transistors 318 may be turned on during the same period.

[0139] 4.3 Example of detection chip configuration Fig. 29 is an example of a plan view of the detection chip according to this embodiment. The detection chip 802 according to this embodiment has a configuration similar to that of the detection chip 202 described in the first embodiment with reference to Fig. 4, with the addition of a column ADC 270 for reading out analog pixel signals output from the gradation pixels 810 as digital pixel signals.

[0140] Each gradation pixel 810 generates an analog pixel signal on a vertical signal line VSL under the control of the row driving circuit 251, thereby supplying the analog pixel signal to the column ADC 270. The column ADC 270 includes, for example, an AD converter for each vertical signal line VSL, and performs AD (Analog to Digital) conversion on the analog pixel signal input via each vertical signal line VSL. The column ADC 270 then supplies the digital signal after AD conversion to the signal processing circuit 240. The signal processing circuit 240 performs a predetermined image processing on the image data consisting of the digital signals. Note that the column ADC 270 may include, for example, a CDS (Correlated Double Sampling) circuit to reduce kTC noise included in the digital pixel signal.

[0141] 4.4 Example of operation The reading of the gradation image data may be performed, for example, by reading pixel signals from all gradation pixels 810 when an address event is detected in any of the detection pixels 300, or by reading pixel signals from gradation pixels 810 that belong to the area where the address event occurs, in other words, the area where an object is detected by the detection pixels 300. FIG. 30 shows an example of an operation performed by switching between an object detection mode and a gradation image reading mode according to the present embodiment. Note that in this description, a case where the control unit 130 (see FIG. 1) in the imaging device 100 controls the operation mode of the solid-state imaging device 200 is illustrated, but the present invention is not limited to this, and for example, the signal processing circuit 240 in the solid-state imaging device 200 may be configured to control the operation mode. In addition, the operation illustrated in FIG. 30 may be ended, for example, by an interrupt operation to the control unit 130 or the solid-state imaging device 200.

[0142] 30, in this operation, after startup, the control unit 130 sets, for example, an object detection mode as the operation mode of the solid-state imaging device 200 (step S201). The object detection mode is an operation mode for detecting the occurrence of an address event, and may be, for example, a mode for executing the operation described with reference to FIG. 20 in the first embodiment.

[0143] Next, the control unit 130 determines whether an object is detected in the object detection mode (step S202), and continues the address event detection mode until an object is detected (NO in step S202). The detection and determination of the object may be the same as the operations described in steps S102, S105, and S108 of FIG. 20 in the first embodiment, for example.

[0144] If an object is detected (YES in step S202), the control unit 130 identifies the area in which the object is detected (step S203), for example, based on the frame data output from the solid-state imaging device 200. Note that the area in which the object is detected may be, for example, an area including pixels in which an ON event (or an OFF event) is detected.

[0145] Next, the control unit 130 instructs the solid-state imaging device 200 to read out pixel signals for the region where the object is detected (step S204). As a result, the solid-state imaging device 200 outputs grayscale image data made up of pixel signals read out from the grayscale pixels 810 that belong to the region where the object is detected.

[0146] 4.5 Actions and Effects As described above, according to this embodiment, it is possible not only to detect an object based on the presence or absence of an address event, but also to obtain gradation image data of an area in which an object is detected or of all pixels.

[0147] The other configurations, operations, and effects may be similar to those of the above-described embodiment, and therefore detailed description thereof will be omitted here.

[0148] 5. Fifth embodiment In the above-described fourth embodiment, in a configuration capable of reading out gradation image data in addition to object detection, a configuration in which the readout circuit 370 is connected to the common line 3101 has been exemplified. In contrast, in the fifth embodiment, an example will be described in which the readout circuit 370 is connected to a common line different from the common line 3101.

[0149] Note that the configurations and operations of the imaging device and solid-state imaging device according to this embodiment may be similar to those of the imaging device 100 and solid-state imaging device 200 according to the fourth embodiment described above, and therefore detailed description thereof will be omitted here. However, in this embodiment, the shared block 821 according to the fourth embodiment is replaced with a shared block 921 described later.

[0150] 5.1 Example of shared block configuration Fig. 31 is a circuit diagram showing a schematic configuration example of a shared block according to this embodiment. The shared block 921 exemplified below is based on the shared block 221 exemplified in Fig. 17, but is not limited thereto, and may be based on, for example, the shared block 621 according to the second embodiment or the shared block 721 according to the third embodiment.

[0151] As shown in FIG. 31, the shared block 921 according to this embodiment has a configuration similar to that of the shared block 221 described in the first embodiment with reference to FIG. 17, except that the cathodes of the photoelectric conversion elements 311 in two or more or all of the logarithmic response units 310An are connected by a common line 3102 separate from the common line 3101. The readout circuit 370 is connected to this common line 3102. A switching transistor 377 that also functions as a transfer transistor is provided between the readout circuit 370 and the photoelectric conversion elements 311 of each logarithmic response unit 310An, and the connection between the photoelectric conversion elements 311 and the readout circuit 370 is controlled by this switching transistor 377. For example, the common line 3102 may be an example of a second common line in the claims.

[0152] 5.1.1 Shared Block Variants Moreover, the shared block 921 according to this embodiment can be based on, for example, the shared block 621 described in the second embodiment with reference to Fig. 21. Even in this case, as shown in Fig. 32, the shared block 921 has a configuration similar to that of the shared block 621 described with reference to Fig. 21, in which the cathodes of the photoelectric conversion elements 311 in two or more or all of the logarithmic response units 310An are connected by a common line 3102, a readout circuit 370 is connected to the common line 3102, and a switching transistor 377 is provided between the readout circuit 370 and the photoelectric conversion elements 311 of each logarithmic response unit 310An.

[0153] 5.2 Example of operation In the above configuration, when reading out pixel signals from the gradation pixels including the readout circuit 370, the switching transistors 317 and 318 of all the logarithmic response units 310An are turned off, and the switching transistors 377 of the gradation pixels corresponding to the logarithmic response units 310An are sequentially connected in a time-division manner to the readout circuit 370. However, during binning, when reading out with an expanded dynamic range at low illuminance or the like, two or more switching transistors 318 are turned on during the same period, thereby executing reading out with an expanded dynamic range.

[0154] 6. Sixth embodiment In the above-described embodiment, a synchronous EVS that does not require arbitration of requests to read out detection signals output from each shared block 221, etc. is applied to the solid-state imaging device 200, but the present invention is not limited to such a configuration. For example, as in the solid-state imaging device illustrated in Fig. 33, an asynchronous EVS including a row arbiter 280 that arbitrates requests output from each row of the address event detection unit 260 and orders the rows for reading out detection signals may be applied. Note that Fig. 33 shows a detection chip 1002 in the solid-state imaging device according to this embodiment.

[0155] In this way, even when an asynchronous EVS is applied, it is possible to collect the photocurrents flowing out from the multiple photoelectric conversion elements 311 into one logarithmic conversion circuit, as in the above-mentioned embodiment, and therefore it is possible to secure a larger amount of photocurrent. This makes it possible to widen the dynamic range in photocurrent detection, and therefore it is possible to secure a sufficiently wide dynamic range even at low illuminance.

[0156] On the other hand, when sufficient illuminance is obtained, by turning off the switching transistor 318 and turning on the switching transistor 317 in all or a necessary and sufficient number of logarithmic response units 310An, etc., it is possible to operate each of these all or a necessary and sufficient number of logarithmic response units 310An, etc. as a single address event detection pixel, which makes it possible to detect address events with high resolution and reduce operating power.

[0157] The other configurations, operations, and effects may be similar to those of the above-described embodiment, so detailed description thereof will be omitted here.

[0158] 7. Application examples for mobile objects The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, etc.

[0159] FIG. 34 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a moving object control system to which the technology according to the present disclosure can be applied.

[0160] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 34, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also, as functional configurations of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053 are illustrated.

[0161] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0162] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as head lamps, back lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves or signals of various switches transmitted from a portable device that replaces a key may be input to the body system control unit 12020. The body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, and the like of the vehicle.

[0163] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for a person, a car, an obstacle, a sign, or characters on a road surface, based on the received image.

[0164] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0165] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing.

[0166] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the outside-of-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0167] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on the driver's operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0168] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0169] The audio / video output unit 12052 transmits at least one output signal of audio and video to an output device capable of visually or audibly notifying information to passengers in the vehicle or the outside of the vehicle. In the example of Fig. 35, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as the output device. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.

[0170] FIG. 35 is a diagram showing an example of the installation position of the imaging unit 12031.

[0171] In FIG. 35, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0172] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin is mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

[0173] 35 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.

[0174] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of a plurality of imaging elements, or may be an imaging element having pixels for detecting a phase difference.

[0175] For example, the microcomputer 12051 can extract, as a preceding vehicle, a three-dimensional object that is the closest three-dimensional object on the travel path of the vehicle 12100 and travels at a predetermined speed (for example, 0 km / h or more) in approximately the same direction as the vehicle 12100, by calculating the distance to each three-dimensional object in the imaging ranges 12111 to 12114 and the change over time of this distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. Furthermore, the microcomputer 12051 can set a vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving that travels autonomously without relying on the driver's operation.

[0176] For example, the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0177] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured images of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

[0178] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. Specifically, the imaging device 100 of FIG. 1 can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, pixels can be miniaturized to obtain a captured image that is easier to see, thereby reducing driver fatigue.

[0179] The above-mentioned embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specified in the claims correspond to each other. Similarly, the matters specified in the claims and the matters in the embodiment of the present technology having the same name correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment without departing from the gist of the technology.

[0180] It should be noted that the effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0181] The present technology can also be configured as follows. (1) A plurality of detection pixels each outputting a luminance change of incident light; a detection circuit that outputs an event signal based on the luminance change output from each of the detection pixels; A first common line connecting the plurality of detection pixels; Equipped with Each of the detection pixels is A photoelectric conversion element; a logarithmic conversion circuit for converting a photocurrent flowing out from the photoelectric conversion element into a voltage signal corresponding to a logarithmic value of the photocurrent; a first circuit that outputs a luminance change of the incident light that is incident on the photoelectric conversion element based on the voltage signal output from the logarithmic conversion circuit; a first transistor connected between the photoelectric conversion element and the logarithmic conversion circuit; a second transistor connected between the photoelectric conversion element and the first common line; Equipped with The detection circuit includes a second circuit that outputs the event signal based on the luminance change output from each of the detection pixels. Solid-state imaging device. (2) Each of the detection pixels is a third transistor connected between a first node connecting the first transistor and the logarithmic conversion circuit and a second node connecting the second transistor and the first common line. The solid-state imaging device according to (1) above. (3) The solid-state imaging device according to (1), wherein the second transistor is connected between the first common line and a node that connects the photoelectric conversion element and the first transistor. (4) The solid-state imaging device according to any one of (1) to (3), further comprising a readout circuit connected to the first common line and configured to generate a pixel signal having a voltage value corresponding to the charge accumulated in the photoelectric conversion element. (5) The read circuit includes: a reset transistor connected between the first common line and a power supply line; an amplifying transistor having a gate connected to the first common line; The solid-state imaging device according to (4) above, (6) A second common line connecting the plurality of detection pixels; a plurality of fourth transistors connected between the photoelectric conversion element and the second common line in each of the detection pixels; The solid-state imaging device according to any one of (1) to (3), further comprising a readout circuit connected to the second common line and configured to generate a pixel signal having a voltage value corresponding to the charge accumulated in the photoelectric conversion element. (7) The read circuit includes: a reset transistor connected between the second common line and a power supply line; an amplifying transistor having a gate connected to the second common line; The solid-state imaging device according to (6) above, (8) Each of the detection pixels is The logarithmic conversion circuit further includes a differentiator for generating a differential signal indicating a conversion amount of the voltage signal output from the logarithmic conversion circuit. The solid-state imaging device according to any one of (1) to (7) above. (9) The detection circuit includes: a selection unit that selects one of the differential signals output from each of the detection pixels; a comparator that outputs the event signal based on the differential signal; The solid-state imaging device according to (8) above, (10) The comparator is a first comparator that detects that a voltage value of the differential signal exceeds a first threshold and outputs the event signal; a second comparator that detects when a voltage value of the differential signal falls below a second threshold that is a voltage level lower than the first threshold and outputs the event signal; The solid-state imaging device according to (9) above, (11) A plurality of the detection circuits are provided, each of the detection circuits outputs a request to request reading of a detection signal from the detection circuit when an address event is detected in at least one of the plurality of detection pixels; The detection circuit further includes an arbiter that arbitrates the requests output from at least one of the plurality of detection circuits to determine a read order of the detection signals from the detection circuits that have output the requests. The solid-state imaging device according to any one of (1) to (10) above. (12) The solid-state imaging device according to any one of (1) to (11), further comprising a first chip having a light receiving section in which a plurality of logarithmic response units, each of which includes the photoelectric conversion element, the logarithmic conversion circuit, the first transistor, and the second transistor, are arranged in a two-dimensional lattice pattern. (13) The logarithmic conversion circuit includes: a fourth transistor having a source connected to the first transistor; a fifth transistor having a gate connected to the source of the fourth transistor and a source grounded; Including, The gate of the fourth transistor is connected to the drain of the fifth transistor. The solid-state imaging device according to (12) above. (14) The logarithmic conversion circuit includes: a sixth transistor having a source connected to the drain of the fourth transistor and a drain connected to a power supply line; a seventh transistor having a gate connected to the drain of the fourth transistor and a source connected to the drain of the fifth transistor; Further comprising: The gate of the sixth transistor is connected to the drain of the seventh transistor. The solid-state imaging device according to (13) above. (15) The light receiving section further includes a pixel separating section extending in a lattice pattern, The logarithmic response units are provided in the pixel regions partitioned into the two-dimensional lattice shape by the pixel separation unit. The solid-state imaging device according to (12) above. (16) the first and second transistors, at least two transistors different from the first and second transistors, and the photoelectric conversion element are arranged in the pixel region; the at least two transistors are disposed in the pixel region at positions sandwiching the photoelectric conversion element, The logarithmic conversion circuit is configured using at least one of the at least two transistors in each of the two pixel regions adjacent to each other. The solid-state imaging device according to (15) above. (17) Further comprising a second chip on which a plurality of the detection circuits are arranged, The first chip and the second chip form a single laminated chip. The solid-state imaging device according to any one of (12) to (16) above. (18) A solid-state imaging device according to any one of (1) to (17) above; A control unit that controls the solid-state imaging device; An imaging device comprising: (19) the solid-state imaging device includes a plurality of shared blocks each including the plurality of detection pixels; The control unit controls the operation mode of the solid-state imaging device to a first mode in which, in at least one of the plurality of shared blocks, the first and second transistors in one detection image of the plurality of detection pixels are turned on, and the first transistor in at least one other detection image of the plurality of detection pixels is turned off and the second transistor is turned on; a second mode in which the first transistor of each of the plurality of detection pixels is turned on and the second transistor of each of the plurality of detection pixels is turned off in all of the plurality of shared blocks; Switch to one of The imaging device according to (18) above. (20) The first mode is a third mode in which, in all of the plurality of shared blocks, the first and second transistors in one detection image of the plurality of detection pixels are turned on, and the first transistor is turned off and the second transistor is turned on in at least one other detection image of the plurality of detection pixels; a fourth mode in which, in a part of the plurality of shared blocks, the first and second transistors in one detection image of the plurality of detection pixels are turned on, the first transistor is turned off and the second transistor is turned on in at least one other detection image of the plurality of detection pixels, and, in the remaining shared blocks of the plurality of shared blocks, the first transistor of each of the plurality of detection pixels is turned on and the second transistor is turned off; Including, The control unit switches the operation mode of the solid-state imaging device from the second mode to any one of the fourth modes. The imaging device according to (19) above. [Explanation of symbols]

[0182] 10, 20 Layout pixels 12 Pixel separation section 100 Imaging device 110 Optics Department 120 Recording Section 130 Control section 200 Solid-state imaging device 201 Photodetector chip 202, 802, 1002 Detection Chip 211, 212, 213, 231, 232, 233 Via placement section 220 Light receiving section 221, 621, 721, 821, 921 shared blocks 240 Signal Processing Circuit 251 Row driver circuit 252 column driver circuit 260 Address Event Detector 270 column ADC 280 Line Arbiter 300 detection pixels 305 Detection Circuit 310, 310A, 310An, 310Bn, 310Cn Logarithmic response unit 311 Photoelectric conversion element 312, 313, 315, 316, 512 nMOS transistors 314, 411, 511 pMOS transistors 314c Contact 317-319, 377 Switching transistors 320 Detection Block 330 Buffer 340 Differentiator 341, 343 Capacitor 342 Inverter 344 Switch 360 Transfer Circuit 370 Readout circuit 373 Reset Transistor 374 Floating Diffusion Region 375 Amplifying Transistor 376 Select Transistor 400 Selection 410, 420 Selector 500 Comparison section 510, 520 Comparator 3101, 3102 common line

Claims

1. A plurality of detection pixels each outputting a luminance change of incident light; a detection circuit that outputs an event signal based on the luminance change output from each of the detection pixels; A first common line connecting the plurality of detection pixels; Equipped with Each of the detection pixels is A photoelectric conversion element; a logarithmic conversion circuit for converting a photocurrent flowing out from the photoelectric conversion element into a voltage signal corresponding to a logarithmic value of the photocurrent; a first circuit that outputs a luminance change of the incident light that is incident on the photoelectric conversion element based on the voltage signal output from the logarithmic conversion circuit; a first transistor connected between the photoelectric conversion element and the logarithmic conversion circuit; a second transistor connected between the photoelectric conversion element and the first common line; a first node connecting the first transistor and the logarithmic conversion circuit; a third transistor connected between the second transistor and a second node connecting the second transistor and the first common line; Equipped with the detection circuit includes a second circuit that outputs the event signal based on the luminance change output from each of the detection pixels; Solid-state imaging device.

2. The solid-state imaging device according to claim 1 , further comprising a readout circuit connected to the first common line and configured to generate a pixel signal having a voltage value corresponding to the charge accumulated in the photoelectric conversion element.

3. The read circuit includes: a reset transistor connected between the first common line and a power supply line; an amplifying transistor having a gate connected to the first common line; The solid-state imaging device according to claim 2 .

4. A plurality of detection pixels, each of which outputs a luminance change of incident light; a detection circuit that outputs an event signal based on the luminance change output from each of the detection pixels; A first common line connecting the plurality of detection pixels; A second common line connecting the plurality of detection pixels; Equipped with Each of the detection pixels is A photoelectric conversion element; a logarithmic conversion circuit for converting a photocurrent flowing out from the photoelectric conversion element into a voltage signal corresponding to a logarithmic value of the photocurrent; a first circuit that outputs a luminance change of the incident light that is incident on the photoelectric conversion element based on the voltage signal output from the logarithmic conversion circuit; a first transistor connected between the photoelectric conversion element and the logarithmic conversion circuit; a second transistor connected between the photoelectric conversion element and the first common line; a readout circuit connected to the second common line and configured to generate a pixel signal having a voltage value corresponding to the charge stored in the photoelectric conversion element; a plurality of fourth transistors connected between the photoelectric conversion element and the second common line in each of the detection pixels; Equipped with the detection circuit includes a second circuit that outputs the event signal based on the luminance change output from each of the detection pixels; Solid-state imaging device.

5. The read circuit includes: a reset transistor connected between the second common line and a power supply line; an amplifying transistor having a gate connected to the second common line; The solid-state imaging device according to claim 4 .

6. A plurality of detection pixels, each of which outputs a luminance change of incident light; a detection circuit that outputs an event signal based on the luminance change output from each of the detection pixels; A first common line connecting the plurality of detection pixels; Equipped with Each of the detection pixels is A photoelectric conversion element; a logarithmic conversion circuit for converting a photocurrent flowing out from the photoelectric conversion element into a voltage signal corresponding to a logarithmic value of the photocurrent; a first circuit that outputs a luminance change of the incident light that is incident on the photoelectric conversion element based on the voltage signal output from the logarithmic conversion circuit; a first transistor connected between the photoelectric conversion element and the logarithmic conversion circuit; a second transistor connected between the photoelectric conversion element and the first common line; a differentiator that generates a differential signal that indicates a conversion amount of the voltage signal output from the logarithmic conversion circuit; Equipped with the detection circuit includes a second circuit that outputs the event signal based on the luminance change output from each of the detection pixels; the second circuit includes a selection unit that selects one of the differential signals output from each of the detection pixels, and a comparator that outputs the event signal based on the differential signal; Equipped with Solid-state imaging device.

7. The comparator is a first comparator that detects that a voltage value of the differential signal exceeds a first threshold and outputs the event signal; a second comparator that detects when a voltage value of the differential signal falls below a second threshold that is a voltage level lower than the first threshold and outputs the event signal; The solid-state imaging device according to claim 6 .

8. A plurality of the detection circuits are provided, each of the detection circuits outputs a request to request reading of a detection signal from the detection circuit when an address event is detected in at least one of the plurality of detection pixels; an arbiter that arbitrates the requests output from at least one of the plurality of detection circuits to determine a read order of the detection signals from the detection circuits that have output the requests; 8. The solid-state imaging device according to claim 1.

9. The solid-state imaging device according to any one of claims 1 to 8, further comprising a first chip having a light receiving section in which a plurality of logarithmic response units, each of which includes the photoelectric conversion element, the logarithmic conversion circuit, the first transistor, and the second transistor, are arranged in a two-dimensional lattice pattern.

10. The logarithmic conversion circuit includes: a fourth transistor having a source connected to the first transistor; a fifth transistor having a gate connected to the source of the fourth transistor and a source grounded; Including, The gate of the fourth transistor is connected to the drain of the fifth transistor. The solid-state imaging device according to claim 9 .

11. The logarithmic conversion circuit includes: a sixth transistor having a source connected to the drain of the fourth transistor and a drain connected to a power supply line; a seventh transistor having a gate connected to the drain of the fourth transistor and a source connected to the drain of the fifth transistor; Further comprising: The gate of the sixth transistor is connected to the drain of the seventh transistor. The solid-state imaging device according to claim 10.

12. A plurality of detection pixels, each of which outputs a luminance change of incident light; a detection circuit that outputs an event signal based on the luminance change output from each of the detection pixels; A first common line connecting the plurality of detection pixels; Equipped with Each of the detection pixels is A photoelectric conversion element; a logarithmic conversion circuit for converting a photocurrent flowing out from the photoelectric conversion element into a voltage signal corresponding to a logarithmic value of the photocurrent; a first circuit that outputs a luminance change of the incident light that is incident on the photoelectric conversion element based on the voltage signal output from the logarithmic conversion circuit; a first transistor connected between the photoelectric conversion element and the logarithmic conversion circuit; a second transistor connected between the photoelectric conversion element and the first common line; Equipped with a first chip including a light receiving unit in which a plurality of logarithmic response units, each of which includes the photoelectric conversion element, the logarithmic conversion circuit, the first transistor, and the second transistor, are arranged in a two-dimensional lattice pattern; the detection circuit includes a second circuit that outputs the event signal based on the luminance change output from each of the detection pixels; The light receiving section further includes a pixel separating section extending in a lattice pattern, the logarithmic response units are provided in respective pixel regions partitioned into the two-dimensional lattice shape by the pixel separation unit, the first and second transistors, at least two transistors different from the first and second transistors, and the photoelectric conversion element are arranged in the pixel region; the at least two transistors are disposed in the pixel region at positions sandwiching the photoelectric conversion element, the logarithmic conversion circuit is configured using at least one of the at least two transistors in each of two adjacent pixel regions; Solid-state imaging device.

13. A second chip on which a plurality of the detection circuits are arranged is further provided, The first chip and the second chip form a single laminated chip. The solid-state imaging device according to any one of claims 9 to 12.

14. A solid-state imaging device; A control unit that controls the solid-state imaging device; An imaging device comprising: The solid-state imaging device includes: A plurality of detection pixels each outputting a luminance change of incident light; a detection circuit that outputs an event signal based on the luminance change output from each of the detection pixels; A first common line connecting the plurality of detection pixels; Equipped with Each of the detection pixels is A photoelectric conversion element; a logarithmic conversion circuit for converting a photocurrent flowing out from the photoelectric conversion element into a voltage signal corresponding to a logarithmic value of the photocurrent; a first circuit that outputs a luminance change of the incident light that is incident on the photoelectric conversion element based on the voltage signal output from the logarithmic conversion circuit; a first transistor connected between the photoelectric conversion element and the logarithmic conversion circuit; a second transistor connected between the photoelectric conversion element and the first common line; Equipped with the detection circuit includes a second circuit that outputs the event signal based on the luminance change output from each of the detection pixels; the solid-state imaging device includes a plurality of shared blocks each including the plurality of detection pixels; The control unit controls the operation mode of the solid-state imaging device to a first mode in which, in at least one of the plurality of shared blocks, the first and second transistors in one detection image of the plurality of detection pixels are turned on, and the first transistor in at least one other detection image of the plurality of detection pixels is turned off and the second transistor is turned on; a second mode in which the first transistor of each of the plurality of detection pixels is turned on and the second transistor of each of the plurality of detection pixels is turned off in all of the plurality of shared blocks; Switch to one of the Imaging device.

15. The first mode is a third mode in which, in all of the plurality of shared blocks, the first and second transistors in one detection image of the plurality of detection pixels are turned on, and the first transistor is turned off and the second transistor is turned on in at least one other detection image of the plurality of detection pixels; a fourth mode in which, in a part of the plurality of shared blocks, the first and second transistors in one detection image of the plurality of detection pixels are turned on, the first transistor is turned off and the second transistor is turned on in at least one other detection image of the plurality of detection pixels, and in the remaining shared blocks of the plurality of shared blocks, the first transistor of each of the plurality of detection pixels is turned on and the second transistor is turned off; Including, the control unit switches the operation mode of the solid-state imaging device from the second mode to any one of the fourth modes. The imaging device according to claim 14.

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