Image sensor and image pickup device

Abstract

To provide an imaging element and an imaging device capable of suppressing noise in a pixel signal caused by heat generated in an image processing block being transmitted to the pixel block side.SOLUTION: An imaging element 400 includes a first substrate 100 on which a first pixel block having pixels and a second pixel block adjacent to the first pixel block are arranged, and a second substrate 200 in which a first circuit block that converts a signal output from the pixel of the first pixel block into a digital signal and a second circuit block that converts a signal output from the pixel of the second pixel block into a digital signal are arranged, and that is laminated on the first substrate. A distance between the first circuit block and the second circuit block is different from a distance between the first pixel block and the second pixel block.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an imaging element and an imaging apparatus. [Background technology]

[0002] An imaging element including an AD conversion unit is known (for example, Patent Document 1). Conventionally, noise caused by heat generated in the AD conversion unit has been a problem. Patent Document 1: JP2013-51674 Summary of the Invention

[0003] In a first aspect of the present invention, an imaging element includes a first substrate on which a first pixel block having pixels and a second pixel block adjacent to the first pixel block are arranged, and a second substrate on which a first circuit block that converts a signal output from a pixel in the first pixel block into a digital signal and a second circuit block that converts a signal output from a pixel in the second pixel block into a digital signal are arranged, the second substrate being stacked on the first substrate, and the distance between the first circuit block and the second circuit block is different from the distance between the first pixel block and the second pixel block.

[0004] In a second aspect of the present invention, an imaging element includes a first pixel block having pixels, a first substrate on which the first pixel block and a second pixel block are arranged, a first circuit block that converts signals output from pixels in the first pixel block into digital signals, and a second circuit block that converts signals output from pixels in the second pixel block into digital signals, and is stacked on the first substrate, wherein the first pixel block and the second pixel block are adjacent to each other, and the first circuit block and the second circuit block are not adjacent to each other.

[0005] In a third aspect of the present invention, an imaging element includes a first substrate on which a plurality of pixel blocks having pixels are arranged two-dimensionally, and a second substrate on which a plurality of circuit blocks are arranged, stacked on the first substrate, each of which converts a signal output by at least one corresponding one of the plurality of pixel blocks into a digital signal, wherein the relative arrangement of the plurality of pixel blocks is different from the relative arrangement of the plurality of circuit blocks corresponding to each of the plurality of pixel blocks.

[0006] In a second aspect of the present invention, an imaging device includes the above-mentioned imaging element.

[0007] The above summary of the invention does not list all of the features of the present invention. Also, subcombinations of these features may also be inventions. [Brief description of the drawings]

[0008] [Figure 1] FIG. 4 is a diagram showing an overview of an image sensor 400 according to the present embodiment. [Diagram 2] An example of a specific configuration of the pixel unit 110 is shown. [Diagram 3] 2 shows an example of a circuit configuration of the pixel 112. [Figure 4] An example of a more specific configuration of the processing circuit unit 210 is shown. [Diagram 5] 2 shows a schematic diagram of the connection relationship between the pixel block 120 and the processing block 220. [Figure 6] 1 is a schematic diagram showing the relationship between brightness of a subject and heat generation; [Figure 7] 2A and 2B are schematic diagrams showing other connection relationships between the pixel block 120 and the processing block 220. [Figure 8] Another connection relationship between the pixel block 120 and the processing block 222 is shown diagrammatically. [Figure 9] Another connection relationship between the pixel block 120 and the processing block 222 is shown diagrammatically. [Figure 10] 2 shows a schematic diagram of the connection relationship between the pixel block 120 and the processing block 220. [Figure 11]FIG. 2 is a block diagram showing an example of the configuration of an imaging device 500 according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0010] In this specification, the X-axis and the Y-axis are mutually orthogonal, and the Z-axis is orthogonal to the XY plane. The XYZ-axes form a right-handed system. The direction parallel to the Z-axis may be referred to as the stacking direction of the image sensor 400. In this specification, the terms "up" and "down" are not limited to the up and down directions in the direction of gravity. These terms merely refer to relative directions in the Z-axis direction. Note that in this specification, the arrangement in the X-axis direction is described as a "row" and the arrangement in the Y-axis direction is described as a "column", but the matrix direction is not limited to this. In addition, the Z-axis direction is the optical axis direction in which light from the subject enters.

[0011] Fig. 1 is a diagram showing an overview of an image sensor 400 according to this embodiment. The image sensor 400 captures an image of a subject. The image sensor 400 generates image data of the captured subject. The image sensor 400 includes a first substrate 100 and a second substrate 200. As shown in Fig. 1, the first substrate 100 is laminated on the second substrate 200.

[0012] The first substrate 100 has a pixel section 110. The pixel section 110 outputs a pixel signal based on incident light. The first substrate 100 may be called a pixel chip.

[0013] The second substrate 200 has a processing circuit section 210 and a peripheral circuit section 230. The second substrate 200 may be called a signal processing chip.

[0014] The processing circuit unit 210 receives the pixel signals output from the first substrate 100. The processing circuit unit 210 processes the input pixel signals. For example, the processing circuit unit 210 performs a process of converting an analog signal into a digital signal. Specifically, the processing circuit unit 210 performs a process of converting the input pixel signals into a digital signal. The processing circuit unit 210 may perform other signal processing. Examples of other signal processing include noise removal processing such as analog or digital CDS (Correlated Double Sampling).

[0015] The processing circuit unit 210 of this example is disposed at a position facing the pixel unit 110 on the second substrate 200. That is, the processing circuit unit 210 is disposed so as to at least partially overlap the pixel unit 110 in the optical axis direction. The processing circuit unit 210 may output a control signal to the pixel unit 110 for controlling the driving of the pixel unit 110.

[0016] The peripheral circuit section 230 controls the driving of the processing circuit section 210. The peripheral circuit section 230 is disposed around the processing circuit section 210 on the second substrate 200. The peripheral circuit section 230 may be electrically connected to the first substrate 100 and control the driving of the pixel section 110.

[0017] The imaging element 400 may have a third substrate stacked on the second substrate 200 in addition to the first substrate 100 and the second substrate 200. For example, the third substrate is a memory chip, and performs image processing according to a signal output by the second substrate 200. The structure of the imaging element 400 may be a back-illuminated type or a front-illuminated type. An example of a back-illuminated type will be described below.

[0018] 2 shows an example of a specific configuration of the pixel section 110. In this example, an enlarged view of the pixel section 110 and a pixel block 120 provided in the pixel section 110 is shown.

[0019] The pixel section 110 has a plurality of pixel blocks 120 arranged two-dimensionally along the row and column directions. In this example, the pixel section 110 has M×N (M and N are natural numbers) pixel blocks 120. In this example, the case where M is equal to N is illustrated, but M and N may be different.

[0020] The pixel block 120 has at least one pixel 112. The pixel block 120 in this example has m×n pixels 112 (m and n are natural numbers). For example, the pixel block 120 has 16×16 pixels 112. The number of pixels 112 corresponding to the pixel block 120 is not limited to this. In this example, a case where m is equal to n is illustrated, but m may be different from n. The pixel block 120 has a plurality of pixels 112 connected to a common control line in the row direction. For example, each pixel 112 of the pixel block 120 is connected to a common control line so as to be set to the same exposure time. In one example, n pixels 112 arranged in the row direction are connected by a common control line.

[0021] On the other hand, different exposure times may be set among the multiple pixel blocks 120. That is, the pixels 112 in each pixel block 120 have the same exposure time, but may be set to different exposure times among the other pixel blocks 120. For example, when the pixels 112 in a pixel block 120 are connected in the row direction by a common control line, the pixels 112 in the other pixel blocks 120 are commonly connected by a different control line.

[0022] In this embodiment, one pixel block 120 is arranged for one processing block 220. The connection relationship between the pixel block 120 and the processing block 220 will be described later.

[0023] The pixels 112 have a photoelectric conversion function of converting light into an electric charge. The pixels 112 accumulate the electric charges generated by the photoelectric conversion. The m pixels 112 are arranged in a line in the column direction and connected to a common signal line 122. The m pixels 112 are arranged in a line in n columns in the row direction in the pixel block 120.

[0024] In other words, the pixel block 120 is a group of multiple pixels 112 connected by a common control line. Also, the pixel block 120 can be said to be the smallest unit of a circuit for multiple pixels 112 to which the same exposure time is set.

[0025] 3 shows an example of a circuit configuration of the pixel 112. The pixel 112 includes a photoelectric conversion unit 104, a transfer unit 123, a reset unit 126, and a pixel output unit 127. The pixel output unit 127 has an amplifier unit 128 and a selection unit 129. In this example, the transfer unit 123, the reset unit 126, the amplifier unit 128, and the selection unit 129 are described as N-channel type FETs, but the type of transistor is not limited to this.

[0026] The photoelectric conversion unit 104 has a photoelectric conversion function of converting light into electric charges. The photoelectric conversion unit 104 accumulates the electric charges resulting from photoelectric conversion. The photoelectric conversion unit 104 is, for example, a photodiode.

[0027] The transfer unit 123 transfers the charge accumulated in the photoelectric conversion unit 104 to the storage unit 125. The transfer unit 123 is an example of a transfer gate that transfers the charge of the photoelectric conversion unit 104. In other words, the transfer unit 123 serves as a gate, the photoelectric conversion unit 104 serves as a source, and the storage unit 125 serves as a drain, constituting a so-called transfer transistor. The gate terminal of the transfer unit 123 is connected to a local transfer control line for each pixel block 120, and a control signal φTX1 is input thereto.

[0028] The charge from the photoelectric conversion unit 104 is transferred to the accumulation unit 125 by the transfer unit 123. The accumulation unit 125 is an example of a floating diffusion (FD).

[0029] The reset unit 126 discharges the charge in the storage unit 125 to a power supply line to which a predetermined power supply voltage VDD is supplied. A gate terminal of the reset unit 126 is connected to a global reset control line spanning multiple pixel blocks 120, and a reset control signal φRST is input thereto.

[0030] The pixel output unit 127 outputs a signal based on the potential of the accumulation unit 125 to the signal line 122. The pixel output unit 127 has an amplifier unit 128 and a selection unit 129. The amplifier unit 128 has a gate terminal connected to the accumulation unit 125, a drain terminal connected to a power supply wiring to which a power supply voltage VDD is supplied, and a source terminal connected to the drain terminal of the selection unit 129.

[0031] The selection unit 129 controls the electrical connection between the pixel 112 and the signal line 122. When the selection unit 129 electrically connects the pixel 112 and the signal line 122, a pixel signal is output from the pixel 112 to the signal line 122. A gate terminal of the selection unit 129 is connected to a global selection control line across the multiple pixel blocks 120 for inputting a selection control signal φSEL. A source terminal of the selection unit 129 is connected to the load current source 121.

[0032] The load current source 121 supplies a current to the signal line 122. The load current source 121 may be provided on the first substrate 100 or may be provided on the second substrate 200.

[0033] Hereinafter, any one of the charges accumulated in the photoelectric conversion unit 104, the charges transferred to the accumulation unit 125, and the signal based on the potential of the accumulation unit 125, or all of these may be referred to as a pixel signal.

[0034] In other words, the pixel 112 includes at least one photoelectric conversion unit 104 and a pixel output unit 127 as a readout unit that reads out an image signal from the at least one photoelectric conversion unit 104 to a signal line 122. The pixel 112 can be said to be the smallest unit of a circuit that outputs a pixel signal that constitutes an image to the signal line 122.

[0035] 4 shows an example of a more specific configuration of the processing circuit section 210. In this example, an enlarged view of the processing circuit section 210 and a processing block 220 provided in the processing circuit section 210 is shown.

[0036] The processing circuit section 210 has processing blocks 220 arranged side by side in the row and column directions. The processing circuit section 210 of this example has M×N processing blocks 220.

[0037] In this embodiment, the processing block 220 and the pixel block 120 are arranged in an overlapping position when viewed from the optical axis direction, but the processing block 220 and the pixel block 120 arranged in an overlapping position are not necessarily connected. In this case, the areas of the processing block 220 and the pixel block 120 may be substantially the same, including the margin between the adjacent blocks.

[0038] The processing block 220 controls the driving of the pixel block 120 electrically connected thereto. The processing block 220 and the pixel block 120 being electrically connected to each other may be referred to as being corresponding to each other. For example, the processing block 220 controls the exposure time of the corresponding pixel block 120. The processing block 220 also has a processing circuit such as an AD converter, and processes a signal output from the corresponding pixel block 120. In one example, the processing block 220 converts an analog pixel signal output from the corresponding pixel block 120 into a digital signal. The processing block 220 in this example includes an exposure control unit 10, a pixel driving unit 20, a joining unit 30, a signal conversion unit 40, and a signal output unit 50.

[0039] The exposure control unit 10 controls exposure of the multiple pixels 112. The exposure control unit 10 generates a signal for controlling the exposure time of the pixels 112. In one example, the exposure control unit 10 controls the exposure time for each pixel block 120 by adjusting at least one of the start timing or end timing of the exposure.

[0040] The pixel driving unit 20 is electrically connected to the multiple pixels 112. The pixel driving unit 20 selects and drives an arbitrary pixel 112 from the multiple pixels 112 based on a signal from the exposure control unit 10. The image sensor 400 can set the exposure time for each pixel block 120 according to the intensity of incident light, thereby expanding the dynamic range.

[0041] The bonding unit 30 bonds the first substrate 100 and the second substrate 200. The bonding unit 30 inputs pixel signals input from the first substrate 100 to the signal conversion unit 40. The bonding units 30 are provided corresponding to n pixels 112 arranged in the row direction, and input pixel signals to the signal conversion unit 40 for each column.

[0042] The signal conversion unit 40 converts the analog signal output by the pixel unit 110 into a digital signal. In this example, the signal conversion unit 40 converts the analog pixel signal into a digital signal. The signal conversion unit 40 sequentially converts analog signals from m pixels 112 arranged in a column direction into digital signals. The signal conversion unit 40 has n AD converters 42 arranged in a row direction. Each of the AD converters 42 converts analog signals from the pixels 112 in a corresponding column of the corresponding pixel block 120 into digital signals in parallel. This can also be said to be a so-called column ADC method for one pixel block 120.

[0043] The signal output section 50 receives the digital signal from the signal conversion section 40. In one example, the signal output section 50 temporarily stores the digital signal. The signal output section 50 may include a latch circuit for storing the digital signal.

[0044] Note that, instead of providing one processing block 220 for one pixel block 120, one processing block 220 may be provided for N pixel blocks 120 (N is a natural number equal to or greater than 2). The N pixel blocks 120 corresponding to one processing block may be referred to as a pixel block group. For example, two pixel blocks 120 arranged side by side in the column direction may be treated as one pixel block group, and one processing block 220 may be provided for each pixel block 120. In this case, the processing block 220 may control the exposure time for each pixel block 120.

[0045] In other words, the processing block 220 is electrically connected to at least one pixel block 120 and can be said to be the smallest unit of a circuit that processes pixel signals of the at least one pixel block 120. The processing circuit unit 210 can also be said to be composed of a group of processing blocks 220.

[0046] Fig. 5 shows a schematic diagram of the connection relationship between the pixel block 120 and the processing block 220. For ease of explanation, Fig. 5 shows 4x4 blocks in the pixel section 110 and the processing circuit section 210, and each block is represented as "1-1", "1-2", etc., in order of the XY direction.

[0047] 5, the columns with "1" in the X direction, i.e., pixel blocks "1-1", "1-2", "1-3" and "1-4", are connected to processing blocks "1-1", "1-2", "1-3" and "1-4" that are stacked in the Z direction, which is the stacking direction, by connection wiring 250. Note that there are n connection wirings 250, which is the number of columns of pixel blocks 120, but in the figure, only one is shown as a representative. The connection wiring 250 extends in approximately the Z direction across the boundary surface 102 between the pixel section 110 and the processing circuit section 210.

[0048] On the other hand, the columns with "2" in the X direction, i.e., pixel blocks "2-1", "2-2", "2-3", and "2-4", are not connected to the processing blocks "2-1", "2-2", "2-3", and "2-4" that overlap in the Z direction, which is the stacking direction. Instead, pixel block "2-1" is connected to processing block "2-3" that does not overlap in the Z direction. Also, pixel block "2-2" is connected to processing block "2-4" that does not overlap in the Z direction, pixel block "2-3" is connected to processing block "2-1" that does not overlap in the Z direction, and pixel block "2-4" is connected to processing block "2-2" that does not overlap in the Z direction.

[0049] The pixel block "2-1" and the processing block "2-3" are electrically connected by a connection wiring 252 that extends substantially in the Z direction across the boundary surface 102 between the pixel unit 110 and the processing circuit unit 210, and a connection wiring 253 that is connected to the connection wiring 252 and extends within the XY plane of the processing circuit unit 210. The other pixel blocks and processing blocks in the column "2" in the X direction are similarly electrically connected by the connection wirings 252, 253.

[0050] The connection wirings 252 and 253 are shown as one representative wiring, similar to the connection wiring 250. The connection wiring 253 extending in the XY plane may be provided on the pixel unit 110 side, or may be provided on both the pixel unit 110 and the processing circuit unit 210.

[0051] The connection relationship between the pixel blocks and processing blocks in the column with "3" in the X direction is the same as that of the column with "1" in the X direction. Furthermore, the connection relationship between the pixel blocks and processing blocks in the column with "4" in the X direction is the same as that of the column with "2" in the X direction. In other words, the connection relationship between the pixel blocks and processing blocks with "1" in the X direction and the connection relationship between the pixel blocks and processing blocks with "2" in the X direction are treated as one unit and are repeatedly applied in the XY directions throughout the pixel unit 110 and the processing circuit unit 210. Note that some of the repetitions may have different connection relationships.

[0052] In the connection relationship between the pixel blocks and the processing blocks shown in FIG. 5, for example, pixel blocks "1-1" and "2-1" are adjacent to each other in the X direction, but the processing blocks "1-1" and "2-3" connected to them are not adjacent to each other in the X direction. Therefore, the connection relationship in FIG. 5 can be said to be an example in which the arrangement relationship of the multiple pixel blocks differs from the arrangement relationship of the multiple circuit blocks corresponding to each of the multiple pixel blocks.

[0053] 5, when focusing on any one of the pixel blocks that are connected and overlap with the processing block in the Z direction, any one of the pixel blocks adjacent to that pixel block is connected to a processing block that does not overlap in the Z direction. For example, when focusing on pixel block "1-1" that is connected and overlaps with the processing block in the Z direction, pixel block "2-1" of the pixel blocks adjacent to pixel block "1-1" is connected to processing block "2-3" that does not overlap in the Z direction.

[0054] Fig. 6 is a schematic diagram showing the relationship between the brightness of an object and heat generation, and shows the connection relationship in Fig. 5 on the XY plane.

[0055] For example, assume that light from a bright subject is incident across pixel blocks “1-1,” “1-2,” “2-1,” and “2-2.” In addition, subjects often span adjacent pixel blocks like this.

[0056] For example, when a method for expanding the dynamic range is used in which pixel signals are read out by changing the exposure time or the number of pixel signal outputs for each pixel block, pixel signals from a pixel block receiving a bright subject may be read out to a processing block more frequently than from other pixel blocks so that the pixels in that pixel block do not become saturated. In this case, the processing block where readout is performed frequently will perform processing such as AD conversion more frequently, resulting in greater heat generation.

[0057] According to the embodiment of FIG. 6, the pixel blocks "1-1", "1-2", "2-1" and "2-2" are connected to the processing blocks "1-1", "1-2", "2-3" and "2-4". Therefore, the processing blocks "1-1", "1-2", "2-3" and "2-4" generate a large amount of heat. Here, the processing blocks "1-1" and "1-2" are not adjacent to the processing blocks "2-3" and "2-4" in either the X or Y direction. Therefore, the area where heat is generated is dispersed as a whole. This makes it possible to suppress noise in pixel signals caused by heat being transmitted to the pixel block side due to the concentration of the areas where heat is generated.

[0058] Fig. 7 is a schematic diagram showing another connection relationship between the pixel block 120 and the processing block 220. In Fig. 7, the same components as in Fig. 5 are given the same reference numerals and the description thereof will be omitted. Fig. 7 is also simplified like Fig. 5.

[0059] 7, pixel block "1-1" is connected to processing block "1-1" that overlaps with it in the Z direction, which is the stacking direction, and processing block "1-3" that does not overlap with it in the Z direction. In this case, some of the pixels 112 in pixel block "1-1" are connected to processing block "1-1" by connection wiring 255 and connection wiring 256 connected thereto and extending mainly in the Z direction. Meanwhile, other pixels 112 in pixel block "1-1" are connected to processing block "1-3" by connection wiring 255 and connection wiring 257 connected thereto and extending also in the X and Y directions.

[0060] Here, since the processing block 220 is a column ADC type, it is preferable that the some pixels 112 and the other some pixels 112 are arranged for each column. From the viewpoint of dispersing heat, it is preferable that the number of the some pixels and the number of the other some pixels are the same or almost the same. For example, the pixels 112 in the odd columns of the pixel block "1-1" may be connected to the processing block "1-1", and the pixels 112 in the even columns of the pixel block "1-1" may be connected to the processing block "1-3".

[0061] In this case, in the drawing, n connection wirings 255, n / 2 connection wirings 256, and n / 2 connection wirings 257 are each shown as one representative. Note that all or a part of the connection wirings 257 may be arranged on the pixel unit 110 side, as in the case of FIG. 5.

[0062] Similarly, pixel block "1-2" is connected to processing block "1-2" that overlaps in the Z direction, which is the stacking direction, and processing block "1-4" that does not overlap in the Z direction. Furthermore, pixel block "1-3" is connected to processing block "1-3" that overlaps in the Z direction, which is the stacking direction, and pixel block "1-1" that does not overlap in the Z direction. Furthermore, pixel block "1-4" is connected to processing block "1-4" that overlaps in the Z direction, which is the stacking direction, and pixel block "1-2" that does not overlap in the Z direction.

[0063] In the example shown in Fig. 7, when one processing block is looked at, the processing block is connected to two pixel blocks. For example, processing block "1-1" is connected to pixel blocks "1-1" and "1-3". In this case, some of the multiple AD converters 42 in processing block "1-1" are connected to one pixel block "1-1", and another part of the multiple AD converters 42 are connected to the other pixel block "1-3". This allows parallel processing similar to that in the case where pixel blocks and processing blocks are connected one-to-one.

[0064] 7, the connection relationships between pixel blocks "1" to "4" in the Y direction and processing blocks are treated as one unit and are repeatedly applied in the XY directions throughout the pixel unit 110 and the processing circuit unit 210. Note that some of the repetitions may have different connection relationships.

[0065] In the connection relationship between the pixel blocks and the processing blocks shown in Fig. 7, for example, pixel block "1-1" overlaps with processing block "1-1" but does not overlap with processing block "1-3," but is connected to both of them. Therefore, the connection relationship in Fig. 7 can be said to be an example in which the layout relationship of the multiple pixel blocks differs from the layout relationship of the multiple circuit blocks corresponding to each of the multiple pixel blocks.

[0066] In the example of Fig. 7, for example, assume that light from a bright subject is incident across pixel blocks "1-1", "1-2", "2-1" and "2-2". In this case, pixel block "1-1" is connected to two processing blocks "1-1" and "1-3", so heat is distributed to these two processing blocks. Furthermore, since these two processing blocks are not adjacent to each other, the area where heat is generated is further distributed.

[0067] Also, looking at the four pixel blocks "1-1", "1-2", "2-1" and "2-2" as a whole, they are connected to eight processing blocks "1-1", "1-2", "1-3", "1-4", "2-1", "2-2", "2-3" and "2-4", and the processing frequency of each processing block is half the frequency of reading out a single pixel block. Therefore, the areas that generate a lot of heat are dispersed overall. This makes it possible to suppress noise in pixel signals caused by heat being transferred to the pixel blocks due to the concentration of areas that generate a lot of heat.

[0068] Fig. 8 is a schematic diagram showing another connection relationship between the pixel block 120 and the processing block 222. In Fig. 8, the same components as those in Figs. 5 to 7 are given the same reference numerals and their explanations are omitted. Fig. 8 is also simplified like Fig. 5.

[0069] 8, two pixel blocks, which are the pixel unit 110 and the processing circuit unit 212 as a whole, are connected to one processing block as one pixel block group. For example, two pixel blocks "1-1" and "1-2" are connected to one processing block "1-1,2" by a connection wiring 250. In this case, each of the processing blocks 222 has 2n AD converters 42.

[0070] Furthermore, pixel blocks "1-1" and "1-2" are connected to processing block "1-1,2" which overlaps with them in the Z direction, and pixel blocks "1-3" and "1-4" are also connected to processing block "1-3,4" which overlaps with them in the Z direction. Meanwhile, pixel blocks "2-1" and "2-2" are connected to processing block "2-3,4" which does not overlap with them in the Z direction by connection wiring 252 and 253, and pixel blocks "2-3" and "2-4" are also connected to processing block "2-1,2" which does not overlap with them in the Z direction.

[0071] 8, the pixel blocks "1" to "4" in the X direction and "1" to "2" in the Y direction, that is, the connection relationships between the pixel block groups and the processing blocks, are treated as one unit and are repeatedly applied in the X and Y directions throughout the pixel unit 110 and the processing circuit unit 210. Note that some of the repetitions may have different connection relationships.

[0072] In the connection relationship between the pixel blocks and the processing blocks shown in Fig. 8, for example, pixel block "1-1" overlaps with processing block "1-1,2," but pixel block "2-1" does not overlap with processing block "2-3,4." Therefore, the connection relationship in Fig. 8 can be said to be an example in which the layout relationship of the multiple pixel blocks differs from the layout relationship of the multiple circuit blocks corresponding to each of the multiple pixel blocks.

[0073] In the example of FIG. 8, for example, assume that light from a bright subject is incident across pixel blocks "1-1", "1-2", "2-1" and "2-2". In this case, due to the above-mentioned connection relationship, the processing frequency is high for processing blocks "1-1,2" and "2-3,4". Since these two processing blocks are not adjacent to each other, the area with high heat generation is dispersed. This makes it possible to suppress noise in pixel signals caused by heat being transferred to the pixel block side due to the concentration of the area with high heat generation.

[0074] Fig. 9 is a schematic diagram showing another connection relationship between the pixel block 120 and the processing block 222. In Fig. 9, the same components as those in Fig. 5 to Fig. 8 are given the same reference numerals and their explanations are omitted. Fig. 8 is also simplified like Fig. 5.

[0075] 9, two pixel blocks are connected to two processing blocks as one pixel block group in the pixel unit 110 and the processing circuit unit 212 as a whole. For example, two pixel blocks "1-1" and "1-2" are connected to two processing blocks "1-1,2" and "1-3,4" by connection wirings 255, 256, and 257.

[0076] In this case, each of the processing blocks 222 has 2n AD converters 42. Furthermore, some of the pixels 112 in the two pixel blocks "1-1" and "1-2" are connected to one processing block "1-1,2", and some of the pixels 112 are connected to the other processing block "1-3,4". For example, the pixels 112 in odd columns of both of the two pixel blocks "1-1" and "1-2" may be connected to one processing block "1-1,2", and the pixels 112 in even columns of both of the pixel blocks "1-1" and "1-2" may be connected to the other processing block "1-3,4".

[0077] 9, the connection relationships between pixel blocks "1" to "4" in the X direction and processing blocks are treated as one unit and are repeatedly applied in the XY directions throughout the pixel unit 110 and the processing circuit unit 210. Note that some of the repetitions may have different connection relationships.

[0078] In the connection relationship between the pixel blocks and the processing blocks shown in Fig. 9, for example, pixel block "1-1" overlaps with processing block "1-1,2" but does not overlap with processing block "1-3,4." Therefore, the connection relationship in Fig. 9 can be said to be an example in which the layout relationship of the multiple pixel blocks differs from the layout relationship of the multiple circuit blocks corresponding to each of the multiple pixel blocks.

[0079] In the example of FIG. 9, for example, assume that light from a bright subject is incident across pixel blocks "1-1", "1-2", "2-1" and "2-2". In this case, due to the above-mentioned connection relationship, heat is distributed to four processing blocks having twice the area. Furthermore, the processing frequency in the four processing blocks is half the readout frequency of one pixel block group. Therefore, the areas with high heat generation are distributed overall. This makes it possible to suppress noise in pixel signals caused by heat being transferred to the pixel blocks due to the concentration of areas with high heat generation.

[0080] Fig. 10 is a schematic diagram showing the connection relationship between the pixel block 120 and the processing block 220. In Fig. 10, the same components as those in Fig. 6 are given the same reference numerals and the description thereof will be omitted.

[0081] 10, a pixel block "1-1" is electrically connected to a processing block "1-1." A pixel block "2-1" is electrically connected to a processing block "2-3."

[0082] Here, the distance L1 between pixel block "1-1" and pixel block "2-1" is different from the distance L2 between the corresponding processing block "1-1" and processing block "2-3". Specifically, the distance L1 is shorter than the distance L2. Here, the distance may be the distance between representative positions in each block, and for example, the representative position may be the geometric center of gravity (also called the center) of each block. Also, when each block is rectangular, it may be one of the corners.

[0083] For ease of explanation, the connection relationships between the pixel blocks "1-1" and "2-1" and the processing blocks "1-1" and "2-3" in Fig. 10 are the same as those in Fig. 6. However, the connection relationships are not limited to those in Fig. 6, and in this embodiment, it is sufficient that the pixel blocks are connected such that the distance between a pixel block of interest and another pixel block is different from the distance between the two corresponding processing blocks.

[0084] In addition, in the above distance relationship, the pixel block of interest and the other pixel blocks do not have to be adjacent to each other. Furthermore, as long as there is at least one pair of a pixel block and a processing block in which the distance between the pixel block of interest and the other pixel block is different from the distance between the corresponding two processing blocks, there may be a pair in which the distance between the other two pixel blocks is the same as the distance between the corresponding processing blocks.

[0085] In any of the above embodiments, a discharge unit may be provided in the pixel 112. The discharge unit discharges the charge accumulated in the photoelectric conversion unit 104 to a power supply wiring to which a power supply voltage VDD is supplied. As another example, the transfer unit 123 may be omitted. In that case, the accumulation unit 125 does not function as a floating diffusion. The accumulation unit 125 and the pixel output unit 127 may be shared with other pixels. The pixel 112 may be composed of a plurality of photoelectric conversion units 104 and transfer units 123.

[0086] Furthermore, in any of the above embodiments, the processing block 220 may not be provided with the exposure control unit 10 and the pixel driving unit 20, and reading may be performed mainly for each processing block 220, and conversion may be performed by the signal conversion unit 40. In this case, the exposure time of the pixels 112 is controlled not for each pixel block 120, but for the entire pixel unit 110.

[0087] 11 is a block diagram showing an example of the configuration of an image capturing apparatus 500 according to an embodiment. The image capturing apparatus 500 includes an image sensor 400, a system control unit 501, a driving unit 502, a photometry unit 503, a work memory 504, a recording unit 505, a display unit 506, a driving unit 514, and a photographing lens 520.

[0088] The photographing lens 520 guides the subject light beam incident along the optical axis OA to the image sensor 400. The photographing lens 520 is composed of a group of multiple optical lenses, and forms an image of the subject light beam from a scene near its focal plane. The photographing lens 520 may be an interchangeable lens that can be attached to and detached from the imaging device 500. Note that in FIG. 11, the photographing lens 520 is represented by a virtual single lens arranged near the pupil.

[0089] The driving unit 514 drives the photographing lens 520. In one example, the driving unit 514 changes the focus position by moving the optical lens group of the photographing lens 520. The driving unit 514 may also drive an iris diaphragm in the photographing lens 520 to control the amount of subject light entering the image sensor 400.

[0090] The drive unit 502 has a control circuit that executes charge accumulation control such as timing control and area control of the image sensor 400 in accordance with instructions from the system control unit 501. Furthermore, the operation unit 508 receives instructions from the photographer via a release button or the like.

[0091] The image sensor 400 transfers the pixel signal to an image processor 511 in the system controller 501. The image processor 511 generates image data by performing various image processes using the work memory 504 as a workspace. For example, when generating image data in a JPEG file format, a color video signal is generated from a signal obtained in the Bayer array, and then compression processing is performed. The generated image data is recorded in a recording unit 505, and is also converted into a display signal and displayed on a display unit 506 for a preset time.

[0092] The photometry unit 503 detects the luminance distribution of a scene prior to a series of shooting sequences for generating image data. The photometry unit 503 includes an AE sensor with, for example, about one million pixels. The calculation unit 512 of the system control unit 501 receives the output of the photometry unit 503 and calculates the luminance of each area of ​​the scene.

[0093] The calculation unit 512 determines the shutter speed, the aperture value, and the ISO sensitivity according to the calculated luminance distribution. The image sensor 400 may also serve as the photometry unit 503. The calculation unit 512 also executes various calculations for operating the image capture device 500. A part or the whole of the drive unit 502 may be mounted on the image sensor 400. A part of the system control unit 501 may be mounted on the image sensor 400.

[0094] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the claims that such modifications and improvements can also be included in the technical scope of the present invention.

[0095] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and may be realized in any order unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is explained using "first," "next," etc. for convenience, it does not mean that it is essential to perform the process in this order. [Explanation of symbols]

[0096] 10 exposure control unit, 20 pixel driving unit, 30 joint unit, 40 signal conversion unit, 42 AD converter, 50 signal output unit, 100 first substrate, 102 boundary surface, 104 photoelectric conversion unit, 110 pixel unit, 112 pixel, 120 pixel block, 121 load current source, 122 signal line, 123 transfer unit, 125 storage unit, 126 reset unit, 127 pixel output unit, 128 amplifier unit, 129 selection unit, 200 second substrate, 210, 212 processing circuit unit, 220, 222 processing block, 250, 252, 253, 255, 256, 257 connection wiring, 400 imaging element, 500 imaging device, 501 system control unit, 502 driving unit, 503 photometry unit, 504 work memory, 505 Recording unit, 506 display unit, 508 operation unit, 511 image processing unit, 512 calculation unit, 514 drive unit, 520 photographing lens

Claims

1. A first substrate on which pixel blocks are arranged in the row and column directions, the pixel blocks including a first photoelectric conversion unit that converts light into an electric charge and a second photoelectric conversion unit that converts light into an electric charge and is arranged in the row direction alongside the first photoelectric conversion unit; a second substrate, which is a substrate stacked on the first substrate, and in which processing blocks each including a plurality of conversion units for converting an analog signal into a digital signal are arranged side by side in the row direction and the column direction; Equipped with the processing block includes a first processing block arranged at a position overlapping a first pixel block among the pixel blocks in a stacking direction in which the first substrate and the second substrate are stacked, the first processing block includes a first conversion unit that converts a signal based on charges converted by the first photoelectric conversion unit of a second pixel block that is disposed at a position different from the first pixel block among the pixel blocks into a digital signal, and a second conversion unit that converts a signal based on charges converted by the second photoelectric conversion unit of the second pixel block into a digital signal; Image sensor.

2. The imaging element according to claim 1, the first processing block is disposed at a position not overlapping with the second pixel block in the stacking direction. Image sensor.

3. The imaging element according to claim 1 or 2, the processing block includes a second processing block disposed at a position overlapping with the second pixel block in the stacking direction; the second processing block includes a third conversion unit that converts a signal based on the charge converted by the first photoelectric conversion unit of the first pixel block into a digital signal, and a fourth conversion unit that converts a signal based on the charge converted by the second photoelectric conversion unit of the first pixel block into a digital signal. Image sensor.

4. The imaging element according to claim 3, the second processing block is disposed at a position not overlapping with the first pixel block in the stacking direction. Image sensor.

5. The imaging element according to any one of claims 1 to 4, the second pixel block is arranged alongside the first pixel block in the column direction; Image sensor.

6. The imaging element according to claim 5, the second pixel block is disposed adjacent to the first pixel block in the column direction. Image sensor.

7. The imaging element according to claim 1 or 2, the processing block includes a second processing block arranged at a position overlapping a third pixel block arranged at a position different from that of the second pixel block in the stacking direction, among the pixel blocks; the second processing block includes a third conversion unit that converts a signal based on the charge converted by the first photoelectric conversion unit of the third pixel block into a digital signal, and a fourth conversion unit that converts a signal based on the charge converted by the second photoelectric conversion unit of the third pixel block into a digital signal. Image sensor.

8. The imaging element according to claim 7, the second processing block is disposed at a position not overlapping with the first pixel block in the stacking direction. Image sensor.

9. The imaging element according to claim 7 or claim 8, the third pixel block is arranged alongside the first pixel block in the column direction; Image sensor.

10. The imaging element according to claim 9, the third pixel block is disposed adjacent to the first pixel block in the column direction. Image sensor.

11. The imaging element according to any one of claims 1 to 10, the first processing block includes a first exposure control unit that controls an accumulation time for accumulating the electric charge converted by the first photoelectric conversion unit of the first pixel block and an accumulation time for accumulating the electric charge converted by the second photoelectric conversion unit of the first pixel block. Image sensor.

12. The imaging element according to claim 11, the first pixel block includes a first transfer unit that transfers charges converted by the first photoelectric conversion unit of the first pixel block, and a second transfer unit that transfers charges converted by the second photoelectric conversion unit of the first pixel block, the first exposure control unit controls a timing at which the first transfer unit transfers electric charges from the first photoelectric conversion unit of the first pixel block and a timing at which the second transfer unit transfers electric charges from the second photoelectric conversion unit of the first pixel block. Image sensor.

13. The imaging element according to any one of claims 1 to 10, the first processing block includes a first exposure control unit that controls an exposure time of the first pixel block; Image sensor.

14. The imaging element according to claim 13, the first exposure control unit controls a timing to start exposure of the first pixel block; Image sensor.

15. The imaging element according to claim 13 or 14, the first exposure control unit controls a timing to end exposure of the first pixel block; Image sensor.

16. The imaging element according to any one of claims 1 to 15, An imaging element comprising a third substrate, which is stacked on the first substrate and performs image processing on a signal output from the second substrate.

17. The imaging element according to any one of claims 1 to 16, The second conversion unit is arranged next to the first conversion unit in the row direction. Image sensor.

18. An imaging device comprising an imaging element according to any one of claims 1 to 17.

19. The imaging device according to claim 18, An imaging device comprising a drive unit that drives a photographing lens that emits light to the imaging element.

20. In the imaging device according to claim 18 or claim 19, An imaging device comprising a generation unit electrically connected to the imaging element and configured to generate image data.

Images