Processing device and memory access method

Abstract

To output data to be read from a memory to an issue source according to an issue order of access requests even when receiving a plurality of memory access requests having different data read-out sizes.SOLUTION: A memory access controller includes an access control part for generating output start timing of data to be read from a memory to the outside in response to a memory access request, a plurality of buffers each holding the data to be read from the memory, and a buffer control part for making any of the plurality of buffers output data on the basis of the output start timing. The access control part delays output start timing of data from a buffer corresponding to a subsequent memory access request more than output start timing of data from a buffer corresponding to the preceding memory access request when receiving the subsequent memory access request during the execution of memory access corresponding to the preceding memory access request.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a processor and a memory access method. [Background technology]

[0002] A method is known in which an access request in a unit larger than the unit data length, which is the access unit of a main memory device, is divided into access requests equivalent to the unit data length, the unit data output from the main memory device is aligned in order, stored in a buffer, and responded to (see, for example, Patent Document 1).

[0003] A method is known for preventing reply buffer overflow by counting the number of times variable-length requests are sent from multiple requesters to a storage device and the number of times reply data is received from the storage device (see, for example, Patent Document 2). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. Hei 1-180663 [Patent Document 2] Japanese Patent Application Publication No. 10-307747 Summary of the Invention [Problem to be solved by the invention]

[0005] When a memory is accessed by a plurality of types of devices, the read size of data read from the memory in response to one memory access request may differ depending on the device. For example, a memory access controller that controls memory access may receive a memory access request with a large data read size followed by a memory access request with a small data read size. In this case, the order of issuing the memory access requests and the order of outputting response data read from the memory in response to the memory access requests to the device may be reversed. In this case, a response to the issuer of the read data corresponding to the preceding memory access request may be delayed, and the processing performance of the device that issues the preceding memory access request may be degraded.

[0006] In one aspect, the present invention has an object to output data read from a memory to an issuer in the order in which the access requests were issued, even when a plurality of memory access requests with different data read sizes are received. [Means for solving the problem]

[0007] According to one aspect, an arithmetic processing device has a memory access controller capable of controlling access to a memory based on a plurality of memory access requests having different data read sizes, wherein the memory access controller, when receiving a plurality of memory access requests, outputs read commands corresponding to the plurality of memory access requests to the memory at a timing that avoids conflicts in read data output from the memory, and has an access control unit that generates a timing to start outputting data read from the memory to the outside, a plurality of buffers that respectively hold data read from the memory corresponding to the read commands, and a buffer control unit that controls operation of the plurality of buffers and outputs data from one of the plurality of buffers based on the output start timing, and when a subsequent memory access request is received during execution of memory access corresponding to a preceding memory access request, the access control unit delays the timing to start outputting data from the buffer corresponding to the subsequent memory access request from a timing to start outputting data from the buffer corresponding to the preceding memory access request. Effect of the Invention

[0008] According to one aspect, even when a plurality of memory access requests with different data read sizes are received, the present invention can output data read from a memory to the issuer in the order in which the access requests were issued. [Brief description of the drawings]

[0009] [Figure 1] FIG. 2 is a block diagram illustrating an example of a processing device including a memory access controller according to an embodiment. [Diagram 2] 2 is a timing diagram showing an example of an operation of the memory access controller of FIG. 1. [Diagram 3] FIG. 11 is a block diagram showing an example of a processing device including a memory access controller according to another embodiment. [Figure 4]FIG. 4 is a block diagram illustrating an example of a memory access controller of FIG. 3. [Diagram 5] 5 is a block diagram showing an example of a scheduling unit in FIG. 4. [Figure 6] 6 is a timing diagram showing an example of the operation of the scheduling unit in FIG. 5. [Figure 7] FIG. 5 is a block diagram illustrating an example of stages in the request holding pipeline of FIG. [Figure 8] FIG. 5 is a block diagram showing an example of a processing unit in FIG. 4. [Figure 9] 5 is a block diagram showing an example of a buffer control unit and a data buffer shown in FIG. 4. [Figure 10] 5 is a timing diagram showing an example of read access to a memory by the memory access controller of FIG. 4. [Figure 11] 11 is a timing diagram showing an example of the operation of the buffer control unit and the data buffer during a read access to the memory. [Figure 12] FIG. 12 is a timing diagram showing an example of the operation of the memory access controller during the same period as FIG. [Figure 13] FIG. 12 is a timing diagram showing a continuation of FIG. [Figure 14] FIG. 13 is a timing diagram showing a continuation of FIG. [Figure 15] FIG. 14 is a timing diagram showing a continuation of FIG. [Figure 16] FIG. 15 is a timing diagram showing a continuation of FIG. [Figure 17] FIG. 16 is a timing diagram showing a continuation of FIG. [Figure 18] FIG. 17 is a timing diagram showing a continuation of FIG. [Figure 19] FIG. 11 is a timing diagram showing an example of an operation of another memory access controller. [Figure 20] FIG. 13 is a block diagram illustrating an example of a memory access controller in another embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, an embodiment will be described with reference to the drawings. In the following, the same reference numerals as the signal names are used for signal lines through which information such as signals is transmitted. In addition, a signal line shown as a single line in the drawings may be a multi-bit signal line.

[0011] Fig. 1 shows an example of a processing device including a memory access controller in one embodiment. The processing device 1 shown in Fig. 1 has a memory access controller 2. The memory access controller 2 can control access to a memory 6 based on a plurality of memory access requests MREQ having different data read sizes. For example, the data read size is the size of data DQ read from the memory 6 in response to one memory access request MREQ or the number of times data DQ is output.

[0012] The memory access controller 2 includes an access control unit 3, a buffer control unit 4, and a plurality of buffers 5 (5a, 5b). When the access control unit 3 receives a plurality of memory access requests MREQ, it outputs an access command to the memory 6. For example, the memory 6 may include a plurality of bank groups BG (BG0, BG1) that hold data.

[0013] In the following, an example will be described in which the memory access request MREQ is a read access request, and the access control unit 3 outputs a read command RD to the memory 6. If the memory 6 is a DRAM (Dynamic Random Access Memory), the access control unit 3 may output an active command ACT before outputting the read command RD.

[0014] The access control unit 3 outputs read commands RD corresponding to the multiple memory access requests MREQ to the memory 30 at timings that avoid contention between data DQ (read data) output from the memory 30 in response to the multiple memory access requests MREQ. The access control unit 3 outputs a data input timing signal DQIN to the buffer control unit 4 in accordance with the timing at which data DQ is output from the memory 6 in response to the read command RD.

[0015] The buffer control unit 4 outputs a write pointer value WP (WPa, WPb) to one of the buffers 5a, 5b based on the data input timing signal DQIN. The write pointer value WP indicates a storage position in the buffer 5 where the data DQ read from the memory 6 is stored. The buffers 5a, 5b store the data DQ read from the memory 6 in response to the read command RD for each memory access request MREQ. For example, each buffer 5 has a shift register structure (i.e., a FIFO (First-In First-Out) structure) that performs a shift operation when the held data DQ is output.

[0016] The access control unit 3 outputs an enable signal EN indicating the start timing of outputting the data DQ held in the buffer 5 to the outside to the buffer control unit 4 for each buffer 5 at the timing when a predetermined amount of data DQ is stored in the buffer 5. The buffer control unit 4 outputs a data shift signal DSFT (DSFTa, DSFTb) to the corresponding buffer 5 based on the enable signal EN. For example, the data shift signal DSFT is a pulse signal and includes pulses equal to the number of data DQ to be output from the buffer 5. The buffer 5 sequentially outputs the held data DQ as output data DOUT in response to the data shift signal DSFT.

[0017] Here, it is assumed that the access control unit 3 receives a subsequent memory access request MREQ while executing memory access corresponding to the preceding memory access request MREQ. In this case, the access control unit 3 outputs the enable signal EN corresponding to the subsequent memory access request MREQ after the enable signal EN corresponding to the preceding memory access request MREQ. That is, the access control unit 3 delays the output start timing of the output data DOUT from the buffer 5 corresponding to the subsequent memory access request MREQ from the output start timing of the output data DOUT from the buffer 5 corresponding to the preceding memory access request MREQ.

[0018] Fig. 2 shows an example of the operation of the memory access controller 2 of Fig. 1. That is, Fig. 2 shows an example of a memory access method by the memory access controller 2. In Fig. 2, the memory access controller 2 sequentially receives a memory access request MREQ0 for the bank group BG0 and a memory access request MREQ1 for the bank group BG1. The memory access controller 2 outputs an active command ACT0 corresponding to the memory access request MREQ0 to the memory 6, and then outputs an active command ACT1 corresponding to the memory access request MREQ1 to the memory 6.

[0019] Next, the memory access controller 2 outputs a plurality of read commands RD0 corresponding to the memory access request MREQ0 and a plurality of read commands RD1 corresponding to the memory access request MREQ1 to the memory 6. For example, the number of times data is output corresponding to the read size of the data of the memory access request MREQ0 is "16", and the number of times data is output corresponding to the read size of the data of the memory access request MREQ1 is "8". Furthermore, four data DQ are output from the memory 6 with one read command RD. Therefore, the memory access controller 2 outputs the read command RD0 four times (burst length="4") in response to the memory access request MREQ0, and outputs the read command RD1 twice in response to the memory access request MREQ1.

[0020] Data DQ0 (DQ00, DQ01, DQ02, DQ03) read from memory 6 in response to read command RD0 is stored sequentially in buffer 5a. Data DQ1 (DQ10, DQ11) read from memory 6 in response to read command RD1 is stored sequentially in buffer 5b. Each of data DQ00, DQ01, DQ02, DQ03, DQ10, DQ11 includes four pieces of data DQ.

[0021] The access control unit 3 outputs an enable signal EN0 to the buffer control unit 4 when a predetermined amount of data DQ0 is stored in the buffer 5a. After outputting the enable signal EN0, the access control unit 3 outputs an enable signal EN1 to the buffer control unit 4 when a predetermined amount of data DQ1 is stored in the buffer 5b.

[0022] The buffer control unit 4 controls the buffer 5a based on the enable signal EN0, and causes the data held in the buffer 5a to be output in sequence as output data DOUT, i.e. DQ00, DQ01, DQ02, and DQ03. When the buffer control unit 4 receives the enable signal EN1, the buffer 5a is outputting data DQ01, so the buffer control unit 4 suspends control over the output of data DQ10 from the buffer 5b.

[0023] Then, the buffer control unit 4 controls the buffer 5b in accordance with the timing of completion of output of the data DQ03 from the buffer 5a, and causes the data held in the buffer 5b to be output in sequence as the output data DQ10 and DQ11 as the output data DOUT. That is, the access control unit 3 delays the output start timing of the output data DOUT from the buffer 5 corresponding to the subsequent memory access request MREQ from the output start timing of the output data DOUT from the buffer 5 corresponding to the preceding memory access request MREQ. This allows the memory access controller 2 to output the data DQ in the order of receipt of the memory access requests MREQ even when reading the data DQ from the memory 30 in response to memory access requests MREQ of various data read sizes.

[0024] Note that the enable signal EN1 shown in brackets indicates an example of the timing of output after a predetermined period from the first read command RD1, regardless of the presence or absence of a preceding memory access request MREQ0. That is, the enable signal EN1 shown in brackets indicates an example in which the memory access controller 2 does not have the function of delaying the output timing of the enable signal EN1 depending on the presence or absence of a preceding memory access request MREQ0.

[0025] In this case, as indicated by the brackets, the data DQ1 corresponding to the memory access request MREQ1 is output before the data DQ0 corresponding to the memory access request MREQ0, i.e., the data DQ1 and DQ0 are output in the reverse order to the order in which the memory access requests MREQ were received.

[0026] As described above, in this embodiment, the memory access controller 2 can output data DQ output from the memory 6 in response to a plurality of memory access requests MREQ having different read sizes of data DQ to the device that issued the access requests MREQ in the order in which the access requests MREQ were issued. This makes it possible to suppress a delay in the response to the device of read data corresponding to a memory access request MREQ0 having a large read size issued before a memory access request MREQ1 having a small read size, for example. As a result, it is possible to suppress a decrease in the processing performance of the device that issued the memory access request MREQ due to the read size of the data of the other memory access requests MREQ.

[0027] When the output of data DQ corresponding to the following memory access request MREQ1 overlaps with the output of data DQ corresponding to the preceding memory access request MREQ0, the buffer control unit 4 delays the start of output of data DQ1 based on receipt of the enable signal EN1. This makes it possible to prevent the collision of data DQ0 and DQ1 from the two buffers 5a and 5b. As a result, it is possible to prevent erroneous data DQ (DOUT) from being output from the memory access controller 2.

[0028] Fig. 3 shows an example of a processing device including a memory access controller in another embodiment. The processing device 10 shown in Fig. 3 is, for example, a CPU (Central Processing Unit). Hereinafter, the processing device 10 is also referred to as a CPU 10.

[0029] The CPU 10 has multiple cores 12, a cache 14, a network control unit 16, an interconnect 18, and a memory access controller 20. Each core 12 executes instructions stored in the cache 14 and performs operations on data stored in the cache 14. Each core 12 is an example of an operation execution unit.

[0030] For example, the cache 14 is a Last Level Cache (LLC) and is commonly connected to the multiple cores 12. The cache 14 can store a portion of data and instructions stored in a memory 30 such as a main memory and a portion of data and instructions stored in a memory connected to another device. Although not limited thereto, the memory 30 is a Double Data Rate (DDR) 4-SDRAM.

[0031] The network control unit 16 interconnects the cache 14, the interconnect 18, and the memory access controller 20. The interconnect 18 is connected to other devices and executes communication with the other devices. Here, the other devices are external devices connected to the CPU 10. The other devices may be other CPUs 10 mounted in an information processing device (system) together with the CPU 10, or may be a DMAC (Direct Memory Access Controller) mounted in an information processing device together with the CPU 10. The interconnect 18 is an example of an interface unit connected to an external device.

[0032] The memory access controller 20 is connected to the memory 30 and controls access to the memory 30. For example, the memory access controller 20 controls access to the memory 30 based on a memory access request (MREQ in FIG. 4) issued from outside the CPU 10 via the core 12 or the interconnect 18.

[0033] When the memory access controller 20 receives memory access requests MREQ from inside and outside the CPU 10, the data read sizes (packet size PS, described later) may vary. As described later, the memory access controller 20 can read data from the memory 30 in response to a plurality of memory access requests MREQ having different data read sizes, and store the read data in a data buffer 280 (FIG. 4). Then, the memory access controller 20 can output the data stored in the data buffer 280 in the order in which the memory access requests MREQ are received.

[0034] For example, when the memory access request is a read access request, the memory access controller 20 performs read access to the memory 30 based on the read access request, and reads data stored in the memory 30. When the memory access request is a write access request, the memory access controller 20 performs write access to the memory 30 based on the write access request, and writes data to the memory 30.

[0035] For example, in response to one memory access request, the memory access controller 20 reads data of a read size included in the memory access request from the memory 30. The data read size may be different between the CPU 10 and another device such as a DMAC, or may be different for each group of the CPU 10.

[0036] The number of cores 12 mounted on the CPU 10 may be one. Also, the CPU 10 does not need to have the cache 14 and the network control unit 16. In that case, each core 12 is connected to a memory access controller 20.

[0037] Fig. 4 shows an example of the memory access controller 20 of Fig. 3. The memory access controller 20 has a request receiving unit 210, a scheduling unit 220, a request holding pipeline 230, a setting register 240, a plurality of processing units 25 (250, 251, 252), and a selector 260. The memory access controller 20 also has a buffer control unit 270 and a data buffer 280. The scheduling unit 220, the request holding pipeline 230, and the plurality of processing units 25 are an example of an access control unit.

[0038] The request receiving unit 210 outputs request information REQINF included in the memory access request MREQ received from the network control unit 16 (FIG. 3) to the scheduling unit 220. For example, the request information REQINF includes an operation type (write or read), a bank address, a row address, a column address, a valid flag, and a packet size PS. The request receiving unit 210 accepts a memory access request MREQ including a valid flag of a valid level, and does not accept a memory access request MREQ including a valid flag of an invalid level.

[0039] The scheduling unit 220 operates in synchronization with a memory clock MCLK, which is a clock supplied to the memory 30. The memory clock MCLK is supplied not only to the scheduling unit 220 but also to a clock synchronization circuit in the memory access controller 20. The scheduling unit 220 outputs the resource number NXTRSC and the shift signal SFTOUT0 to the request holding pipeline 230 together with the request information REQINF, based on the parallelism l, phase difference m, and average request interval n set in the setting register 240.

[0040] Furthermore, the scheduling unit 220 outputs the longest packet size MPS set in the setting register 240 to the request holding pipeline 230 by including it in the request information REQINF. For example, assume that the scheduling unit 220 receives other request information REQINF when a memory access corresponding to the request information REQINF is not being executed. In this case, the scheduling unit 220 outputs to the request holding pipeline 230 the request information REQINF by including individual request information REQALN indicating that a memory access request has been received independently.

[0041] The parallelism l indicates the parallelism of memory access and indicates the number of processing units 25 (250, 251, 252) that operate in parallel and control access to the memory 30. The parallelism l may be changed according to the operating frequency of the memory 30. In the following, the parallelism of memory access is described as being "2". The phase difference m indicates the minimum supply interval (the number of cycles of the memory clock MCLK) of the active command ACT supplied to the memory 30 and differs according to the parallelism l (the number of operating processing units 25).

[0042] The average request interval n indicates the average supply interval of active commands ACT (the number of cycles of the memory clock MCLK). The longest packet size MPS indicates the longest packet size PS among the packet sizes PS indicated by the memory access requests MREQ supplied to the memory access controller 20, and is set according to the specifications of the system in which the CPU 10 and memory 30 are mounted. The packet size PS indicates the size of the data DQ read from the memory 30 in response to one memory access request MREQ, or the number of times the data DQ is output. The longest packet size MPS is an example of the maximum data read size.

[0043] The resource number NXTRSC is a number that identifies the processing unit 25 that generates access commands such as the active command ACT and the read command RD, where "0" indicates the processing unit 250, "1" indicates the processing unit 251, and "2" indicates the processing unit 252. An example of the scheduling unit 220 is shown in FIG. 5, and examples of the active command ACT and the read command RD are shown in FIG. 10 and subsequent figures. For example, the active command ACT is output to the memory 30 to select one of a plurality of word lines included in the memory 30. The read command RD is output to the memory 30 to select a predetermined number of memory cells connected to the selected word line.

[0044] The request holding pipeline 230 has a plurality of (j+1 in this example) stages STG (STG0-STGj) connected in series and operating based on a shift signal SFTOUT0. "j" is an integer equal to or greater than 2, for example, "7". Each stage STG has a holding area for holding a resource number NXTRSC (hereinafter also simply referred to as a resource number RSC), an elapsed cycle CYC, and request information REQINF. For example, the elapsed cycle CYC is represented by the number of clock cycles of the memory clock MCLK. The shifting of information between adjacent stages STG is performed in synchronization with a shift input signal SFTIN described in FIG. 7.

[0045] The request holding pipeline 230 operates as a shift register that shifts the resource number RSC, the elapsed cycle CYC, and the memory access request REQINF from the first stage STG0 to the subsequent stages STG1-STGj at a timing according to the operation mode. However, the request holding pipeline 230 differs from a normal shift register in that the period (number of cycles) during which the stage STG holds information changes according to the parallelism 1 and the resource number RSC. An example of each stage STG of the request holding pipeline 230 is shown in FIG. 7.

[0046] The setting register 240 has registers in which the parallelism l, phase difference m, average request interval n, longest packet size MPS, row timing TROW, and column timing TCOL are set. For example, the parallelism l, phase difference m, average request interval n, longest packet size MPS, row timing TROW, and column timing TCOL are set in the setting register 240 according to the specifications of the memory 30, the CPU 10, and the like. For example, the setting in the setting register 240 is executed by an initialization program of the CPU 10. The parallelism l, phase difference m, and average request interval n are supplied to each processing unit 25 and the scheduling unit 220. The longest packet size MPS is supplied to the scheduling unit 220. The row timing TROW and column timing TCOL are supplied to each processing unit 25.

[0047] Each processing unit 25 (250, 251, 252) outputs a plurality of access commands to the memory 30 based on information including request information REQINF (memory access request) output from each stage STG of the request holding pipeline 230. The plurality of access commands are output to the memory 30 as a row control signal ROW and a column control signal COL. The row control signal ROW includes an active command ACT, a bank address, and a row address. The column control signal COL includes a read command RD (or a write command), a bank address, and a column address.

[0048] For example, each processing unit 25 outputs a row control signal ROW or a column control signal COL using the request information REQINF based on the elapsed cycle CYC output by the stage STG holding the resource number RSC indicating the processing unit 25. For example, when the parallelism l=2, the processing units 250 and 251 operate, and the processing unit 252 stops operating. When the parallelism l=3, the processing units 250, 251, and 252 operate.

[0049] Each processing unit 25 also has a data timing control unit 255 that generates a data input timing signal DQIN and an enable signal EN. The data timing control unit 255 generates the data input timing signal DQIN in accordance with the timing at which data DQ is output from the memory 30 in response to a read command RD. The data timing control unit 255 also generates an enable signal EN based on the fact that output of output data DOUT from the data buffer 290 is possible for each memory access request MREQ. The enable signal EN indicates the output start timing at which data DQ held in the data buffer 280 is output to the outside of the memory access controller 20.

[0050] Furthermore, the data timing control unit 255 may output the request information REQINF used for outputting the column control signal COL to the buffer control unit 270. The request information REQINF output to the buffer control unit 270 may be output from another element in the processing unit 25. An example of the processing unit 25 is shown in FIG.

[0051] The selector 260 selects the row control signal ROW and the column control signal COL output from each processing unit 25 and outputs them to the memory 30. The selector 260 may be designed using OR circuit logic.

[0052] The buffer control unit 270 executes control to store the data DQ read from the memory 30 in the data buffer 280 based on a data input timing signal DQIN. Also, the buffer control unit 270 executes control to output the data DQ held in the data buffer 280 as output data DOUT based on an enable signal EN. The data buffer 280 has a plurality of buffers that hold the data DQ read from the memory 30. Examples of the buffer control unit 270 and the data buffer 280 are shown in FIG. 9.

[0053] Fig. 5 shows an example of the scheduling unit 220 of Fig. 4. The scheduling unit 220 has a request information output unit 221, a resource number output unit 222, a clock counter 223, and a shift signal generation unit 224.

[0054] The request information output unit 221 sequentially holds the request information REQINF received from the request receiving unit 210 and the longest packet size MPS held in the setting register 240. The request information output unit 221 sequentially outputs the held information and single request information REQALN as request information REQINF to the request holding pipeline 230 in synchronization with the shift signal SFTOUT0.

[0055] The resource number output unit 222 sequentially generates and outputs resource numbers NXTRSC indicating the processing units 25 (250, 251, 252) that use the request information REQINF to generate access commands to be output to the memory 30. When the parallelism l=2, the resource number output unit 222 alternately outputs, for example, "0" and "1" indicating the processing units 250 and 251 as the resource numbers NXTRSC in synchronization with the shift signal SFTOUT0. When the parallelism l=3, the resource number output unit 222 alternately outputs "0", "1", and "2" indicating the processing units 250, 251, and 252 as the resource numbers NXTRSC in synchronization with the shift signal SFTOUT0.

[0056] This allows the resource number output unit 222 to operate as a counter that alternately generates resource numbers NXTRSC with "parallelism l-1" as the maximum value, and allows the total number of resource numbers NXTRSC to differ according to the parallelism l (operation mode). Since the resource numbers NXTRSC can be output alternately according to the parallelism l, the request holding pipeline 230 can operate regardless of the setting of the parallelism l. As a result, the memory access controller 20 can output an access command to the memory 30 at a timing according to the parallelism l.

[0057] The clock counter 223 generates a counter value CNT in synchronization with the memory clock MCLK, and outputs the generated counter value CNT to the shift signal generating unit 224. For example, the clock counter 223 increments the counter value CNT in synchronization with the memory clock MCLK while the shift signal SFTOUT0 is not being output. Also, the clock counter 223 resets the counter value CNT to "1" in response to the output of the shift signal SFTOUT0.

[0058] The shift signal generating unit 224 generates and outputs a shift signal SFTOUT0 at a time interval determined based on the resource number NXTRSC, the counter value CNT, the parallelism l, the phase difference m, and the average request interval n.

[0059] When parallelism l=2 and resource number NXTRSC=0, the shift signal generation unit 224 outputs a shift signal SFTOUT0 when the counter value CNT=m. When parallelism l=2 and resource number NXTRSC=1, the shift signal generation unit 224 outputs a shift signal SFTOUT0 when the counter value CNT="2n-m". When parallelism l=3, the shift signal generation unit 224 outputs a shift signal SFTOUT0 every time the counter value CNT becomes "n".

[0060] Fig. 6 shows an example of the operation of the scheduling unit 220 in Fig. 5. Fig. 6 shows an example where the parallelism l=2, the phase difference m=4, and the average request interval n=8.

[0061] When the parallelism l=2 and the resource number NXTRSC=0, the scheduling unit 220 outputs the shift signal SFTOUT0 based on the clock counter 223 counting "4." Also, when the parallelism l=2 and the resource number NXTRSC=1, the scheduling unit 220 outputs the shift signal SFTOUT0 based on the clock counter 223 counting "12."

[0062] The scheduling unit 220 can change the maximum value of the counter value CNT based on the parallelism l, phase difference m, and average request interval n set according to the specifications of the memory 30 connected to the CPU 10, and the current resource number NXTRSC. Then, the scheduling unit 220 can output the shift signal SFTOUT0 at a desired timing based on the counter value CNT whose maximum value is variable, and can update the resource number NXTRSC in accordance with the output of the shift signal SFTOUT0.

[0063] Fig. 7 shows an example of a stage STG of the request holding pipeline 230 of Fig. 4. Since each stage STG has the same configuration, Fig. 7 shows two stages (the k-1th stage and the kth stage (k is an integer between 1 and 8)). Each stage STG has a resource number holding unit 231, an elapsed cycle holding unit 232, a request information holding unit 233, and a shift signal generating unit 234.

[0064] The initial stage STG0 receives the resource number RSC, request information REQINF, and shift signal SFTOUT0 output from the scheduling unit 220 in Fig. 5. The stage STG0 receives the shift signal SFTOUT0 from the scheduling unit 220 as a shift input signal SFTIN. The elapsed cycle CYC supplied to the stage STG0 is an elapsed cycle accumulated from the time when the request information REQINF is received from the scheduling unit 220 as a reference (="0"), and is generated by a clock counter not shown. Moreover, the information input to the initial stage STG0 is not supplied to each processing unit 25.

[0065] While the resource number holding unit 231 receives a valid level (e.g., high level) shift input signal SFTIN at the enable terminal EN1, it takes in and holds the resource number RSC from the previous stage, and outputs the held resource number RSC to the subsequent stage STG and each processing unit 25. The second and subsequent stages STG operate by receiving the shift signal SFTOUT0 output by the previous stage STG as the shift input signal SFTIN. The resource number holding unit 231 of the first stage STG0 sequentially receives the resource number NXTRSC (repeated "0" and "1" when the parallelism l=2) output by the resource number output unit 222 of the scheduling unit 220 in FIG. 5.

[0066] The elapsed cycle holding unit 232 has a selector SEL, a flip-flop FF, and an incrementer INC. The selector SEL selects the elapsed cycle CYC from the previous stage while the shift input signal SFTIN is at a high level, and selects the elapsed cycle CYC from the incrementer INC while the shift input signal SFTIN is at a low level. Then, the selector SEL outputs the selected elapsed cycle CYC to the flip-flop FF.

[0067] The flip-flop FF captures the elapsed cycle CYC received from the selector SEL in synchronization with a memory clock MCLK (not shown), and outputs the captured elapsed cycle CYC to the incrementer INC. The incrementer INC increments the elapsed cycle CYC by "1," returns the incremented elapsed cycle CYC to the input of the selector SEL, and outputs it to the next stage STG and each processing unit 25.

[0068] The elapsed cycle holding unit 232 of each stage STG1-STG8 from the second stage onwards holds the elapsed cycle CYC (number of cycles) held by the elapsed cycle holding unit 232 of the previous stage STG in synchronization with the shift signal SFTOUT output by the previous stage STG. Also, the elapsed cycle holding unit 232 of each stage STG1-STGj sequentially updates the number of cycles held while the previous stage STG does not output the shift signal SFTOUT. This allows the elapsed cycle holding unit 232 of each stage STG to hold the number of cycles since the request information REQINF was received at the first stage STG0, and to output the held number of cycles to each processing unit 25. As a result, each processing unit 25 can determine the output timing of an access command to the memory 30 based on the number of cycles from each stage STG.

[0069] The shift signal generating unit 234 generates a shift signal SFTOUT based on the parallelism l, the phase difference m, the average request interval n, and the elapsed cycle CYC output by the elapsed cycle holding unit 232. The shift signal SFTOUT generated by the shift signal generating unit 234 is supplied to the next stage STG as a shift input signal SFTIN. In this manner, the shift signal generating unit 234 of each stage STG outputs the shift signal SFTOUT when the elapsed cycle CYC reaches a value determined by the parallelism l, the phase difference m, the average request interval n, and the position (=k) of the own stage STG.

[0070] When the parallelism l=2 and the resource number RSC held by the resource number holding unit 231 is "0", the shift signal generation unit 234 sets the shift signal SFTOUT to a valid level (e.g., high level) for one cycle period when the elapsed time is "k*n+m". The symbol * indicates a product. When the parallelism l=2 and the resource number RSC held by the resource number holding unit 231 is "1", the shift signal generation unit 234 sets the shift signal SFTOUT to a valid level for one cycle period when the elapsed time is "(k+1)*n". When the parallelism l=3 and the resource number RSC held by the resource number holding unit 231 is "1", the shift signal generation unit 234 sets the shift signal SFTOUT to a valid level for one cycle period when the elapsed time is "(k+1)*n".

[0071] That is, the shift signal generating unit 234 can change the output timing of the shift signal SFTOUT according to the parallelism l, phase difference m, and average request interval n preset according to the specifications of the memory 30, and the current resource number NXTRSC. As a result, even if the supply interval of the active command ACT is not constant, the output timing of the shift signal SFTOUT of each stage STG can be aligned, and malfunction of the request holding pipeline 230 can be suppressed.

[0072] For example, assume that the parallelism l=2, phase difference m=4, and average request interval n=8. In this case, the first stage STG0, which holds resource number RSC=0, outputs a shift signal SFTOUT four cycles after receiving request information REQINF. The second stage STG1, which holds resource number RSC=0, outputs a shift signal SFTOUT 12 cycles after receiving request information REQINF. The third stage STG2, which holds resource number RSC=0, outputs a shift signal SFTOUT 20 cycles after receiving request information REQINF.

[0073] Additionally, the first stage STG0, which holds resource number RSC=1, outputs a shift signal SFTOUT 8 cycles after receiving the request information REQINF. The second stage STG1, which holds resource number RSC=1, outputs a shift signal SFTOUT 16 cycles after receiving the request information REQINF. The third stage STG2, which holds resource number RSC=1, outputs a shift signal SFTOUT 24 cycles after receiving the request information REQINF.

[0074] On the other hand, assume that the degree of parallelism l=3, the phase difference m=8, and the average request interval n=8. In this case, the first stage STG0 outputs the shift signal SFTOUT 8 cycles after receiving the request information REQINF. The second stage STG1 outputs the shift signal SFTOUT 16 cycles after receiving the request information REQINF. The third stage STG2 outputs the shift signal SFTOUT 24 cycles after receiving the request information REQINF.

[0075] The request information holding unit 233 receives and holds the request information REQINF from the previous stage while receiving the shift input signal SFTIN at a valid level at the enable terminal EN1. The request information holding unit 233 outputs the received request information REQINF to the next stage STG and each processing unit 25. The request information holding unit 233 of the first stage STG0 receives the request information REQINF output by the request information output unit 221 of the scheduling unit 220.

[0076] Fig. 8 shows an example of the processing unit 25 (250, 251, 252) in Fig. 4. In Fig. 8, it is assumed that the request holding pipeline 230 has nine stages STG0-STG8. Each processing unit 25 has, in addition to the data timing control unit 255, a row control unit 253 having a selector 2531 and a row information output unit 2532, and a column control unit 254 having a selector 2541, a column information output unit 2542, and a counter 2543.

[0077] The selector 2531 receives the resource number RSC, the elapsed cycle CYC, and the request information REQINF from each stage STG0-STG8 of the request holding pipeline 230. The selector 2531 also receives the row timing TROW and the degree of parallelism 1 from the setting register 240.

[0078] The selector 2531 selects the request information REQINF output from the stage STG that outputs the resource number RSC that matches the own resource number, which is the identification number of the own processing unit 25, and the elapsed cycle CYC that matches the cycle indicated by the row timing TROW. Then, the selector 2531 outputs the selected request information REQINF to the row information output unit 2532. In response to the request information REQINF received from the selector 2531, the row information output unit 2532 generates a row control signal ROW using the request information REQINF, and outputs it to the memory 30.

[0079] The selector 2541 receives the resource number RSC, the elapsed cycle CYC, and the request information REQINF from each stage STG0-STG8 of the request holding pipeline 230. The selector 2541 also receives the column timing TCOL and the degree of parallelism 1 from the setting register 240.

[0080] The selector 2541 selects the request information REQINF output from the stage STG that outputs the resource number RSC that coincides with the own resource number, which is the identification number of the own processing unit 25, and the elapsed cycle CYC that coincides with the cycle indicated by the column timing TCOL. Then, the selector 2541 outputs the selected request information REQINF to the column information output unit 2542. The counter 2543 counts the number of times the column control signal COL is output. In response to the request information REQINF received from the selector 2541, the column information output unit 2542 generates a column control signal COL using the request information REQINF and outputs it to the memory 30. At this time, the column information output unit 2542 outputs the column control signal COL the number of times counted by the counter 2543 every time a predetermined number of cycles elapse.

[0081] In this way, each processing unit 25 receives the resource number RSC, the elapsed cycle CYC, and the request information REQINF held by the multiple stages STG of the request holding pipeline 230. Then, when the received resource number RSC matches its own resource number, each processing unit 25 outputs an access command (such as an active command ACT or a read command RD) corresponding to the received request information REQINF to the memory 30. In other words, when the number of cycles indicated by the elapsed cycle CYC held by the stage STG that outputs its own resource number RSC indicates the output cycle of the access command determined according to the parallelism degree l, each processing unit 25 outputs the corresponding access command to the memory 30. Therefore, even when the output cycle of the access command is changed according to the parallelism degree l, the access command can be output to the memory 30 at the correct timing based on the parallelism degree l, the resource number RSC, and the elapsed cycle CYC.

[0082] The data timing control unit 255 receives request information REQINF output from a stage STG that outputs a resource number RSC that matches its own resource number and an elapsed cycle CYC that matches the cycle indicated by the column timing TCOL. The request information REQINF includes independent request information REQALN. The data timing control unit 255 generates a data input timing signal DQIN and an enable signal EN based on the received information. In addition, the data timing control unit 255 outputs the request information REQINF used to output the column control signal COL as described in FIG. 4.

[0083] The data input timing signal DQIN and the enable signal EN may include identification information for identifying which memory access request MREQ (read access request) they correspond to. In this case, the identification information may be a sequence number. The generation timing of the write pointer value WP and the generation timing of the enable signal EN based on the data input timing signal DQIN are described in FIG. 13, FIG. 15, etc.

[0084] Moreover, the memory access controller 20 controls access to the memory 30 based on the parallelism l, phase difference m, and average request interval n set in the setting register 240. For example, the parallelism l is "2" or "3". Since the parallelism l, phase difference m, and average request interval n are variable, the control circuit for memory access becomes complicated as shown in FIG. 5, FIG. 7, and FIG. 8. However, the control circuit shown in FIG. 5, FIG. 7, and FIG. 8 is an example, and the memory access controller 20 may have other control circuits. For example, when the parallelism l is limited to 2, the phase difference m is limited to 4, and the average request interval n is limited to 8, the output timing of the shift signal SFTOUT0 is fixed as shown in FIG. 6. Therefore, the control circuit for memory access can be simplified compared to FIG. 5, FIG. 7, and FIG. 8.

[0085] Examples of the timing of the active command ACT and the read command RD issued by the memory access controller 20 to the memory 30 are described in Figures 9 to 17 of Japanese Patent Application No. 2020-097826.

[0086] Fig. 9 shows an example of the buffer control unit 270 and the data buffer 280 of Fig. 4. Examples of the operations of the buffer control unit 270 and the data buffer 280 are described in Fig. 11-Fig. 18. The buffer control unit 270 has a data output control unit DQCNTL, a buffer selector BSEL, a counter CONT (CONT0, CONT1), and a selector SEL (SEL0, SEL1, SEL2). The buffer control unit 270 also has an OR circuit OR, a selection signal generation unit SELGEN, and an output timing generation unit OTGEN.

[0087] The data buffer 280 has buffers BUF (BUF0, BUF1, BUF2). Each of the buffers BUF0-BUF2 has p+1 entries that hold data DQ read from the memory 30, and writes the data DQ to an entry designated by a write pointer value WP. Each of the buffers BUF0-BUF2 has a shift register structure. In this example, "p" is an integer equal to or greater than "3."

[0088] The data output control unit DQCNTL outputs a write selection signal BWSEL indicating one of the buffers BUF0-BUF2 to the buffer selector BSEL in response to a data input timing signal DQIN from the data timing control unit 255 of each processing unit 25. Also, the data output control unit DQCNTL outputs a count-up signal CUP to one of the counters CONT0, CONT1 in response to the data input timing signal DQIN. Furthermore, the data output control unit DQCNTL outputs a count-down signal CDWN to the counter CONT0 (or CONT1) according to a predetermined condition that is set in advance. The data output control unit DQCNTL is an example of a counter control unit that counts up or down each of the counters CONT0, CONT1.

[0089] The predetermined condition is when the output of the data DQ held in the buffer BUF starts before the write pointer value WP0 (or WP1) of the counter CONT0 (or CONT1) reaches the maximum value corresponding to the packet size PS. For example, the data output control unit DQCNTL may determine the timing of generating the countdown signal CDWN based on the request information REQINF received from the data timing control unit 255 of FIG. 8.

[0090] For the buffer BUF having a shift register structure, the data output control unit DQCNTL counts down the counter CONT when outputting data DQ from the buffer BUF. This allows the data DQ to be stored in the correct position even if the storage position of new data DQ is shifted due to the shift operation of the buffer BUF.

[0091] Furthermore, the data output control unit DQCNTL stops counting up and down of the counter CONT when storing data DQ in the buffer BUF and outputting data DQ from the buffer BUF at the same time. This allows new data DQ to be stored at the same position in the buffer BUF regardless of the shift operation of the buffer BUF. In other words, new data DQ can be stored at the correct position even when storing data DQ in the buffer BUF and outputting data DQ from the buffer BUF at the same time.

[0092] When the data output control unit DQCNTL receives a data input timing signal DQIN in an idle state in which no access to the memory 30 is being performed, it outputs a write selection signal BWSEL of "0." Furthermore, in the idle state, the data output control unit DQCNTL outputs a count-up signal CUP to the counter CONT0. After that, when the data output control unit DQCNTL receives a data input timing signal DQIN corresponding to a different memory access request MREQ, it outputs the count-up signal CUP to the counter CONT1.

[0093] The data output control unit DQCNTL can determine the idle state based on the independent request information REQALN included in the request information REQINF, which indicates that the memory access request MREQ has been received alone. Also, the data output control unit DQCNTL can determine that the data output control unit DQCNTL is not in the idle state when the independent request information REQALN is not included in the request information REQINF.

[0094] The data output control unit DQCNTL outputs a predetermined number (for example, "4") of count-up signals CUP to the same counter CONT every time it receives a data input timing signal DQIN corresponding to the same memory access request MREQ. Also, every time the processing unit 25 that outputs the data input timing signal DQIN changes, the data output control unit DQCNTL switches the counter CONT that outputs the count-up signal CUP in order to alternately use the counters CONT0 and CONT1.

[0095] The buffer selector BSEL has three holding units BSEL0, BSEL1, and BSEL2, each of which holds a buffer selection value that identifies a buffer BUF to be selected. The buffer selection values ​​held in the holding units BSEL0-BSEL2 are output to the selectors SEL0-SEL2 in response to a data input timing signal DQIN from the data timing control unit 255 of each processing unit 25. Hereinafter, the buffer selection values ​​held in the holding units BSEL0-BSEL2, respectively, are also referred to as buffer selection values ​​BSEL0-BSEL2.

[0096] The buffer selector BSEL uses the holding units BSEL0, BSEL1, and BSEL2 in ascending order of numbers. For example, when the buffer selector BSEL receives a write selection signal BWSEL of "0" in the idle state, it holds the received "0" in the holding unit BSEL0, which has the highest priority. When the buffer selector BSEL receives a write selection signal BWSEL of "1" in this state, it holds the received "1" in the holding unit BSEL1, which has the next highest priority. When the buffer selector BSEL further receives a write selection signal BWSEL of "2" in this state, it holds the received "2" in the holding unit BSEL2, which has the lowest priority.

[0097] The buffer selector BSEL outputs the buffer selection value held in the holding unit BSEL0 to the selection signal generation unit SELGEN. Then, the buffer selector BSEL moves the buffer selection values ​​held in the holding units BSEL1 and BSEL2 to the holding units BSEL0 and BSEL1, which have one lower priority, based on the shift signal SFT.

[0098] The counter CONT0 increments the write pointer value WP0 by "1" in response to the count-up signal CUP, and decrements the write pointer value WP0 by "1" in response to the count-down signal CDWN. The counter CONT1 increments the write pointer value WP1 by "1" in response to the count-up signal CUP, and decrements the write pointer value WP1 by "1" in response to the count-down signal CDWN.

[0099] The selectors SEL0-SEL2 are disposed between the counters CONT0, CONT1 and the buffers BUF0-BU2. The selector SEL0 outputs either the write pointer value WP0 or WP1 to the buffer BUF0 as the write pointer value WP based on the output of a write selection signal BWSEL of "0" from the data output control unit DQCNTL. The selector SEL1 outputs either the write pointer value WP0 or WP1 to the buffer BUF1 as the write pointer value WP based on the output of a write selection signal BWSEL of "1" from the data output control unit DQCNTL.

[0100] The selector SEL2 outputs either the write pointer value WP0 or WP1 to the buffer BUF2 as the write pointer value WP based on the output of the write selection signal BWSEL of "2" from the data output control unit DQCNTL. As described above, after the counter CONT0 is used in the idle state, the counters CONT1 and CONT0 are used alternately each time the processing unit 25 that outputs the data input timing signal DQIN is changed. Then, each selector SEL continues to select the initially selected write pointer value WP until the number of data DQ corresponding to the packet size PS included in the memory access request MREQ is stored in the corresponding buffer BUF. For example, each selector SEL detects the packet size PS based on the request information REQINF.

[0101] By disposing the selectors SEL0-SEL2 between the counters CONT0, CONT1 and the buffers BUF0-BUF2, the write pointer value WP generated by any counter CONT can be supplied to any buffer BUF. As a result, the number of counters CONT can be made smaller than the number of buffers BUF, and the circuit scale of the memory access controller 20 can be reduced compared to the case where the same number of counters CONT as the number of buffers BUF are provided.

[0102] The OR circuit OR outputs the enable signal EN from the data timing control unit 255 of each processing unit 25 as a response enable signal RETEN to the selection signal generation unit SELGEN. When the selection signal generation unit SELGEN receives the response enable signal RETEN, it outputs the buffer selection value held in the holding unit BSEL0 to the output timing generation unit OTGEN as a read selection signal BRSEL. The read selection signal BRSEL indicates the buffer BUF that holds the data DQ read from the memory 30 in response to the memory access request MREQ.

[0103] The output timing generation unit OTGEN decodes the read selection signal BRSEL from the selection signal generation unit SELGEN and selects a buffer BUF indicated by the value of the read selection signal BRSEL. The output timing generation unit OTGEN outputs a data shift signal DSFT to the selected buffer BUF. Here, the output timing generation unit OTGEN continuously outputs a data shift signal DSFT having pulses for the number of data indicated by the packet size PS included in the memory access request MREQ. Note that if the memory 30 is a DDR type, the pulse of the data shift signal DSFT is output twice per cycle of the memory clock MCLK.

[0104] In response to the shift signal DSFT, each of the buffers BUF0-BUF2 shifts the data DQ held therein from an entry with a larger numerical value to an entry with a smaller numerical value. Then, each of the buffers BUF0-BUF2 outputs the data DQ extracted from the "0" entry as output data DOUT to a common output data line DOUT. The buffer control unit 270 generates the shift signal DSFT so that the output data DOUT output from the buffers BUF0-BUF2 do not collide on the output data line DOUT.

[0105] Fig. 10 shows an example of read access to the memory 30 by the memory access controller 20 of Fig. 4. Fig. 10 shows an example of operation when the parallelism l is set to 2, the phase difference m is set to 4, and the average request interval n is set to 8. The row control signal ROW0 and the column control signal COL0 are output from the processing unit 250, and the row control signal ROW1 and the column control signal COL1 are output from the processing unit 251. The memory 30 has two bank groups BG0 and BG1. In Fig. 10, the sequentially increasing numerical values ​​indicate the elapsed cycle CYC (the accumulated value of the number of cycles of the memory clock MCLK).

[0106] First, the processing unit 250 outputs an active command ACT0 to the bank group BG0 in CYC1. For example, the active command ACT is supplied to the memory 30 using two clock cycles. The processing unit 251 outputs an active command ACT1 to the bank group BG1 in CYC5, which is tRRDS (RAS to RAS Delay) after the processing unit 250 outputs the active command ACT0. tRRDS is a specification of the minimum interval between active commands ACT between different bank groups BG.

[0107] The processing unit 250 outputs the first read command RD0 to the bank group BG0 in CYC16, which is tRCDRD (RAS to CAS Delay) after outputting the active command ACT0. The processing unit 250 outputs the second read command RD0 to the bank group BG0 in CYC20, which is tCCDL (CAS to CAS Delay Long) after outputting the read command RD0. tCCDL is a specification for the minimum interval between column system commands (such as the read command RD) between the same bank group BG.

[0108] The processing unit 251 outputs the first read command RD1 to the bank group BG1 in CYC22, which is tCCDS (CAS to CAS Delay Short) after the processing unit 250 outputs the read command RD0. tCCDS is a specification for the minimum interval between column-related commands between different bank groups BG.

[0109] Thereafter, the processing units 250 and 251 alternately output the read command RD (RD0 or RD1) every two cycles. The output interval of the read command RD by each of the processing units 250 and 251 is four cycles.

[0110] After the processing unit 250 outputs the first read command RD0, and after a cycle corresponding to the read latency RL, the first read data D0 corresponding to the first read command RD0 is output from the bank group BG0. In this example, since the burst length is set to "4", four data are read out in synchronization with the rising edge and the falling edge of the memory clock MCLK, respectively. Furthermore, after the read latency RL has elapsed from each read command RD, the read data D (D0 or D1) is read out from each bank group BG.

[0111] 10 is realized by the scheduling unit 220 that outputs the shift signal SFTOUT0 in accordance with the parallelism l=2, the phase difference m=4, and the average request interval n=8, and the request holding pipeline 230 that executes the shift operation of the stage STG. This allows the memory access controller 20 to execute a read access operation with a parallelism l=2 by using information that is sequentially transferred to the stage STG of the request holding pipeline 230 that is common to a plurality of parallelism l.

[0112] 11 to 18 show an example of the operation of the buffer control unit 270 and the data buffer 280 during read access to the memory 30. That is, Fig. 11 to 18 show an example of a memory access method by the memory access controller 20. Detailed description of the same operations as those in Fig. 10 will be omitted.

[0113] 11 to 18 are executed with the parallelism l set to 2, the phase difference m set to 4, and the average request interval n set to 8, as in the case of Fig. 10. The maximum packet size MPS is set to "32" which means that data DQ is read 32 times from the memory 30 in response to one memory access request MREQ.

[0114] 11 and 12 show operations in the same cycle period, and Figs. 13 and 14 show operations in the same cycle period. Figs. 15 and 16 show operations in the same cycle period, and Figs. 17 and 18 show operations in the same cycle period. Below, cycles CYC1-CYC74, which are the number of elapsed cycles of the memory clock MCLK, are explained using only symbols. The packet size PS of the memory access request MREQ that is the source of the active command ACT0 is "32", and the packet size PS of the memory access request MREQ that is the source of the active command ACT1 is "16".

[0115] Access to the memory 30 up to CYC37 is the same as in Fig. 10. For example, in Fig. 11 to Fig. 18, the processing unit 250 of the memory access controller 20 outputs the first read command RD0 in CYC16, and outputs the subsequent read command RD0 seven times every four cycles. The processing unit 251 of the memory access controller 20 outputs the first read command RD1 in CYC22, and outputs the subsequent read command RD1 three times every four cycles.

[0116] 13, the processing unit 251 outputs the first read command RD2 of the access of the second packet size PS corresponding to the active command ACT1, and outputs the subsequent read command RD2 three times every four cycles. The first read command RD2 of the second access is issued four cycles after the fourth read command RD1.

[0117] The processing unit 250 outputs the first read command RD3 of the third access with packet size PS corresponding to the active command ACT1 in CYC48 of Fig. 15, and outputs the subsequent read command RD3 seven times every four cycles. The first read command RD2 of the second access is issued four cycles after the fourth read command RD1. The processing unit 251 outputs the first read command RD4 in CYC54, and outputs the subsequent read command RD4 seven times every four cycles.

[0118] When the memory access controller 20 outputs the active command ACT0, it is not executing any access to the memory 30 by another active command ACT, and at the start of Fig. 11, the memory 30 is in an idle state where it is not operating. That is, the memory access controller 20 receives only the memory access request MREQ which triggers the active command ACT0. As described above, the idle state is determined based on the single request information REQALN included in the request information REQINF.

[0119] When the memory 30 is in an idle state, the data output control unit DQCNTL of Fig. 9 outputs a write selection signal BWSEL of "0" in CYC21 of Fig. 11 based on reception of a data input timing signal DQIN from the processing unit 250 that issued the active command ACT0. The write selection signal BWSEL of "0" indicates that the data DQ read from the memory 30 is to be stored in the buffer BUF0. The processing unit 250 outputs a data input timing signal DQIN (not shown) in accordance with the output timing of four consecutive data DQ from the memory 30 (for example, CYC21, CYC22).

[0120] The data output control unit DQCNTL outputs a count-up signal CUP to the counter CONT0 based on the data input timing signal DQIN from the processing unit 250. In response to the count-up signal CUP, the counter CONT0 increments the write pointer value WP0 by "1" in synchronization with the output timing of the data DQ. The initial values ​​of the write pointer values ​​WP0 and WP1 output by the counters CONT0 and CONT1, respectively, are "0".

[0121] 9, in CYC21, the buffer selector BSEL holds the write selection signal BSSEL at "0" in the holding unit BSEL0, which has the highest priority. The selector SEL0 is selected by the "0" held in the holding unit BSEL0, and the write pointer value WP0 is supplied to the buffer BUF0 via the selector SEL0. The buffer BUF0 then writes data DQ0-DQ31 corresponding to the read command RD0 sequentially to the entry indicated by the write pointer value WP0 over CYC21-CYC51.

[0122] 13, in response to the second read command RD0 in FIG. 11, data DQ4-DQ7 are sequentially read from memory 30 at CYC25 and CYC26. After that, four data DQ are alternately read from memory in response to read commands RD1 and RD0. To read 32 pieces of data DQ0-DQ31 corresponding to the packet size PS from memory 30, read command RD0 is issued eight times. To read 16 pieces of data DQ0-DQ15 corresponding to the packet size PS from memory 30, read command RD1 is issued four times.

[0123] The data output control unit DQCNTL outputs a write selection signal BWSEL of "0" based on reception of the data input timing signal DQIN from the processing unit 250. The data output control unit DQCNTL also outputs a write selection signal BWSEL of "1" based on reception of the data input timing signal DQIN from the processing unit 251. The write selection signal BWSEL of "1" indicates that the data DQ read from the memory 30 is to be stored in the buffer BUF1.

[0124] 11 to 18, the numbers "0" to "24" attached to each of the buffers BUF0 to BUF2 indicate entry numbers. On the timing diagrams, the numbers attached to the entries of each of the buffers BUF0 to BUF2 indicate the numbers of the data DQ held by each entry.

[0125] The data output control unit DQCNTL outputs a count-up signal CUP to each of the counters CONT0, CONT1 based on a data input timing signal DQIN from each of the processing units 250, 251. Each count-up signal CUP is output in synchronization with the reception timing of the data DQ from the memory 30. As a result, each of the counters CONT0, CONT1 increments each of the write pointer values ​​WP0, WP1 by "1".

[0126] 11 and 13, the holding unit BSEL0 holds "0" until data DQ15 is stored in the buffer BUF0. Therefore, the buffer BUF0, which receives the write pointer value WP0 via the selector SEL0, sequentially writes the data DQ corresponding to the read command RD0 to the entry indicated by the write pointer value WP0.

[0127] 13, in response to the first reception of the write selection signal BWSEL of "1", the buffer selector BSEL holds the write selection signal BSSEL of "1" in the holding unit BSEL1 having the highest priority among the available holding units BSEL. The selector SEL1 is selected by the "1" held in the holding unit BSEL1, and the write pointer value WP1 is supplied to the buffer BUF1.

[0128] The holding unit BSEL1 holds "1" during CYC27-CYC35, and the selector SEL1 is selected by the holding unit BSEL1 of "1." Therefore, during CYC27-CYC35, the buffer BUF1 that receives the write pointer value WP1 via the selector SEL1 sequentially writes the data DQ corresponding to the read command RD1 to the entry indicated by the write pointer value WP0.

[0129] The data timing control unit 255 of the processing unit 250 that has output the active command ACT0 generates an enable signal EN (RD0) in CYC35 of FIG. 13. In this example, the data timing control unit 255 generates the enable signal EN (RD0) 18 cycles (CYC35) after the output of the first read command RD0. The 18 cycles are calculated by subtracting 16 cycles required for the output of 32 pieces of output data DOUT from the 34 cycles required from the output of the first read command RD0 to the completion of the output of the output data DOUT. By outputting the enable signal EN corresponding to the read command RD0 in CYC35, the data DQ31 can be output as output data DOUT from the buffer BUF0 to CYC51 where the data DQ31 is held in the buffer BUF0.

[0130] The selection signal generation unit SELGEN, which receives the enable signal EN from the processing unit 250 as the response enable signal RETEN, outputs the buffer selection value "0" held in the holding unit BSEL0 as the read selection signal BRSEL in CYC35 of Fig. 14. The output timing generation unit OTGEN of Fig. 9 sequentially outputs the data shift signal DSFT to the buffer BUF0 based on the read selection signal BRSEL of "0". As a result, the memory access controller 20 applies CYC34-CYC51 to the data DQ0-DQ31 held in the buffer BUF0 and outputs them as output data DOUT to the network control unit 16 of Fig. 3 in succession (Figs. 14 and 16).

[0131] The selection signal generation unit SELGEN outputs a shift signal SFT to the buffer selector BSEL in response to the output of the read selection signal BRSEL of "0". The buffer selector BSEL performs a shift operation in response to the shift signal SFT, and transfers the buffer selection value "1" held in the holding unit BSEL1 to the holding unit BSEL0 in CYC36 of Fig. 13. This determines that after the output data DOUT from the buffer BUF0 is output, the output data DOUT is output from the buffer BUF1.

[0132] The holding unit BSEL0 holds "1" during CYC36-CYC51, and the selector SEL1 continues to be selected by the holding unit BSEL1 holding "1." During CYC36-CYC41, the buffer BUF1 that receives the write pointer value WP1 via the selector SEL1 sequentially writes the data DQ corresponding to the read command RD1 to the entry indicated by the write pointer value WP0.

[0133] The data output control unit DQCNTL outputs a countdown signal CDWN in synchronization with the timing at which data DQ is output from the buffer BUF0. As a result, the write pointer value WP0 is decremented by "1" from CYC36 in FIG. 13. However, if the output of data DQ from the buffer BUF0 and the storage of data DQ read from the memory 30 in the buffer BUF0 are executed simultaneously, the data output control unit DQCNTL stops the output of the countdown signal CDWN and the countup signal CUP. Therefore, for example, in CYC37, CYC38, and the first half of CYC39, data DQ15-DQ19 are sequentially stored in the entry indicated by the write pointer value WP0="12" in the buffer BUF0.

[0134] 15, the data timing control unit 255 of the processing unit 251 that outputs the read command RD1 generates an enable signal EN (RD1). In this example, the data timing control unit 255 generates the enable signal EN 18 cycles after the output of the first read command RD1. The 18 cycles are calculated by subtracting 8 cycles required for the output of 16 pieces of output data DOUT from the 18 cycles from the output of the first read command RD1 to the completion of the output of the output data DOUT, and then adding another 8 cycles.

[0135] 11, when the memory access controller 20 issues an active command ACT1, it issues another active command ACT0 to the memory 30. Therefore, the memory 30 is not in an idle state. If the memory 30 is not in an idle state, eight cycles are added so that the output data DOUT corresponding to the active command ACT1 is output after the output data DOUT corresponding to the preceding active command ACT0 is output.

[0136] Here, 18 cycles is equal to the period from the first read command to the output of the enable signal EN in a memory access request MREQ of the longest packet size MPS among the memory access requests MREQ that can be accepted by the memory access controller 20. That is, when the memory 30 is not in an idle state, the data timing control unit 255 sets the output start timing of data corresponding to the subsequent memory access request MREQ to the output start timing when a memory access request of the longest packet size MPS is received. For example, in this embodiment, the longest packet size MPS corresponds to 32 pieces of data DQ.

[0137] This makes it possible to keep constant the period from the first read command RD to the output start timing of the data DQ, regardless of the packet size PS of the memory access request MREQ. Therefore, the output control of the enable signal EN by the data timing control unit 255 can be simplified compared to the case where the output start timing is set according to the packet size PS of the preceding memory access request MREQ. Note that the data timing control unit 255 may set the output timing (i.e., the output start timing) of the enable signal EN according to the packet size PS of the preceding memory access request MREQ.

[0138] If no other active command ACT is issued when the active command ACT1 is issued and the memory 30 is in an idle state, the data timing control section 255 generates the enable signal EN 10 cycles after the output of the first read command RD1. The 10 cycles are the output timing of the enable signal EN that is set according to the access specifications (e.g., packet size PS=16 pieces of data DQ) of the device that issues the memory access request MREQ (ACT1). This allows the memory access controller 20 to output the data DOUT corresponding to the memory access request MREQ to the device that issued the memory access request MREQ at the shortest possible timing.

[0139] 15, the selection signal generation unit SELGEN receives the enable signal EN (RD1) from the processing unit 251 as the response enable signal RETEN. Since data DQ is being output from the buffer BUF0, the selection signal generation unit SELGEN inhibits the output of data DQ in response to the response enable signal RETEN with a buffer selection value="1" held in the holding unit BSEL1.

[0140] That is, the selection signal generating unit SELGEN sets the output start timing of the subsequent data DOUT so that the data DOUT of the subsequent memory access request MREQ is not output earlier than the final data DOUT corresponding to the preceding memory access request MREQ. This makes it possible to prevent the outputs of the data DQ from the buffers BUF0 and BUF1 from colliding with each other, thereby making it possible to prevent malfunction of the memory access controller 20.

[0141] In response to the first reception of a write selection signal BWSEL of "2" in CYC43 of Fig. 15, the buffer selector BSEL stores the write selection signal BWSEL of "2" in the storage unit BSEL1, which has the highest priority among the available storage units BSEL. The selector SEL2 is selected by the "2" stored in the storage unit BSEL1, and the write pointer value WP1 is supplied to the buffer BUF2. The buffer BUF2 then writes the data DQ corresponding to the read command RD2 to the entries indicated by the sequentially increasing write pointer values ​​WP1, sequentially from CYC43 of Fig. 16.

[0142] The data output control unit DQCNTL determines whether to use the write pointer value WP0 or WP1. After the idle state of the memory 30 is released, the data output control unit DQCNTL determines to use the write pointer value WP0, and then sequentially determines to use an available write pointer value WP.

[0143] In CYC51, the selection signal generator SELGEN reads out the buffer selection value "1" held in the holding unit BSEL0 in accordance with the completion of output of the data DQ31 from the buffer BUF0, and outputs it as the selection signal BRSEL (FIG. 16). The output timing generator OTGEN sequentially outputs the data shift signal DSFT to the buffer BUF1 based on the read selection signal BRSEL of "1". As a result, the memory access controller 20 sequentially outputs the data DQ0-DQ15 held in the buffer BUF1 as output data DOUT to the network control unit 16 in FIG. 3 through CYC51-CYC59 (FIGS. 16 and 18).

[0144] In this way, when the memory 30 is not in an idle state, the memory access controller 20 can output the output data DOUT in the order in which the memory access requests MREQ are issued by delaying the output of the output data DOUT corresponding to the active command ACT. This makes it possible to suppress delays in data processing by the device that issued the memory access request MREQ due to delays in the output data DOUT. As a result, it is possible to suppress a decrease in the processing performance of the device that receives the output data DOUT, which is dependent on the operation of the memory access controller 20 that can process memory access requests MREQ of multiple packet sizes PS.

[0145] When the data DQ is output from the buffer BUF1, the data DQ0-DQ15 read from the memory 30 in response to the read command RD1 is already held in the buffer BUF1. Therefore, the data output control unit DQCNTL does not generate a countdown signal CDWN that decreases the write pointer value WP1, and the write pointer value WP1 is not decreased from "15" (FIG. 13).

[0146] The selection signal generation unit SELGEN outputs a shift signal SFT to the buffer selector BSEL in response to the output of the read selection signal BRSEL of "1". The buffer selector BSEL performs a shift operation in response to the shift signal SFT, and transfers the buffer selection value "2" held in the holding unit BSEL1 to the holding unit BSEL0 in CYC52 of Fig. 15. This determines that after the output data DOUT from the buffer BUF1 is output, the output data DOUT is output from the buffer BUF2.

[0147] 15, the data timing control unit 255 of the processing unit 251 that outputs the read command RD2 generates an enable signal EN (RD2) so that the data DQ from the buffer BUF2 is output after the data DQ from the buffer BUF1 is output. The enable signal EN corresponding to the read command RD2 is generated 18 cycles after the output of the first read command RD2, similar to the enable signal EN corresponding to the read command RD1.

[0148] In response to the first reception of the write selection signal BWSEL of "0" corresponding to the read command RD3 in CYC53 of FIG. 15, the buffer selector BSEL holds the write selection signal BWSEL of "0" in the holding unit BSEL1. The holding unit BSEL1 holding the write selection signal BWSEL of "0" has the highest priority among the free holding units BSEL. The selector SEL0 is selected by the "0" held in the holding unit BSEL1, and the write pointer value WP0 is supplied to the buffer BUF0. Then, the buffer BUF0 writes the data DQ corresponding to the read command RD3 to the entries indicated by the sequentially increasing write pointer value WP0 after multiplying them by CYC53-CYC83 (not shown) and sequentially writing them.

[0149] The selection signal generation unit SELGEN receives the enable signal EN (RD2) from the processing unit 251 as the response enable signal RETEN. Since data DQ is being output from the buffer BUF1, the selection signal generation unit SELGEN inhibits the output of data DQ in response to the response enable signal RETEN of the buffer selection value="2" held in the holding unit BSEL0. Then, in accordance with the completion of the output of data DQ15 from the buffer BUF1, the selection signal generation unit SELGEN reads out the buffer selection value="2" held in the holding unit BSEL0 in CYC59 and outputs it as the selection signal BRSEL (FIG. 18).

[0150] The output timing generation unit OTGEN sequentially outputs the data shift signal DSFT to the buffer BUF2 based on the read selection signal BRSEL of "2." As a result, the memory access controller 20 sequentially outputs the data DQ0-DQ15 held in the buffer BUF2 as output data DOUT to the network control unit 16 in FIG. 3 through CYC59-CYC67 in FIG. 18.

[0151] When the data DQ is output from the buffer BUF2, the data DQ0-DQ15 read from the memory 30 in response to the read command RD2 is already held in the buffer BUF2. Therefore, the data output control unit DQCNTL does not generate a countdown signal CDWN that decreases the write pointer value WP1, and the write pointer value WP1 is not decreased from "15" (FIG. 15).

[0152] In response to the first reception of the write selection signal BWSEL of "1" corresponding to the read command RD4 in CYC59 of Fig. 17, the buffer selector BSEL holds the write selection signal BWSEL of "1" in an empty holding unit BSEL2. The selector SEL1 is selected by the "1" held in the holding unit BSEL2, and the write pointer value WP1 is supplied to the buffer BUF1. Then, the buffer BUF1 writes the data DQ corresponding to the read command RD4 to the entries indicated by the sequentially increasing write pointer value WP1, sequentially from CYC59 of Fig. 18.

[0153] In CYC59 of FIG. 18, the selection signal generation unit SELGEN outputs a shift signal SFT to the buffer selector BSEL in response to the output of the read selection signal BRSEL of "2". The buffer selector BSEL performs a shift operation in response to the shift signal SFT. Then, in CYC60 of FIG. 17, the buffer selector BSEL transfers the buffer selection value "0" held in the holding unit BSEL1 to the holding unit BSEL0, and transfers the buffer selection value "1" held in the holding unit BSEL2 to the holding unit BSEL1. This determines that the output data DOUT is output from the buffer BUF2, and then the output data DOUT is output from the buffer BUF0.

[0154] 17, the data timing control unit 255 of the processing unit 250 that outputs the read command RD3 generates an enable signal EN (RD3) so that the data DQ from the buffer BUF0 is output after the data DQ from the buffer BUF2 is output. The enable signal EN corresponding to the read command RD3 is generated 18 cycles after the output of the first read command RD3, similar to the enable signal EN corresponding to the read command RD1.

[0155] The selection signal generation unit SELGEN receives the enable signal EN (RD3) from the processing unit 250 as a response enable signal RETEN. When the output of the data DQ15 from the buffer BUF2 is completed, the selection signal generation unit SELGEN reads out the buffer selection value "0" held in the holding unit BSEL0 in CYC67 and outputs it as the selection signal BRSEL (FIG. 18).

[0156] The output timing generation unit OTGEN sequentially outputs the data shift signal DSFT to the buffer BUF0 based on the read selection signal BRSEL of "0." As a result, the memory access controller 20 sequentially outputs the data DQ0-DQ31 held in the buffer BUF0 as output data DOUT through CYC67-CYC83 (not shown) to the network control unit 16 in FIG.

[0157] 17, the data timing control unit 255 of the processing unit 251 that outputs the read command RD4 generates an enable signal EN (RD4) so ​​that the data DQ from the buffer BUF2 is output after the data DQ from the buffer BUF0 is output. The enable signal EN is generated 18 cycles after the output of the first read command RD4, similar to the enable signal EN corresponding to the read command RD1.

[0158] The selection signal generation unit SELGEN receives the enable signal EN from the processing unit 251 as the response enable signal RETEN. Since data DQ is being output from the buffer BUF0, the selection signal generation unit SELGEN inhibits the output of data DQ in response to the response enable signal RETEN with a buffer selection value="1" held in the holding unit BSEL0.

[0159] Thereafter, the selection signal generator SELGEN reads out the buffer selection value "1" held in the holding unit BSEL0 in accordance with the completion of output of the data DQ31 from the buffer BUF0, and outputs it as the selection signal BRSEL. Then, although not shown in the figure, the memory access controller 20 sequentially outputs the data DQ0-DQ31 held in the buffer BUF1 as output data DOUT to the network control unit 16 in FIG. 3. Fig. 19 shows an example of the operation of another memory access controller. Detailed description of the same operations as those in Figs. 10 to 18 will be omitted. The timing of the active commands ACT0 and ACT1 and the read commands RD0 and RD1 output from the memory access controller to the memory is the same as in Figs. 10, 11, 13 and 15. Note that in Fig. 19, the read commands RD3 and RD4 are not issued.

[0160] The memory access controller that executes the operation of Fig. 19 does not have a function to determine whether or not another active command ACT has been issued when an active command ACT is issued. In other words, the memory access controller that executes the operation of Fig. 19 does not have a function to delay the output of the output data DOUT from the buffer BUF when the memory is not in the idle state.

[0161] Therefore, the memory access controller generates an enable signal EN (RD1) in CYC33, which is 10 cycles after the output of the first read command RD1. Because no other output data DOUT is being output from the buffer BUF, the memory access controller multiplies the data DQ0-DQ15 held in the buffer BUF in response to the read command RD1 by CYC33-CYC41 and outputs them as output data DOUT.

[0162] The memory access controller generates an enable signal EN(RD0) in CYC35, which is 18 cycles after the output of the first read command RD0. In CYC35, the output data DOUT corresponding to the read command RD1 is output from the buffer BUF. Therefore, after the output data DOUT corresponding to the read command RD1 is output from the buffer BUF, the memory access controller outputs the output data DOUT corresponding to the read command RD0 in CYC41-CYC57.

[0163] 19, the output data DOUT enclosed by a dashed line in brackets indicates the output timing in response to the enable signal EN (RD0) when no other output data DOUT is being output from the buffer BUF. It is preferable that the memory access controller outputs the data DQ read from the memory in the order in which the commands are received.

[0164] However, as shown in Fig. 19, in a memory access controller capable of processing memory access requests MREQ with different packet sizes PS, the order in which the output data DOUT is output to the network control unit may be reversed depending on the order in which the memory access requests MREQ are received. For example, when a memory access request MREQ with a small packet size PS is issued after a memory access request MREQ with a large packet size PS, the order in which the output data DOUT is output may be reversed.

[0165] If the output order of the output data DOUT is reversed, data processing using data read from memory by the device that issued the memory access request MREQ may be delayed, and the processing performance of the device may be degraded. Also, if the system that issued the memory access request MREQ predicts the completion time of receiving the data read from memory and operates speculatively based on the predicted completion time, the speculative operation may be wasted.

[0166] As described above, the same effects as those of the above-mentioned embodiment can be obtained in this embodiment as well. For example, the memory access controller 20 can output data DQ read from the memory 30 based on memory access requests MREQ with different packet sizes PS received from inside or outside the CPU 10 in the order in which the memory access requests MREQ are received.

[0167] When the output of the data DQ corresponding to the following read command RD1 overlaps with the output of the data DQ corresponding to the preceding read command RD0, the buffer control unit 270 delays the start of the output of the data DQ based on the enable signal EN (RD1). This makes it possible to prevent the collision of the data DQ from the multiple buffers BUF, and to prevent the memory access controller 20 from outputting erroneous data DQ (DOUT).

[0168] Furthermore, in this embodiment, the following effects can be obtained. For example, when the memory 30 is not in an idle state, the data timing control unit 255 sets the output start timing of data corresponding to a subsequent memory access request MREQ to the output start timing when a memory access request of the longest packet size MPS is received. This makes it possible to make the period from the first read command RD to the output start timing of data DQ constant, regardless of the packet size PS of the memory access request MREQ. Therefore, the output control of the enable signal EN by the data timing control unit 255 can be simplified compared to the case where the output start timing is set according to the packet size PS of the preceding memory access request MREQ.

[0169] The selection signal generator SELGEN sets the output start timing of the subsequent data DOUT so that the data DOUT of the subsequent memory access request MREQ is not output earlier than the final data DOUT corresponding to the preceding memory access request MREQ. This makes it possible to prevent the outputs of the data DQ from the buffers BUF0 and BUF1 from colliding with each other, thereby making it possible to prevent malfunction of the memory access controller 20.

[0170] When the memory 30 is in an idle state, the data timing control section 255 sets the output timing of the enable signal EN according to the access specification (e.g., packet size PS) of the device that issues the memory access request MREQ. This enables the memory access controller 20 to output the data DOUT corresponding to the memory access request MREQ to the device that issued the memory access request MREQ at the shortest possible timing.

[0171] For the buffer BUF having a shift register structure, the data output control unit DQCNTL counts down the counter CONT when outputting data DQ from the buffer BUF. This allows the data DQ to be stored in the correct position even if the storage position of new data DQ is shifted due to the shift operation of the buffer BUF.

[0172] Furthermore, the data output control unit DQCNTL stops the count-up and count-down of the counter CONT when storing data DQ in the buffer BUF and outputting data DQ from the buffer BUF at the same time, so that new data DQ can be stored in the same position of the buffer BUF regardless of the shift operation of the buffer BUF.

[0173] By disposing the selectors SEL0-SEL2 between the counters CONT0, CONT1 and the buffers BUF0-BUF2, the write pointer value WP generated by any counter CONT can be supplied to any buffer BUF. As a result, the number of counters CONT can be made smaller than the number of buffers BUF, and the circuit scale of the memory access controller 20 can be reduced compared to the case where the same number of counters CONT as the number of buffers BUF are provided.

[0174] 20 shows an example of a memory access controller in another embodiment. The memory access controller 21 has two processing units 25 and a request holding pipeline 230 corresponding to each processing unit 25, and the parallelism l is "2". The memory access controller 22 has three processing units 25 and a request holding pipeline 230 corresponding to each processing unit 25, and the parallelism l is "3".

[0175] The memory access controller 23 has three processing units 25 and a request holding pipeline 230 corresponding to each processing unit 25, and supports both parallelism l of "2" and "3". When the parallelism l is "2", the memory access controller 23 uses two processing units 25 connected to four stages STGs, and when the parallelism l is "3", the memory access controller 23 uses three processing units 25. The configuration of each processing unit 25 is similar to that of the processing unit 25 shown in FIG. 8, except that the number of stages STGs connected is smaller.

[0176] Each of the memory access controllers 21, 22, and 23 has a buffer control unit 270 and a data buffer 280 connected to each processing unit 25. The configurations of the buffer control unit 270 and the data buffer 280 are the same as those in FIG. 9. This allows each of the memory access controllers 21, 22, and 23 to obtain the same effects as those of the above-mentioned embodiment. For example, each of the memory access controllers 21, 22, and 23 can output data DQ read from the memory 30 based on memory access requests MREQ having different packet sizes PS in the order in which the memory access requests MREQ are received.

[0177] The features and advantages of the embodiments will be apparent from the above detailed description. It is intended that the claims cover the features and advantages of the embodiments as described above without departing from the spirit and scope of the claims. In addition, any improvements and modifications can be easily made by a person having ordinary skill in the art. Therefore, it is not intended to limit the scope of the inventive embodiments to the above, and appropriate improvements and equivalents within the scope of the embodiments disclosed can be used. [Explanation of symbols]

[0178] 1 Processing Unit 2. Memory Access Controller 3. Access Control Section 4 Buffer control section 5(5a, 5b) Buffer 6. Memory 10 Processing unit 12 cores 14 Cache 16 Network Control Unit 18 Interconnect 20, 21, 22, 23 Memory access controller 25 (250, 251, 252) Processing section 30 Memory 210 Request Reception Unit 220 Scheduling Department 221 Request information output section 222 Resource number output section 223 Clock Counter 224 Shift signal generator 230 Request Holding Pipeline 231 Resource number holding section 232 Elapsed cycle storage unit 233 Request Information Storage Unit 234 Shift signal generator 240 Configuration Register 253 Row control section 254 Column control section 255 Data Timing Control Unit 260 Selector 270 Buffer control section 280 Data Buffer 2531 Selector 2532 Raw Information Output Unit 2541 Selector 2542 Column information output part 2543 Counter ACT Active Command BG(BG0-BG3) Bank Group BSEL Buffer Selector BSEL0-BSEL2 holding part BUF0-BUF2 buffers BWSEL Write select signal BRSEL Read select signal CNT Counter value CDWN Countdown signal COL(COL0, COL1) Column control signal CONT0, CONT1 counters CUP Count up signal CYC Cycle DOUT Output data DQ Data DQCNTL Data output control unit DQIN Data input timing signal DSFT, DSFTa, DSFTb Data shift signals EN Enable signal FF Flip-Flop INC Incrementer l Degree of parallelism m phase difference MCLK Memory Clock MPS Maximum Packet Size MREQ Memory access request n Average request interval OTGEN Output timing generator PS Packet Size RD (RD0-RD4) Read command REQALN Single requirement information REQINF Request information RETEN Response enable signal RL Read Latency ROW (ROW0, ROW1) Row control signal RSC resource number SEL, SEL0-SEL2 selector SELGEN Selection signal generator SFTIN Shift input signal STG(STG0-STG10) Stage T elapsed time TCOL Column Timing TROW Low Timing WP, WP0, WP1, WPa, WPb Write pointer values

Claims

1. A processing device having a memory access controller capable of controlling memory access based on a plurality of memory access requests each having a different data read size, The memory access controller includes: an access control unit that, when receiving a plurality of memory access requests, outputs to the memory read commands corresponding to the plurality of memory access requests at a timing that avoids contention of read data output from the memory, and generates a timing to start outputting the data read from the memory to an external device; a plurality of buffers each holding data read from the memory in response to the read command; a buffer control unit that controls operations of the plurality of buffers and causes any one of the plurality of buffers to output data based on the output start timing; When receiving a subsequent memory access request during execution of memory access corresponding to a preceding memory access request, the access control unit delays a timing at which data output from the buffer corresponding to the subsequent memory access request starts from a timing at which data output from the buffer corresponding to the preceding memory access request starts. Processing unit.

2. The access control unit When a subsequent memory access request is received during execution of memory access corresponding to a preceding memory access request, the output start timing corresponding to the subsequent memory access request is set to the output start timing at the time of receiving a memory access request having the largest data read size among the acceptable memory access requests. The processor according to claim 1 .

3. When the output start timing corresponding to the subsequent memory access request is earlier than the output timing of the final data from the buffer corresponding to the preceding memory access request, the buffer control unit sets the output start timing corresponding to the subsequent memory access request to be later than the output timing of the final data. The processor according to claim 1 or 2.

4. When a memory access request is received and a memory access corresponding to a preceding memory access request is not being executed, the access control unit sets an output start timing according to an access specification of the received memory access request. The processor according to any one of claims 1 to 3.

5. Each of the plurality of buffers has a shift register structure that performs a shift operation when outputting data, the buffer control unit includes a plurality of counters that generate write pointer values ​​indicating storage destinations of data in each of the plurality of buffers, and a counter control unit that counts up or down each of the plurality of counters; The counter control unit counts up the counter when storing data in the buffer without outputting the data from the buffer, counts down the counter when outputting data from the buffer without storing the data in the buffer, and stops counting up and down the counter when outputting data from the buffer and storing data in the buffer. The processor according to any one of claims 1 to 4.

6. a selector for supplying a write pointer value generated by the counter to any one of the buffers; The number of counters is less than the number of buffers. The processor according to claim 5 .

7. an operation execution unit that executes an operation; An interface unit connected to an external device; a network control unit that receives the memory access request output by the operation execution unit and the memory access request output by an external device via the interface unit, and outputs the received memory access request to the memory access controller. The processor according to any one of claims 1 to 6.

8. A memory access method using a memory access controller capable of controlling memory access based on a plurality of memory access requests each having a different data read size, comprising: when receiving a plurality of memory access requests, outputting read commands corresponding to the plurality of memory access requests to the memory at a timing that avoids contention of read data output from the memory; generating a timing for starting output of data read from the memory to an external device; controlling operations of a plurality of buffers each holding data read from the memory in response to the read command, and outputting data from any one of the plurality of buffers based on the output start timing; When a subsequent memory access request is received during execution of memory access corresponding to a preceding memory access request, a timing at which data output from the buffer corresponding to the subsequent memory access request starts is delayed from a timing at which data output from the buffer corresponding to the preceding memory access request starts. Memory access method.

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