Photodetector

Abstract

To provide a photodetector capable of stably integrating and amplifying the output of a photodetection element.SOLUTION: A photodetector includes a plurality of detection elements 31 (photodetection elements) provided in a detection region, an integration and amplification circuit 32 for integrating and amplifying electrical signals output from the detection elements 31, and an output circuit 33 connected to the output of the integration and amplification circuit 32. The integration and amplification circuit 32 includes an amplifier array 300 in which odd-numbered stages of inversion amplifiers 301, 302, and 303 are connected in series, an integration capacitor Cfb connected between the input and output of the amplifier array 300, and a first reset circuit SW1 connected to both ends of a first-stage inversion amplifier 301 constituting the amplifier array 300.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a light detection device. [Background technology]

[0002] For example, a detection device using a photoelectric conversion element for detection is known (see, for example, Patent Document 1). A detection device using a photoelectric conversion element converts electric charges generated by the photoelectric conversion element into a voltage signal, outputs the voltage signal to a detection circuit, and integrates the voltage signal in an integration circuit provided in the detection circuit, thereby performing detection processing. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2011-10054 A Summary of the Invention [Problem to be solved by the invention]

[0004] Photoelectric conversion elements for detection include photodiodes such as OPDs (Organic Photo Diodes). In detection devices used for detection under low illuminance, the amount of change in the signal obtained from a detection element such as a photodiode is small, so the output of the detection element needs to be amplified. It is desirable to amplify the output of the detection element near the detection element to prevent noise contamination. For this reason, a configuration in which an integrating circuit with multiple amplifier stages is placed near the detection element is considered. In particular, when detecting neutron rays, X-rays, etc., a large area and improved detection efficiency are desired, and thin film transistors (TFTs) made of low temperature polycrystalline silicon (LTPS), which can be easily made large, are used.

[0005] However, TFTs made of LTPS have issues such as lower electron mobility compared to transistors made of crystalline silicon, and large variations in element characteristics such as threshold voltage and response characteristics. Therefore, as the circuit scale increases, the delay between the input and output of the circuit increases, making it easier for circuit oscillation and ringing to occur.

[0006] An object of the present invention is to provide a photodetection device capable of stably integrating and amplifying the output of a photodetection element. [Means for solving the problem]

[0007] A photodetection device according to one embodiment of the present invention includes a detection area divided into a plurality of divided regions, a plurality of photodetection elements provided in each of the divided regions, an integral amplification circuit that integrates and amplifies an electrical signal output from the photodetection elements, and an output circuit connected to the output of the integral amplification circuit, wherein the integral amplification circuit includes an amplifier array in which an odd number of stages of inverting amplifiers are connected in series, an integral capacitance connected between the input and output of the amplifier array, and a first reset circuit connected to both ends of a first-stage inverting amplifier that constitutes the amplifier array. [Brief description of the drawings]

[0008] [Figure 1A] FIG. 1A is a cross-sectional view showing a schematic cross-sectional configuration of a detection instrument with an illumination device having a detection device according to an embodiment. [Figure 1B] FIG. 1B is a cross-sectional view showing a schematic cross-sectional configuration of a detection instrument with an illumination device according to a modified example. [Diagram 2] FIG. 2 is a plan view showing the detection device according to the embodiment. [Diagram 3] FIG. 3 is a block diagram showing an example of the configuration of the divided regions according to the first embodiment. [Figure 4] FIG. 4 is a diagram showing a specific example of the configuration of an inverting amplifier that constitutes the integral amplifier circuit. [Diagram 5] FIG. 5 is a diagram showing a specific example of the configuration of each reset circuit. [Figure 6]FIG. 6 is a timing chart showing an example of the operation of the divided regions according to the first embodiment. [Figure 7] FIG. 7 is a block diagram showing a configuration example of an integral amplifier circuit according to a comparative example. [Figure 8] FIG. 8 is a block diagram showing an example of the configuration of divided regions according to a modified example of the first embodiment. [Figure 9] FIG. 9 is a block diagram showing an example of the configuration of the divided regions according to the second embodiment. [Figure 10] FIG. 10 is a timing chart showing an example of the operation of the divided regions according to the second embodiment. [Figure 11] FIG. 11 is a block diagram showing an example of the configuration of divided regions according to Modification 1 of the second embodiment. [Figure 12] FIG. 12 is a block diagram showing an example of the configuration of divided regions according to Modification 2 of Embodiment 2. In FIG. [Figure 13] FIG. 13 is a timing chart showing an example of the operation of the divided regions according to the second modification of the second embodiment. [Figure 14] FIG. 14 is a block diagram showing an example of the configuration of the divided regions according to the third embodiment. [Figure 15] FIG. 15 is a timing chart showing an example of the operation of the divided regions according to the third embodiment. [Figure 16] FIG. 16 is a diagram showing a modified example of the detection element. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The form (embodiment) for carrying out the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited by the contents described in the following embodiment. In addition, the components described below include those that a person skilled in the art can easily imagine and those that are substantially the same. Furthermore, the components described below can be appropriately combined. In addition, the disclosure is merely an example, and those that a person skilled in the art can easily imagine appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, in order to make the explanation clearer, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment, but they are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each figure, elements similar to those described above with respect to the previous figures may be given the same reference numerals, and detailed explanations may be omitted as appropriate.

[0010] In this specification and the claims, when expressing an aspect of arranging another structure on top of a certain structure, the term "on top" is used, unless otherwise specified, to include both a case in which another structure is arranged directly on top of a certain structure so as to be in contact with the certain structure, and a case in which another structure is arranged above a certain structure via yet another structure.

[0011] First, an application example of the detection device according to this embodiment will be described with reference to FIGS. 1A and 1B.

[0012] Fig. 1A is a cross-sectional view showing a schematic cross-sectional configuration of a detection device with an illumination device having a detection device according to an embodiment. As shown in Fig. 1A, a detection device with an illumination device 120 has a detection device 1 (light detection device), an illumination device 121, and a cover glass 122. In a direction perpendicular to the surface of the detection device 1, the illumination device 121, the detection device 1, and the cover glass 122 are stacked in this order.

[0013] The illumination device 121 has a light irradiation surface 121a for emitting light, and irradiates light L1 from the light irradiation surface 121a toward the detection device 1. The illumination device 121 is a backlight. The illumination device 121 may be, for example, a so-called side light type backlight having a light guide plate provided at a position corresponding to the detection area AA and a plurality of light sources arranged at one end or both ends of the light guide plate. For example, a light emitting diode (LED: Light Emitting Diode) that emits light of a predetermined color is used as the light source. The illumination device 121 may also be a so-called direct type backlight having a light source (for example, an LED) provided directly below the detection area AA. The illumination device 121 is not limited to a backlight, and may be provided on the side or above the detection device 1, and may irradiate light L1 from the side or above the finger Fg.

[0014] The detection device 1 is provided facing the light irradiation surface 121a of the illumination device 121. Light L1 emitted from the illumination device 121 passes through the detection device 1 and the cover glass 122. The detection device 1 can detect the detection object (in the example shown in FIG. 1A, unevenness on the surface of the finger Fg (e.g., a fingerprint)) by detecting light L2 reflected at the interface between the cover glass 122 and air. The color of the light L1 from the illumination device 121 may be varied depending on the detection object.

[0015] The cover glass 122 is a member for protecting the detection device 1 and the illumination device 121, and covers the detection device 1 and the illumination device 121. The cover glass 122 is, for example, a glass substrate. Note that the cover glass 122 is not limited to a glass substrate, and may be a resin substrate or the like. Also, the cover glass 122 may not be provided. In this case, a protective layer is provided on the surface of the detection device 1, and the detection target (here, a finger Fg) comes into contact with the protective layer of the detection device 1.

[0016] The detection device with illumination device 120 may be provided with a display panel instead of the illumination device 121. The display panel may be, for example, an organic EL display panel (OLED: Organic Light Emitting Diode) or an inorganic EL display (micro LED, mini LED). Alternatively, the display panel may be a liquid crystal display panel (LCD: Liquid Crystal Display) using liquid crystal elements as display elements, or an electrophoretic display panel (EPD: Electrophoretic Display) using electrophoretic elements as display elements.

[0017] Fig. 1B is a cross-sectional view showing a schematic cross-sectional configuration of a detector with an illumination device according to a modified example. As shown in Fig. 1B, in a detector with an illumination device 120A, the detector 1, an illumination device 121, and a cover glass 122 are stacked in this order in a direction perpendicular to the surface of the detector 1. In this modified example, a display panel such as an organic EL display panel can be used as the illumination device 121.

[0018] Light L1 emitted from the illumination device 121 is reflected by the finger Fg after passing through the cover glass 122. Light L2 reflected by the finger Fg passes through the cover glass 122 and further passes through the illumination device 121. The detection device 1 receives the light L2 that has passed through the illumination device 121, thereby enabling the detection of information related to a living body, such as a fingerprint.

[0019] Fig. 2 is a plan view showing a detection device according to an embodiment. As shown in Fig. 2, the detection device 1 has a sensor unit 3, a power supply circuit 4, a drive circuit 5, and a detection circuit 6 on a substrate 2.

[0020] The substrate 2 has a detection area AA and a peripheral area GA. The detection area AA is an area that overlaps with the multiple divided areas 30 of the sensor unit 3. That is, the detection area AA is divided into the multiple divided areas 30. The peripheral area GA is an area outside the detection area AA and does not overlap with the divided areas 30. That is, the peripheral area GA is an area between the outer periphery of the detection area AA and the end of the substrate 21. FIG. 2 shows an example in which a power supply circuit 4, a drive circuit 5, and a detection circuit 6 are provided in the peripheral area GA.

[0021] 2, the sensor unit 3 has a detection area AA with divided areas 30 arranged in a matrix. The embodiment of the sensor unit 3 is not limited to this, and may be any embodiment in which the detection area AA is divided into a plurality of divided areas 30.

[0022] The power supply circuit 4 is a circuit that supplies various potentials and various power supply voltages to be applied to the divided regions 30. The various potentials and various power supply voltages to be applied to the divided regions 30 will be described later in the configuration of the divided regions 30 according to the embodiment.

[0023] The drive circuit 5 is a circuit that outputs a read control signal and various reset control signals to the divided regions 30 and controls the operation of the divided regions 30. The read control signal and various reset control signals output to the divided regions 30 will be described later in the configuration of the divided regions 30 according to the embodiment.

[0024] The detection circuit 6 is a circuit that performs a predetermined detection process based on the detection signal output from the divided region 30. The detection circuit 6 converts the detection signal output from the divided region 30, for example, into digital image data by AD conversion, and outputs the digital image data to a downstream processing device (not shown) or the like.

[0025] The configuration of the divided region 30 according to the embodiment will be described below.

[0026] (Embodiment 1) Fig. 3 is a block diagram showing an example of the configuration of a divided region according to embodiment 1. As shown in Fig. 3, a divided region 30 according to embodiment 1 includes a detection element 31 (light detection element), an integral amplifier circuit 32, and an output circuit 33.

[0027] The detection element 31 has a photodiode PD such as an OPD (Organic Photo Diode). The photodiode PD outputs an electrical signal according to charges accumulated in response to radiation irradiated thereto. The capacitance Cs is the parasitic capacitance of the photodiode PD. In the present disclosure, the radiation detected by the photodiode PD includes visible light, X-rays, neutron rays, and the like. Note that the detection target of the detection element 31 is not limited to radiation, and may be, for example, an object in the vicinity of or in contact with the detection area AA. In this case, the sensor unit 3 may be, for example, a capacitance type or pressure detection type touch sensor.

[0028] A potential VPD (for example, −1.0 [V]) is applied to the anode of the photodiode PD from the power supply circuit 4. A potential Vref (for example, 1.0 [V]) is applied to the cathode of the photodiode PD via the reset circuit SW0.

[0029] The reset circuit SW0 is supplied with a reset control signal RST0 from the drive circuit 5. When the reset circuit SW0 is controlled to an on state by the reset control signal RST0 supplied from the drive circuit 5, the cathode potential of the photodiode PD is initialized to the potential Vref. In other words, the cathode potential of the photodiode PD is initialized to the potential Vref via the reset circuit SW0.

[0030] The detection element 31 is AC-connected to an integrating amplifier circuit 32 via a capacitance C0.

[0031] In the present disclosure, the integral amplifier circuit 32 is configured by connecting an integral capacitance Cfb between the input and output of an amplifier array 300 in which odd-numbered stages of inverting amplifiers 301, 302, and 303 are connected in series. Fig. 3 illustrates an amplifier array 300 in which three stages of inverting amplifiers 301, 302, and 303 are connected in series.

[0032] The electrical signal output from the detection element 31 is input to the integral amplifier circuit 32 via a capacitance C0. The integral amplifier circuit 32 integrates and amplifies the electrical signal output from the detection element 31.

[0033] A reset circuit (first reset circuit) SW1 is connected between both ends (input section and output section) of the inverting amplifier 301 in the first stage of the integral amplifier circuit 32.

[0034] A reset control signal RST1 is supplied to the reset circuit SW1 from the drive circuit 5. When the reset circuit SW1 is controlled to the on state by the reset control signal RST1 supplied from the drive circuit 5, the potential between the input and output of the integral amplifier circuit 32 is initialized. In other words, the potential between the input and output of the amplifier array 300 constituting the integral amplifier circuit 32 is initialized via the reset circuit SW1. That is, the potentials of the input and output of the amplifier array 300 constituting the integral amplifier circuit 32 become the same potential.

[0035] The integral amplifier circuit 32 is AC-connected to an output circuit 33 via a capacitor C1.

[0036] The output circuit 33 includes a reset transistor Mrst, a source follower transistor Msf, and a read transistor Mrd.

[0037] The source follower transistor Msf outputs a signal that has been integrated and amplified by the integral amplifier circuit 32 in accordance with the charge accumulated by the photodiode PD.

[0038] The read transistor Mrd reads out the output signal of the source follower transistor Msf and outputs it to the detection circuit 6.

[0039] An electrical signal output from the integral amplifier circuit 32 is input to the gate of the source follower transistor Msf via a capacitor C1. A reference potential GNDA (e.g., 0 [V]) is applied from the power supply circuit 4 to one of the source or drain of the source follower transistor Msf. The other of the source or drain of the source follower transistor Msf is connected to one of the source or drain of the readout transistor Mrd. The other of the source or drain of the readout transistor Mrd is connected to the detection circuit 6.

[0040] A read control signal RD is supplied from the drive circuit 5 to the gate of the read transistor Mrd. When the read control signal RD supplied from the drive circuit 5 becomes a high potential (for example, 6.0 [V]) and the read transistor Mrd is controlled to be turned on, an electric signal corresponding to the charge accumulated by the photodiode PD is output as a detection signal to the detection circuit 6. A constant current source for passing a bias current Ib to the read transistor Mrd is connected to an input terminal of the detection circuit 6. This makes it possible to detect the detection signal output from the division region 30. This constant current source may be provided in the detection circuit 6 or in the substrate 2. A pull-up resistor may be used instead of the constant current source.

[0041] The gate of the source follower transistor Msf is connected to one of the source and drain of the reset transistor Mrst. A reset potential Vrst (for example, −1.0 [V]) is applied from the power supply circuit 4 to the other of the source and drain of the reset transistor Mrst.

[0042] A reset control signal RST is supplied to the gate of the reset transistor Mrst from the drive circuit 5. When the reset control signal RST supplied from the drive circuit 5 becomes a high potential (e.g., 6.0 [V]) and the reset transistor Mrst is controlled to an on state, the gate potential of the source follower transistor Msf is initialized to the reset potential Vrst. In other words, the gate potential of the reset transistor Mrst is initialized to the reset potential Vrst (e.g., -1.0 [V]) via the reset transistor Mrst.

[0043] The reset transistor Mrst, the readout transistor Mrd, and the source follower transistor Msf are not limited to the form shown in Fig. 3. The reset transistor Mrst, the readout transistor Mrd, and the source follower transistor Msf are each composed of an n-type TFT (Thin Film Transistor) or a p-type TFT, and are configured in a circuit form according to the transistors used. The reset transistor Mrst and the readout transistor Mrd may have a single gate structure as shown in Fig. 3, may have a so-called double gate structure in which two transistors are connected in series, or may have a form in which three or more transistors are connected in series.

[0044] Fig. 4 is a diagram showing a specific example of the configuration of an inverting amplifier constituting the integral amplifier circuit. As shown in Fig. 4, the inverting amplifiers 301, 302, and 303 constituting the integral amplifier circuit 32 are configured by connecting a p-type TFT and an n-type TFT in series between a high potential power supply VDD (e.g., 6.0 [V]) and a low potential power supply VSS (e.g., 0 [V]) supplied from the power supply circuit 4. In other words, the inverting amplifiers 301, 302, and 303 constituting the integral amplifier circuit 32 are operated by being supplied with the high potential power supply VDD and the low potential power supply VSS from the power supply circuit 4.

[0045] Fig. 5 is a diagram showing a specific configuration example of each reset circuit. As shown in Fig. 5, the reset circuit SW0 of the detection element 31 and the reset circuit SW1 of the integral amplifier circuit 32 are configured by connecting a p-type TFT and an n-type TFT in parallel between the input and output. A positive logic control signal (for example, 6.0 [V] for on control and -3.0 [V] for off control) is input to the gate of the n-type TFT. A negative logic control signal (for example, 6.0 [V] for off control and -3.0 [V] for on control) is input to the gate of the p-type TFT.

[0046] The operation of the division region 30 according to the first embodiment will be described with reference to FIG. 6. FIG. 6 is a timing chart showing an example of the operation of the division region according to the first embodiment. FIG. 6 shows a positive logic reset control signal RST0 for the reset circuit SW0, and a positive logic reset control signal RST1 for the reset circuit SW1. In FIG. 6, the period T1A+T2 from time t1 to time t3 is the reset period in the division region 30, the period TSTB from time t3 to time t4 is the accumulation period in the division region 30, and the period T3 from time t4 to time t5 is the readout period.

[0047] The divided region 30 is initialized in a reset period T1A+T2 from time t1 to time t3. The reset period T1A+T2 is a period in which an initial voltage that serves as a reference value for the voltage fluctuation of the detection signal output from the divided region 30 is set.

[0048] In addition, in the divided region 30, charges corresponding to the radiation irradiated to the photodiode PD are accumulated during an accumulation period TSTB from time t3 to time t4. The accumulation period TSTB is a period during which charges corresponding to the radiation irradiated to the photodiode PD are accumulated.

[0049] Furthermore, the divided region 30 reads out the voltage fluctuation of the detection signal that has changed according to the charge accumulated by the photodiode PD during a readout period T3 from time t4 to time t5. The readout period T3 is a period during which the voltage fluctuation of the detection signal that has changed according to the charge accumulated by the photodiode PD is read out and output to the detection circuit 6.

[0050] At time t1, when the reset control signal RST0 is controlled to a high potential (e.g., 6.0 [V]), the reset circuit SW0 is controlled to an on state, and the cathode potential of the photodiode PD is reset to a potential Vref (e.g., 1.0 [V]). At this time, the anode-cathode potential of the photodiode PD is reverse-biased by the difference between the potential Vref and the potential VPD (e.g., −1.0 [V]).

[0051] Also, at the same time t1, when the reset control signal RST1 is controlled to a high potential (e.g., 6.0 [V]), the reset circuit SW1 is controlled to the on state, and the input-output potential of the amplifier array 300 constituting the integral amplifier circuit 32 is initialized to be substantially 0 V (the input and output potentials are substantially the same potential).

[0052] Also, at the same time t1, when the reset control signal RST is controlled to a high potential (e.g., 6.0 [V]), the reset transistor Mrst is controlled to an on state, and the gate potential of the source follower transistor Msf is initialized to a reset potential Vrst (e.g., −1.0 [V]).

[0053] At time t2, when the reset control signal RST0 is controlled to a low potential (for example, −3.0 [V]), the reset circuit SW0 is controlled to an off state, and the reset period T1A of the photodiode PD ends. The reset period T1A of the photodiode PD is set to approximately 50 [μs].

[0054] Furthermore, when the reset control signal RST1 is controlled to a low potential (for example, −3.0 [V]) approximately 5 [μs] after time t2, the reset circuit SW1 is controlled to the off state, and the reset period T1B of the amplifier array 300 constituting the integral amplifier circuit 32 ends. The reset period T1B of the integral amplifier circuit 32 is set to approximately 55 [μs].

[0055] Furthermore, when the reset control signal RST is controlled to a low potential (for example, −3.0 [V]) at time t3 when the period T2 has elapsed after time t2 when the reset period T1A of the photodiode PD ends, the reset transistor Mrst is controlled to an off state, and the reset period T1A+T2 ends in the divided region 30. The period T2 is set to approximately 20 [μs].

[0056] The accumulation period TSTB from time t3 to time t4 may be set to an appropriate length according to the amount of radiation or light irradiated to the photodiode PD, the value of the capacitance Cs, the photocurrent characteristics of the photodiode PD, etc. The readout period T3 from time t4 to time t5 is set to approximately 50 [μs].

[0057] According to the configuration of the above-mentioned embodiment 1, the integral amplifier circuit 32 is configured by the amplifier array 300 in which an odd number of stages (here, three stages) of inverting amplifiers 301, 302, and 303 are connected in series, so that it is possible to increase the sensitivity of the detection device 1. Here, a comparative example will be shown to explain further advantages of the configuration of the present disclosure. Fig. 7 is a block diagram showing an example of the configuration of an integral amplifier circuit according to the comparative example.

[0058] In the comparative integral amplifier circuit shown in FIG. 7, a reset circuit SW1 is connected to both ends (input section and output section) of an amplifier array in which an odd number of stages (three stages here) of inverting amplifiers are connected in series, i.e., in parallel with the integral capacitance Cfb.

[0059] In an amplifier array with multiple inverting amplifiers connected in series, the delay between the input and output becomes large. Therefore, if the reset circuit SW1 is connected between the input and output of the amplifier array, that is, between the input and output of an integrating amplifier circuit with multiple inverting amplifiers connected in series, circuit oscillation or ringing may occur during the initialization operation, which may cause the operation to become unstable.

[0060] In this embodiment, as shown in Fig. 3, a reset circuit SW1 is connected to both ends (between the input section and the output section) of a first-stage inverting amplifier 301 of an amplifier array 300 constituting an integral amplifier circuit 32. Therefore, the scale of the circuit connected between both ends of the reset circuit SW1 can be made smaller than that of the comparative example. This makes it possible to suppress the occurrence of circuit oscillation, ringing, and the like during the initialization operation of the integral amplifier circuit 32, which contributes to the stable operation of the detection device 1.

[0061] (Modification) Fig. 8 is a block diagram showing a configuration example of a divided region according to a modified example of embodiment 1. The timing chart showing an operation example of divided region 30a in the modified example of embodiment 1 shown in Fig. 8 is similar to that of embodiment 1 described above, and therefore description thereof will be omitted here.

[0062] In the divided region 30a according to the modification of the first embodiment shown in FIG. 8, the integral amplifier circuit 32a is configured by further providing an inverting amplifier 304 in the rear stage of the integral amplifier circuit 32 configured by the amplifier array 300 in which the odd number of stages of inverting amplifiers 301, 302, and 303 shown in FIG. 3 are connected in series, and an integral capacitance Cfb. When the degree of amplification is insufficient in the configuration shown in FIG. 3 described in the first embodiment, an inverting amplifier 304 may be further provided as shown in FIG. 8. The configuration of the inverting amplifier 304 is the same as the inverting amplifiers 301, 302, and 303 described above. Moreover, the number of inverting amplifiers 304 added to the configuration shown in FIG. 3 is not limited to one, and a configuration in which a plurality of inverting amplifiers 304 are provided may be provided.

[0063] (Embodiment 2) 9 is a block diagram showing an example of the configuration of divided regions according to embodiment 2. Note that duplicated explanations of components equivalent or identical to those in embodiment 1 will be omitted.

[0064] In the division region 30b according to the second embodiment shown in FIG. 9, the integral amplifier circuit 32b is configured with an amplifier array 300 in which odd-numbered stages of inverting amplifiers 301, 302, and 303 shown in FIG. 3 are connected in series, and an integral capacitance Cfb. A reset circuit (second reset circuit) SW2 similar to the reset circuit (first reset circuit) SW1 connected to both ends (between the input and output parts) of the first stage inverting amplifier 301 is connected to both ends (between the input and output parts) of the final stage inverting amplifier 303. In the integral amplifier circuit 32b, the final stage inverting amplifier 303 of the amplifier array 300 is AC-connected to the inverting amplifier 302 in the previous stage via a capacitance C2. The configuration of the reset circuit SW2 is similar to the reset circuit SW0 and reset circuit SW1 shown in FIG. 5.

[0065] A reset control signal RST1 is supplied to the reset circuit SW1 from the drive circuit 5. When the reset circuit SW1 is controlled to the on state by the reset control signal RST1 supplied from the drive circuit 5, the input and output voltages of the inverting amplifier 301 are initialized to be substantially the same potential. In addition, a reset control signal RST2 is supplied to the reset circuit SW2 from the drive circuit 5. When the reset circuit SW2 is controlled to the on state by the reset control signal RST2 supplied from the drive circuit 5, the input and output voltages of the inverting amplifier 303 are initialized to be substantially the same potential. As a result, the input and output voltages of the integral amplifier circuit 32b are initialized to be substantially the same potential.

[0066] The operation of the divided region 30b according to the second embodiment will be described with reference to Fig. 10. Fig. 10 is a timing chart showing an example of the operation of the divided region according to the second embodiment. Fig. 10 shows a positive logic reset control signal RST2 for the reset circuit SW2. Note that the reset period T1A+T2, accumulation period TSTB, and readout period T3 in the divided region 30b according to the second embodiment are the same as those in the first embodiment, and therefore will not be described here.

[0067] At time t1, when the reset control signal RST0 is controlled to a high potential (e.g., 6.0 [V]), the reset circuit SW0 is controlled to an on state, and the cathode potential of the photodiode PD is reset to a potential Vref (e.g., 1.0 [V]). At this time, the anode-cathode potential of the photodiode PD is reverse-biased by the difference between the potential Vref and the potential VPD (e.g., −1.0 [V]).

[0068] At the same time t1, when the reset control signal RST1 is controlled to a high potential (for example, 6.0 [V]), the reset circuit SW1 is controlled to an on state, and the input and output voltages of the inverting amplifier 301 are initialized to be substantially the same potential.

[0069] At the same time t1, when the reset control signal RST2 is controlled to a high potential (for example, 6.0 [V]), the reset circuit SW2 is controlled to an on state, and the input and output voltages of the inverting amplifier 303 are initialized to be substantially the same potential.

[0070] At time t2, when the reset control signal RST0 is controlled to a low potential (for example, −3.0 [V]), the reset circuit SW0 is controlled to an off state, and the reset period T1A of the photodiode PD ends. The reset period T1A of the photodiode PD is set to approximately 50 [μs].

[0071] Furthermore, when the reset control signal RST1 is controlled to a low potential (for example, -3.0 [V]) approximately 5 [μs] after time t2, the reset circuit SW1 is controlled to the off state, and the reset period T1B of the potential between the input of the first-stage inverting amplifier 301 and the output of the next-stage inverting amplifier 302 of the amplifier array 300 constituting the integral amplifier circuit 32b ends. The reset period T1B is set to approximately 55 [μs].

[0072] Furthermore, when the reset control signal RST2 is controlled to a low potential (for example, -3.0 [V]) approximately 10 [μs] after time t2, the reset circuit SW2 is controlled to the off state, and the reset period T1C of the input-output potential of the final-stage inverting amplifier 303 of the integral amplifier circuit 32b ends. The reset period T1C of the input-output potential of the final-stage inverting amplifier 303 of the integral amplifier circuit 32b is set to approximately 60 [μs].

[0073] According to the configuration of the above-mentioned embodiment 2, as in the first embodiment, the integral amplifier circuit 32b is configured by the amplifier array 300 in which an odd number of stages (three stages in this case) of inverting amplifiers 301, 302, and 303 are connected in series, so that it is possible to increase the sensitivity of the detection device 1. In addition, it is possible to suppress the occurrence of circuit oscillation, ringing, and the like during the initialization operation of the integral amplifier circuit 32b, which contributes to the stable operation of the detection device 1.

[0074] The configuration of embodiment 2 is effective in cases where variations in element characteristics cannot be tolerated in the configuration of embodiment 1. That is, the configuration of embodiment 2 can contribute to more stable operation of the detection device 1 than the configuration of embodiment 1.

[0075] (Variation 1) Fig. 11 is a block diagram showing a configuration example of a divided region according to Modification 1 of Embodiment 2. The timing chart showing an operation example of the divided region 30c in Modification 1 of Embodiment 2 shown in Fig. 11 is similar to that of the above-mentioned Embodiment 2, and therefore the description thereof will be omitted here.

[0076] In a divided region 30c according to the first modification of the second embodiment shown in Fig. 11, an integral amplifier circuit 32c is configured by further providing an inverting amplifier 304 in the configuration shown in Fig. 9, as in the modification of the first embodiment. When the degree of amplification is insufficient in the configuration shown in Fig. 9 described in the second embodiment, an inverting amplifier 304 may be further provided as shown in Fig. 11. Note that the number of inverting amplifiers 304 added to the configuration shown in Fig. 9 is not limited to one, and a configuration in which a plurality of inverting amplifiers 304 are provided may be used.

[0077] (Variation 2) 12 is a block diagram showing an example of the configuration of divided regions according to Modification 2 of Embodiment 2. Here, differences from Modification 1 of Embodiment 2 will be described.

[0078] In a divided region 30d according to the second modification of the second embodiment shown in Fig. 12, an integral amplifier circuit 32d has a reset circuit (third reset circuit) SW3 connected to both ends (between the input section and the output section) of an inverting amplifier 304 added to the configuration shown in Fig. 11. In the integral amplifier circuit 32d, the inverting amplifier 304 added to the configuration shown in Fig. 11 is AC-connected to the amplifier array 300 constituting the integral amplifier circuit 32d via a capacitance C3. The configuration of the reset circuit SW3 is similar to that of the reset circuit SW0, reset circuit SW1 (first reset circuit), and reset circuit 2 (second reset circuit) described above.

[0079] A reset control signal RST3 is supplied to the reset circuit SW3 from the drive circuit 5. When the reset circuit SW3 is controlled to the on state by the reset control signal RST3 supplied from the drive circuit 5, the reset circuit SW3 is initialized so that the input and output voltages of the inverting amplifier 304 have substantially the same potential. As a result, the input and output voltages of the integral amplifier circuit 32d are initialized so as to have substantially the same potential.

[0080] The operation of the divided region 30d according to the second modification of the second embodiment will be described with reference to Fig. 13. Fig. 13 is a timing chart showing an example of the operation of the divided region according to the second modification of the second embodiment. Fig. 13 shows a positive logic reset control signal RST3 for the reset circuit SW3. Note that the reset period T1A+T2, the accumulation period TSTB, and the readout period T3 in the divided region 30d according to the second modification of the second embodiment are the same as those in the first and second embodiments, and therefore will not be described here.

[0081] At time t1, when the reset control signal RST0 is controlled to a high potential (e.g., 6.0 [V]), the reset circuit SW0 is controlled to an on state, and the cathode potential of the photodiode PD is reset to a potential Vref (e.g., 1.0 [V]). At this time, the anode-cathode potential of the photodiode PD is reverse-biased by the difference between the potential Vref and the potential VPD (e.g., −1.0 [V]).

[0082] At the same time t1, when the reset control signal RST1 is controlled to a high potential (for example, 6.0 [V]), the reset circuit SW1 is controlled to an on state, and the input and output voltages of the inverting amplifier 301 are initialized to be substantially the same potential.

[0083] At the same time t1, when the reset control signal RST2 is controlled to a high potential (for example, 6.0 [V]), the reset circuit SW2 is controlled to an on state, and the input and output voltages of the inverting amplifier 303 are initialized to be substantially the same potential.

[0084] At the same time t1, when the reset control signal RST3 is controlled to a high potential (for example, 6.0 [V]), the reset circuit SW3 is controlled to an on state, and the input and output voltages of the inverting amplifier 304 are initialized to be substantially the same potential.

[0085] At time t2, when the reset control signal RST0 is controlled to a low potential (for example, −3.0 [V]), the reset circuit SW0 is controlled to an off state, and the reset period T1A of the photodiode PD ends. The reset period T1A of the photodiode PD is set to approximately 50 [μs].

[0086] Furthermore, when the reset control signal RST1 is controlled to a low potential (for example, -3.0 [V]) approximately 5 [μs] after time t2, the reset circuit SW1 is controlled to the off state, and the reset period T1B of the potential between the input of the first-stage inverting amplifier 301 and the output of the next-stage inverting amplifier 302 of the amplifier array 300 constituting the integral amplifier circuit 32d ends. The reset period T1B is set to approximately 55 [μs].

[0087] Furthermore, when the reset control signal RST2 is controlled to a low potential (for example, -3.0 [V]) approximately 10 [μs] after time t2, the reset circuit SW2 is controlled to the off state, and the reset period T1C of the input-output potential of the final-stage inverting amplifier 303 of the integral amplifier circuit 32d ends. The reset period T1C of the input-output potential of the final-stage inverting amplifier 303 of the integral amplifier circuit 32d is set to approximately 60 [μs].

[0088] Furthermore, when the reset control signal RST3 is controlled to a low potential (for example, -3.0 [V]) approximately 15 [μs] after time t2, the reset circuit SW3 is controlled to the off state, and the reset period T1D of the input-output potential of the inverting amplifier 304 connected to the amplifier array 300 constituting the integral amplifier circuit 32d ends. The reset period T1D of the input-output potential of the inverting amplifier 304 connected to the amplifier array 300 constituting the integral amplifier circuit 32d is set to approximately 65 [μs].

[0089] According to the configuration of the above-mentioned variant 2 of the second embodiment, similarly to the first embodiment, the integral amplifier circuit 32d is formed by the amplifier array 300 in which an odd number of stages (here, three stages) of inverting amplifiers 301, 302, and 303 are connected in series, so that the sensitivity of the detection device 1 can be increased.

[0090] The configuration of Modification 2 of Embodiment 2 is effective in cases where variations in element characteristics cannot be tolerated in the configuration of Modification 1 of Embodiment 2. That is, the configuration of Modification 2 of Embodiment 2 can suppress the occurrence of circuit oscillation, ringing, and the like during the initialization operation of the integral amplifier circuit 32d more effectively than the configuration of Modification 1 of Embodiment 2, and can contribute to stable operation of the detection device 1.

[0091] (Embodiment 3) 14 is a block diagram showing an example of the configuration of divided regions according to embodiment 3. Note that duplicated explanations of components equivalent or identical to those in embodiment 1 or embodiment 2 will be omitted.

[0092] In the divided region 30e of the third embodiment shown in FIG. 14, the integral amplifier circuit 32e has a configuration in which the reset circuit SW3 described in the second modification of the second embodiment is provided in addition to the configuration of FIG. 8 described in the first modification of the first embodiment.

[0093] The operation of the divided region 30e according to the above-mentioned embodiment 3 will be described with reference to Fig. 15. Fig. 15 is a timing chart showing an example of the operation of the divided region according to embodiment 3. Note that the reset period T1A+T2, the accumulation period TSTB, and the readout period T3 in the divided region 30e according to embodiment 3 are the same as those in embodiments 1 and 2, and therefore will not be described here.

[0094] At time t1, when the reset control signal RST0 is controlled to a high potential (e.g., 6.0 [V]), the reset circuit SW0 is controlled to an on state, and the cathode potential of the photodiode PD is reset to a potential Vref (e.g., 1.0 [V]). At this time, the anode-cathode potential of the photodiode PD is reverse-biased by the difference between the potential Vref and the potential VPD (e.g., −1.0 [V]).

[0095] At the same time t1, when the reset control signal RST1 is controlled to a high potential (for example, 6.0 [V]), the inverting amplifier 301 is initialized so that the input and output voltages are substantially at the same potential.

[0096] At the same time t1, when the reset control signal RST3 is controlled to a high potential (for example, 6.0 [V]), the inverting amplifier 304 is initialized so that the input and output voltages are substantially at the same potential.

[0097] At time t2, when the reset control signal RST0 is controlled to a low potential (for example, −3.0 [V]), the reset circuit SW0 is controlled to an off state, and the reset period T1A of the photodiode PD ends. The reset period T1A of the photodiode PD is set to approximately 50 [μs].

[0098] Furthermore, when the reset control signal RST1 is controlled to a low potential (for example, -3.0 [V]) approximately 5 [μs] after time t2, the reset circuit SW1 is controlled to the off state, and the reset period T1B of the potential between the input of the first-stage inverting amplifier 301 and the output of the next-stage inverting amplifier 302 of the amplifier array 300 constituting the integral amplifier circuit 32e ends. The reset period T1B is set to approximately 55 [μs].

[0099] Furthermore, when the reset control signal RST3 is controlled to a low potential (for example, -3.0 [V]) approximately 15 [μs] after time t2, the reset circuit SW3 is controlled to the off state, and the reset period T1D of the input-output potential of the inverting amplifier 304 connected to the amplifier array 300 constituting the integral amplifier circuit 32e ends. The reset period T1D of the input-output potential of the inverting amplifier 304 connected to the amplifier array 300 constituting the integral amplifier circuit 32e is set to approximately 65 [μs].

[0100] According to the configuration of the above-mentioned embodiment 3, similarly to the embodiments 1 and 2, the integral amplifier circuit 32e is formed by an amplifier array 300 in which an odd number of stages (here, three stages) of inverting amplifiers 301, 302, and 303 are connected in series, so that the sensitivity of the detection device 1 can be increased.

[0101] The configuration of the third embodiment is effective in cases where variations in element characteristics cannot be tolerated in the configuration of the modified example of the first embodiment. That is, the configuration of the third embodiment can suppress the occurrence of circuit oscillation, ringing, and the like during the initialization operation of the integral amplifier circuit 32e more than the configuration of the modified example of the first embodiment, and can contribute to the stable operation of the detection device 1.

[0102] According to the above-described embodiment, the detection device 1 can stably integrate and amplify the output of the detection element.

[0103] As described above, the detection target by the detection element of the detection device of the present disclosure is not limited to radiation, and may be, for example, an object in the vicinity of or in contact with the detection area AA. FIG. 16 is a diagram showing a modified example of the detection element. In the above-mentioned embodiment, the photodiode PD is exemplified as the detection element 31, but as described above, it is also possible to apply it to a capacitance-type touch sensor using a self-capacitance method or a mutual capacitance method. For example, in the case of a touch sensor using a self-capacitance method, the detection element 31a may be configured to supply a drive signal to an electrode provided in the detection area AA and detect a detection signal that changes with a change in the capacitance C generated in the electrode. Also, in the case of a touch sensor using a mutual capacitance method, for example, the detection element 31a may be configured to supply a drive signal to one of two layers of electrodes provided in the detection area AA and detect a detection signal that changes with a change in the capacitance C generated in the other electrode.

[0104] The above-described embodiment can be combined with each of the components as appropriate. In addition, other effects and advantages brought about by the aspects described in the present embodiment that are obvious from the description in this specification or that can be appropriately conceived by a person skilled in the art are naturally considered to be brought about by the present invention. [Explanation of symbols]

[0105] 1. Detection device (photodetection device) 2. Board 3 Sensor section 4 Power circuit 5. Drive circuit 6 Detection circuit 30,30a,30b,30c,30d,30e divided area 31, 31a Detector element (photodetector element) 32, 32a, 32b, 32c, 32d, 32e Integral amplifier circuit 33 Output circuit 300 Amplifier Array 301, 302, 303, 304 Inverting amplifier AA detection area GA Peripheral Areas Mrst Reset Transistor Mrd Readout transistor Msf Source Follower Transistor SW0 Reset circuit SW1 Reset circuit (first reset circuit) SW2 Reset circuit (second reset circuit) SW3 Reset circuit (third reset circuit)

Claims

1. A detection area is divided into a plurality of divided regions, and a plurality of photodetection elements are provided in each of the plurality of divided regions; an integrating and amplifying circuit that integrates and amplifies an electrical signal output from the photodetector; an output circuit connected to an output of the integral amplifier circuit; Equipped with The integral amplifier circuit includes: an amplifier array in which an odd number of inverting amplifier stages are connected in series; an integrating capacitance connected between an input and an output of the amplifier array; a first reset circuit connected to both ends of a first-stage inverting amplifier constituting the amplifier array; Equipped with Light detection device.

2. a second reset circuit connected to both ends of the inverting amplifier in the final stage constituting the amplifier array; 2. The optical detection device according to claim 1.

3. An inverting amplifier is further connected in series to the rear stage of the amplifier array.

3. The optical detection device according to claim 1 or 2.

4. a third reset circuit connected to both ends of an inverting amplifier provided in a subsequent stage of the amplifier array; 4. The optical detection device according to claim 3.

5. The light detection element includes a photodiode.

5. A light detection device according to claim 1.

6. The output circuit includes: a source follower transistor that outputs a signal that is integrated and amplified by the integration amplifier circuit in response to the charge accumulated by the photodiode; a read transistor that reads out and outputs an output signal of the source follower transistor; Equipped with 6. The optical detection device according to claim 5.

7. the integral amplifier circuit and the output circuit are provided in the divided regions together with the plurality of light detection elements, respectively; 7. A light detection device according to claim 1.

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