Temperature-Based Tuning for In-Memory Matrix Multiplication

JP7650825B2Active Publication Date: 2025-03-25ADVANCED MICRO DEVICES INC
4 Cites 0 Cited by

Patent Information

Application Number
JP2021568589
Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
Priority Date
2019-05-31
Filing Date
2020-05-08
Publication Date
2025-03-25
Estimated Expiration
2040-05-08
Patent Text Reader

Abstract

A technique for performing in-memory matrix multiplication that takes into account temperature variations within the memory is disclosed. In one example, a matrix multiplication memory uses ohmic multiplication and current addition to perform the dot products involved in the matrix multiplication. One drawback of this analog form of multiplication is that temperature affects the accuracy of the result. Therefore, a technique is provided herein that compensates for the effect of temperature increases on the accuracy of the in-memory matrix multiplication. According to this technique, portions of an input matrix are classified as valid or invalid. The valid portions are mapped to a low-temperature region of the in-memory matrix multiplier, and the invalid portions are mapped to a high-temperature region of the in-memory matrix multiplier. Then, the matrix multiplication is performed.
Need to check novelty before this filing date? Find Prior Art

Citation Information

Patent Citations

  • MEMORY DEVICE AND DATA PROCESSING METHOD BASED ON A MULTI-LAYER RRAM CROSSBAR ARRAY - Patent application

    JP2019502225A

  • Temperature compensation circuits

    US20180108403A1

  • Linear transformation accelerators

    US20190066780A1

  • Sensor device with resistive memory for signal compression and reconstruction

    US20190122727A1