Selective generation of miss requests for cache lines - Patents.com

Abstract

The graphics pipeline [200] includes a texture cache [207] having cache lines [300, 305] divided into a plurality of subsets. The graphics pipeline includes one or more computation units [121, 122, 123] that selectively generate a miss request for a first subset of the plurality of subsets of cache lines in the texture cache in response to a cache miss for a memory access request to an address associated with the first subset of the cache lines. In some embodiments, the cache lines are divided into a first sector and a second sector. The computation units generate the miss request for the first sector and bypass generation of the miss request for the second sector in response to a cache miss for a memory access request received during a request cycle being in the first sector.

Description

[Background technology]

[0001] A Graphics Processing Unit (GPU) processes three-dimensional (3D) graphics using a graphics pipeline formed of a sequence of programmable shaders and fixed-function hardware blocks. For example, a 3D model of an object visible in a frame may be represented by a set of triangles, other polygons, or patches, which are processed in the graphics pipeline to generate pixel values ​​for display to the user. The triangles, other polygons, or patches are collectively called primitives. The rendering process involves mapping textures onto the primitives to incorporate visual details that have a higher resolution than the resolution of the primitives. The GPU includes dedicated memory that is used to store texture values ​​so that they are available for mapping onto primitives being processed in the graphics pipeline. Textures can be stored on disk or can be generated procedurally as needed by the graphics pipeline. Texture data stored in the dedicated GPU memory is populated by loading textures from disk or by procedurally generating data. Frequently used texture data is cached in one or more texture caches that are accessed by shaders or fixed-function hardware blocks.

[0002] The present disclosure may be better understood, and its numerous features and advantages made apparent to those skilled in the art by reference to the following drawings, in which: The use of the same reference numbers in different drawings indicates similar or identical items. [Brief description of the drawings]

[0003] [Figure 1] 1 is a block diagram of a processing system that selectively generates miss requests for portions of a cache line in accordance with some embodiments. [Diagram 2] FIG. 2 illustrates a graphics pipeline configured to process high-order geometric primitives to generate a rasterized image of a three-dimensional (3D) scene at a given resolution, according to some embodiments. [Diagram 3] FIG. 1 is a block diagram of a cache line having requests distributed across multiple sectors in a first read cycle and requests constrained to a single sector in a second read cycle, according to some embodiments. [Figure 4] FIG. 2 is a block diagram of a cache line having requests that do not exhibit a high degree of temporal locality during a first read cycle and a second read cycle, in accordance with some embodiments. [Diagram 5] 1 is a flow diagram of a method for selectively generating miss requests for portions of a cache line according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0004] A cache line in a texture cache is typically configured to hold large amounts of data, e.g., a texture cache line may be as wide as 128 bytes or 1024 (1K) bits. Wide cache lines facilitate caching of large and / or variable sized blocks of data that are characteristic of graphics processing. Texture data is stored in tiles, such as tiles having a 4x4 pixel footprint or an 8x8 pixel footprint. The size of the tiles also depends on the texture format, which indicates the number of bits used to represent each pixel, such as an 8-bit format, a 32-bit format, a 128-bit format, etc. Thus, a tile with an 8x8 pixel footprint may be represented by 526 bits, 2048 bits, 8192 bits, or other number of bits, depending on the texture format. In operation, the texture cache receives up to N memory access requests (e.g., read requests or write requests) per cycle, where N is the size of the vector (e.g., the vector size may be 64, 32, or 16), and each cache miss generates a request to retrieve a cache line from a higher level cache or memory. Given the large size of a cache line, a cache miss request consumes significant memory bandwidth if the requested data is distributed across multiple cache lines, regardless of the amount of data in the original access request. Furthermore, enabling a full cache line for every request cycle limits opportunities for power savings by invalidating portions of the cache that are not needed to store data being used by the graphics pipeline.

[0005] 1-5 disclose systems and techniques for potentially reducing power consumption while conserving memory bandwidth between a texture cache and a system memory (or higher level cache) by selectively generating miss requests for a subset of cache lines in a texture cache in response to a cache miss for a memory access request to an address associated with the subset of the cache line. In some embodiments, a cache line is divided into two or more sectors. A miss request for a full cache line is generated in response to a cache miss due to a memory access request (e.g., a read request) that maps to all sectors in a cache line, for example, based on an address in the memory access request. If the memory access request maps to a single sector of a cache line, the miss request is selectively generated for either the full cache line or a sector of the cache line based on an evaluation of one or more heuristics or characteristics of the texture data. For example, if color compression or depth compression is enabled for the texture data, then the miss request is generated for the full cache line. If compression is not enabled for the texture data, then the miss request is generated only for the sector of the cache line indicated by the memory access request. Also, the miss request is selectively generated for a subset of cache lines based on the temporal locality of the memory access requests. For example, if the memory access request sequence is expected to access different sectors of the cache line, a miss request for a full cache line is generated in response to a cache miss in any sector. Also, the miss request is selectively generated for a subset of cache lines based on the spatial locality of the memory access requests. For example, if the memory access request sequence is expected to access adjacent, adjacent, or nearby addresses, a miss request is generated for a full cache line in response to a miss in any sector. In contrast, if the addresses of the memory access requests are distributed and have low spatial locality, a miss request is generated only for the sector of the cache line that includes the cache miss.

[0006] FIG. 1 is a block diagram of a processing system 100 that selectively generates miss requests for portions of a cache line, according to some embodiments. The processing system 100 includes or has access to a memory 105 or other storage components implemented using a non-transitory computer-readable storage medium, such as Dynamic Random-Access Memory (DRAM). However, in some cases, the memory 105 may be implemented using other types of memory, including Static Random-Access Memory (SRAM), non-volatile RAM, and the like. The memory 105 is referred to as an external memory because it is implemented external to the processing unit implemented in the processing system 100. The processing system 100 also includes a bus 110 to support communication between entities implemented in the processing system 100, such as the memory 105. Some embodiments of the processing system 100 include other buses, bridges, switches, routers, and the like, which are not shown in FIG. 1 for clarity.

[0007] The techniques described herein may be utilized in various embodiments in any of a variety of parallel processors, such as vector processors, graphics processing units (GPUs), general purpose GPUs (GPGPUs), non-scalar processors, highly parallel processors, artificial intelligence (AI) processors, inference engines, machine learning processors, other multi-threaded processing units, etc. FIG. 1 illustrates an example of a parallel processor, in particular a graphics processing unit (GPU) 115, according to some embodiments. The graphics processing unit (GPU) 115 renders images for presentation on a display 120. For example, the GPU 115 renders objects to generate pixel values ​​that are provided to the display 120, which uses the pixel values ​​to display images representing the rendered objects. The GPU 115 implements multiple computation units (CUs) 121, 122, 123 (collectively referred to herein as "computation units 121-123") that execute instructions simultaneously or in parallel. In some embodiments, the computation units 121-123 include one or more single instruction multiple data (SIMD) units, and the computation units 121-123 are aggregated into a workgroup processor, a shader array, a shader engine, or the like. The number of computation units 121-123 implemented in the GPU 115 is a matter of design choice, and some embodiments of the GPU 115 include more or fewer computation units than shown in FIG. 1. The computation units 121-123 may be used to implement a graphics pipeline, as described herein. Some embodiments of the GPU 115 are used for general-purpose computing. The GPU 115 executes instructions, such as program code 125 stored in the memory 105, and the GPU 115 stores information, such as results of executed instructions, in the memory 105.

[0008] The processing system 100 also includes a central processing unit (CPU) 130 connected to the bus 110 and thus in communication with the GPU 115 and the memory 105 via the bus 110. The CPU 130 implements multiple processor cores 131, 132, 133 (collectively referred to herein as "processor cores 131-133") that execute instructions simultaneously or in parallel. The number of processor cores 131-133 implemented in the CPU 130 is a matter of design choice, and some embodiments include more or fewer processor cores than are shown in FIG. 1. The processor cores 131-133 execute instructions, such as program code 135 stored in the memory 105, and the CPU 130 stores information, such as results of executed instructions, in the memory 105. The CPU 130 can also initiate graphics processing by issuing a draw call to the GPU 115. Some embodiments of the CPU 130 include multiple processor cores (not shown in FIG. 1 for clarity) that independently execute instructions simultaneously or in parallel.

[0009] An Input / Output (I / O) engine 145 handles input or output operations associated with the display 120 and other elements of the processing system 100, such as a keyboard, a mouse, a printer, an external disk, etc. The I / O engine 145 is coupled to the bus 110 such that the I / O engine 145 communicates with the memory 105, the GPU 115, or the CPU 130. In the illustrated embodiment, the I / O engine 145 reads information stored on an external storage component 150, which is implemented using a non-transitory computer-readable storage medium, such as a Compact Disk (CD), a Digital Video Disc (DVD), etc. The I / O engine 145 can also write information, such as results of processing by the GPU 115 or the CPU 130, to the external storage component 150.

[0010] In the illustrated embodiment, the compute units 121-123 in the GPU 115 include (or are associated with) one or more caches 151, 153, 154, collectively referred to herein as “caches 151-152.” The caches 151-153 may include L1 caches, L2 caches, L3 caches, or other caches in a cache hierarchy. Portions of the caches 151-153 are used to implement texture caches for the graphics pipelines executing on the compute units 121-123. The cache lines in the caches 151-153 are divided into subsets, such as one or more sectors of the cache lines. The graphics pipeline selectively generates miss requests for the subset of cache lines in the texture cache in response to a cache miss for a memory access request to an address associated with the subset of the cache lines. In some embodiments, the cache lines are divided into a first sector and a second sector. As described herein, in response to a cache miss for a memory access request received during a request cycle being (exclusively or primarily) within a first sector, a miss request is generated for the first sector and generation of a miss request for a second sector is bypassed.

[0011] 2 illustrates a graphics pipeline 200 configured to process high-order geometric primitives to generate a rasterized image of a three-dimensional (3D) scene at a given resolution, according to some embodiments. The graphics pipeline 200 is implemented in some embodiments of the processing system 100 illustrated in FIG. 1. The illustrated embodiment of the graphics pipeline 200 is implemented according to the DX11 specification. Other embodiments of the graphics pipeline 200 are implemented according to other Application Programming Interfaces (APIs), such as Vulkan, Metal, DX12, etc. The graphics pipeline 200 is subdivided into a geometry section 201 that includes the portion of the graphics pipeline 200 before rasterization, and a pixel processing section 202 that includes the portion of the graphics pipeline 200 after rasterization.

[0012] Graphics pipeline 200 has access to storage resources 205, such as one or more memories or hierarchies of caches used to implement buffers and store vertex data, texture data, etc. In the illustrated embodiment, storage resources 205 include a local data store (LDS) 206 circuit used to store data and a cache 207 used to cache data that is frequently used during rendering by graphics pipeline 200. Storage resources 205 may be implemented using some embodiments of memory 105 shown in FIG.

[0013] The input assembler 210 accesses information from storage resources 205 that is used to define objects that represent portions of a model of a scene. An example of a primitive is shown in Figure 2 as a triangle 211, although some embodiments of the graphics pipeline 200 process other types of primitives. A triangle 211 includes one or more vertices 212 (only one of each is shown in Figure 2 for clarity) connected by one or more edges 214. The vertices 212 are shaded during the geometry processing unit 201 of the graphics pipeline 200.

[0014] Vertex shader 215, which in the illustrated embodiment is implemented in software, logically receives as input a single vertex 212 of a primitive and outputs a single vertex. Some embodiments of shaders, such as vertex shader 215, implement single instruction-multiple data (SIMD) processing so that multiple vertices are processed simultaneously. Graphics pipeline 200 implements a unified shader model so that all shaders included in graphics pipeline 200 have the same execution platform on a shared massive SIMD compute unit. Thus, shaders, including vertex shader 215, are implemented using a common set of resources, referred to herein as a unified shader pool 216.

[0015] The hull shader 218 operates on input high-order patches or control points used to define the input patches. The hull shader 218 outputs tessellation coefficients and other patch data. In some embodiments, the primitives generated by the hull shader 218 are provided to the tessellator 220. The tessellator 220 receives objects (such as patches) from the hull shader 218 and generates information identifying primitives corresponding to the input objects, e.g., by tessellating the input objects based on tessellation coefficients provided to the tessellator 220 by the hull shader 218. The tessellation subdivides the input high-order primitives, such as patches, into a set of lower-order output primitives representing finer levels of detail, e.g., as indicated by tessellation coefficients that specify the granularity of the primitives generated by the tessellation process. Thus, a model of the scene is represented by a smaller number of high-order primitives (to save memory or bandwidth) and additional detail is added by tessellating the high-order primitives.

[0016] The domain shader 224 inputs the domain location and (optionally) other patch data. The domain shader 224 operates on the provided information and generates a single vertex for output based on the input domain location and other information. In the illustrated embodiment, the domain shader 224 generates a primitive 222 based on the triangle 211 and the tessellation factors. The geometry shader 226 receives the input primitive and outputs up to four primitives that are generated by the geometry shader 226 based on the input primitive. In the illustrated embodiment, the geometry shader 226 generates an output primitive 228 based on the tessellated primitive 222.

[0017] One stream of primitives is provided to one or more scan converters 230, and in some embodiments up to four streams of primitives are concatenated into buffers in storage resources 205. Scan converter 230 performs shading operations and other operations such as clipping, perspective division, cutting, and viewport selection. Scan converter 230 produces a set of pixels 232 that are subsequently processed in pixel processing unit 202 of graphics pipeline 200.

[0018] In the illustrated embodiment, pixel shader 234 inputs a pixel flow (e.g., including set of pixels 232) and outputs zero or another pixel flow depending on the input pixel flow. Output merger block 236 performs blending, depth, stencil, or other operations on the pixels received from pixel shader 234.

[0019] Some or all of the shaders in graphics pipeline 200 perform texture mapping using texture data stored in storage resources 205. For example, pixel shader 234 may read texture data from storage resources 205 and shade one or more pixels using the texture data. The shaded pixels are then provided to a display for presentation to a user. As described herein, texture data used by shaders in graphics pipeline 200 is cached using cache 207. Miss requests are selectively generated in response to a cache miss in cache 207, e.g., based on the location of an address in a portion of a cache line of cache 207, heuristics or characteristics of the request or data, temporal locality, spatial locality, etc.

[0020] FIG. 3 is a block diagram of a cache line having requests distributed across multiple sectors in a first read cycle 301 and requests constrained to a single sector in a second read cycle 302, according to some embodiments. Cache lines 300, 305 represent cache lines in some embodiments of caches 151-153 shown in FIG. 1 and some embodiments of cache 207 shown in FIG. 2. Cache lines 300, 305 are used to store textures for graphics processing, and thus the cache lines are relatively large. For example, each of cache lines 300, 305 may store 128 bytes, i.e., 1 Kbit, of data for access by a corresponding computing unit or other processor, processor core, processing element, etc. In the illustrated embodiment, cache lines 300, 305 are divided into two sectors. However, in some embodiments, cache lines 300, 305 are divided into three or more sectors.

[0021] During a first read cycle 301, cache line 300 receives a read request to an address indicating location 310, which holds a subset of the bytes stored by cache line 300. Location 310 is in a first sector 311 of cache line 300. Cache line 300 also receives a read request to an address indicating location 315, which holds another subset of the bytes stored by cache line 300. Location 315 is in a second sector 312 of cache line 300. In the illustrated embodiment, the read requests to location 315 and location 310 miss in cache line 300.

[0022] During the second read cycle 302, cache line 305 receives a read request to an address indicating locations 320 that hold a subset of the bytes stored by cache line 305. Locations 320 are within a first sector 321 of cache line 305, and none of locations 320 are within a second sector 322 of cache line 305. In the illustrated embodiment, the read request to locations 320 misses in cache line 305.

[0023] A miss request is selectively generated for the first sector 311, 321, the second sector 312, 322, or both sectors 311, 312, 321, 322 (e.g., full cache lines 300 and 305) based on the location of the cache miss in the cache lines 300, 305. In some embodiments, other heuristics or characteristics of the cache miss are also used to determine whether a miss request is generated for the first sector 311, 321, the second sector 312, 322, or both sectors 311, 312, 321, 322, as described herein. For example, measurements, expected or predicted spatial locality or temporal locality of the cache miss may be used to determine how the miss request is generated. In the illustrated embodiment, in response to a cache miss in a first read cycle 301 that includes location 310 in a first sector 311 and location 315 in a second sector 312, a miss request is generated for the full cache line 300 (e.g., sectors 311 and 312). During a second read cycle 302, in response to the cache miss in the second read cycle 302 being for location 320 that is only in the first sector 321, a miss request is generated only for the first sector 321 (the generation of a miss request for the second sector 322 is bypassed).

[0024] FIG. 4 is a block diagram of a cache line 400 having requests that do not exhibit a high degree of temporal locality in a first read cycle 401 and a second read cycle 402, according to some embodiments. Cache line 400 represents a cache line in some embodiments of caches 151-153 shown in FIG. 1 and some embodiments of cache 207 shown in FIG. 2. Cache line 400 is used to store textures for graphics processing, and thus the cache line is relatively large, e.g., 128 bytes of data. In the illustrated embodiment, cache line 400 is divided into sectors 411, 412. However, in some embodiments, cache line 400 is divided into three or more sectors.

[0025] During a first read cycle 401, cache line 400 receives a read request to an address indicating locations 415 that hold a subset of the bytes stored by cache line 400. Locations 415 are all found within first sector 411. During a second read cycle 402, cache line 400 receives a read request to an address indicating locations 420 that hold a subset of the bytes stored by cache line 400. Locations 420 are all found within second sector 412 of cache line 400. In the illustrated embodiment, a miss request is selectively generated to first sector 411 or second sector 412 based at least in part on the actual or predicted temporal locality of the cache miss. Thus, miss requests are generated for the full cache line (e.g., first sector 411 and second sector 412) because cache misses in successive read cycles (e.g., first read cycle 401 and second read cycle 402) are distributed across first sector 411 and second sector 412. In contrast, if read requests to cache line 400 exhibit a high degree of temporal locality, e.g., read requests during multiple cycles are expected or predicted to be for addresses located in only one of sectors 411, 412, then miss requests are generated only for the corresponding sector.

[0026] Also, miss requests are generated for different portions of the cache line 400 based on the predicted spatial locality of the read requests. For example, when a pixel shader is scanning across a screen, a sequence of read requests is likely to be for local addresses associated with adjacent or nearby pixel locations. Thus, the efficiency and performance of the memory access system is likely to be improved by fetching a full cache line when the predicted spatial locality is high (e.g., above a threshold) even if the cache miss during the current read cycle is only (or primarily) within a single sector, because subsequent read requests are likely to be for nearby addresses that may be in other sectors of the cache line. In contrast, when the predicted spatial locality is low (e.g., below a threshold), a miss request may only be generated for a single sector if the cache miss during the current read cycle is for a location within a single sector. In some embodiments, information associated with the read or miss request is retained for a hysteresis window, and information within the hysteresis window is used to determine or predict the temporal or spatial locality of the read or miss request.

[0027] Figure 5 is a flow diagram of a method 500 for selectively generating miss requests for portions of a cache line, according to some embodiments. The method 500 is implemented in some embodiments of the processing system 100 shown in Figure 1 and the graphics pipeline 200 shown in Figure 2. A cache line includes two sectors (or portions or halves), although in some embodiments a cache line includes more sectors.

[0028] In block 505, the cache receives a read request for a cacheline from a thread during a request cycle. The read request includes an address indicating the cacheline and a corresponding location in memory. In the illustrated embodiment, the read request misses in the cacheline, which triggers the selective generation of a miss request to fetch the requested data from a backing memory or a higher level cache.

[0029] At decision block 510, the cache determines whether the thread that generated the cache miss maps to locations in both sectors of the cache line during the current request cycle. If so, method 500 proceeds to block 520. If not, method 500 proceeds to decision block 515.

[0030] At decision block 515, the cache determines the likelihood of spatial or temporal locality based on a particular heuristic. In some embodiments, the likelihood of spatial or temporal locality is determined based on whether there is a match with a fixed or programmable heuristic. For example, whether the information in the cache line was generated using color or depth compression indicates that the associated data has a high degree of spatial locality and that a subsequent read request is likely to include addresses in both sectors of the cache line. Thus, if the information is expected to have a high degree of locality, method 500 proceeds to block 520. If not, method 500 proceeds to block 525.

[0031] In block 520, the cache generates a miss request for a full cache line, i.e., the cache generates a miss request that includes all sectors of the cache line. In block 525, the cache generates a miss request for a sector (or a portion or half) of the cache line that includes the location corresponding to the address in the cache miss for the thread in the request cycle.

[0032] As disclosed herein, in some embodiments, an apparatus includes a texture cache including cache lines divided into a plurality of subsets, and at least one computation unit in a graphics pipeline, where the processor is configured to selectively generate a miss request for a first subset of the plurality of subsets of cache lines in the texture cache in response to a cache miss for a memory access request to an address associated with the first subset of the cache lines. In one aspect, the at least one computation unit is configured to determine whether a cache miss associated with the memory access request maps to only the first subset of the plurality of subsets, or to one or more subsets in addition to or other than the first subset of the plurality of subsets. In another aspect, the at least one computation unit is configured to generate a miss request for a full cache line in response to the mapping of the cache miss to a subset in addition to or other than the first subset of the plurality of subsets. In yet another aspect, the at least one computation unit is configured to determine whether at least one of color compression and depth compression is enabled for the texture data in response to the memory access request mapping to only the first subset.

[0033] In one aspect, the at least one computing unit is configured to generate a miss request for a full cache line in response to at least one of color compression and depth compression being enabled for the texture data. In another aspect, the at least one computing unit is configured to generate a miss request for a first subset of the cache lines in response to at least one of color compression and depth compression not being enabled for the texture data. In yet another aspect, the at least one computing unit is configured to selectively generate a miss request to the first subset or the subsets based on at least one of a temporal locality and a spatial locality of the memory access request.

[0034] In one aspect, the at least one computing unit is configured to generate miss requests to the multiple subsets in response to a cache miss in a first subset in response to a sequence of memory access requests being expected to access the multiple subsets. In another aspect, the at least one computing unit is configured to generate miss requests to the multiple subsets in response to a cache miss in the first subset and in response to a sequence of memory access requests having spatial locality above a threshold. In yet another aspect, the at least one computing unit is configured to generate miss requests to the first subset in response to the memory access requests having spatial locality below a threshold.

[0035] In some embodiments, a method includes detecting a miss request for a cache line in a texture cache including cache lines divided into a plurality of subsets, and selectively generating a miss request for a first subset of the plurality of subsets of cache lines in response to the cache miss being to an address associated with the first subset of the cache line. In one aspect, the method includes determining whether a cache miss associated with the memory access request maps to only the first subset of the plurality of subsets, or to one or more subsets of the plurality of subsets in addition to or other than the first subset. In another aspect, the method includes generating a miss request for a full cache line in response to mapping of the cache miss to the plurality of subsets. In yet another aspect, the method includes determining whether at least one of color compression and depth compression is enabled for the texture data.

[0036] In one aspect, selectively generating the miss request includes generating a miss request for the plurality of subsets in response to at least one of color compression and depth compression being enabled for the texture data. In another aspect, selectively generating the miss request includes generating a miss request for a first subset of the cache lines in response to at least one of color compression and depth compression not being enabled for the texture data. In another aspect, selectively generating the miss request includes generating a miss request for the plurality of subsets in response to a cache miss in the first subset and in response to the sequence of memory access requests being expected to access different sectors of the cache lines.

[0037] In one aspect, selectively generating the miss request includes generating a miss request to the plurality of subsets in response to a cache miss in the first subset and in response to a memory access request sequence having spatial locality above a threshold. In another aspect, selectively generating the miss request includes generating a miss request to the first subset in response to the memory access request having spatial locality below a threshold.

[0038] In some embodiments, an apparatus includes a texture cache including cache lines divided into a first sector and a second sector, and at least one compute unit in a graphics pipeline, the at least one compute unit configured to generate a miss request for the first sector and bypass generation of the miss request for the second sector in response to a cache miss in the first sector for a memory access request received during a request cycle. In one aspect, the at least one compute unit is configured to generate miss requests for the first sector and the second sector in response to a cache miss in the first sector and the second sector for a memory access request received during a request cycle.

[0039] A computer-readable storage medium includes any non-transitory storage medium or combination of non-transitory storage media that can be accessed by a computer system during use to provide instructions and / or data to the computer system. Such storage media may include, but are not limited to, optical media (e.g., compact discs (CDs), digital versatile discs (DVDs), Blu-ray discs), magnetic media (e.g., floppy disks, magnetic tape, magnetic hard drives), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or micro-electromechanical systems (MEMS) based storage media. The computer-readable storage medium (e.g., system RAM or ROM) may be internal to the computing system, the computer-readable storage medium (e.g., a magnetic hard drive) may be permanently attached to the computing system, the computer-readable storage medium (e.g., an optical disk or Universal Serial Bus (USB)-based flash memory) may be removably attached to the computing system, or the computer-readable storage medium (e.g., network-accessible storage (NAS)) may be coupled to the computer system via a wired or wireless network.

[0040] In some embodiments, certain aspects of the techniques described above are implemented by one or more processors of a processing system executing software. The software includes one or more sets of executable instructions stored or otherwise tangibly embodied in a non-transitory computer-readable storage medium. The software may include instructions and specific data that, when executed by the one or more processors, operate the one or more processors to perform one or more aspects of the techniques described above. The non-transitory computer-readable storage medium may include, for example, a magnetic or optical disk storage device, a solid-state storage device such as a flash memory, a cache, a random access memory (RAM), or other non-volatile memory device(s), etc. The executable instructions stored in the non-transitory computer-readable storage medium may be implemented as source code, assembly language code, object code, or other form of instructions that can be interpreted or otherwise executed by one or more processors.

[0041] In addition to the above, it should be noted that not all activities or elements described in the summary description are required, some of the specific activities or devices may not be required, one or more additional activities may be performed, and one or more additional elements may be included. Furthermore, the order in which the activities are listed is not necessarily the order in which they are performed. Also, the concepts have been described with reference to specific embodiments. However, those skilled in the art will appreciate that various changes and modifications can be made without departing from the scope of the invention as set forth in the claims. Thus, the specification and drawings should be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the invention.

[0042] Benefits, other advantages, and solutions to problems have been described above with respect to specific embodiments. However, the benefits, advantages, solutions to problems, and features by which any benefit, advantage, or solution may occur or be manifested are not to be construed as critical, essential, or essential features of any or all claims. Moreover, the specific embodiments described above are illustrative only, as the disclosed invention may be modified and practiced in different but similar manners apparent to those skilled in the art having the benefit of the teachings herein. No limitations are intended to the details of construction or design herein shown, other than as set forth in the appended claims. It is therefore apparent that the specific embodiments described above may be altered or modified, and all such variations are considered to be within the scope of the disclosed invention. Accordingly, the protection sought herein is set forth in the appended claims.

Claims

1. An apparatus comprising: a texture cache including cache lines divided into a plurality of subsets; at least one compute unit in a graphics pipeline; the computation unit is configured to selectively generate a miss request for a first subset of a plurality of subsets of cache lines in the texture cache in response to a cache miss for a memory access request to an address associated with a first subset of the subsets of cache lines in the texture cache and a characteristic of data stored in the cache line that indicates whether color compression or depth compression is enabled; Device.

2. the at least one computing unit is configured to determine whether a cache miss associated with a memory access request maps to only the first subset of the plurality of subsets or to one or more subsets of the plurality of subsets in addition to or other than the first subset.

2. The apparatus of claim 1.

3. the at least one compute unit is configured to generate a miss request for a full cache line in response to the cache miss being added to the first subset of the plurality of subsets or mapping to a subset other than the first subset.

3. The apparatus of claim 2.

4. the at least one computing unit is configured to determine whether at least one of color compression and depth compression is enabled for texture data in response to the memory access request mapping to only the first subset.

4. The apparatus of claim 3.

5. the at least one computation unit is configured to generate a miss request for the full cache line in response to at least one of color compression and depth compression being enabled for the texture data.

5. The apparatus of claim 4.

6. the at least one computing unit is configured to generate a miss request for the first subset of cache lines in response to at least one of color compression and depth compression not being enabled for the texture data.

5. The apparatus of claim 4.

7. the at least one computing unit is configured to selectively generate a miss request to the first subset or the plurality of subsets based on at least one of a temporal locality and a spatial locality of the memory access request.

2. The apparatus of claim 1.

8. the at least one computing unit is configured to generate a miss request to the plurality of subsets in response to a cache miss in the first subset in response to a sequence of memory access requests being predicted to access the plurality of subsets.

8. The apparatus of claim 7.

9. the at least one computing unit is configured to generate a miss request to the plurality of subsets in response to a cache miss in the first subset and in response to a sequence of memory access requests having spatial locality above a threshold.

8. The apparatus of claim 7.

10. the at least one computing unit is configured to generate a miss request to the first subset in response to the memory access request having a spatial locality below the threshold.

10. The apparatus of claim 9.

11. 1. A method comprising: Detecting a miss request for a cache line in a texture cache that includes cache lines divided into a plurality of subsets; selectively generating miss requests for the first subset in response to cache misses for addresses associated with a first subset of the cache lines and a characteristic of data stored in the cache lines that indicates whether color compression or depth compression is enabled. method.

12. determining whether a cache miss associated with the memory access request maps to only the first subset of the plurality of subsets or to one or more subsets of the plurality of subsets in addition to or other than the first subset.

12. The method of claim 11.

13. generating a miss request for a full cache line in response to the cache miss mapping to the plurality of subsets.

13. The method of claim 12.

14. determining whether at least one of color compression and depth compression is enabled for the texture data; 14. The method of claim 13.

15. selectively generating the miss requests includes generating miss requests for the plurality of subsets in response to at least one of color compression and depth compression being enabled for the texture data.

15. The method of claim 14.

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