Silicon carbide semiconductor device

Abstract

A silicon carbide semiconductor device (100) is provided with a silicon carbide substrate (10) having a first principal surface (1) and a second principal surface (2) on the opposite side from the first principal surface. The silicon carbide substrate has an element region (120) including a plurality of transistors (21) and a termination region (110) that surrounds the element region and that includes a first Schottky barrier diode (22) in plan view in a direction orthogonal to the first principal surface. The silicon carbide substrate has: a first semiconductor region (11) that constitutes the second principal surface and that has a first conductivity type; a first surface (11C) located between the first principal surface and the second principal surface; and a second semiconductor region (16) that is provided on the first surface and that has a second conductivity type, which differs from the first conductivity type. The second semiconductor region has a first embedded region (150) that is provided in the termination region and in which a first opening (150X) is formed. The first Schottky barrier diode has a first Schottky electrode (111) that is provided on the first principal surface and that overlaps the first opening in plan view in a direction orthogonal to the first principal surface.

Description

[Technical field]

[0001] The present disclosure relates to silicon carbide semiconductor devices.

[0002] This application claims priority to Japanese Application No. 2020-187492, filed on November 10, 2020, and incorporates by reference all of the contents of said Japanese application. [Background technology]

[0003] 2. Description of the Related Art As one type of silicon carbide semiconductor device, a silicon carbide semiconductor device in which a transistor is provided in an element region and a Schottky barrier diode is provided in a guard ring region has been disclosed (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2014-170778 Summary of the Invention

[0005] A silicon carbide semiconductor device according to the present disclosure comprises a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate having, when viewed in a plan view from a direction perpendicular to the first main surface, an element region including a plurality of transistors, and a termination region surrounding the element region and including a first Schottky barrier diode, the silicon carbide substrate having the second main surface and including a first semiconductor region having a first conductivity type, a first surface located between the first main surface and the second main surface, and a second semiconductor region provided on the first surface and having a second conductivity type different from the first conductivity type, the second semiconductor region having a first buried region provided in the termination region and having a first opening formed therein, and the first Schottky barrier diode has a first Schottky electrode provided on the first main surface and overlapping with the first opening when viewed in a plan view from the direction perpendicular to the first main surface. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram showing an outline of the layout of a MOSFET according to an embodiment. [Diagram 2] FIG. 2 is an enlarged view of region A in FIG. [Diagram 3] FIG. 3 is an enlarged view of region B in FIG. [Figure 4] FIG. 4 is a cross-sectional view (part 1) showing the configuration of a silicon carbide semiconductor device according to an embodiment. [Diagram 5] FIG. 5 is a cross-sectional view (part 2) showing the configuration of the silicon carbide semiconductor device according to the embodiment. [Figure 6] FIG. 6 is a cross-sectional view (part 3) showing the configuration of the silicon carbide semiconductor device according to the embodiment. [Figure 7] FIG. 7 is a fourth cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the embodiment. [Figure 8] FIG. 8 is a diagram showing the configuration of the first surface in the element region. [Figure 9] FIG. 9 is a diagram showing the configuration of the first surface in the termination region. [Figure 10] 10A to 10C are cross-sectional views (part 1) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 11] FIG. 11 is a cross-sectional view (part 2) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 12] 12A to 12C are cross-sectional views (part 3) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 13] 13A to 13C are cross-sectional views (part 4) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 14] 14A to 14C are cross-sectional views (part 5) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 15] FIG. 15 is a cross-sectional view (part 6) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 16]FIG. 16 is a cross-sectional view (part 7) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 17] FIG. 17 is a cross-sectional view (part 8) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 18] FIG. 18 is a ninth cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 19] FIG. 19 is a cross-sectional view (part 10) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 20] FIG. 20 is a cross-sectional view (part 11) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 21] FIG. 21 is a twelfth cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 22] FIG. 22 is a thirteenth cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 23] FIG. 23 is a fourteenth cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 24] FIG. 24 is a fifteenth cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Diagram 25] FIG. 25 is a sixteenth cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 26] FIG. 26 is a cross-sectional view (part 17) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 27] FIG. 27 is a cross-sectional view (part 18) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 28] FIG. 28 is a cross-sectional view (part 19) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 29] FIG. 29 is a twentieth cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Diagram 30] FIG. 30 is a 21st cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Diagram 31] FIG. 31 is a 22nd cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Diagram 32] FIG. 32 is a 23rd cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Diagram 33] FIG. 33 is a 24th cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Diagram 34] FIG. 34 is a 25th cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Diagram 35] FIG. 35 is a 26th cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Diagram 36] FIG. 36 is a 27th cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 37] FIG. 37 is a 28th cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 38] FIG. 38 is a cross-sectional view showing an example of a silicon carbide semiconductor device including a sense structure. [Figure 39] FIG. 39 is a cross-sectional view showing another example of a silicon carbide semiconductor device including a sense structure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] [Problem that this disclosure aims to solve] In a conventional silicon carbide semiconductor device, there is a risk that a diode including a pn junction parasitic in the silicon carbide semiconductor device will operate before the Schottky barrier diode operates, resulting in a deterioration in characteristics.

[0008] An object of the present disclosure is to provide a silicon carbide semiconductor device capable of suppressing degradation of characteristics associated with the operation of a pn junction diode.

[0009] [Effects of this disclosure] According to the present disclosure, it is possible to suppress the deterioration of characteristics that accompanies the operation of a pn junction diode.

[0010] The embodiments for carrying out the invention are described below.

[0011] [Description of the embodiments of the present disclosure] First, the embodiments of the present disclosure will be listed and described. In the following description, the same or corresponding elements are given the same symbols, and the same description will not be repeated. In the crystallographic description in this specification, individual orientations are represented by [], collective orientations by <>, individual planes by (), and collective planes by {}. In addition, when a crystallographic index is negative, it is usually represented by placing a "-" (bar) above the number, but in this specification, a negative sign is placed before the number.

[0012] [1] A silicon carbide semiconductor device according to an aspect of the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate having, when viewed in a plan view from a direction perpendicular to the first main surface, an element region including a plurality of transistors, and a termination region surrounding the element region and including a first Schottky barrier diode, the silicon carbide substrate having the second main surface and including a first semiconductor region having a first conductivity type, a first surface located between the first main surface and the second main surface, and a second semiconductor region provided on the first surface and having a second conductivity type different from the first conductivity type, the second semiconductor region having a first buried region provided in the termination region and having a first opening formed therein, and the first Schottky barrier diode has a first Schottky electrode provided on the first main surface and overlapping with the first opening when viewed in a plan view from the direction perpendicular to the first main surface.

[0013] The first Schottky electrode is provided so as to overlap with the first opening formed in the first buried region when viewed in a plan view perpendicular to the first main surface. Therefore, when the first Schottky barrier diode operates, a current flows through the first opening. If the first opening is not formed, the current flows to bypass the first buried region, whereas the current path can be shortened by forming the first opening. Furthermore, the first Schottky barrier diode can be easily started up by reducing the resistance of the current path. Therefore, the first Schottky barrier diode can be operated earlier than a diode including a pn junction parasitic in the silicon carbide semiconductor device, and the deterioration of characteristics due to the operation of the pn junction diode can be suppressed.

[0014] [2] In [1], the first opening may have a rectangular planar shape, the second semiconductor region may have a plurality of electric field relaxation regions provided in the element region, and when viewed in a plan view from a direction perpendicular to the first main surface, a distance between adjacent electric field relaxation regions may be greater than a length of the shortest side of the first opening. In this case, electric field concentration in the first buried region can be relaxed, and a decrease in the breakdown voltage of the termination region can be suppressed.

[0015] [3] In the configuration of [1] or [2], the element region may have an active region in which a plurality of the transistors are arranged, and a non-active region provided around the active region and including a plurality of second Schottky barrier diodes, the second semiconductor region may have a second buried region provided in the non-active region and having a second opening formed therein, and the second Schottky barrier diode may have a second Schottky electrode provided on the first main surface and overlapping with the second opening when viewed in a plan view from a direction perpendicular to the first main surface. In this case, it is possible to suppress a deterioration in characteristics due to the operation of a pn junction diode in the non-active region.

[0016] [4] In the above [3], a gate pad to which gate electrodes of the plurality of transistors are connected may be provided above the first main surface, and the plurality of second Schottky barrier diodes may be arranged along the gate pad when viewed in a plan view perpendicular to the first main surface. In this case, it is possible to suppress a deterioration in characteristics due to the operation of a pn junction diode including a second buried region below the gate pad.

[0017] [5] In the configuration of [3] or [4], a gate runner to which gate electrodes of the plurality of transistors are connected may be provided above the first main surface, and the plurality of second Schottky barrier diodes may be arranged along the gate runner when viewed in a plan view perpendicular to the first main surface. In this case, it is possible to suppress a decrease in characteristics due to the operation of a pn junction diode including a second buried region below the gate runner.

[0018] [6] In any one of [3] to [5], a sense structure may be provided in the inactive region, and the second Schottky barrier diodes may be arranged along the sense structure when viewed in a plan view from a direction perpendicular to the first main surface. In this case, it is possible to suppress a decrease in characteristics due to the operation of a pn junction diode including a second buried region below the sense structure.

[0019] [7] In any of [3] to [6], the turn-on voltage of the second Schottky barrier diode may be lower than the turn-on voltage of a diode including a pn junction between the second buried region and the first semiconductor region, in order to further suppress deterioration in characteristics associated with the operation of the diode including a pn junction.

[0020] [Embodiments of the present disclosure] An embodiment of the present disclosure relates to a so-called vertical MOSFET (silicon carbide semiconductor device). Fig. 1 is a diagram showing an outline of a layout of a MOSFET according to an embodiment. Fig. 2 is a diagram showing an enlarged view of a region A in Fig. 1. Fig. 3 is a diagram showing an enlarged view of a region B in Fig. 1.

[0021] First, an overview of the layout of the MOSFET 100 according to this embodiment will be described. As shown in Fig. 1, the MOSFET 100 has a rectangular planar shape with two sides parallel to the X direction and two sides parallel to the Y direction. The MOSFET 100 includes an element region 120 and a termination region 110. The termination region 110 surrounds the element region 120 in a planar view.

[0022] A gate pad 84 and a gate runner 85 connected to the gate pad 84 are provided within the element region 120. The gate pad 84 and the gate runner 85 are made of a metal with low electrical resistance, such as aluminum or an aluminum alloy. The gate pad 84 is configured so that a gate voltage is applied from the outside.

[0023] The gate pad 84 is disposed in the center in the X direction near one side parallel to the X direction. For example, three gate runners 85 are provided, one of which extends in the -Y direction from the gate pad 84 to near the boundary between the element region 120 and the termination region 110. The other extends in the +X direction from the gate pad 84, bends in the -Y direction near the boundary between the element region 120 and the termination region 110, and extends in the -Y direction to near the boundary between the element region 120 and the termination region 110. The other extends in the -X direction from the gate pad 84, bends in the -Y direction near the boundary between the element region 120 and the termination region 110, and extends in the -Y direction to near the boundary between the element region 120 and the termination region 110.

[0024] Although details will be described later, a plurality of transistors 21 (see FIGS. 3 and 4) each having a gate electrode 82 connected to a gate runner 85 are provided in the element region 120. A plurality of first Schottky barrier diodes 22 (see FIG. 7) connected to the transistors 21 are provided in the termination region 110, and a plurality of second Schottky barrier diodes 23 (see FIG. 5) connected to the transistors 21 are provided in the element region 120.

[0025] 1 and 2, a Schottky electrode 111 of a first Schottky barrier diode 22 is provided in the termination region 110. The Schottky electrodes 111 are arranged to be aligned along the outer edge of the MOSFET 100 when viewed in a plan view from the Z direction perpendicular to the first main surface 1. The Schottky electrode 111 is an example of a first Schottky electrode.

[0026] As shown in FIG. 1 and FIG. 3, the element region 120 has an active region 120A in which the transistors 21 are arranged, and a non-active region 120B including the second Schottky barrier diode 23. A gate pad 84, a gate runner 85, and a second Schottky barrier diode 23 are provided in the non-active region 120B. The second Schottky barrier diode 23 has a Schottky electrode 121. The Schottky electrode 121 is arranged to be aligned along the gate pad 84 and the gate runner 85 when viewed in a plan view from the Z direction. The Schottky electrode 121 may surround the gate pad 84 intermittently. The Schottky electrode 121 does not need to surround the entire periphery of the gate pad 84, and may be arranged to be aligned along three sides of the gate pad 84, which has a rectangular planar shape, for example. The Schottky electrode 121 is an example of a second Schottky electrode.

[0027] The Schottky electrodes 111 and 121 are preferably made of a metal having a work function smaller than 4.33 eV, which is the work function of Ti. The Schottky electrodes 111 and 121 are preferably made of a metal having a work function larger than 3.7 eV, which corresponds to the electric affinity of silicon carbide. The Schottky electrodes 111 and 121 preferably have a melting point of 1000° C. or higher in terms of stability at high temperatures. The electronegativity of the atoms contained in the Schottky electrodes 111 and 121 is preferably smaller than the electronegativity of the atoms contained in silicon carbide, that is, the electronegativity of each of Si and C. Examples of metals that satisfy the above conditions include Hf, Zr, Ta, Mn, Nb, and V. The Schottky electrodes 111 and 121 may be made of any of these metal elements alone, or may be made of an alloy containing two or more of these metal elements.

[0028] Next, a detailed cross section of the MOSFET 100 according to the embodiment will be described. FIGS. 4 to 7 are cross-sectional views showing the configuration of a silicon carbide semiconductor device according to the embodiment. FIG. 4 corresponds to a cross-sectional view taken along line IV-IV in FIG. 3. FIG. 5 corresponds to a cross-sectional view taken along line VV in FIG. 3. FIG. 6 corresponds to a cross-sectional view taken along line VI-VI in FIG. 3. FIG. 7 corresponds to a cross-sectional view taken along line VII-VII in FIG. 2. FIG. 8 is a diagram showing the configuration of the first surface in the element region. FIG. 9 is a diagram showing the configuration of the first surface in the termination region.

[0029] As shown in FIGS. 4 to 7, the MOSFET 100 according to this embodiment mainly includes a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, a drain electrode 70, a Schottky electrode 111, and a Schottky electrode 121. The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50. The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The silicon carbide epitaxial layer 40 constitutes the first main surface 1, and the silicon carbide single crystal substrate 50 constitutes the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are made of, for example, hexagonal silicon carbide of polytype 4H. Silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen (N) and has n-type (first conductivity type).

[0030] The first main surface 1 is a {0001} plane or a plane inclined at an off angle of 8° or less in the off direction. Preferably, the first main surface 1 is a (000-1) plane or a plane inclined at an off angle of 8° or less in the off direction. The off direction may be, for example, the <11-20> direction or the <1-100> direction. The off angle may be, for example, 1° or more, or 2° or more. The off angle may be 6° or less, or 4° or less.

[0031] As shown in FIGS. 3 and 4, the silicon carbide epitaxial layer 40 mainly includes a drift region 11, a body region 12, a source region 13, an electric field reduction region 16, and a contact region .

[0032] The drift region 11 has n-type by being doped with a donor such as nitrogen or phosphorus (P). The drift region 11 has a first region 11A and a second region 11B. A first surface 11C is located between the first region 11A and the second region 11B. The second region 11B is provided on the first region 11A. The donor is preferably doped to the drift region 11 by doping with an impurity during epitaxial growth of the drift region 11, rather than by ion implantation. The donor concentration of the drift region 11 is preferably lower than the donor concentration of the silicon carbide single crystal substrate 50. The donor concentrations of the first region 11A and the second region 11B are preferably 1×10 15 cm -3 5×10 or more 16 cm -3 For example, 8×10 1 5 cm -3 The donor concentration may be different between the first region 11A and the second region 11B. The drift region 11 is an example of a first semiconductor region.

[0033] The body region 12 is provided on the drift region 11. The body region 12 has a p-type (second conductivity type) by being doped with an acceptor such as aluminum (Al). The acceptor concentration of the body region 12 is, for example, 1×10 18 cm -3 That's about it.

[0034] The source region 13 is provided on the body region 12 so as to be separated from the drift region 11 by the body region 12. The source region 13 has n-type conductivity by being doped with a donor such as nitrogen or phosphorus. The source region 13 constitutes the first main surface 1. The donor concentration of the source region 13 is, for example, 1×10 19 cm -3 That's about it.

[0035] The contact region 18 is doped with an acceptor such as aluminum and has a p-type conductivity. The contact region 18 constitutes the first main surface 1. The contact region 18 penetrates the source region 13 and contacts the body region 12. The acceptor concentration of the contact region 18 is, for example, 1×10 18 cm -3 More than 1×10 20 cm -3 The following is the result.

[0036] In the active region 120A, a plurality of gate trenches 5 are provided in the first major surface 1. The gate trenches 5 extend, for example, in the X direction parallel to the first major surface 1, and the plurality of gate trenches 5 are arranged in the Y direction parallel to the first major surface 1 and perpendicular to the X direction. The gate trenches 5 have a bottom surface 4 made of the drift region 11. The gate trenches 5 have a side surface 3 that penetrates the contact region 18, the source region 13, and the body region 12 and continues to the bottom surface 4. The bottom surface 4 is, for example, a plane parallel to the second major surface 2. The angle θ1 of the side surface 3 with respect to the plane including the bottom surface 4 is, for example, 45° or more and 65° or less. The angle θ1 may be, for example, 50° or more. The angle θ1 may be, for example, 60° or less. The side surface 3 preferably has a {0-33-8} plane. The {0-33-8} plane is a crystal plane that provides excellent mobility.

[0037] The electric field relaxation region 16 contains p-type impurities such as Al and has p-type conductivity. The electric field relaxation region 16 is provided on the surface of the first region 11A and constitutes the first surface 11C. The electric field relaxation region 16 is provided between adjacent gate trenches 5 in the Y direction when viewed in a plan view from the Z direction. The acceptor concentration of the electric field relaxation region 16 is, for example, 5×10 17 cm - 3 5×10 or more 18 cm -3 The electric field reduction region 16 is a part of the second semiconductor region.

[0038] The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is made of, for example, a material containing silicon dioxide. The gate insulating film 81 contacts the side surface 3 and the bottom surface 4. The gate insulating film 81 contacts the drift region 11 at the bottom surface 4. The gate insulating film 81 contacts each of the contact region 18, the source region 13, the body region 12, and the drift region 11 at the side surface 3. The gate insulating film 81 may be in contact with the source region 13 at the first main surface 1.

[0039] The gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is made of, for example, polysilicon (poly-Si) containing conductive impurities. The gate electrode 82 is disposed inside the gate trench 5. The gate electrode 82 extends into the non-active region 120B and is connected to a gate pad 84 or a gate runner 85.

[0040] The interlayer insulating film 83 is provided in contact with the gate electrode 82 and the gate insulating film 81. The interlayer insulating film 83 is made of a material containing, for example, silicon dioxide. The interlayer insulating film 83 electrically insulates the gate electrode 82 and the source electrode 60 from each other.

[0041] Contact holes 90 are formed in the interlayer insulating film 83 and the gate insulating film 81 at regular intervals in the Y direction. The contact holes 90 are provided such that the gate trench 5 is located between the contact holes 90 adjacent to each other in the Y direction. The contact holes 90 extend in the X direction. Through the contact holes 90, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81.

[0042] The source electrode 60 is in contact with the first main surface 1. The source electrode 60 has a contact electrode 61 provided in the contact hole 90 and a source wiring 62. The contact electrode 61 is in contact with the source region 13 and the contact region 18 on the first main surface 1. The contact electrode 61 is made of a material containing, for example, nickel silicide (NiSi). The contact electrode 61 may be made of a material containing titanium (Ti), Al, and Si. The contact electrode 61 is in ohmic junction with the source region 13 and the contact region 18. The source wiring 62 is made of a material containing, for example, Al.

[0043] The drain electrode 70 is in contact with the second main surface 2. The drain electrode 70 is in contact with the silicon carbide single crystal substrate 50 at the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is made of a material containing NiSi, for example. The drain electrode 70 may be made of a material containing Ti, Al, and Si. The drain electrode 70 is in ohmic junction with the silicon carbide single crystal substrate 50.

[0044] 3, 5, and 6, in the non-active region 120B, the Schottky electrode 121 is provided between the gate electrodes 82 adjacent to each other in the Y direction when viewed in a plan view from the Z direction. The Schottky electrode 121 is disposed between the active region 120A and the gate pad 84 or the gate runner 85 in the X direction.

[0045] A contact hole 122 for the Schottky electrode 121 is formed in the interlayer insulating film 83 and the gate insulating film 81. An opening 18X is formed in the contact region 18 and an opening 12X is formed in the body region 12 so as to overlap with the contact hole 122 when viewed in a plan view from the Z direction. The second region 11B is exposed from the interlayer insulating film 83 and the gate insulating film 81 through the contact hole 122. The Schottky electrode 121 is provided in the contact hole 122, and is connected to the second region 11B by a Schottky junction. The Schottky electrode 121 is connected to the source wiring 62.

[0046] As shown in FIG. 5 and FIG. 8, an opening 16X is formed in the electric field relaxation region 16 in the non-active region 120B. The opening 16X has, for example, a rectangular planar shape. The first region 11A is exposed in the opening 16X. When viewed in a plane from the Z direction, the distance L1 between adjacent electric field relaxation regions 16 may be greater than the length L3 of the shortest side of the opening 16X. As shown in FIG. 5 and FIG. 6, a connection region 17 containing p-type impurities such as Al and having a p-type conductivity may be provided between the body region 12 and the electric field relaxation region 16. In this case, an opening 17X is formed in the connection region 17 so as to overlap with the contact hole 122 when viewed in a plane from the Z direction. The second region 11B and the first region 11A are in direct contact with each other at the first surface 11C directly below the Schottky electrode 121. The portion of the electric field relaxation region 16 in the non-active region 120B is an example of a second buried region and is a part of the second semiconductor region. Moreover, the opening 16X is an example of a second opening.

[0047] A contact hole 123 for a gate pad 84 is formed in the interlayer insulating film 83. The gate pad 84 is connected to some of the gate electrodes 82 through the contact hole 123. A contact hole (not shown) for a gate runner 85 is also formed in the interlayer insulating film 83, and the gate runner 85 is connected to some of the gate electrodes 82 through this contact hole. Each gate electrode 82 is connected to at least either the gate pad 84 or the gate runner 85.

[0048] 2, 7, and 9, in the termination region 110, a contact hole 112 for the Schottky electrode 111 is formed in the interlayer insulating film 83 and the gate insulating film 81. Through the contact hole 112, the second region 11B is exposed from the interlayer insulating film 83 and the gate insulating film 81. The Schottky electrode 111 is provided in the contact hole 112, and is in Schottky junction with the second region 11B. The Schottky electrode 111 is connected to the source wiring 62.

[0049] In termination region 110, buried region 150, buried junction termination extension (JTE) region 151, and buried guard ring region 152 are provided on the surface of first region 11A. Buried region 150, buried JTE region 151, and buried guard ring region 152 contain p-type impurities such as Al, and have p-type conductivity. The acceptor concentration of buried region 150 is, for example, 5×10 17 cm -3 5×10 or more 18 cm -3 The acceptor concentration of the buried JTE region 151 is, for example, 5×10 16 cm -3 More than 1×10 18 cm -3 The acceptor concentration of the buried guard ring region 152 is, for example, 5×10 16 cm -3 More than 1×10 18 cm -3 The buried region 150 is an example of a first buried region, and is a part of the second semiconductor region.

[0050] An opening 150X is formed in the buried region 150 so as to overlap with the contact hole 112 when viewed in a plan view from the Z direction. When viewed in a plan view from the Z direction, a distance L1 between adjacent electric field relaxation regions 16 may be greater than a length L2 of the shortest side of the opening 150X. The first region 11A is exposed in the opening 150X. The buried region 150 is electrically connected to the electric field relaxation region 16. The buried JTE region 151 is provided outside the buried region 150, contacts the buried region 150, and is electrically connected to the buried region 150. The buried guard ring region 152 is provided outside the buried JTE region 151 and spaced apart from the buried JTE region 151. The opening 150X is an example of a first opening.

[0051] A junction region 160, a JTE region 161, and a guard ring region 162 are provided on the surface of the second region 11B. The junction region 160, the JTE region 161, and the guard ring region 162 contain p-type impurities such as Al and have p-type conductivity. The acceptor concentration of the junction region 160 is, for example, 5×10 16 cm -3 More than 1×10 18 cm -3 The acceptor concentration in the JTE region 161 is, for example, 5×10 16 cm -3 More than 1×10 18 cm -3 The acceptor concentration of the guard ring region 162 is, for example, 5×10 16 cm -3 More than 1×10 18 cm -3 The following is the result.

[0052] An opening 160X is formed in the junction region 160 so as to overlap with the contact hole 112 when viewed in a plan view from the Z direction. The second region 11B is exposed in the opening 160X. The junction region 160 is electrically connected to the contact region 18. The JTE region 161 is provided outside the junction region 160, in contact with the junction region 160, and electrically connected to the junction region 160. The guard ring region 162 is provided outside the JTE region 161 and spaced apart from the JTE region 161.

[0053] The acceptor concentration and donor concentration in each of the impurity regions are measured using, for example, a scanning capacitance microscope (SCM) or a secondary electron microscope. This can be measured by secondary ion mass spectrometry (SIMS) or the like.

[0054] Next, a method for manufacturing the MOSFET 100 according to the embodiment will be described. Figs. 10 to 37 are cross-sectional views showing the method for manufacturing the MOSFET 100 according to the embodiment. Figs. 10, 13, 16, 19, 22, 23, 26, 29, 32, and 35 show changes in the cross section shown in Fig. 4. Figs. 11, 14, 17, 20, 24, 27, 30, 33, and 36 show changes in the cross section shown in Fig. 5. Figs. 12, 15, 18, 21, 25, 28, 31, 34, and 37 show changes in the cross section shown in Fig. 7.

[0055] First, as shown in Figures 10, 11 and 12, the first region 11A of the drift region 11 is formed by epitaxial growth on a silicon carbide single crystal substrate 50. This epitaxial growth can be performed by a chemical vapor deposition (CVD) method using, for example, a mixed gas of silane (SiH4) and propane (C3H8) as a source gas and, for example, hydrogen gas (H2) as a carrier gas. It is preferable to introduce, for example, nitrogen (N) or phosphorus (P).

[0056] 13, 14, and 15, electric field reduction region 16, buried region 150, buried JTE region 151, and buried guard ring region 152 are formed on the upper surface of first region 11A. Specifically, ion implantation is performed on the upper surface of first region 11A. In the ion implantation for forming electric field reduction region 16, buried region 150, buried JTE region 151, and buried guard ring region 152, an acceptor such as aluminum (Al) is ion implanted.

[0057] Next, as shown in Figures 16, 17, and 18, the second region 11B is formed on the first region 11A by epitaxial growth. This epitaxial growth can be performed by a CVD method using, for example, a mixed gas of silane (SiH4) and propane (C3H8) as a source gas and, for example, hydrogen gas (H2) as a carrier gas. In addition, it is preferable to introduce, for example, nitrogen (N) or phosphorus (P) as a donor.

[0058] Next, as shown in FIG. 19, FIG. 20, and FIG. 21, the connection region 17, the body region 12, the source region 13, the contact region 18, the junction region 160, the JTE region 161, and the guard ring region 162 are formed. Specifically, ion implantation is performed on the upper surface of the drift region 11. In the ion implantation for forming the connection region 17, the body region 12, the contact region 18, the junction region 160, the JTE region 161, and the guard ring region 162, an acceptor such as aluminum (Al) is ion-implanted. In the ion implantation for forming the source region 13, a donor such as phosphorus (P) is ion-implanted. As a result, the silicon carbide substrate 10 having the drift region 11, the body region 12, the source region 13, and the like is formed. Note that epitaxial growth accompanied by the addition of impurities may be used instead of the ion implantation.

[0059] Next, an activation heat treatment is performed to activate the impurities added by ion implantation. The temperature of this heat treatment is preferably 1500°C or higher and 1900°C or lower, for example, about 1700°C. The heat treatment time is, for example, about 30 minutes. The heat treatment atmosphere is preferably an inert gas atmosphere, for example, an Ar atmosphere. In this manner, silicon carbide substrate 10 is prepared.

[0060] Next, as shown in FIG. 22, a gate trench 5 is formed in the silicon carbide substrate 10. For example, a mask layer (not shown) having an opening at a position where the gate trench 5 is to be formed is formed on the first main surface 1. Using the mask layer, a part of the source region 13, a part of the body region 12, and a part of the drift region 11 are removed by etching. As an etching method, for example, reactive ion etching, particularly inductively coupled plasma reactive ion etching, can be used. Specifically, for example, inductively coupled plasma reactive ion etching using sulfur hexafluoride (SF6) or a mixed gas of SF6 and oxygen (O2) as a reactive gas can be used. By etching, a recess (not shown) having a side portion substantially perpendicular to the first main surface 1 and a bottom portion provided continuously with the side portion and substantially parallel to the first main surface 1 is formed in the region where the gate trench 5 is to be formed.

[0061] Next, thermal etching is performed in the recess. The thermal etching can be performed, for example, by heating in an atmosphere containing a reactive gas having at least one or more types of halogen atoms, with the mask layer formed on the first main surface 1. The at least one or more types of halogen atoms include at least one of chlorine (Cl) atoms and fluorine (F) atoms. The atmosphere includes, for example, chlorine (Cl2), boron trichloride (BCl3), SF6, or carbon tetrafluoride (CF4). For example, a mixed gas of chlorine gas and oxygen gas is used as the reactive gas, and the thermal etching is performed at a heat treatment temperature of, for example, 800°C or more and 900°C or less. The reactive gas may contain a carrier gas in addition to the above-mentioned chlorine gas and oxygen gas. For example, nitrogen gas, argon gas, or helium gas can be used as the carrier gas.

[0062] By the above thermal etching, a gate trench 5 is formed in the first main surface 1 of the silicon carbide substrate 10. The gate trench 5 is defined by a side surface 3 and a bottom surface 4. The side surface 3 is defined by the source region 13, the body region 12, and the drift region 11. The bottom surface 4 is defined by the second region 11B of the drift region 11. Next, the mask layer is removed from the first main surface 1.

[0063] Next, as shown in FIG. 23, FIG. 24, and FIG. 25, a gate insulating film 81 is formed. For example, by thermally oxidizing the silicon carbide substrate 10, the gate insulating film 81 in contact with the source region 13, the body region 12, the drift region 11, the contact region 18, the second region 11B, the junction region 160, the JTE region 161, and the guard ring region 162 is formed. Specifically, the silicon carbide substrate 10 is heated in an atmosphere containing oxygen at a temperature of, for example, 1300° C. or higher and 1400° C. or lower. As a result, the gate insulating film 81 in contact with the first main surface 1, the side surface 3, and the bottom surface 4 is formed. Note that, when the gate insulating film 81 is formed by thermal oxidation, strictly speaking, a part of the silicon carbide substrate 10 is taken into the gate insulating film 81. For this reason, in the subsequent processing, it is assumed that the first main surface 1, the side surface 3, and the bottom surface 4 have moved slightly to the interface between the gate insulating film 81 and the silicon carbide substrate 10 after thermal oxidation.

[0064] Next, the silicon carbide substrate 10 may be subjected to a heat treatment (NO annealing) in a nitric oxide (NO) gas atmosphere. In the NO annealing, the silicon carbide substrate 10 is held, for example, for about one hour under conditions of 1100° C. or higher and 1400° C. or lower. This introduces nitrogen atoms into the interface region between the gate insulating film 81 and the body region 12. As a result, the formation of an interface state in the interface region is suppressed, and channel mobility can be improved.

[0065] 26, 27, and 28, a gate electrode 82 is formed. The gate electrode 82 is formed on the gate insulating film 81. The gate electrode 82 is formed by, for example, a low pressure chemical vapor deposition (LP-CVD) method. The gate electrode 82 is formed so as to face each of the source region 13, the body region 12, and the drift region 11.

[0066] 29, 30, and 31, an interlayer insulating film 83 is formed. Specifically, the interlayer insulating film 83 is formed so as to cover the gate electrode 82 and to be in contact with the gate insulating film 81. The interlayer insulating film 83 is formed by, for example, a CVD method. The interlayer insulating film 83 is made of, for example, a material containing silicon dioxide. A part of the interlayer insulating film 83 may be formed inside the gate trench 5.

[0067] 32 , the interlayer insulating film 83 and the gate insulating film 81 are etched to form contact holes 90 in the interlayer insulating film 83 and the gate insulating film 81. As a result, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81.

[0068] Next, a metal film (not shown) for the contact electrode 61 is formed on the first main surface 1 in contact with the source region 13 and the contact region 18. The metal film for the contact electrode 61 is formed by, for example, a sputtering method. The metal film for the contact electrode 61 is made of, for example, a material containing Ni. Next, a metal film (not shown) for the drain electrode 70 is formed on the second main surface 2 in contact with the silicon carbide single crystal substrate 50. The metal film for the drain electrode 70 is formed by, for example, a sputtering method. The metal film for the drain electrode 70 is made of, for example, a material containing Ni.

[0069] Next, alloying annealing is performed. The metal film for the contact electrode 61 and the metal film for the drain electrode 70 are held at a temperature of, for example, 900° C. or higher and 1100° C. or lower for about 5 minutes. As a result, at least a part of the metal film for the contact electrode 61 and at least a part of the metal film for the drain electrode 70 reacts with silicon contained in the silicon carbide substrate 10 and is silicided. As a result, the contact electrode 61 that makes ohmic contact with the source region 13 and the contact region 18, and the drain electrode 70 that makes ohmic contact with the silicon carbide single crystal substrate 50 are formed. The contact electrode 61 may be made of a material containing Ti, Al, and Si. The drain electrode 70 may be made of a material containing Ti, Al, and Si.

[0070] 33 and 34 , the interlayer insulating film 83 and the gate insulating film 81 are etched to form contact holes 112 and 122 in the interlayer insulating film 83 and the gate insulating film 81. As a result, the second region 11B is exposed from the interlayer insulating film 83 and the gate insulating film 81.

[0071] Next, the Schottky electrodes 111 and 121 in contact with the second region 11B are formed on the first main surface 1. The Schottky electrodes 111 and 121 are formed by, for example, a sputtering method. The Schottky electrodes 111 and 121 are made of a material containing, for example, Hf, Zr, Ta, Mn, Nb, and V.

[0072] Next, as shown in FIG. 35, FIG. 36, and FIG. 37, the interlayer insulating film 83 and the gate insulating film 81 are etched to form a contact hole 123 in the interlayer insulating film 83 and the gate insulating film 81. As a result, the gate electrode 82 is exposed from the interlayer insulating film 83 and the gate insulating film 81. Next, the source wiring 62, the gate pad 84, and the gate runner 85 are formed. The source wiring 62, the gate pad 84, and the gate runner 85 are formed by, for example, film formation by a sputtering method and RIE. The source wiring 62, the gate pad 84, and the gate runner 85 are made of, for example, a material containing aluminum. A source electrode 60 having a contact electrode 61 and a source wiring 62 is formed.

[0073] In this manner, the MOSFET 100 according to the embodiment is completed.

[0074] In the MOSFET 100 according to this embodiment, the Schottky electrode 111 is provided so as to overlap with the opening 150X formed in the buried region 150 when viewed in a plan view from the Z direction. Therefore, when the first Schottky barrier diode 22 operates, a current flows toward the drain electrode 70 through the opening 150X. If the opening 150X is not formed, the current flows to bypass the buried region 150, whereas the current path can be shortened by forming the opening 150X. Furthermore, the first Schottky barrier diode 22 can be easily started up by reducing the resistance of the current path. Therefore, the first Schottky barrier diode 22 can be operated earlier than a diode including a pn junction parasitic in the MOSFET 100, and the deterioration of characteristics due to the operation of the pn junction diode can be suppressed.

[0075] When viewed in a plane from the Z direction, the distance L1 between adjacent electric field reduction regions 16 in the active region 120A is greater than the length L2 of the shortest side of the opening 150X, thereby alleviating electric field concentration in the buried region 150 and suppressing a decrease in the breakdown voltage of the termination region 110.

[0076] The second Schottky barrier diode 23 is provided in the non-active region 120B, and the Schottky electrode 121 of the second Schottky barrier diode 23 is provided so as to overlap with the opening 16X formed in the electric field relaxation region 16 when viewed in a plan view from the Z direction. This makes it possible to suppress deterioration in characteristics due to the operation of the pn junction diode in the non-active region 120B.

[0077] By arranging the multiple second Schottky barrier diodes 23 along the gate pad 84 when viewed in a plan view from the Z direction, it is possible to suppress deterioration in characteristics due to operation of the pn junction diode including the electric field relaxation region 16 below the gate pad 84. In addition, by arranging the multiple second Schottky barrier diodes 23 along the gate runner 85 when viewed in a plan view from the Z direction, it is possible to suppress deterioration in characteristics due to operation of the pn junction diode including the electric field relaxation region 16 below the gate runner 85.

[0078] The turn-on voltage of the second Schottky barrier diode 23 is preferably lower than the turn-on voltage of a diode including a pn junction between the portion of the electric field relaxation region 16 in the inactive region 120B and the drift region 11. This is to further suppress the deterioration of the characteristics accompanying the operation of the diode including a pn junction.

[0079] A sense structure may be provided in the non-active region 120B, in which case a plurality of second Schottky barrier diodes 23 may be arranged along the sense structure when viewed in a plan view from the Z direction. Fig. 38 is a cross-sectional view showing an example of a silicon carbide semiconductor device including a sense structure. Fig. 39 is a cross-sectional view showing another example of a silicon carbide semiconductor device including a sense structure.

[0080] In the example shown in FIG. 38, the second Schottky barrier diode 23 is disposed along the sense structure 24. The sense structure 24 includes an n-type region 31 formed on the surface of the second region 11B. The n-type region 31 has an n-type property by being doped with a donor such as nitrogen or phosphorus. The n-type region 31 constitutes the first main surface 1. The donor concentration of the n-type region 31 is, for example, 1×10 18 cm -3 More than 1×10 20 cm -3 The structure is as follows. Contact holes 124 and 125 exposing n-type region 31 are formed in interlayer insulating film 83 and gate insulating film 81. Sense structure 24 has a terminal 86 that makes an ohmic junction with n-type region 31 through contact hole 124, and a terminal 87 that makes an ohmic junction with n-type region 31 through contact hole 125. In this sense structure 24, the electrical resistance of n-type region 31, which changes depending on the temperature, is measured through terminals 86 and 87, thereby making it possible to measure the temperature of the silicon carbide semiconductor device.

[0081] In the example shown in FIG. 39, the second Schottky barrier diode 23 is disposed along the sense structure 25. The sense structure 25 includes a p-type region 32 and an n-type region 33 formed on the surface of the second region 11B. The p-type region 32 has a p-type by being doped with an acceptor such as aluminum. The p-type region 32 constitutes the first main surface 1. The acceptor concentration of the p-type region 32 is, for example, 1×10 18 cm -3 More than 1×10 20 cm -3 The n-type region 33 has an n-type by being doped with a donor such as nitrogen or phosphorus. The n-type region 33 constitutes the first main surface 1. The donor concentration of the n-type region 33 is, for example, 1×10 18 cm -3 More than 1×10 20 cm -3 The structure is as follows. A contact hole 126 exposing p-type region 32 and a contact hole 127 exposing n-type region 33 are formed in interlayer insulating film 83 and gate insulating film 81. Sense structure 25 has a terminal 88 that makes an ohmic junction with p-type region 32 through contact hole 126, and a terminal 89 that makes an ohmic junction with n-type region 33 through contact hole 127. In this sense structure 25, the electrical resistance of a diode including p-type region 32 and n-type region 33, which changes depending on temperature, is measured through terminals 88 and 89, thereby making it possible to measure the temperature of the silicon carbide semiconductor device.

[0082] Since the multiple second Schottky barrier diodes 23 are arranged along the sense structures 24 and 25 when viewed in a plane from the Z direction, deterioration of characteristics due to the operation of the pn junction diode including the electric field relaxation region 16 below the sense structures 24 and 25 can be suppressed.

[0083] Although the embodiments have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0084] 1 First main surface 2 Second main surface 3. Aspects 4 Bottom 5. Gate trench 10 Silicon carbide substrate 11 Drift region (an example of a first semiconductor region) 11A 1st area 11B 2nd area 11C 1st page 12 Body Region 12X, 16X, 17X, 18X, 150X, 160X aperture 13 Source Area 16 Electric field relaxation region (part of the second semiconductor region) 17 Connection Area 18 Contact Area 21 Transistor 22 First Schottky Barrier Diode 23 Second Schottky Barrier Diode 24, 25 Sense structure 31, 33 n-type region 32 p-type region 40 Silicon carbide epitaxial layer 50 Silicon carbide single crystal substrate 60 Source electrode 61 Contact electrode 62 Source wiring 70 Drain electrode 81 Gate insulating film 82 Gate electrode 83 Interlayer insulating film 84 Gate Pad 85 Gate Runner 86, 87, 88, 89 terminals 90 Contact Hole 100 MOSFET 110 Termination area 111 Schottky electrode 112 Contact Hole 120 Element Area 120A active area 120B Inactive area 121 Schottky electrode 122, 123, 124, 125, 126, 127 Contact holes 150 Buried region (part of second semiconductor region) 151 Embedded JTE Area 152 Buried Guard Ring Area 160 Junction Area 161 JTE area 162 Guard Ring Area A, B area

Claims

1. a silicon carbide substrate having a first main surface and a second main surface opposite the first main surface; When viewed in a plan view from a direction perpendicular to the first main surface, the silicon carbide substrate has an element region including a plurality of transistors; a termination region surrounding the element region and including a first Schottky barrier diode; having The silicon carbide substrate is a first semiconductor region having a first conductivity type and defining the second major surface; a first surface located between the first main surface and the second main surface; a second semiconductor region provided on the first surface and having a second conductivity type different from the first conductivity type; having the second semiconductor region is provided in the termination region and has a first buried region having a first opening formed therein; the first Schottky barrier diode is provided on the first main surface, and has a first Schottky electrode overlapping with the first opening when viewed in a plan view from a direction perpendicular to the first main surface.

2. The first opening has a rectangular planar shape, the second semiconductor region has a plurality of electric field relaxation regions provided in the element region, 2 . The silicon carbide semiconductor device according to claim 1 , wherein a distance between adjacent said electric field buffer regions is larger than a length of the shortest side of said first opening when viewed in a plan view from a direction perpendicular to said first main surface.

3. The element region is an active region in which a plurality of the transistors are arranged; a non-active region provided around the active region and including a plurality of second Schottky barrier diodes; having the second semiconductor region is provided in the non-active region and has a second buried region having a second opening formed therein; 3. The silicon carbide semiconductor device according to claim 1, wherein the second Schottky barrier diode has a second Schottky electrode provided on the first main surface and overlapping with the second opening when viewed in a plan view from a direction perpendicular to the first main surface.

4. a gate pad to which gate electrodes of a plurality of the transistors are connected is provided above the first main surface; The silicon carbide semiconductor device according to claim 3 , wherein a plurality of the second Schottky barrier diodes are arranged along the gate pad when viewed in a plan view from a direction perpendicular to the first main surface.

5. a gate runner connected to gate electrodes of a plurality of the transistors above the first main surface; 5 . The silicon carbide semiconductor device according to claim 3 , wherein a plurality of the second Schottky barrier diodes are arranged along the gate runner when viewed in a plan view from a direction perpendicular to the first main surface.

6. a sense structure disposed in the non-active region; 6 . The silicon carbide semiconductor device according to claim 3 , wherein a plurality of the second Schottky barrier diodes are arranged along the sense structure when viewed in a plan view from a direction perpendicular to the first main surface.

7. 7. The silicon carbide semiconductor device according to claim 3, wherein a turn-on voltage of the second Schottky barrier diode is lower than a turn-on voltage of a diode including a pn junction between the second buried region and the first semiconductor region.

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