Semiconductor Device

Abstract

This semiconductor device is a field effect transistor (100) comprising: a first barrier layer (101) made of a compound semiconductor; a channel layer (102) made of a compound semiconductor formed on the first barrier layer; a second barrier layer (103) made of a compound semiconductor formed on the channel layer; a gate electrode (104) formed on the second barrier layer; and a source electrode (105) and a drain electrode (106) formed with the gate electrode (104) interposed therebetween. The field effect transistor (100) also includes a first carrier supply layer (107) formed on the first barrier layer (101) side of the channel layer (102), and a second carrier supply layer (108) formed between the gate electrode (104) and the channel layer (102). A trench (109) is provided in a region where the gate electrode (104) is formed. The source electrode (105) and the drain electrode (106) are formed on the first barrier layer (101) side of the channel layer (102).

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Electronic devices and integrated circuits that can handle the terahertz frequency band of 0.3 to 3.0 THz are attracting attention as elemental technologies for high-speed wireless communication using millimeter waves, non-destructive internal inspection by 3D imaging, and component analysis using electromagnetic wave absorption. Generally, field-hardened transistors made of compound semiconductors, which have particularly high electron mobility in physical properties, are used as electronic devices with good high-frequency characteristics.

[0003] A field effect transistor includes a semiconductor substrate, a gate electrode formed on the surface of the semiconductor substrate, and a source electrode and a drain electrode formed on both sides of the gate electrode in ohmic contact. In particular, a high electron mobility transistor (HEMT), which has excellent high frequency characteristics, has a structure in which a buffer layer, a channel layer, a barrier layer, and a cap layer are stacked on a semiconductor substrate in this order from the substrate side (Non-Patent Document 1). In addition, a carrier supply layer is formed on the barrier layer side of the channel layer, or on the buffer layer side of the channel layer. In such a structure, the position and doping amount of the carrier supply layer are designed according to the energy band design.

[0004] When a potential is applied to the gate electrode, carriers are supplied from the carrier supply layer to the channel layer according to the strength of the applied potential, modulating the concentration of the two-dimensional electron gas, and electrons move through the conduction channel formed between the source and drain electrodes. In the HEMT structure, the channel layer through which the carriers travel and the electron supply layer are spatially separated to suppress scattering by impurities. This configuration can improve electron mobility, thereby enabling terahertz operation.

[0005] In order to apply HEMT to terahertz integrated circuits, it is important to improve the high frequency characteristics. One method for achieving this is to minimize the parasitic capacitance between the gate electrode and the source and drain electrodes. A fundamental method for reducing this parasitic capacitance is to form the gate electrode surface and the source and drain electrode surfaces separately above and below the channel surface.

[0006] Focusing on the field-effect transistor structure, for example, in Non-Patent Document 2, as shown in Fig. 3(b), a thin film transistor (TFT) for a display using organic electroluminescence is used in which a bottom gate electrode is embedded in a layer of SiO2, and a channel and source / drain region made of InGaZnO (IGZO) are formed on top of the bottom gate electrode. In this example, the sheet resistance of the source / drain region is selectively reduced by irradiating the bottom gate electrode with an excimer laser, thereby reducing the on-resistance. Furthermore, since the gate electrode and the source / drain region can be formed in a self-aligned manner, it is possible to suppress an increase in unnecessary parasitic capacitance.

[0007] In addition, in Non-Patent Document 3, as shown in Fig. 1, in an electrophysiological and chemical FET sensor array, a via is formed that penetrates the well region in the source-drain region of each FET to the back side, and this via is connected to the source-drain region. This structure allows for a larger space for the sensor part on the front side, improving the sensing accuracy of biosignals. [Prior art documents] [Non-patent literature]

[0008] [Non-Patent Document 1] T. Suemitsu et al., "Improved Recessed-Gate Structure for Sub-0.1-μm-Gate InP-Based High Electron Mobility Transistors", Japanese Journal of Applied Physics, vol. 37, no. 1363-1372, 1998. [Non-Patent Document 2] M. Nakata et al., "Fabrication method for self-aligned bottom-gate oxide thin-film transistors by utilizing backside excimer-laser irradiation through substrate", Applied Physics Letters, vol. 103, 142111, 2013. [Non-Patent Document 3] S. Ingebrandt et al., "Backside contacted field effect transistor array for extracellular signal recording", Biosensors and Bioelectronics, vol. 18, pp. 429-435, 2003. Summary of the Invention [Problem to be solved by the invention]

[0009] However, when attempting to apply the field effect transistors in the techniques of Non-Patent Documents 2 and 3 to a HEMT structure, the following problems arise.

[0010] In Non-Patent Document 2, a gate electrode made of metal is disposed on the substrate side as viewed from a channel made of IGZO and is buried in SiO2, and SiO2 is used as a barrier layer, with the channel region, source and drain regions disposed on top of it. In the HEMT structure shown in Non-Patent Document 1, the source and drain electrodes and the gate electrode are disposed on the upper surface side of the channel as viewed from the substrate, so the configuration of Non-Patent Document 2 cannot be applied as it is. In addition, in Non-Patent Document 2, the gate electrode is connected to the gate wiring disposed on the upper side of the channel via a through wiring that penetrates the channel and the SiO2 layer. Such wiring routing may cause delays and parasitic capacitance, which may cause problems in the operation of the terahertz frequency band as described above. In this state, no improvement in high frequency characteristics can be obtained.

[0011] In Non-Patent Document 3, a well region for forming an ohmic junction is formed by doping or diffusion, and an ohmic junction is formed on the back side of this well region. However, in order to sufficiently reduce the sheet resistance of the well region, it is necessary to perform an annealing process for dopant activation. In the case of HEMTs, particularly in the case of channels using InP or GaAs, due to the problem of thermal stability, if a high-temperature annealing process is performed as in the case of FETs using Si, the performance of the transistor may be degraded due to a decrease in impurity concentration caused by the diffusion of impurities in the carrier supply layer and diffusion of the gate electrode material.

[0012] The present invention has been made to solve the above problems, and has an object to realize a higher speed of a high electron mobility transistor without causing deterioration of the transistor characteristics. [Means for solving the problem]

[0013] The semiconductor device according to the present invention is composed of a field effect transistor including a first barrier layer made of a compound semiconductor, a channel layer made of a compound semiconductor formed on the first barrier layer, a second barrier layer made of a compound semiconductor formed on the channel layer, a gate electrode formed on the second barrier layer, a source electrode and a drain electrode formed on either side of the gate electrode, a first carrier supply layer formed on the first barrier layer side of the channel layer, a second carrier supply layer formed between the gate electrode and the channel layer, and a groove penetrating the first barrier layer in a region where the gate electrode is formed, and at least one of the source electrode and the drain electrode is formed on the first barrier layer side of the channel layer. Effect of the Invention

[0014] As described above, according to the present invention, a gate electrode is disposed on the second barrier layer that is disposed on the channel layer, and at least one of a source electrode and a drain electrode is disposed on the underside of a first barrier layer that is disposed below the channel layer, thereby achieving a further increase in the speed of a high electron mobility transistor without causing deterioration of the transistor characteristics. [Brief description of the drawings]

[0015] [Figure 1] FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention. [Diagram 2] Second Embodiment FIG. 2 is a cross-sectional view showing a configuration of a semiconductor device according to a second embodiment of the present invention. [Diagram 3] Third Embodiment FIG. 3 is a cross-sectional view showing a configuration of a semiconductor device according to a third embodiment of the present invention. [Figure 4] Fourth Embodiment FIG. 4 is a cross-sectional view showing a configuration of a semiconductor device according to a fourth embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Hereinafter, a semiconductor device according to an embodiment of the present invention will be described.

[0017] [Embodiment 1] First, a semiconductor device according to a first embodiment of the present invention will be described with reference to Fig. 1. This semiconductor device is a field effect transistor 100 including a first barrier layer 101 made of a compound semiconductor, a channel layer 102 made of a compound semiconductor formed on the first barrier layer 101, a second barrier layer 103 made of a compound semiconductor formed on the channel layer 102, a gate electrode 104 formed on the second barrier layer 103, and a source electrode 105 and a drain electrode 106 formed on either side of the gate electrode 104. The field effect transistor 100 is a so-called high electron mobility transistor (HEMT).

[0018] Here, the field effect transistor 100 includes a first carrier supply layer 107 formed on the first barrier layer 101 side of the channel layer 102, and a second carrier supply layer 108 formed between the gate electrode 104 and the channel layer 102. The first carrier supply layer 107 may be formed in the first barrier layer 101, and the second carrier supply layer 108 may be formed in the second barrier layer 103. The field effect transistor 100 also includes a groove 109 penetrating the first barrier layer 101, extending in the gate width direction, in a region where the gate electrode 104 is formed.

[0019] In the above-described configuration, in the semiconductor device according to the first embodiment, at least one of the source electrode 105 and the drain electrode 106 is formed on the side (lower side) of the first barrier layer 101 of the channel layer 102. Also, a part of at least one of the source electrode 105 and the drain electrode 106 is formed in contact with the first barrier layer 101. In this example, both the source electrode 105 and the drain electrode 106 are formed on the side (lower side) of the first barrier layer 101 of the channel layer 102. Also, a part of both the source electrode 105 and the drain electrode 106 is formed in contact with the first barrier layer 101. Hereinafter, the channel layer 102 is used as a reference, and the side of the first barrier layer 101 is referred to as the lower side, and the side of the second barrier layer 103 is referred to as the upper side.

[0020] In this example, the first barrier layer 101, the channel layer 102, and the second barrier layer 103 are formed in this order on the substrate 111. In this case, the groove 109 is formed penetrating the substrate 111 and the first barrier layer 101. In this example, the etching stop layer 110 is also provided. When the etching stop layer 110 is provided, the lower surface of the etching stop layer 110 is exposed by the groove 109. In this example, the gate electrode 104 is formed on (above) the second barrier layer 103 via the gate insulating layer 112.

[0021] For example, the substrate 111 may be made of semi-insulating InP. The first barrier layer 101 may be made of, for example, 1×10 Si. 19 ~2×10 19 cm -3 The first barrier layer 101 may be made of doped InGaAs. The first barrier layer 101 may have a thickness of 5 to 20 nm. The first carrier supply layer 107 may be made of the first barrier layer 101 doped with 1×10 Si as an impurity by well-known sheet doping. 12 cm -3 ~1×10 13 cm -3 It can be a doped layer (δ-doped layer). In general, a buffer layer (not shown) made of InAlAs and having a thickness of 100 to 300 nm is formed on the substrate 111, and the first barrier layer 101 is formed thereon.

[0022] The etching stop layer 110 may be made of InP and have a thickness of 2 to 5 nm. The channel layer 102 may be made of InGaAs and have a thickness of 5 to 20 nm. The channel layer 102 may have a composite structure of an InGaAs layer and an InAs layer. The second barrier layer 103 may be made of InAlAs and have a thickness of 5 to 20 nm. The second carrier supply layer 108 may be formed by doping the second barrier layer 103 with 1×10 ions of Si as an impurity by well-known sheet doping. 12 cm -3 ~1×10 13 cm -3 It may be a doped layer (δ-doped layer).

[0023] The compound semiconductor layers described above can be formed by crystal growth using metal organic chemical vapor deposition, molecular beam epitaxy, or the like.

[0024] The gate insulating layer 112 can be made of an oxide such as SiO2, SiN, Al2O3, HfO2, or TiO2, a nitride film, or a composite film of these. The thickness of the gate insulating layer 112 depends on the gate length, but can be about 1 to 10 nm.

[0025] The gate electrode 104 can be formed mainly from a composite structure of Ti, Pt, Au, and Mo. In order to achieve a short gate length while minimizing gate resistance, the gate electrode 104 can be T-shaped, Y-shaped, or Γ-shaped, with the upper part having a larger area than the lower part in a plan view. A gate insulating layer can also be formed on the etching stop layer.

[0026] The grooves 109 can be formed by etching from the back surface of the substrate 111. For example, a mask pattern having openings at locations where the grooves 109 are to be formed is formed by known lithography techniques. Using this mask pattern as a mask, the grooves 109 and the first barrier layer 101 are first removed by a well-known etching process, thereby forming the grooves 109.

[0027] For example, first, the substrate 111 is thinned to a certain extent by dry etching, and the thinned portion is selectively etched away by an etching process using a hydrochloric acid-based wet etching solution. In this etching process, the first barrier layer 101 made of InGaAs is hardly etched, so that the first barrier layer 101 functions as an etching stop layer, and the thinned portion of the substrate 111 made of InP can be selectively etched.

[0028] Next, the first barrier layer 101 is selectively etched away using, for example, an etching solution made of phosphoric acid and hydrogen peroxide, or an etching solution made of citric acid and hydrogen peroxide. In this etching process, the substrate 111 made of InP and the etching stop layer 110 made of InP are not etched. Therefore, the etching stop layer 110 functions as an etching stop layer, and the first barrier layer 101 can be selectively etched.

[0029] The center position of the groove 109 in plan view basically coincides with the center position of the gate electrode 104 formed on the upper side (front surface side) of the channel layer 102. The length of the groove 109 in the gate length direction can be approximately 20 to 200 nm, but in consideration of the difficulty of miniaturizing the back surface side processing, it can be approximately 10 to 20 μm. The groove 109 can also be filled with an insulating compound semiconductor formed by crystal regrowth, an insulating resin, or the like.

[0030] The source electrode 105 and the drain electrode 106 can be configured with a laminated structure of metals such as Ti, Pt, Au, and Ni. The source electrode 105 and the drain electrode 106 are formed in ohmic contact with the first barrier layer 101 in through holes formed in the substrate 111. The source electrode 105 and the drain electrode 106 are obtained by forming an electrode material conformally in the through holes formed in the substrate 111 at corresponding positions, or by forming the electrode material so as to fill the through holes.

[0031] According to the above-mentioned first embodiment, by providing the first barrier layer 101 below the channel layer 102 to which the source electrode 105 and the drain electrode 106 make a low-resistance ohmic junction, the gate electrode 104 can be arranged above the channel layer 102, and the source electrode 105 and the drain electrode 106 can be arranged below the channel layer 102. In this structure, since it is not necessary to form a well region that requires high-temperature treatment, it is possible to realize low-resistance ohmic junctions in the source electrode 105 and the drain electrode 106 without incurring thermal property deterioration that is a problem in compound semiconductors. According to the first embodiment, by arranging the gate electrode 104 above the channel layer 102 and arranging the source electrode 105 and the drain electrode 106 below the channel layer 102, a structure that reduces the parasitic capacitance between them can be formed without incurring property deterioration of the transistor, and the high-frequency characteristics can be further improved.

[0032] [Embodiment 2] Next, a semiconductor device according to a second embodiment of the present invention will be described with reference to Fig. 2. This semiconductor device is a field effect transistor 100a including a first barrier layer 101 made of a compound semiconductor, a channel layer 102 made of a compound semiconductor formed on the first barrier layer 101, a second barrier layer 103 made of a compound semiconductor formed on the channel layer 102, a gate electrode 104 formed on the second barrier layer 103, and a source electrode 105a and a drain electrode 106a formed on either side of the gate electrode 104.

[0033] In the second embodiment, similarly to the first embodiment, the field effect transistor 100a includes a first carrier supply layer 107 formed on the first barrier layer 101 side of the channel layer 102, and a second carrier supply layer 108 formed between the gate electrode 104 and the channel layer 102. The first carrier supply layer 107 may be formed in the first barrier layer 101, and the second carrier supply layer 108 may be formed in the second barrier layer 103. The field effect transistor 100a also includes a groove 109 penetrating the first barrier layer 101, extending in the gate width direction, in a region where the gate electrode 104 is formed.

[0034] At least one of the source electrode 105a and the drain electrode 106a is formed on the side (lower side) of the first barrier layer 101 of the channel layer 102. At least one of the source electrode 105a and the drain electrode 106a is formed in contact with the first barrier layer 101. In this example, both the source electrode 105a and the drain electrode 106a are formed on the side (lower side) of the first barrier layer 101 of the channel layer 102. Also, both the source electrode 105a and the drain electrode 106a are formed in contact with the first barrier layer 101. In the second embodiment, unlike the first embodiment, the substrate 111 is removed and a groove 109 is formed in the first barrier layer 101.

[0035] According to the second embodiment, since no grooves are formed in the substrate, finer grooves 109 can be formed, and control of the transistor characteristics becomes easier.

[0036] [Embodiment 3] Next, a semiconductor device according to a third embodiment of the present invention will be described with reference to Fig. 3. This semiconductor device is a field-effect transistor 100b including a first barrier layer 101 made of a compound semiconductor, a channel layer 102 made of a compound semiconductor formed on the first barrier layer 101, a second barrier layer 103 made of a compound semiconductor formed on the channel layer 102, a gate electrode 104 formed on the second barrier layer 103, and a source electrode 105a and a drain electrode 106a formed to sandwich the gate electrode 104.

[0037] In the second embodiment, similarly to the second embodiment described above, the field effect transistor 100b includes a first carrier supply layer 107 formed on the first barrier layer 101 side of the channel layer 102, and a second carrier supply layer 108 formed between the gate electrode 104 and the channel layer 102. The first carrier supply layer 107 may be formed in the first barrier layer 101, and the second carrier supply layer 108 may be formed in the second barrier layer 103. The field effect transistor 100b also includes a groove 109 penetrating the first barrier layer 101, which is formed to extend in the gate width direction, in the region where the gate electrode 104 is formed.

[0038] At least one of the source electrode 105a and the drain electrode 106a is formed on the side (lower side) of the first barrier layer 101 of the channel layer 102. At least one of the source electrode 105a and the drain electrode 106a is formed in contact with the first barrier layer 101. In this example, both the source electrode 105a and the drain electrode 106a are formed on the side (lower side) of the first barrier layer 101 of the channel layer 102. Also, both the source electrode 105a and the drain electrode 106a are formed in contact with the first barrier layer 101. Also in the third embodiment, similarly to the second embodiment, the substrate 111 is removed and a groove 109 is formed in the first barrier layer 101.

[0039] Furthermore, in the third embodiment, the source electrode 105a formed on the first barrier layer 101 side of the channel layer 102 is connected to a source wiring 115 formed on the upper side of the first barrier layer 101 via a through wiring 114 penetrating the first barrier layer 101, the channel layer 102, the second barrier layer 103, the first carrier supply layer 107, and the second carrier supply layer 108. Similarly, the drain electrode 106a formed on the first barrier layer 101 side of the channel layer 102 is connected to a drain wiring 117 formed on the upper side of the first barrier layer 101 via a through wiring 116 penetrating the first barrier layer 101, the channel layer 102, the second barrier layer 103, the first carrier supply layer 107, and the second carrier supply layer 108.

[0040] [Embodiment 4] Next, a semiconductor device according to a fourth embodiment of the present invention will be described with reference to Fig. 4. This semiconductor device includes two field-effect transistors 100, each of which shares a drain electrode 106. An interlayer insulating layer 119 is formed on the two field-effect transistors 100, and a gate wiring 120 is formed on the interlayer insulating layer 119. The gate wiring 120 is connected to the gate electrode 104 of each of the two field-effect transistors 100 by a through electrode formed to penetrate the interlayer insulating layer 119.

[0041] The interlayer insulating layer 119 can be made of a thermosetting or UV-curable resin, or an oxide or nitride-based material (insulating material) such as SiON or SiO2. The interlayer insulating layer 119 can typically have a thickness of several hundred nm to several μm. On the lower side of the channel layer 102 (the rear surface of the substrate 111), a source wiring is connected to the source electrode 105, and a drain wiring is connected to the drain electrode 106. These wirings can be made of a metal such as Au, Cu, or Al.

[0042] According to the fourth embodiment, in an integrated circuit in which a plurality of field effect transistors 100 are integrated, the source wiring and drain wiring can be arranged on the back surface side, so that the degree of freedom in layout is increased for the connection and connection distance between the gate electrodes 104 of adjacent field effect transistors 100, and it becomes possible to further reduce the electrical resistance and parasitic capacitance.

[0043] In addition, by appropriately laying out the source wiring and drain wiring, the degree of freedom in circuit design can be greatly improved. For example, in the case of a common-source circuit, by grounding the source wiring directly on the back surface, a more stable ground can be achieved than by grounding it on the front surface side. Also, in the drain power supply circuit, the bias can be handled using the wide area of ​​the drain wiring arranged on the back surface side, so not only does the degree of freedom in the front surface layout increase, but the application of thick back surface wiring also makes it possible to form wiring with a higher current capacity.

[0044] As described above, according to the present invention, a gate electrode is disposed on the second barrier layer disposed on the channel layer, and at least one of a source electrode and a drain electrode is disposed on the lower surface of a first barrier layer disposed below the channel layer, thereby making it possible to realize a high-speed high electron mobility transistor without causing deterioration of the transistor characteristics. According to the present invention, by forming the source electrode and drain electrode as ohmic electrodes on the back surface side without providing a well region as disclosed in Non-Patent Document 3, it becomes possible to reduce the parasitic capacitance generated between the gate electrode formed on the front surface side and improve the high frequency characteristics.

[0045] It should be noted that the present invention is not limited to the above-described embodiments, and it is apparent that many modifications and combinations can be made by a person having ordinary knowledge in the art within the technical concept of the present invention. [Explanation of symbols]

[0046] 100...field effect transistor, 101...first barrier layer, 102...channel layer, 103...second barrier layer, 104...gate electrode, 105...source electrode, 106...drain electrode, 107...first carrier supply layer, 108...second carrier supply layer, 109...groove, 110...etching stop layer, 111...substrate, 112...gate insulating layer.

Claims

1. a first barrier layer made of a compound semiconductor; a channel layer made of a compound semiconductor formed on the first barrier layer; a second barrier layer made of a compound semiconductor formed on the channel layer; a gate electrode formed on the second barrier layer; a source electrode and a drain electrode formed on either side of the gate electrode; a first carrier supply layer formed on the first barrier layer side of the channel layer; a second carrier supply layer formed between the gate electrode and the channel layer; a trench penetrating the first barrier layer in a region in which the gate electrode is formed; A field effect transistor comprising: At least one of the source electrode and the drain electrode is formed on the first barrier layer side of the channel layer. A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, A semiconductor device comprising two of the field effect transistors, each of which shares the drain electrode.

3. 3. The semiconductor device according to claim 1, At least one of the source electrode and the drain electrode is formed in contact with the first barrier layer.

4. The semiconductor device according to any one of claims 1 to 3, At least one of the source electrode and the drain electrode formed on the first barrier layer side of the channel layer is connected to a source wiring or a drain wiring formed on the upper side of the first barrier layer via a through wiring that penetrates the first barrier layer, the channel layer, the second barrier layer, the first carrier supply layer, and the second carrier supply layer. A semiconductor device comprising:

5. The semiconductor device according to any one of claims 1 to 4, the first carrier supply layer is formed in the first barrier layer; The second carrier supply layer is formed in the second barrier layer. A semiconductor device comprising:

6. The semiconductor device according to any one of claims 1 to 5, A semiconductor device, comprising: said first barrier layer, said channel layer, and said second barrier layer formed in this order on a substrate.

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