Semiconductor device manufacturing method

Abstract

Provided is a semiconductor device manufacturing method capable of suppressing variance in characteristics attributable to the concentration of carbon in a semiconductor substrate. This semiconductor device manufacturing method: includes a process in which trenches (11) are formed from an upper surface side of a first-conductivity-type semiconductor substrate (10), a process in which an insulated-gate-type electrode structure (6, 7) is embedded in the trenches (11), a process in which second-conductivity-type base regions (3) in contact with the trenches (11) are formed in an upper part of the semiconductor substrate (10), a process in which first-conductivity-type first main electrode regions (4) in contact with the trenches (11) are formed on top of the base regions (3), and a process in which a second-conductivity-type second main electrode region (9) is formed on a lower surface side of the semiconductor substrate (10); and adjusts manufacturing conditions of the base regions (3) and / or the second main electrode region (9) according to the concentration of carbon in the semiconductor substrate (10).

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] Semiconductor substrates (wafers) used in semiconductor devices inherently contain carbon as an unintended impurity element. The impurity concentration (carbon concentration) of carbon in a semiconductor substrate varies between wafer manufacturers due to differences in the manufacturing method of the semiconductor substrate for each wafer manufacturer. Furthermore, even in semiconductor substrates manufactured by the same wafer manufacturer, the carbon concentration varies between ingots of semiconductor crystal, and even in the same ingot, the carbon concentration varies depending on the part. When the carbon concentration of a semiconductor substrate differs, variations in characteristics occur due to the carbon concentration of the semiconductor substrate.

[0003] US Patent Publication No. 2009 / 0133633 discloses a method for forming a semiconductor device comprising implanting a prescribed dose of protons into a semiconductor substrate and annealing the semiconductor substrate according to a prescribed temperature profile, at least one of which is selected depending on a carbon-related parameter that is indicative of information regarding a carbon concentration within at least a portion of the semiconductor substrate.

[0004] Patent Document 2 discloses that even if the impurity densities of carbon and oxygen contained in the base wafer as the starting material are different, the composition ratio of various complex defects with different levels between processed wafers after electron beam irradiation is made equal, making it easy to adjust the variation in device characteristics. The crystal defects generated by irradiation with an electron beam or the like include a first complex defect consisting of vacancies and oxygen and a second complex defect consisting of carbon and oxygen, and the defect density of the crystal defects is set so that the signal peak intensity of the level of the first complex defect identified in the measurement by deep level transient spectroscopy is five times or more the signal peak intensity of the level of the second complex defect. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent Publication No. 2021-82829 [Patent Document 2] International Publication No. 2017 / 002619 Summary of the Invention [Problem to be solved by the invention]

[0006] However, Patent Documents 1 and 2 do not take into consideration adjusting the manufacturing conditions of the semiconductor region formed in the semiconductor substrate depending on the carbon concentration of the semiconductor substrate in order to suppress the variation in characteristics caused by the carbon concentration of the semiconductor substrate.

[0007] An object of the present invention is to provide a method for manufacturing a semiconductor device that can suppress variations in characteristics caused by the carbon concentration of a semiconductor substrate. [Means for solving the problem]

[0008] In order to achieve the above-mentioned object, one aspect of the present invention is a method for manufacturing a semiconductor device, comprising the steps of: (a) forming a trench from an upper surface side of a semiconductor substrate of a first conductivity type; (b) embedding an insulated gate electrode structure in the trench; (c) forming a base region of a second conductivity type in an upper part of the semiconductor substrate and in contact with the trench; (d) forming a first main electrode region of the first conductivity type in an upper part of the base region and in contact with the trench; and (e) forming a second main electrode region of the second conductivity type on a lower surface side of the semiconductor substrate, wherein a manufacturing condition of at least one of the base region and the second main electrode region is adjusted depending on a carbon concentration of the semiconductor substrate. Effect of the Invention

[0009] According to the present invention, it is possible to provide a method for manufacturing a semiconductor device that can suppress variations in characteristics caused by the carbon concentration of a semiconductor substrate. [Brief description of the drawings]

[0010] [Figure 1]1 is a plan view illustrating an example of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view taken along the line AA in FIG. [Diagram 3] 1 is a graph showing the carbon concentration dependence of collector-emitter saturation voltage. [Figure 4] 1 is a graph showing the carbon concentration dependence of turn-off loss. [Diagram 5] 1 is a graph showing the carbon concentration dependency of a diode forward voltage. [Figure 6] 1 is a graph showing the carbon concentration dependence of switching loss during reverse recovery operation. [Figure 7] 13 is another graph showing the carbon concentration dependence of the collector-emitter saturation voltage. [Figure 8] 13 is another graph showing the carbon concentration dependence of turn-off loss. [Figure 9] 11 is yet another graph showing the carbon concentration dependence of the collector-emitter saturation voltage. [Figure 10] 11 is yet another graph showing the carbon concentration dependence of turn-off loss. [Figure 11] 2A to 2C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 12] 12 is a cross-sectional view continuing from FIG. 11 for illustrating an example of the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 13] 13 is a cross-sectional view continuing from FIG. 12 for illustrating an example of the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 14] 14 is a cross-sectional view continuing from FIG. 13 for illustrating an example of the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 15] 15 is a cross-sectional view continuing from FIG. 14 for illustrating an example of the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 16] 16 is a cross-sectional view continuing from FIG. 15 for illustrating an example of the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 17]17 is a cross-sectional view continuing from FIG. 16 for illustrating an example of the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 18] 18 is a cross-sectional view continuing from FIG. 17 for illustrating an example of the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 19] 19 is a cross-sectional view continuing from FIG. 18 for illustrating an example of the method for manufacturing the semiconductor device according to the first embodiment. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the first and second embodiments of the present invention will be described with reference to the drawings. In the drawings referred to in the following description, the same or similar parts are denoted with the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc., differ from the actual ones. Therefore, the specific thickness and dimensions should be determined with reference to the following description. In addition, it goes without saying that the drawings include parts with different dimensional relationships and ratios.

[0012] In the following description, the "first main electrode region" and the "second main electrode region" are main electrode regions of a semiconductor element into which a main current flows in or out. The "first main electrode region" means a semiconductor region that becomes either an emitter region or a collector region in the case of an insulated gate bipolar transistor (IGBT). The "first main electrode region" means a semiconductor region that becomes either a source region or a drain region in the case of a field effect transistor (FET) or a static induction transistor (SIT). The "second main electrode region" means a region that becomes either an emitter region or a collector region that is not the first main electrode region in the case of an IGBT. The "second main electrode region" means a semiconductor region that becomes either a source region or a drain region that is not the first main electrode region in the case of a FET or a SIT. The "second main electrode region" means a region that becomes either an anode region or a cathode region that is not the first main electrode region in the case of an SI thyristor or a GTO. That is, if the "first main electrode region" is the source region, the "second main electrode region" means the drain region. If the "first main electrode region" is the emitter region, the "second main electrode region" means the collector region. If the "first main electrode region" is the anode region, the "second main electrode region" means the cathode region. Note that when the term "main electrode region" is simply used, it comprehensively means either the first main electrode region or the second main electrode region, whichever is technically and contextually appropriate.

[0013] In addition, the definitions of directions such as up and down in the following description are merely for the convenience of explanation and do not limit the technical idea of ​​the present invention. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read, and if it is rotated 180 degrees and observed, up and down are reversed and read.

[0014] In the following description, the first conductivity type is n-type and the second conductivity type is p-type. However, the conductivity types may be selected in the opposite relationship, with the first conductivity type being p-type and the second conductivity type being n-type. The + or - attached to n or p means that the semiconductor region has a relatively high or low impurity concentration, respectively, compared to a semiconductor region without + or -. However, even if the semiconductor regions have the same n and n attached, it does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same.

[0015] (First embodiment) <Structure of Semiconductor Device> 1 is a plan view of a part of an active region of a semiconductor device according to the first embodiment, seen from the top (front) side. As shown in FIG. 1, the semiconductor device according to the first embodiment includes a transistor section 101 including a transistor element such as an IGBT, and a diode section 102 including a diode element, on the same semiconductor chip. For example, the semiconductor device according to the first embodiment is a reverse conducting IGBT (RC-IGBT) including an IGBT as the transistor section 101 and a free wheel diode (FWD) connected in anti-parallel to the IGBT as the diode section 102, on the same semiconductor chip. The transistor section 101 and the diode section 102 may be arranged alternately in the left-right direction of FIG. 1.

[0016] Fig. 2 shows a cross section taken along line AA crossing the transistor portion 101 and the diode portion 102 in Fig. 1. As shown in Fig. 2, the semiconductor device according to the first embodiment includes a semiconductor substrate 10. The semiconductor substrate 10 is configured of a Si wafer made of single crystal silicon (Si) manufactured by, for example, a magnetic field applied Czochralski method (MCZ method) or the like.

[0017] The semiconductor substrate 10 is a first conductivity type (n -The transistor section 101 includes an n-type (n-type) drift layer 1. In the transistor section 101, an n-type accumulation layer 2 having a higher impurity concentration than the drift layer 1 is provided on the upper surface side of the drift layer 1. The lower surface of the accumulation layer 2 contacts the upper surface of the drift layer 1. By providing the accumulation layer 2, it is possible to increase the carrier injection enhancement effect (IE effect) and reduce the on-voltage.

[0018] In the transistor section 101, the upper surface side of the accumulation layer 2 is provided with a second conductivity type (p - The bottom surface of the base region 3 is in contact with the top surface of the accumulation layer 2. The top surface of the base region 3 is provided with an n + A first main electrode region (emitter region) 4 of a type is provided. The lower surface of the emitter region 4 contacts the upper surface of the base region 3. The impurity concentration of the emitter region 4 is higher than the impurity concentrations of the drift layer 1 and the accumulation layer 2.

[0019] On the other hand, in the diode section 102, no accumulation layer is provided on the upper surface side of the drift layer 1, unlike the transistor section 101. Note that an n-type accumulation layer having a higher impurity concentration than the drift layer 1 may also be provided on the upper surface side of the drift layer 1 of the diode section 102. - An anode region 13 having a gate insulating layer 13a is provided on the semiconductor substrate 10. A lower surface of the anode region 13 is in contact with an upper surface of the drift layer 1. The anode region 13 is provided up to the upper surface of the semiconductor substrate 10. The anode region 13 may be provided at the same depth as the base region 3 of the transistor portion 101 and with the same impurity concentration as the base region 3 of the transistor portion 101.

[0020] In the transistor section 101 and the diode section 102, a plurality of trenches 11 are provided at intervals from one another in the depth direction from the upper surface of the semiconductor substrate 10. In the transistor section 101, the trenches 11 reach the drift layer 1 through the emitter region 4, the base region 3, and the accumulation layer 2. The side surfaces (sidewalls) of the trenches 11 are in contact with the side surfaces of the emitter region 4, the base region 3, and the accumulation layer 2. In the diode section 102, the trenches 11 reach the drift layer 1 through the anode region 13. The side surfaces of the anode region 13 are in contact with the side surfaces of the trenches 11.

[0021] In the parallel direction of the trenches 11, a mesa portion constituted by an upper portion of the semiconductor substrate 10 is provided between adjacent trenches 11. The mesa portion is a region of the semiconductor substrate 10 sandwiched between adjacent trenches 11, and is a region above the deepest position of the trenches 11. The mesa portion of the transistor portion 101 is provided with an upper portion of the drift layer 1, an accumulation layer 2, a base region 3, and an emitter region 4. The mesa portion of the diode portion 102 is provided with an upper portion of the drift layer 1 and an anode region 13.

[0022] A gate insulating film 6 is provided so as to cover the bottom and side surfaces of the trench 11. As the gate insulating film 6, for example, any one of a silicon dioxide film (SiO2 film), a silicon oxynitride (SiON) film, a strontium oxide (SrO) film, a silicon nitride (Si3N4) film, an aluminum oxide (Al2O3) film, a magnesium oxide (MgO) film, an yttrium oxide (Y2O3) film, a hafnium oxide (HfO2) film, a zirconium oxide (ZrO2) film, a tantalum oxide (Ta2O5) film, and a bismuth oxide (Bi2O3) film, a single layer film or a composite film in which a plurality of these films are laminated can be used.

[0023] A gate electrode 7 is buried inside the trench 11 via a gate insulating film 6. The gate insulating film 6 and the gate electrode 7 form an insulated gate electrode structure (6, 7). The material for the gate electrode 7 can be, for example, a polysilicon film (doped polysilicon film) doped with a high concentration of impurities such as phosphorus (P) or boron (B).

[0024] Some of the insulated gate electrode structures (6, 7) in the transistor section 101 may be gate trench sections connected to a gate runner, and the remaining insulated gate electrode structures (6, 7) may be dummy trench sections not connected to a gate runner. Also, the insulated gate electrode structures (6, 7) in the diode section 102 may be dummy trench sections not connected to a gate runner.

[0025] 1, in a planar pattern, the trenches 11 have linear (striped) portions extending parallel to each other in one direction (the vertical direction in FIG. 1). In the diode section 102, the anode region 13 has linear (striped) portions extending parallel to the extension direction of the trenches 11. In the transistor section 101, p + Contact regions 5 and n + The emitter regions 4 are alternately and periodically arranged. The contact regions 5 are in contact with the emitter regions 4. The contact regions 5 are provided on the upper surface side of the base region 3 shown in FIG. 2. The lower surface of the contact region 5 is in contact with the upper surface of the base region 3. The impurity concentration of the contact region 5 is higher than that of the base region 3.

[0026] 2, an interlayer insulating film 20 is provided on the upper surfaces of the semiconductor substrate 10 and the insulated gate electrode structure (6, 7). The interlayer insulating film 20 is composed of a single layer film such as a non-doped silicon oxide film (SiO2 film) that does not contain phosphorus (P) or boron (B) and is called "NSG", a silicon oxide film with added phosphorus (PSG film), a silicon oxide film with added boron (BSG film), a silicon oxide film with added boron and phosphorus (BPSG film), a silicon nitride film (Si3N4 film), a high-temperature oxide film (HTO), or a laminated film thereof.

[0027] An interlayer insulating film 20 located on the mesa portion of the semiconductor substrate 10 is provided with a contact hole 20a penetrating the interlayer insulating film 20. A contact plug 30 such as tungsten (W) is embedded in the contact hole 20a via a titanium silicide (TiSi2) layer and a barrier metal film (not shown) such as titanium nitride (TiN). In the transistor portion 101, the lower surface of the contact plug 30 contacts the upper surfaces of the emitter region 4 and the contact region 5. In the diode portion 102, the lower surface of the contact plug 30 contacts the upper surface of the anode region 13.

[0028] A surface electrode 40 is provided on the interlayer insulating film 20. In the transistor section 101, the surface electrode 40 is electrically connected to the emitter region 4 and the contact region 5 via the contact plug 30, and functions as an emitter electrode. In the diode section 102, the surface electrode 40 is electrically connected to the anode region 13 via the contact plug 30, and functions as an anode electrode. A high-concentration p-type region may be provided between the contact plug 30 and the anode region 13. The surface electrode 40 can be made of metal such as aluminum (Al), an Al alloy, or copper (Cu). Examples of Al alloys include Al-silicon (Si), Al-copper (Cu)-Si, and Al-Cu.

[0029] 1, the interlayer insulating film 20, the contact plug 30, and the surface electrode 40 shown in FIG. 2 are omitted. In addition, in FIG. 1, the position of the contact hole 20a in the interlayer insulating film 20 shown in FIG. 2 is typically indicated by a dashed line. In a planar pattern, the contact hole 20a has a linear (striped) portion extending parallel to the longitudinal direction of the trench 11. In the transistor section 101, the contact hole 20a is provided on the upper surface side of the emitter region 4 and the contact region 5. In the diode section 102, the contact hole 20a is provided on the upper surface side of the anode region 13.

[0030] In the transistor section 101 and the diode section 102, an n-type field stop (FS) layer 8 having a higher impurity concentration than the drift layer 1 is provided on the lower surface side of the drift layer 1. The upper surface of the FS layer 8 is in contact with the lower surface of the drift layer 1. The FS layer 8 prevents a depletion layer spreading from the lower surface sides of the base region 3 and the anode region 13 from reaching a second main electrode region (collector region) 9 and a cathode region 12, which will be described later.

[0031] In the transistor section 101, the lower surface side of the FS layer 8 is provided with p + An n-type collector region 9 is provided. The upper surface of the collector region 9 is in contact with the lower surface of the FS layer 8. The impurity concentration of the collector region 9 is higher than the impurity concentration of the base region 3. On the other hand, in the diode section 102, an n-type collector region 9 having a higher impurity concentration than the FS layer 8 is provided on the lower surface side of the FS layer 8. + A molded cathode region 12 is provided. The upper surface of the cathode region 12 is in contact with the lower surface of the FS layer 8. The cathode region 12 is provided at the same depth as the FS layer 8. The side surface of the cathode region 12 is in contact with the side surface of the collector region 9.

[0032] A back electrode 50 is provided on the lower surface side of the collector region 9 and the cathode region 12. The back electrode 50 can be formed of, for example, a single layer film made of gold (Au) or a metal film laminated in the order of titanium (Ti), nickel (Ni), and gold (Au). The back electrode 50 functions as a collector electrode in the transistor section 101 and functions as a cathode electrode in the diode section 102.

[0033] 2, a lifetime control region 61 is provided inside the drift layer 1. The lifetime control region 61 is provided throughout the diode portion 102 and extends to a part of the transistor portion 101. The lifetime control region 61 may be provided only in the diode portion 102.

[0034] The FS layer 8 is provided with a lifetime control region 62. The lifetime control region 62 is provided uniformly over the entire transistor portion 101 and the diode portion 102, for example.

[0035] The lifetime control regions 61 and 62 are composed of crystal defects (point defects) formed by, for example, helium (He) or protons (hydrogen) injected as a lifetime killer. By providing the lifetime control regions 61 and 62, it is possible to improve and enhance the characteristics of the semiconductor device (for example, the diode forward voltage Vf of the FWD).

[0036] During operation of the semiconductor device according to the first embodiment, in the transistor portion 101, when the front electrode 40 is at ground potential, a positive voltage is applied to the back electrode 50, and a positive voltage equal to or greater than a threshold value is applied to the gate electrode 7, an inversion layer (channel) is formed on the side surface of the trench 11 in the base region 3, resulting in an ON state. In the ON state, a current flows from the back electrode 50 through the collector region 9, the FS layer 8, the drift layer 1, the accumulation layer 2, the inversion layer in the base region 3, and the emitter region 4 to the front electrode 40.

[0037] On the other hand, when the voltage applied to the gate electrode 7 is less than the threshold value, no inversion layer is formed in the base region 3, resulting in an off state and no current flowing from the back electrode 50 to the front electrode 40. The diode portion 102 passes a return current that conducts in the reverse direction when the transistor portion 101 is turned off.

[0038] 2, which is a base wafer, contains impurity elements such as carbon due to the manufacturing method of the semiconductor substrate 10, etc., although not intentionally added. The impurity concentration of carbon (carbon concentration) in the semiconductor substrate 10 is, for example, 1×10 15 atoms / cm 3 That's it, 3.5 x 10 15 atoms / cm 3 The carbon concentration in the semiconductor substrate 10 can be measured by, for example, secondary ion mass spectrometry (SIMS).

[0039] Depending on the carbon concentration of the semiconductor substrate 10, the characteristics of the IGBT constituting the transistor section 101 (hereinafter referred to as "IGBT characteristics") and the characteristics of the FWD constituting the diode section 102 (hereinafter referred to as "diode characteristics") change.

[0040] FIG. 3 shows the relationship between the carbon concentration of the semiconductor substrate 10 and the collector-emitter saturation voltage Vce(sat), which is an IGBT characteristic. As shown by the solid line in FIG. 3, the lower the carbon concentration of the semiconductor substrate 10, the lower the collector-emitter saturation voltage Vce(sat), and in the region of the semiconductor substrate 10 with a low carbon concentration, the collector-emitter saturation voltage Vce(sat) changes steeply and the amount of decrease is large. The dashed line in FIG. 3 shows the standard upper limit V1 of the collector-emitter saturation voltage Vce(sat). The standard upper limit V1 can be set appropriately according to the rated current of the semiconductor device according to the first embodiment. The collector-emitter saturation voltage Vce(sat) is adjusted to be equal to or lower than the standard upper limit V1.

[0041] FIG. 4 shows the relationship between the carbon concentration of the semiconductor substrate 10 and the turn-off loss Eoff, which is an IGBT characteristic. As shown by the solid line in FIG. 4, the lower the carbon concentration of the semiconductor substrate 10, the higher the turn-off loss Eoff. In the range of low carbon concentration of the semiconductor substrate 10, the turn-off loss Eoff changes steeply and increases greatly. That is, there is a trade-off relationship between the collector-emitter saturation voltage Vce(sat) shown in FIG. 3 and the turn-off loss Eoff shown in FIG. 4. The dashed line in FIG. 4 shows the standard upper limit E1 of the turn-off loss Eoff. The standard upper limit E1 can be set appropriately according to the rated current of the semiconductor device according to the first embodiment. The turn-off loss Eoff is adjusted to be equal to or lower than the standard upper limit E1.

[0042] FIG. 5 shows the relationship between the carbon concentration of the semiconductor substrate 10 and the diode forward voltage Vf, which is a diode characteristic. As shown by the solid line in FIG. 5, the lower the carbon concentration of the semiconductor substrate 10, the lower the diode forward voltage Vf, and in the region of the semiconductor substrate 10 with a low carbon concentration, the diode forward voltage Vf changes steeply and the amount of decrease is large. The dashed line in FIG. 5 shows the standard upper limit V2 of the diode forward voltage Vf, and the dashed line in FIG. 5 shows the standard lower limit V3 of the diode forward voltage Vf. The standard upper limit V2 and the standard lower limit V3 can be appropriately set according to the rated current of the semiconductor device according to the first embodiment. The diode forward voltage Vf is adjusted to be between the standard upper limit V2 and the standard lower limit V3.

[0043] FIG. 6 shows the relationship between the carbon concentration of the semiconductor substrate 10 and the switching loss Err during reverse recovery operation, which is a diode characteristic. As shown by the solid line in FIG. 6, the lower the carbon concentration of the semiconductor substrate 10, the higher the switching loss Err during reverse recovery operation. In the region of the semiconductor substrate 10 with a low carbon concentration, the switching loss Err during reverse recovery operation changes steeply and the increase amount is large. That is, there is a trade-off relationship between the diode forward voltage Vf shown in FIG. 5 and the switching loss Err during reverse recovery operation shown in FIG. 6. The dashed line in FIG. 6 shows the standard upper limit E2 of the switching loss Err during reverse recovery operation. The standard upper limit E2 can be appropriately set according to the rated current of the semiconductor device according to the first embodiment. The switching loss Err during reverse recovery operation is adjusted to be equal to or lower than the standard upper limit E2.

[0044] As described above, the carbon concentration of the semiconductor substrate 10 varies due to differences in the manufacturing method of the wafer (semiconductor substrate) for each wafer manufacturer. If the carbon concentration of the semiconductor substrate 10 varies greatly, for example, when a semiconductor substrate 10 with a low carbon concentration is used, the turn-off loss Eoff shown in FIG. 4 may exceed the standard upper limit value E1, resulting in a defective product. Also, when a semiconductor substrate 10 with a high carbon concentration is used, the collector-emitter saturation voltage Vce(sat) shown in FIG. 3 may exceed the standard upper limit value V1, resulting in a defective product.

[0045] In order to suppress such variations in characteristics due to the carbon concentration of the semiconductor substrate 10, in the manufacturing method of the semiconductor device according to the first embodiment, the carbon concentration of the semiconductor substrate 10 is acquired in advance, and the manufacturing conditions of the collector region 9 of the transistor portion 101 are determined (adjusted) depending on the carbon concentration of the semiconductor substrate 10. As the manufacturing conditions of the collector region 9, for example, the dose of ion implantation for forming the collector region 9 is adjusted. The adjustment amount of the dose of ion implantation for forming the collector region 9 can be set within a range of about ±10% of the dose before adjustment, for example.

[0046] FIG. 7 shows the relationship between the carbon concentration of the semiconductor substrate 10 and the collector-emitter saturation voltage Vce(sat) before and after adjusting the dose of the ion implantation for forming the collector region 9. The solid line in FIG. 7 shows the collector-emitter saturation voltage Vce(sat) before adjusting the dose of the ion implantation for forming the collector region 9, and the dotted line in FIG. 7 shows the collector-emitter saturation voltage Vce(sat) after adjusting the dose of the ion implantation for forming the collector region 9 to a lower value. As shown in FIG. 7, when the dose of the ion implantation for forming the collector region 9 is adjusted to a lower value, the collector-emitter saturation voltage Vce(sat) increases. Conversely, when the dose of the ion implantation for forming the collector region 9 is adjusted to a higher value, the collector-emitter saturation voltage Vce(sat) decreases.

[0047] FIG. 8 shows the relationship between the carbon concentration of the semiconductor substrate 10 and the turn-off loss Eoff before and after adjusting the dose of the ion implantation to form the collector region 9. The solid line in FIG. 8 shows the turn-off loss Eoff before adjusting the dose of the ion implantation to form the collector region 9, and the dotted line in FIG. 8 shows the turn-off loss Eoff after adjusting the dose of the ion implantation to form the collector region 9 to a lower value. As shown in FIG. 8, when the dose of the ion implantation to form the collector region 9 is adjusted to a lower value, the turn-off loss Eoff is reduced. Conversely, when the dose of the ion implantation to form the collector region 9 is adjusted to a higher value, the turn-off loss Eoff is increased.

[0048] Therefore, in the method for manufacturing the semiconductor device according to the first embodiment, the lower the carbon concentration of the semiconductor substrate 10, the lower the dose of the ion implantation for forming the collector region 9 is adjusted to reduce the turn-off loss Eoff and increase the collector-emitter saturation voltage Vce(sat). For example, when the carbon concentration of the semiconductor substrate 10 is relatively low and there is a possibility that the turn-off loss Eoff will exceed the standard upper limit E1, the dose of the ion implantation for forming the collector region 9 is adjusted to be lower to reduce the turn-off loss Eoff to be equal to or lower than the standard upper limit E1, and the collector-emitter saturation voltage Vce(sat) is increased within a range equal to or lower than the standard upper limit V1.

[0049] On the other hand, when the carbon concentration in the semiconductor substrate 10 is relatively high and there is a possibility that the collector-emitter saturation voltage Vce(sat) will exceed the standard upper limit V1, the dose of ion implantation for forming the collector region 9 is increased to reduce the collector-emitter saturation voltage Vce(sat) to the standard upper limit V1 or less, and to increase the turn-off loss Eoff to a range not exceeding the standard upper limit E1.

[0050] For example, it is determined whether or not the carbon concentration in the semiconductor substrate 10 is equal to or higher than a predetermined threshold, and the dose of ion implantation for forming the collector region 9 is adjusted according to the determination result. The predetermined threshold can be set appropriately according to the rated current of the semiconductor device according to the first embodiment, the standard upper limit V1 of the collector-emitter saturation voltage Vce(sat), the standard upper limit E1 of the turn-off loss Eoff, etc.

[0051] For example, when the carbon concentration of the semiconductor substrate 10 is equal to or higher than a predetermined threshold, the dose of the ion implantation for forming the collector region 9 is set to a first dose before adjustment. On the other hand, when the carbon concentration of the semiconductor substrate 10 is lower than the predetermined threshold, the dose of the ion implantation for forming the collector region 9 is adjusted to a second dose that is larger than the first dose. Note that the dose may be adjusted in multiple stages by setting a plurality of predetermined thresholds and comparing the carbon concentration of the semiconductor substrate 10 with the plurality of predetermined thresholds.

[0052] 9 shows the relationship between the carbon concentration of the semiconductor substrate 10 and the collector-emitter saturation voltage Vce(sat) before and after adjusting the dose of ion implantation to form the collector region 9 when a predetermined threshold N1 is set for the carbon concentration of the semiconductor substrate 10. FIG. 10 shows the relationship between the carbon concentration of the semiconductor substrate 10 and the turn-off loss Eoff before and after adjusting the dose of ion implantation to form the collector region 9 when a predetermined threshold N1 is set for the carbon concentration of the semiconductor substrate 10. In FIG. 9 and FIG. 10, the predetermined threshold N1 is 0.1×10 16 atoms / cm 3 However, it is not limited to this value.

[0053] 9 and 10, when the carbon concentration of the semiconductor substrate 10 is equal to or higher than a predetermined threshold N1, the dose of the ion implantation for forming the collector region 9 is maintained at a first dose (shown by a solid line in FIG. 9 and FIG. 10) before adjustment. On the other hand, when the carbon concentration of the semiconductor substrate 10 is lower than the predetermined threshold N1, the dose of the ion implantation for forming the collector region 9 is adjusted to a second dose (shown by a dotted line in FIG. 9 and FIG. 10) lower than the first dose. As a result, in a region where the carbon concentration of the semiconductor substrate 10 is lower than the predetermined threshold N1, the collector-emitter saturation voltage Vce(sat) can be increased within a range equal to or lower than the standard upper limit V1, while the turn-off loss Eoff can be reduced, as shown in FIG. 9 and FIG. 10.

[0054] <Method of Manufacturing Semiconductor Device> Next, an example of a method for manufacturing the semiconductor device according to the first embodiment will be described. Note that the method for manufacturing the semiconductor device described below is just one example, and it goes without saying that various other manufacturing methods, including modifications thereof, can be used within the scope of the spirit described in the claims.

[0055] First, as shown in FIG. - A semiconductor substrate 10 (type 100) is prepared. The semiconductor substrate 10 is a Si wafer made of single crystal Si manufactured by, for example, the magnetic field applied Czochralski method (MCZ method) or the like. Here, before the step of forming a collector region 9, which will be described later, the carbon concentration of the semiconductor substrate 10 is obtained in advance. The carbon concentration of the semiconductor substrate 10 may be obtained by measurement or through a wafer manufacturer. The carbon concentration of the semiconductor substrate 10 can be measured by, for example, secondary ion mass spectrometry (SIMS) or the like.

[0056] Next, by photolithography and dry etching, a portion of the drift layer 1 is selectively removed from the upper surface side of the semiconductor substrate 10. As a result, a plurality of trenches 11 are formed in the upper part of the semiconductor substrate 10, as shown in FIG.

[0057] Next, a gate insulating film 6 is formed on the bottom and side surfaces of the trench 11 by thermal oxidation or chemical vapor deposition (CVD). Next, a polysilicon film (doped polysilicon film) doped with a high concentration of impurities such as phosphorus (P) or boron (B) is deposited by CVD or the like so as to fill the inside of the trench 11 via the gate insulating film 6. Thereafter, the polysilicon film and the gate insulating film 6 on the semiconductor substrate 10 are selectively removed by photolithography and dry etching. As a result, an insulated gate electrode structure (6, 7) consisting of the gate insulating film 6 and a gate electrode 7 of a polysilicon film is formed inside the trench 11, as shown in FIG. 13.

[0058] Next, the p - The p-type base region 3 and the diode portion 102 -At the same time, p-type impurities such as boron (B) are ion-implanted to simultaneously form the anode region 13. Thereafter, the photoresist film is removed.

[0059] Next, a photoresist film is applied to the upper surface of the drift layer 1, and the photoresist film is patterned by photolithography. Using the patterned photoresist film as an ion implantation mask, n-type impurities such as phosphorus (P) or arsenic (As) are ion-implanted to form the n-type accumulation layer 2 of the transistor section 101. Thereafter, the photoresist film is removed.

[0060] Next, a photoresist film is applied to the upper surface of the drift layer 1, and the photoresist film is patterned by photolithography. The patterned photoresist film is used as a mask for ion implantation to implant p + In order to form a p-type contact region 5 (see FIG. 1), a p-type impurity such as boron (B) is ion-implanted, and then the photoresist film is removed.

[0061] Next, a photoresist film is applied to the upper surface of the drift layer 1, and the photoresist film is patterned by photolithography. The patterned photoresist film is used as an ion implantation mask to implant n-type ions of the transistor portion 101. + An n-type impurity is ion-implanted to form an n-type emitter region 4. Thereafter, the photoresist film is removed. Note that the order of the ion implantation to form the accumulation layer 2, the ion implantation to form the base region 3 and the anode region 13, the ion implantation to form the emitter region 4, and the ion implantation to form the contact region 5 is not particularly limited, and the order may be changed.

[0062] Next, the impurity ions implanted in the semiconductor substrate 10 are activated by heat treatment. As a result, as shown in FIG. 14, in the transistor section 101, an n-type accumulation layer 2 and a p - Base region of type 3, n + Type emitter region 4 and p +In the diode section 102, a p-type contact region 5 (see FIG. 1) is formed on the upper part of the semiconductor substrate 10. - A molded anode region 13 is formed.

[0063] Next, an interlayer insulating film 20 is formed on the upper surfaces of the insulated gate electrode structure (6, 7), the emitter region 4, the contact region 5, and the anode region 13 by a CVD method or the like. Next, a photoresist film is applied to the upper surface of the interlayer insulating film 20, and the photoresist film is patterned using a photolithography technique. Using the patterned photoresist film as an etching mask, a portion of the interlayer insulating film 20 is selectively removed by dry etching. As a result, a contact hole 20a is opened in the interlayer insulating film 20, as shown in FIG.

[0064] Next, the contact plug 30 is embedded in the contact hole 20a via a barrier metal film by sputtering or vapor deposition, dry etching, etc. Next, the surface electrode 40 is deposited on the upper surface of the contact plug 30 and the interlayer insulating film 20 by sputtering or vapor deposition, etc., as shown in FIG.

[0065] Next, the semiconductor substrate 10 is ground from the bottom side by chemical mechanical polishing (CMP) or the like to adjust the thickness of the semiconductor substrate 10 to the product thickness. Next, n-type impurities such as phosphorus (P) or selenium (Se) are ion-implanted over the entire bottom surface of the semiconductor substrate 10 to form an n-type FS layer 8.

[0066] Next, p + In order to form the p-type collector region 9, p-type impurities such as boron (B) are ion-implanted. Here, as described above, depending on the carbon concentration of the semiconductor substrate 10, + The conditions for forming the collector region 9, such as the dose of ion implantation for forming the collector region 9, are adjusted. For example, the lower the carbon concentration of the semiconductor substrate 10, the greater the p +The dose of ion implantation for forming collector region 9 of the mold is adjusted to a low value, and ion implantation is performed at the adjusted dose.

[0067] Next, a photoresist film is applied to the lower surface of the drift layer 1, and the photoresist film is patterned by photolithography. The patterned photoresist film is used as an ion implantation mask to implant n + Then, n-type impurities such as phosphorus (P) are ion-implanted to form a cathode region 12 of the n-type.

[0068] Next, the impurity ions implanted in the semiconductor substrate 10 are activated by heat treatment. As a result, an n-type FS layer 8 is formed in the lower part of the semiconductor substrate 10, as shown in FIG. 17. In addition, in the transistor portion 101, + A collector region 9 of the n-type is formed in the diode portion 102. + The cathode region 12 is formed. Note that the ion implantation for forming the FS layer 8 is carried out by p + ion implantation to form a collector region 9 of type n + The order of ion implantation for forming the cathode region 12 of the mold is not particularly limited, and the order may be changed.

[0069] 18, a shielding film 60 such as aluminum is used as a mask to irradiate the semiconductor substrate 10 from the upper surface side with a particle beam of a light element such as helium (He) or protons (H), thereby selectively forming a lifetime control region 61. Note that the shielding film 60 may be disposed on the lower surface side of the semiconductor substrate 10, and the particle beam may be irradiated from the lower surface side of the semiconductor substrate 10, rather than from the upper surface side. Alternatively, a particle beam such as an electron beam may be irradiated. Thereafter, the shielding film 60 is removed.

[0070] 19, a particle beam of a light element such as helium (He) or proton (H) is irradiated from the lower surface side of the semiconductor substrate 10 to uniformly form a lifetime control region 62 inside the FS layer 8. The particle beam may be irradiated from the upper surface side of the semiconductor substrate 10 instead of from the lower surface side. Alternatively, a particle beam such as an electron beam may be irradiated. The lifetime control region 62 may be provided inside the drift layer 1.

[0071] Next, a heat treatment (annealing) is performed. The annealing may be performed in an atmosphere containing hydrogen. The formation of crystal defects in the lifetime control regions 61 and 62 is adjusted by the annealing to obtain a desired lifetime.

[0072] Next, a back electrode 50 made of gold (Au) or the like is formed by sputtering, vapor deposition, or the like on the entire lower surface of the semiconductor substrate 10. Thereafter, the semiconductor substrate 10 is cut (diced) into individual pieces, thereby completing the semiconductor device according to the first embodiment shown in FIGS.

[0073] According to the method for manufacturing the semiconductor device according to the first embodiment, the carbon concentration of the semiconductor substrate 10 is obtained in advance, and the manufacturing conditions for the collector region 9 are adjusted depending on the obtained carbon concentration. This makes it possible to suppress the variation in the IGBT characteristics caused by the carbon concentration of the semiconductor substrate, even if the carbon concentration of the semiconductor substrate 10 varies.

[0074] Furthermore, in the RC-IGBT, adjusting the irradiation conditions of the light elements when forming the lifetime control regions 61, 62 in order to suppress the variation in the IGBT characteristics caused by the carbon concentration of the semiconductor substrate may affect the diode characteristics (e.g., diode forward voltage Vf) of the diode portion 102. In contrast, according to the manufacturing method of the semiconductor device according to the first embodiment, by adjusting the manufacturing conditions of the collector region 9 formed only in the transistor portion 101, it is possible to suppress the variation in the IGBT characteristics of the transistor portion 101 while suppressing the effect on the diode characteristics of the diode portion 102 without increasing the number of steps.

[0075] Second embodiment The configuration of the semiconductor device according to the second embodiment is similar to that of the semiconductor device according to the first embodiment shown in Figures 1 and 2. The manufacturing method of the semiconductor device according to the second embodiment differs from the manufacturing method of the semiconductor device according to the first embodiment in that, instead of adjusting the manufacturing conditions of the collector region 9 of the transistor portion 101 depending on the carbon concentration of the semiconductor substrate 10, the manufacturing conditions of the base region 3 of the transistor portion 101 are adjusted.

[0076] For example, the conditions for forming the base region 3, such as the dose of ion implantation for forming the base region 3, are adjusted depending on the carbon concentration of the semiconductor substrate 10. The adjustment amount of the dose can be set within a range of, for example, about ±10% of the dose before adjustment. As shown in FIG. 15, the base region 3 of the transistor section 101 and the anode region 13 of the diode section are simultaneously formed by a common ion implantation. However, since the adjustment amount of the dose is small, the effect on the diode characteristics of the diode section 102 is small.

[0077] When the dose of ion implantation for forming the base region 3 is adjusted to be high, the gate threshold Vth increases, so that the collector-emitter saturation voltage Vce(sat) increases and the turn-off loss Eoff decreases. Conversely, when the dose of ion implantation for forming the base region 3 is adjusted to be low, the gate threshold Vth decreases, so that the collector-emitter saturation voltage Vce(sat) decreases and the turn-off loss Eoff increases.

[0078] Therefore, in the manufacturing method of the semiconductor device according to the second embodiment, the lower the carbon concentration of the semiconductor substrate 10, the higher the dose of the ion implantation for forming the base region 3 is adjusted to reduce the turn-off loss Eoff and increase the collector-emitter saturation voltage Vce(sat). For example, when the carbon concentration of the semiconductor substrate 10 is relatively low and there is a possibility that the turn-off loss Eoff will exceed the standard upper limit E1, the dose of the ion implantation for forming the base region 3 is adjusted to be higher to reduce the turn-off loss Eoff to the standard upper limit E1 or less and increase the collector-emitter saturation voltage Vce(sat) within the range of the standard upper limit V1 or less.

[0079] On the other hand, when the carbon concentration of the semiconductor substrate 10 is relatively high and there is a possibility that the collector-emitter saturation voltage Vce(sat) will exceed the standard upper limit V1, the dose of ion implantation for forming the base region 3 is lowered to reduce the collector-emitter saturation voltage Vce(sat) to the standard upper limit V1 or less, and the turn-off loss Eoff is increased within a range not exceeding the standard upper limit E1.

[0080] For example, it is determined whether the carbon concentration in the semiconductor substrate 10 is equal to or higher than a predetermined threshold, and depending on the determination result, the dose of ion implantation for forming the base region 3 is adjusted. The predetermined threshold can be set appropriately depending on the rated current of the semiconductor device according to the first embodiment, the standard upper limit V1 of the collector-emitter saturation voltage Vce(sat), the standard upper limit E1 of the turn-off loss Eoff, etc.

[0081] For example, when the carbon concentration of the semiconductor substrate 10 is equal to or higher than a predetermined threshold, the dose of the ion implantation for forming the base region 3 is set to a first dose before adjustment. On the other hand, when the carbon concentration of the semiconductor substrate 10 is lower than the predetermined threshold, the dose of the ion implantation for forming the base region 3 is adjusted to a second dose that is larger than the first dose. Note that the dose may be adjusted in multiple stages by setting multiple predetermined thresholds and comparing the carbon concentration of the semiconductor substrate 10 with the multiple predetermined thresholds.

[0082] Other steps of the method for manufacturing a semiconductor device according to the second embodiment are similar to those of the method for manufacturing a semiconductor device according to the first embodiment shown in FIGS. 11 to 19, and therefore will not be described again.

[0083] According to the manufacturing method of the semiconductor device according to the second embodiment, it is possible to reduce defects by adjusting the manufacturing conditions of the base region 3 instead of adjusting the manufacturing conditions of the collector region 9 depending on the carbon concentration of the semiconductor substrate 10. Furthermore, compared to the case where the manufacturing conditions of the collector region 9 are adjusted, it is possible to suppress the influence on the contact resistance of the collector region 9.

[0084] Furthermore, in the RC-IGBT, by adjusting the manufacturing conditions of the base region 3 of the transistor section 101, it is possible to suppress the variation in the IGBT characteristics of the transistor section 101 while minimizing the effect on the diode characteristics of the diode section 102 having the anode region 13 formed simultaneously with the base region 3, without increasing the number of steps.

[0085] In the method for manufacturing the semiconductor device according to the second embodiment, the dose of ion implantation for forming the base region 3 is adjusted instead of adjusting the conditions for forming the collector region 9, but the acceleration voltage of ion implantation for forming the base region 3 may be adjusted depending on the carbon concentration of the semiconductor substrate 10. For example, the lower the carbon concentration of the semiconductor substrate 10, the higher the acceleration voltage of ion implantation for forming the base region 3 is adjusted to implant ions at a deeper position, thereby lowering the gate threshold voltage Vth.

[0086] For example, it is determined whether the carbon concentration of the semiconductor substrate 10 is equal to or higher than a predetermined threshold, and the acceleration voltage of the ion implantation for forming the base region 3 is adjusted according to the determination result. The predetermined threshold can be appropriately set according to the rated current of the semiconductor device according to the first embodiment, the standard upper limit V1 of the collector-emitter saturation voltage Vce(sat), the standard upper limit E1 of the turn-off loss Eoff, and the like. For example, when the carbon concentration of the semiconductor substrate 10 is equal to or higher than the predetermined threshold, the acceleration voltage of the ion implantation for forming the base region 3 is set to the first acceleration voltage before adjustment. On the other hand, when the carbon concentration of the semiconductor substrate 10 is less than the predetermined threshold, the acceleration voltage of the ion implantation for forming the base region 3 is adjusted to a second acceleration voltage higher than the first acceleration voltage. Note that the acceleration voltage may be adjusted in multiple stages by setting a plurality of predetermined thresholds and comparing the carbon concentration of the semiconductor substrate 10 with the plurality of predetermined thresholds.

[0087] In addition, both the dose of ion implantation for forming collector region 9 and the dose of ion implantation for forming base region 3 may be adjusted according to the carbon concentration of semiconductor substrate 10. In addition, the dose of ion implantation for forming collector region 9, the dose of ion implantation for forming base region 3, and the acceleration voltage of ion implantation for forming base region 3 may each be adjusted according to the carbon concentration of semiconductor substrate 10.

[0088] (Other embodiments) Although the first and second embodiments have been described above, the description and drawings forming part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments, examples and operating techniques will become apparent to those skilled in the art from this disclosure.

[0089] For example, although an RC-IGBT has been exemplified as the semiconductor device according to the first and second embodiments, the present invention can be applied to IGBTs other than the RC-IGBT. For example, the present invention can be applied to an IGBT alone. Even in the case of an IGBT alone, the variation in IGBT characteristics can be suppressed by adjusting the dose of at least one of the collector region 9 and the base region 3.

[0090] In addition, the configurations disclosed in the first and second embodiments can be appropriately combined within a range that does not cause a contradiction. As such, the present invention naturally includes various embodiments not described here. Therefore, the technical scope of the present invention is determined only by the invention-specifying matters related to the claims that are appropriate from the above description. [Explanation of symbols]

[0091] 1. Drift layer 2…Accumulation layer 3...Base area 4…Emitter area 5…Contact area 6...Gate insulating film 7...Gate electrode 8...Field stop layer 9…Collector region 10...Semiconductor substrate 11. Trench 12…Cathode region 13...Anode region 20...Interlayer insulating film 20a…Contact hole 30…Contact plug 40…Surface electrode 50…Back electrode 60…shielding film 61,62…Lifetime control area 101...Transistor section 102...Diode section

Claims

1. forming a trench from an upper surface side of a first conductivity type semiconductor substrate; embedding an insulated gate electrode structure in the trench; forming a second conductivity type base region in contact with the trench in an upper portion of the semiconductor substrate; forming a first main electrode region of a first conductivity type on an upper portion of the base region and in contact with the trench; forming a second main electrode region of a second conductivity type on a lower surface side of the semiconductor substrate; Including, A method for manufacturing a semiconductor device, comprising adjusting a manufacturing condition for at least one of said base region and said second main electrode region depending on a carbon concentration of said semiconductor substrate.

2. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the manufacturing condition is a dose of ion implantation for forming the second main electrode region.

3. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the manufacturing condition is a dose of ion implantation for forming the base region.

4. 4. The method for manufacturing a semiconductor device according to claim 2, wherein the dose is made smaller as the carbon concentration is lower.

5. 4. The method for manufacturing a semiconductor device according to claim 2, wherein when the carbon concentration is less than a predetermined threshold, the dose is made lower than when the carbon concentration is equal to or greater than the predetermined threshold.

6. 3. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of implanting a light element into the semiconductor substrate.

7. 7. The method for manufacturing a semiconductor device according to claim 6, wherein the light element is helium or proton.

8. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a reverse conducting insulated gate bipolar transistor further comprising a diode portion provided on the semiconductor substrate.

9. 9. The method for manufacturing a semiconductor device according to claim 8, further comprising the step of forming an anode region of the diode portion simultaneously with the step of forming the base region.

10. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is manufactured by a Czochralski method using an applied magnetic field.

11. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the manufacturing condition is an acceleration voltage for forming the base region.

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