Memory and manufacturing method thereof

Abstract

The present disclosure relates to the field of semiconductor technology, and provides a memory and a manufacturing method thereof that solves the technical problem of the difficulty of manufacturing word lines, the manufacturing method including: forming a stacked structure on a substrate, the stacked structure including a sacrificial layer and an active layer alternately stacked in a first direction; removing a part of the stacked structure located in a first region to form a plurality of first trenches spaced apart and extending in a second direction, the first trenches exposing the substrate to separate the active layer located in the first region into a plurality of active pillars spaced apart; removing the sacrificial layers located in the first region and the second region to remove a part of the active layer located in the second region to form a plurality of step-shaped connection layers at an end of the second region away from the first region; and forming a gate material layer covering the connection layers and the active pillars. The gate material layer is used as the word line, and the connection layers are provided to facilitate the manufacturing and drawing out of the word line.

Description

[Technical field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to a Chinese patent application filed with the China Patent Office on March 23, 2022, bearing application number 202210289745.9 and entitled "Memory and its manufacturing method", the entire contents of which are incorporated herein by reference.

[0002] The present application relates to the field of semiconductor technology, and more particularly to memories and methods for manufacturing the same. [Background technology]

[0003] 2. Description of the Related Art With the development of semiconductor technology, memories, especially dynamic random access memories (DRAMs), have been widely applied to various electronic devices due to their high storage density and fast read / write speed.

[0004] A DRAM typically includes multiple memory cells, each of which includes a transistor and a capacitor. The gate of the transistor is electrically connected to a word line (WL) of the DRAM, and the transistor is controlled to be turned on and off by the voltage of the word line. One of the source and drain of the transistor is electrically connected to a bit line (BL), and the other of the source and drain is electrically connected to a capacitor, and data information is stored or output via the bit line.

[0005] To further miniaturize memories and increase storage density, it is common to place the capacitors horizontally to facilitate fabrication of large aspect ratio capacitors, but fabrication of matching word lines is difficult. Summary of the Invention

[0006] In view of this, the embodiments of the present disclosure provide a memory and a manufacturing method thereof for reducing the manufacturing difficulty of word lines.

[0007] According to some embodiments, a first aspect of the present disclosure provides a method for manufacturing a memory, the method comprising: Providing a substrate; forming a layered structure on the substrate, the layered structure including sacrificial layers and active layers alternately stacked in a first direction; removing a portion of the stack in a first region to form a plurality of spaced apart first trenches extending in a second direction, the first trenches exposing the substrate to separate the active layer in the first region into a plurality of spaced apart active pillars; removing the sacrificial layer located in the first region and the second region by using the first trench, so that the active pillar located in the first region and the active layer in the second region are both spaced apart from each other along the first direction, and the second region is adjacent to the first region; removing a portion of the active layer located in the second region to form a plurality of step-shaped connection layers at an end of the second region away from the first region; forming a gate material layer covering the connection layer and the active pillar, wherein the connection layer located at the same hierarchical level and the gate material layer formed on the active pillar are in communication with each other, and the connection layer located at different hierarchical levels and the gate material layer formed on the active pillar are isolated from each other.

[0008] The memory manufacturing method provided by the embodiments of the present disclosure has at least the following advantages: In a method for manufacturing a memory provided by an embodiment of the present disclosure, a stacked structure is formed on a substrate, the stacked structure includes a sacrificial layer and an active layer alternately stacked in a first direction, and a part of the sacrificial layer and the active layer is removed so that the active layer located in the first region forms a plurality of active pillars spaced apart from each other, and the active layer located in the second region forms a plurality of step-shaped connection layers. Next, a gate material layer is formed on the connection layers and the active pillars, and the connection layers and the gate material layers formed on the active pillars located at the same hierarchical level are connected to each other, and the connection layers and the gate material layers formed on the active pillars located at different hierarchical levels are isolated from each other. By using the gate material layer as a word line and providing a connection layer, it is easy to manufacture and draw out the word line. In addition, since the end of the plurality of connection layers away from the first region is step-shaped, the end of the gate material layer covering the active pillars and the connection layer away from the first region is also step-shaped, that is, since the word line is step-shaped, it is easy to form other structures on the word line, and electrical connection between the word line and the peripheral circuit can be realized.

[0009] According to some embodiments, a second aspect of the present disclosure provides a memory having adjacent first and second regions, the memory including: a plurality of connection layers located in the second region and spaced apart along a first direction, where ends of the plurality of connection layers remote from the first region are formed in a stepped shape; a plurality of active pillar layers located in the first region and spaced apart along the first direction, where each of the active pillar layers is provided in the same layer as one of the connection layers, each of the active pillar layers has a plurality of active pillars spaced apart from each other, and each of the active pillars extends along a second direction; and a gate material layer located on the connection layers and on the active pillars, where the connection layers located at the same hierarchical level and the gate material layer formed on the active pillars are in communication with each other, and the connection layers located at different hierarchical levels and the gate material layer formed on the active pillars are isolated from each other.

[0010] The memory provided by the embodiments of the present disclosure has at least the following advantages: In the memory provided by the embodiment of the present disclosure, by providing a gate material layer on the connection layer and on the active pillar, the connection layer located at the same hierarchical level and the gate material layer formed on the active pillar are communicated with each other, and the connection layer located at different hierarchical levels and the gate material layer formed on the active pillar are isolated from each other. By using the gate material layer as the word line and providing the connection layer, the word line can be easily manufactured and drawn out. In addition, since the end of the multiple connection layers away from the first region is stepped, the end of the gate material layer covering the active pillar and the connection layer away from the first region is also stepped, that is, since the word line is stepped, it is easy to form other structures on the word line, and electrical connection between the word line and the peripheral circuit can be realized. [Brief description of the drawings]

[0011] [Figure 1] FIG. 2 is an architecture diagram of a memory according to an embodiment of the present disclosure. [Diagram 2] 1 is a flowchart of a method for manufacturing a memory according to an embodiment of the present disclosure. [Diagram 3] FIG. 2 is a schematic diagram of a first region and a second region after a laminate structure is formed in an embodiment of the present disclosure. [Figure 4] FIG. 2 is an exemplary schematic diagram of a first region and a second region after a first trench is formed in an embodiment of the present disclosure. [Diagram 5] FIG. 4 is another schematic diagram of the first region and the second region after the formation of the first trench in an embodiment of the present disclosure. [Figure 6] FIG. 2 is an illustrative schematic diagram of a first region and a second region after a protective layer is formed in an embodiment of the present disclosure. [Figure 7] FIG. 2 is an exemplary schematic diagram of a first region and a second region after a first mask layer is formed in an embodiment of the present disclosure. [Figure 8] FIG. 2 is an exemplary schematic diagram of a first region and a second region after removing a sacrificial layer in an embodiment of the present disclosure. [Figure 9]4 is an illustrative schematic diagram of a first region and a second region after a connection layer is formed in an embodiment of the present disclosure. FIG. [Figure 10] FIG. 2 is an exemplary schematic diagram of a first region and a second region after forming a gate material layer in one embodiment of the present disclosure. [Figure 11] FIG. 2 is an illustrative schematic diagram of a first region and a second region after a contact plug is formed in an embodiment of the present disclosure. [Figure 12] FIG. 4 is an illustrative schematic diagram of a third region after a laminated structure is formed in an embodiment of the present disclosure. [Figure 13] FIG. 2 is an illustrative schematic diagram of a third region after a protective layer is formed in an embodiment of the present disclosure. [Figure 14] FIG. 4 is an illustrative schematic diagram of a third region after a first mask layer is formed in an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] In the related art, in order to further increase the memory capacity of the memory, it is common to arrange the capacitor horizontally, i.e., the extension direction of the capacitor is parallel to the substrate, which makes it easier to manufacture the capacitor, but when the capacitor is arranged horizontally, the corresponding word line needs to be arranged again, which makes the manufacturing of the word line more difficult.

[0013] In view of the above, the embodiments of the present disclosure provide a memory and a manufacturing method thereof, forming a connection layer and an active pillar, and an end of the connection layer remote from the active pillar is stepped, and forming a gate material layer on the connection layer and the gate material layer of the active pillar, so that the connection layer and the gate material layer formed on the active pillar located at the same hierarchical level are communicated with each other, and the connection layer and the gate material layer formed on the active pillar located at different hierarchical levels are isolated from each other. By using the gate material layer as a word line, it is easy to manufacture and draw out, and since the word line is stepped, it is easy to form other structures on the word line, and electrical connection between the word line and the peripheral circuit can be realized.

[0014] In order to make the above objectives, features and advantages of the embodiments of the present disclosure more easily understandable, the following will more clearly and completely describe the technical solutions in the embodiments of the present disclosure with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, and are not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative efforts are within the scope of protection of the present disclosure.

[0015] In a first aspect of an embodiment of the present disclosure, a method for manufacturing a memory is provided, the memory including a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, an electrically erasable programmable read-only memory (EEPROM), a phase change random access memory (PRAM), a magneto-resistive random access memory (MRAM), etc. The embodiment of the present disclosure will be described taking a DRAM as an example.

[0016] Referring to FIG. 1, the memory includes a word line 4, a bit line 1, a transistor 2, and a capacitor 3, where the gate of the transistor 2 is electrically connected to the word line 4, one of the source and drain of the transistor 2 is electrically connected to the bit line 1, and the other is electrically connected to the capacitor 3. The word line 4 is used to control the transistor 2 to be on or off, and the bit line 1 is used to write data information to the capacitor 3 or read data information in the capacitor 3. As shown in FIG. 1, the transistor 2 and the capacitor 3 both extend along a second direction (Z direction shown in FIG. 1), which is parallel to the substrate, i.e., the transistor 2 and the capacitor 3 are both provided parallel to the substrate, so that it is easy to manufacture the capacitor 3 with a large aspect ratio, thereby increasing the storage capacity of the memory.

[0017] Referring to FIG. 2, FIG. 2 is a flowchart of a memory manufacturing method in one embodiment of the present disclosure, and the manufacturing method may include the following steps.

[0018] In step S10, a substrate is provided.

[0019] Referring to FIG. 3, the substrate 10 can provide a support base for structural layers on the substrate 10, and the material of the substrate 10 can be a semiconductor, for example, the material of the substrate 10 can be single crystal silicon, polycrystalline silicon, polysilicon, amorphous silicon, germanium, silicon carbide, silicon germanium (SiGe: Silicon Germanium), germanium on insulator (GOI: Germanium on Insulator), or silicon on insulator (SOI: Silicon on Insulator), etc.

[0020] In some possible embodiments, the substrate 10 includes a first region and a second region, the first region being shown as B in FIG. 3 and the second region being shown as A in FIG. 3, and the first region being adjacent to the second region, e.g., the first region being adjacent to and connected to the second region. Here, a semiconductor device such as a transistor 2 can be provided on the first region, and a connection structure such as a connection layer 60 (see FIG. *) can be provided on the second region. By drawing out the semiconductor device on the first region through the structure on the second region, the semiconductor device becomes electrically connected to the peripheral circuit. The substrate 10 located in the first region and the substrate 10 located in the second region are integral, thereby providing the substrate 10.

[0021] In step S20, a stacked structure is formed on a substrate, and the stacked structure includes sacrificial layers and active layers alternately stacked in a first direction.

[0022] 3, the laminated structure 20 includes a plurality of sacrificial layers 21 and a plurality of active layers 22, and the plurality of sacrificial layers 21 and the plurality of active layers 22 are alternately laminated along a first direction. Here, the first direction is a direction perpendicular to the substrate 10, such as the Y direction shown in FIG. 3. Along the first direction, the active layer 22 is provided between two adjacent sacrificial layers 21, or the sacrificial layer 21 is provided between two adjacent active layers 22, so that the sacrificial layer 21 and the active layer 22 are alternately laminated in sequence. By disposing in this manner, the two adjacent active layers 22 can be isolated by the sacrificial layer 21, so that the active layers 22 are electrically isolated along the first direction.

[0023] Specifically, forming the laminated structure 20 on the substrate 10 includes forming a sacrificial layer 21 and an active layer 22 on the substrate 10 in a sequential, alternating manner, one by one, overlapping manner until the laminated structure 20 is formed, where the layer of the laminated structure 20 closest to the substrate 10 is the sacrificial layer 21, and the layer of the laminated structure 20 furthest from the substrate 10 is the active layer 22. Specifically, when forming the laminated structure 20, one sacrificial layer 21 is formed on the substrate 10, then one active layer 22 is formed on the sacrificial layer 21, then one sacrificial layer 21 is formed on the active layer 22, and the process of forming the active layer 22 and the sacrificial layer 21 is repeated until a desired number of sacrificial layers 21 and active layers 22 are formed.

[0024] 3, the layer of the stacked structure 20 closest to the substrate 10 is the sacrificial layer 21, so that the active layer 22 on the sacrificial layer 21 is spaced apart from the substrate 10, and the transistors 2 can be subsequently formed in the active layer 22 of each layer, thereby increasing the number of transistors 2 and thereby increasing the memory capacity of the semiconductor structure. The layer of the stacked structure 20 furthest from the substrate 10 is the active layer 22, and by providing in this way, when the stacked structure 20 has the same number of active layers 22, the height of the stacked structure 20 is reduced, which makes it easier to subsequently etch the stacked structure 20.

[0025] In some possible embodiments, the sacrificial layer 21 and the active layer 22 are formed on the substrate 10 by a deposition process, which may include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or the like.

[0026] In some other possible embodiments, the sacrificial layer 21 and the active layer 22 are formed on the substrate 10 by an epitaxial growth process (EPI: Epitaxy). Specifically, the substrate 10, the active layer 22, and the sacrificial layer 21 have the same element, for example, silicon, and the sacrificial layer 21 is epitaxially grown on the substrate 10, the active layer 22 is epitaxially grown on the sacrificial layer 21, and the sacrificial layer 21 is epitaxially grown on the active layer 22. Exemplarily, the material of the substrate 10 includes silicon, the material of the active layer 22 includes silicon, and the material of the sacrificial layer 21 includes germanium silicon. On the one hand, it is easy to form the active layer 22 and the sacrificial layer 21 by epitaxial growth, and on the other hand, the sacrificial layer 21 and the active layer 22 have a large selectivity, and then only the sacrificial layer 21 can be removed, and the damage to the active layer 22 during the removal of the sacrificial layer 21 can be reduced. Preferably, the material of the active layer 22 includes doped silicon, for example, the material of the active layer 22 includes N-type doped silicon, which improves the electrical properties of the active layer 22 .

[0027] In step S30, a portion of the stacked structure located in the first region is removed to form a plurality of first trenches spaced apart and extending in the second direction, and the first trenches expose the substrate, thereby separating the active layer located in the first region into a plurality of active pillars spaced apart.

[0028] 4, a plurality of first trenches 51 are formed in the stacked structure 20 located in the first region, the plurality of first trenches 51 are spaced apart from each other and extend along a second direction, which is the horizontal direction (Z direction) shown in FIG. 1, parallel to the substrate 10, and perpendicular to the first direction. The first trenches 51 penetrate the stacked structure 20 located in the first region to expose the substrate 10.

[0029] 5, in some possible embodiments, the first trench 51 can extend into the substrate 10, i.e., the bottom of the first trench 51 is located in the substrate 10. By providing in this manner, the first trench 51 can separate the stacked structure 20 into a plurality of isolations, whereby each active layer 22 in the stacked structure 20 is separated into a plurality of active pillars 50 spaced apart from each other, thereby increasing the number of active pillars 50 and increasing the storage capacity of the semiconductor structure.

[0030] As shown in FIG. 4 and FIG. 5, the active pillars 50 are arranged in an array, and the active pillars 50 extend along the second direction. The active pillars 50 are arranged at intervals along the first direction and at intervals along the third direction, which cross the first direction and are all perpendicular to the second direction. Here, the third direction is a direction parallel to the substrate 10, and exemplarily, the third direction is a horizontal direction (X direction) shown in FIG. 4 and FIG. 5, and the first direction, the second direction, and the third direction are perpendicular to each other. This arrangement method can make the arrangement of the active pillars 50 more compact, and can maximize the number of the active pillars 50. The active pillars 50 include a source, a drain, and a channel located between the source and the drain. The shape of the active pillars 50 may be a cylinder, a prism, a rectangular parallelepiped, or other shapes, and is not limited thereto in the embodiments of the present disclosure.

[0031] Specifically, removing a portion of the stacked structure 20 located in the first region to form a plurality of first trenches 51 spaced apart and extending along the second direction includes etching the stacked structure 20 located in the first region to form the first trenches 51, the first trenches 51 penetrating the stacked structure 20.

[0032] 4 to 7, in some possible embodiments, etching the stacked structure 20 located in the first region to form a first trench 51 penetrating the stacked structure 20 includes: A first mask layer 40 is formed on the laminate structure 20, and the first mask layer 40 located in a first region has a first pattern. The first mask layer 40 is formed on the laminate structure 20, and the tops of the laminate structure 20 located in the first and second regions are both covered with the first mask layer 40, and the first mask layer 40 located in the first region has the first pattern, thereby exposing a part of the laminate structure 20 located in the first region and not exposing the laminate structure 20 located in the second region.

[0033] Using the first mask layer 40 as a mask, the stacked structure 20 located in the first region is etched to form a first trench 51. By etching the stacked structure 20 using the first mask layer 40 as a mask, the first pattern is transferred to the stacked structure 20 located in the first region, and the first trench 51 is formed in the stacked structure 20.

[0034] In some other possible embodiments, forming the first mask layer 40 on the stacked structure 20 includes forming a protective layer 30 on the stacked structure 20 and forming the first mask layer 40 on the protective layer 30. With reference to Figures 4 and 6, the stacked structure 20 is covered with the protective layer 30, which is a silicon oxide layer and can reduce or prevent oxidation of the active layer 22. With reference to Figures 6 and 7, the protective layer 30 is covered with the first mask layer 40, and the first mask layer 40 located in the first region has a first pattern.

[0035] 7 and 5, etching the stacked structure 20 located in the first region using the first mask layer 40 as a mask includes: etching the protective layer 30 located in the first region using the first mask layer 40 as a mask to transfer a first pattern to the protective layer 30; and removing the first mask layer 40 to continue etching the stacked structure 20 with the patterned protective layer 30. That is, first, the first pattern of the first mask layer 40 is transferred to the protective layer 30 located in the first region, then the first mask layer 40 is removed to expose the protective layer 30, and etching the stacked structure 20 is continued using the patterned protective layer 30 as a mask to form a first trench 51 in the stacked structure 20.

[0036] In step S40, a first trench is used to remove the sacrificial layer located in the first region and the second region, such that the active pillar located in the first region and the active layer in the second region are both spaced apart along a first direction, where the second region is adjacent to the first region.

[0037] 5 and 8, the sacrificial layer 21 in the first region and the second region is completely removed, the active pillars 50 located in the first region are spaced apart along the first direction, and the active layer 22 located in the second region are spaced apart along the first direction. In some possible embodiments, removing the sacrificial layer 21 located in the first region and the second region using the first trench 51 includes exposing the sidewall of the sacrificial layer 21 by the first trench 51, and removing the sacrificial layer 21 located in the first region and the second region by a wet etching process. The wet etching process has a good selectivity, and when removing the sacrificial layer 21 using wet etching, damage to the exposed active layer 22, the active pillars 50, and the substrate 10 can be avoided.

[0038] In step S50, a portion of the active layer located in the second region is removed to form a plurality of step-shaped connection layers at the end of the second region away from the first region.

[0039] Referring to FIG. 9, a part of the active layer 22 located in the second region is removed, and the remaining active layer 22 located in the second region forms a connection layer 60, and the length of the multiple connection layers 60 is gradually reduced along the direction away from the substrate 10, so that the end of the multiple connection layers 60 away from the first region is stepped. As shown in FIG. 9, the step shape is upward along the first direction and upward along the third direction, the first direction is a direction perpendicular to the substrate 10 as the Y direction shown in FIG. 9, and the third direction is a direction parallel to the substrate 10 as the X direction shown in FIG. 9. In order to form other structures on the connection layer 60, a part of the surface of the connection layer 60 of each layer is exposed. Specifically, in the surface of the connection layer 60 of each layer away from the substrate 10, a part of the surface away from the first region is exposed, that is, the left end of the upper surface of the connection layer 60 of each layer is exposed.

[0040] In some possible embodiments, removing a portion of the active layer 22 located in the second region and forming a plurality of stepped connection layers 60 at an end of the second region away from the first region includes forming a second mask layer on the active layer 22, where the second mask layer located in the second region has a second pattern, etching the active layer 22 located in the second region using the second mask layer as a mask to form a plurality of stepped connection layers 60 at an end of the second region away from the first region, and removing the second mask layer.

[0041] In the above embodiment, the active layer 22 of each layer corresponds to a second mask layer of a different size, and the second mask layer is sequentially reduced and etched into the corresponding active layer 22 to form the required connection layer 60. Specifically, a second mask layer is first formed on the active layer 22, and the second mask layer is used as a mask to etch down to the lowest active layer 22, so that the lowest active layer 22 forms the connection layer 60, and then a part of the second mask layer away from the first region is removed, and the second mask layer is used as a mask to etch down to the second lowest active layer 22, so that the second lowest active layer 22 forms the connection layer 60. This is repeated until the topmost active layer 22 forms the connection layer 60. Here, the bottommost layer refers to the layer of the active layer 22 closest to the substrate 10, and the topmost layer refers to the layer of the active layer 22 furthest from the substrate 10.

[0042] In step S60, a gate material layer is formed to cover the connection layer and the active pillar, and the connection layer and the gate material layer formed on the active pillar located at the same hierarchical level are communicated with each other, and the connection layer and the gate material layer formed on the active pillar located at different hierarchical levels are isolated from each other.

[0043] 10, after the gate material layer 70 is formed, the connection layer 60 and the gate material layer 70 of the active pillar 50 in the same layer are communicated, and the connection layer 60 and the gate material layer 70 of the active pillar 50 in different layers are isolated from each other, so that the gate material layer 70 is electrically isolated in the first direction. The gate material layers 70 are stepped, and the length of each step changes stepwise, specifically, the length of each gate material layer 70 gradually decreases along the direction away from the substrate 10.

[0044] Here, the gate material layer 70 includes a gate dielectric layer and a gate conductive layer, the gate dielectric layer covers the outer peripheral surface of the active pillar 50, the gate conductive layer covers the outer peripheral surface of the gate dielectric layer, and is integrally formed along the second direction, and a part of the gate conductive layer can be used for the gate of the transistor 2. As shown in FIG. 10, the gate conductive layer further extends to the connection layer 60 and covers at least two surfaces of the connection layer 60 facing each other along the first direction. A gate dielectric layer may be provided between the gate conductive layer and the connection layer 60, so that the connection layer 60 and the gate dielectric layer on the active pillar 50 are formed together, which facilitates the formation of the gate dielectric layer. The material of the gate dielectric layer can be silicon oxide, and the material of the gate conductive layer can be titanium nitride. The gate conductive layer is used as the word line 4, which facilitates the manufacturing and drawing of the word line 4.

[0045] In some possible embodiments, forming a gate material layer 70 overlying the connecting layer 60 and the active pillars 50 includes: A gate dielectric layer is formed covering the surfaces of the connecting layer 60 and the active pillars 50, with a gap between the gate dielectric layer on the surface of each connecting layer 60 and each active pillar 50. Exemplarily, the gate dielectric layer is deposited on the surfaces of the connecting layer 60 and the active pillars 50, with the gate dielectric layer covering the outer circumferential surface of the active pillars 50 and covering at least two surfaces of the connecting layer 60 that face each other along the first direction and the surface facing the active pillars 50. In an embodiment in which the active pillars 50 include a source, a channel, and a drain, the gate dielectric layer faces the channel.

[0046] A gate conductive layer is deposited to cover the surface of the gate dielectric layer. The gate conductive layers on the gate dielectric layers provided in the same layer are connected to each other, and the gate conductive layers on the gate dielectric layers provided in different layers are isolated from each other. That is, the gate conductive layer is formed in multiple layers, and the multiple gate conductive layers are provided at intervals along a first direction, and the gate conductive layer of each layer covers the surface of the gate dielectric layer provided in the same layer and is filled between each gate dielectric layer. The gate conductive layer forms a word line 4, and the gate conductive layer located in the first region is used as a gate, and the gate is a part of the word line 4, and the gate conductive layer located in the second region is used as a gate lead end connecting a peripheral circuit.

[0047] It should be explained that, in addition to forming the gate material layer 70 covering the connection layer 60 and the active pillars 50, the manufacturing method of the memory further includes forming the gate material layer 70 on the substrate 10 located in the first region and the second region, and the gate material layer 70 on the substrate 10 is isolated from the gate material layer 70 on the active pillars 50 and the gate material layer 70 on the connection layer 60. As shown in FIG. 10, there is a gap between the active pillars 50 located in the first region and the substrate 10, and there is a gap between the connection layer 60 located in the second region and the substrate 10, so that when depositing the gate material layer 70, the gate material layer 70 also covers the substrate 10 in the first region and the second region, and the gate material layer 70 on the substrate 10 is spaced apart from the gate material layer 70 on the active pillars 50 and is spaced apart from the gate material layer 70 on the connection layer 60, so that each gate material layer 70 is isolated from each other.

[0048] In some possible embodiments, a gate material layer 70 is formed covering the connection layer 60 and the active pillars 50, and the gate material layer 70 formed on the connection layer 60 and the active pillars 50 located at the same hierarchical level are connected to each other, and the gate material layer 70 formed on the connection layer 60 and the active pillars 50 located at different hierarchical levels are isolated from each other (step S60), and then the memory manufacturing method further includes forming a plurality of contact plugs 80 spaced apart and extending along the first direction, and each contact plug 80 contacts one gate material layer 70 located in the second region.

[0049] 11, the contact plugs 80 are used to connect the gate material layer 70 to the peripheral circuit, and the contact plugs 80 are provided at a distance from each other, thereby isolating the contact plugs 80 and preventing mutual interference between the gate material layers 70. The contact plugs 80 contact the gate material layers 70 in one-to-one correspondence, thereby electrically connecting each gate material layer 70 to the peripheral circuit and controlling the transistor 2 corresponding to the gate material layer 70 via the peripheral circuit.

[0050] The contact plug 80 may include a first conductive portion and a second conductive portion provided on the first conductive portion, the first conductive portion being a portion close to the substrate 10, and the second conductive portion being a portion far from the substrate 10, i.e., the second conductive portion is located on the side of the first conductive portion far from the substrate 10. The first conductive portion and the second conductive portion may each include a core layer and an outer layer covering the side and bottom surfaces of the core layer. Here, the core layer may be an insulating layer, and the material thereof may be silicon nitride or silicon oxide. The outer layer may be a metal layer, and the material thereof may be tungsten or titanium nitride. By providing them in this manner, the thickness of the metal layer can be thinned and costs can be reduced while ensuring the electrical properties of the first conductive portion and the second conductive portion.

[0051] It should be noted that the substrate 10 in the embodiment of the present disclosure further includes a third region, which is adjacent to the first region, and the third region is indicated by C in Fig. 11, and a capacitor 3 can be formed on the third region. The capacitor 3 is usually formed after the gate material layer 70 is formed.

[0052] Specifically, referring to FIG. 12, when a laminated structure 20 is formed on a substrate 10 and includes a sacrificial layer 21 and an active layer 22 stacked along a first direction, the laminated structure 20 is formed on the first region, the second region, and the third region of the substrate 10, and the laminated structure 20 located in the first region then forms the active pillar 50, the laminated structure 20 located in the second region then forms the connecting layer 60, and the laminated structure 20 located in the third region then forms the support layer of the capacitor 3.

[0053] 13 and 14, when the protective layer 30 is formed on the stacked structure 20 and the first mask layer 40 is formed on the protective layer 30, the protective layer 30 and the first mask layer 40 are formed on the stacked structure 20 located in the first region, the second region, and the third region, respectively, and in the subsequent manufacturing process, the protective layer 30 and the first mask layer 40 located in the third region are maintained until the gate material layer 70 is formed. By providing in this manner, damage to the active layer 22 in the third region during the manufacturing process of the word lines 4 is prevented.

[0054] As described above, in the method for manufacturing a memory provided by the embodiment of the present disclosure, a stacked structure 20 is formed on a substrate 10, the stacked structure 20 includes a sacrificial layer 21 and an active layer 22 alternately stacked along a first direction, and a part of the sacrificial layer 21 and the active layer 22 is removed to form a plurality of active pillars 50 spaced apart from each other in the active layer 22 located in a first region, and a plurality of step-shaped connection layers 60 are formed in the active layer 22 located in a second region, and then a gate material layer 70 is formed on the connection layer 60 and the active pillars 50, and the gate material layers 70 formed on the connection layers 60 and the active pillars 50 located at the same hierarchical level are connected to each other, and the gate material layers 70 formed on the connection layers 60 and the active pillars 50 located at different hierarchical levels are isolated from each other. By using the gate material layer 70 as the word line 4 and providing the connection layer 60, the word line 4 can be easily manufactured and drawn out. In addition, since the ends of the multiple connection layers 60 away from the first region are stepped, the ends of the gate material layer 70 covering the active pillars 50 and the connection layers 60 away from the first region are also stepped. In other words, since the word lines 4 are stepped, it becomes easier to form other structures on the word lines 4, and electrical connection between the word lines 4 and peripheral circuits becomes possible.

[0055] In a second aspect of the embodiment of the present disclosure, a memory is provided, and referring to FIG. 1 and FIG. 11, the memory has adjacent first and second regions, the first region is shown as B in FIG. 11, and the second region is shown as A in FIG. 11, and the first region is adjacent to the second region, for example, the first region is adjacent to and connected to the second region. A semiconductor device such as a transistor 2 can be provided on the first region, and a connection structure such as a connection layer 60 can be provided on the second region, and the semiconductor device on the first region is electrically connected to a peripheral circuit by drawing out the semiconductor device on the first region through the structure on the second region. The memory includes a plurality of connection layers 60 located in the second region and spaced apart along the first direction, and the ends of the plurality of connection layers 60 on the side away from the first region are stepped.

[0056] 11, the multiple connection layers 60 are located in the second region and are stacked along the first direction, and the multiple connection layers 60 are spaced apart from each other, thereby ensuring electrical isolation between the multiple connection layers 60. As shown in FIG. 11, a step is formed at the end of the multiple connection layers 60 away from the first region, and the left end of the multiple connection layers 60 is stepped. Specifically, the step is upward along the first direction and upward along the third direction, the first direction being a direction perpendicular to the substrate 10 as the Y direction shown in FIG. 11, and the third direction being a direction parallel to the substrate 10 as the X direction shown in FIG. 11.

[0057] In some possible examples, referring to Fig. 11, the lengths of the multiple connection layers 60 are gradually decreased along the direction away from the substrate 10, so that the ends of the multiple connection layers 60 away from the first region are stepped. As shown in Fig. 11, a part of the surface of each connection layer 60 is exposed in order to form another structure on the connection layer 60. Specifically, a part of the surface of each connection layer 60 away from the substrate 10, away from the first region, is exposed.

[0058] Continuing to refer to FIG. 11, the memory further includes a plurality of active pillar layers located in the first region and spaced apart along the first direction, each active pillar layer being arranged in the same layer as one connection layer 60, each active pillar layer having a plurality of active pillars 50 spaced apart, and each active pillar 50 extending along the second direction.

[0059] 11, the active pillar layers are located in a first region, stacked along a first direction, and the active pillar layers 50 are spaced apart from each other, thereby ensuring electrical isolation between the active pillar layers. To form a gate material layer 70 on the active pillar layers and the connection layer 60, the active pillar layers correspond to the connection layers 60 in a one-to-one manner, and the corresponding active pillar layers are disposed in the same layer as the connection layer 60.

[0060] As shown in FIG. 11, each active pillar layer includes a plurality of active pillars 50 spaced apart from each other, and the plurality of active pillars 50 extend along the second direction. The plurality of active pillars 50 are arranged in an array, specifically, the plurality of active pillars 50 are spaced apart from each other along the first direction and the third direction, which crosses the first direction and is perpendicular to the second direction. Here, the second direction is a direction parallel to the substrate 10, and exemplarily, the second direction is the horizontal direction (Z direction) shown in FIG. 1, and the first direction, the second direction, and the third direction are perpendicular to each other. This arrangement method can make the arrangement of the active pillars 50 more compact, and can maximize the number of the active pillars 50. The shape of the active pillars 50 may be a cylinder, a prism, a rectangular parallelepiped, or other shapes, and is not limited thereto in the embodiments of the present disclosure.

[0061] Continuing to refer to FIG. 11, the memory further includes a gate material layer 70 located on the connection layer 60 and the active pillars 50, where the connection layer 60 and the gate material layer 70 formed on the active pillars 50 located at the same hierarchical level are in communication with each other, and the connection layer 60 and the gate material layer 70 formed on the active pillars 50 located at different hierarchical levels are isolated from each other.

[0062] As shown in FIG. 11, the connection layer 60 and the gate material layer 70 of the active pillar 50 provided in the same layer are connected to each other, and the connection layer 60 and the gate material layer 70 of the active pillar 50 provided in different layers are isolated from each other, so that the gate material layer 70 is electrically isolated along the first direction. Since the connection layer 60 is stepped, the multiple gate material layers 70 are stepped, and the length of the gate material layer 70 changes stepwise in order to form other structures on the gate material layer 70. Thus, the gate material layer 70 can be drawn out. Specifically, the length of the gate material layer 70 gradually decreases along the direction away from the substrate 10.

[0063] Here, the gate material layer 70 includes a gate dielectric layer and a gate conductive layer, the gate dielectric layer covers the outer peripheral surface of the active pillar 50, the gate conductive layer covers the outer peripheral surface of the gate dielectric layer, and is integrally formed along the second direction, and a part of the gate conductive layer can be used for the gate of the transistor 2. As shown in FIG. 11, the gate conductive layer further extends to the connection layer 60 and covers at least two surfaces of the connection layer 60 facing each other along the first direction. A gate dielectric layer may be provided between the gate conductive layer and the connection layer 60, so that the connection layer 60 and the gate dielectric layer on the active pillar 50 are formed together, which facilitates the formation of the gate dielectric layer. The material of the gate dielectric layer can be silicon oxide, and the material of the gate conductive layer can be titanium nitride. The gate conductive layer is used as the word line 4, which facilitates the manufacturing and drawing of the word line 4.

[0064] In some possible embodiments, the memory further includes a plurality of spaced apart contact plugs 80 extending along the first direction, each contact plug 80 contacting one gate material layer 70 located in the second region.

[0065] 11, the contact plugs 80 are used to connect the gate material layer 70 to the peripheral circuit, and the contact plugs 80 are spaced apart to ensure insulation and isolation between the contact plugs 80, thereby preventing mutual interference between the gate material layers 70. The contact plugs 80 contact the gate material layers 70 in one-to-one correspondence, thereby electrically connecting each gate material layer 70 to the peripheral circuit, and the transistor 2 corresponding to the gate material layer 70 can be controlled via the peripheral circuit.

[0066] The contact plug 80 may include a first conductive portion and a second conductive portion provided on the first conductive portion, the first conductive portion being a portion close to the substrate 10, and the second conductive portion being a portion far from the substrate 10, i.e., the second conductive portion is located on the side of the first conductive portion far from the substrate 10. The first conductive portion and the second conductive portion may each include a core layer and an outer layer covering the side and bottom surfaces of the core layer. Here, the core layer may be an insulating layer, and the material thereof may be silicon nitride or silicon oxide. The outer layer may be a metal layer, and the material thereof may be tungsten or titanium nitride. By providing them in this manner, the thickness of the metal layer can be thinned to reduce costs while ensuring the electrical characteristics of the first conductive portion and the second conductive portion.

[0067] In some possible implementations, the memory further includes a third region adjacent to the first region, and the memory further includes a plurality of capacitors 3 located in the third region and spaced apart, the capacitors 3 extending along the second direction, and each capacitor 3 electrically connected to one active pillar 50. Specifically, the third region and the first region may be arranged along the second direction (Z direction shown in FIG. 11 ), and the third region includes a plurality of capacitors 3 spaced apart, and the plurality of capacitors 3 are electrically connected in one-to-one correspondence to the plurality of active pillars 50.

[0068] In the memory provided by the embodiment of the present disclosure, the gate material layer 70 is provided on the connection layer 60 and on the active pillar 50, and the connection layer 60 and the gate material layer 70 formed on the active pillar 50 at the same hierarchical level are connected to each other, and the connection layer 60 and the gate material layer 70 formed on the active pillar 50 at different hierarchical levels are isolated from each other, and the gate material layer 70 is used as the word line 4, and the connection layer 60 is provided, so that the word line 4 can be easily manufactured and drawn out. In addition, since the end of the multiple connection layers 60 away from the first region is stepped, the end of the gate material layer 70 covering the active pillar 50 and the connection layer 60 away from the first region is also stepped, that is, since the word line 4 is stepped, it is easy to form other structures on the word line 4, and the word line 4 can be electrically connected to the peripheral circuit.

[0069] Each example in the present specification is described step by step, and each example focuses on the differences from other examples, and the same or similar parts between each example can be referred to each other. A description referring to terms such as "one embodiment", "some embodiments", "exemplary embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in the example or examples are included in at least one embodiment or example of the present disclosure. In the present specification, the exemplary expressions of the above terms do not necessarily refer to the same example or example. Furthermore, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in any one or more embodiments or examples.

[0070] Finally, the above examples are only used to explain the technical solutions of the present disclosure, and are not intended to limit them. Although the present disclosure has been described in detail with reference to the above examples, those skilled in the art may modify the technical solutions described in the above examples, or perform equivalent replacements for part or all of the technical features, and these modifications or replacements should be understood to not cause the essence of the corresponding technical solutions to depart from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A method for manufacturing a memory, comprising the steps of: Providing a substrate; forming a layered structure on the substrate, the layered structure including sacrificial layers and active layers alternately stacked in a first direction; removing a portion of the stack located in a first region to form a plurality of spaced apart first trenches extending in a second direction, the first trenches exposing the substrate to separate the active layer located in the first region into a plurality of spaced apart active pillars; removing the sacrificial layer located in the first region and the second region using the first trench such that the active pillar located in the first region and the active layer in the second region are both spaced apart along the first direction, the second region being adjacent to the first region in a third direction; removing a portion of the active layer located in the second region to form a plurality of step-shaped connection layers at an end of the second region away from the first region; forming a gate material layer covering the connection layer and the active pillar, the connection layer and the gate material layer formed on the active pillar located at the same hierarchical level being communicated with each other, and the connection layer and the gate material layer formed on the active pillar located at different hierarchical levels being isolated from each other; removing the sacrificial layer located in a third region to form a capacitor, the third region being adjacent to the first region in the second direction, the first direction being a direction perpendicular to the substrate, the second direction being a length direction of the active pillar parallel to the substrate, and the third direction being a direction perpendicular to the second direction parallel to the substrate; How memory is manufactured.

2. The lengths of the plurality of connection layers are gradually decreased along a direction away from the substrate, so that ends of the plurality of connection layers away from the first region are stepped. A method for manufacturing the memory according to claim 1 .

3. forming a laminate structure on the substrate, forming the sacrificial layer and the active layer on the substrate in a sequential, alternating manner, one layer at a time, until the laminate structure is formed, the layer of the laminate structure closest to the substrate being the sacrificial layer, and the layer of the laminate structure furthest from the substrate being the active layer; A method for manufacturing the memory according to claim 1 .

4. the sacrificial layer and the active layer are formed on the substrate by an epitaxial growth process; A method for manufacturing the memory according to claim 1 .

5. The material of the active layer includes N-type doped silicon, and the material of the sacrificial layer includes germanium silicon; A method for manufacturing the memory according to claim 4.

6. Removing a portion of the stacked structure located in the first region to form a plurality of the first trenches spaced apart from each other and extending in the second direction includes: Etching the stack in the first region to form the first trench through the stack; Etching the stacked structure in the first region to form the first trench penetrating the stacked structure includes: forming a first mask layer over the stack, the first mask layer located in the first region having a first pattern; and etching the stacked structure located in the first region using the first mask layer as a mask to form the first trench. A method for manufacturing the memory according to claim 1 .

7. Removing the sacrificial layer located in the first region and the second region using the first trench includes: exposing a sidewall of the sacrificial layer through the first trench, and removing the sacrificial layer located in the first region and the second region by a wet etching process. A method for manufacturing the memory according to claim 6.

8. forming the first mask layer on the stack structure, forming a protective layer on the stacked structure; and forming the first mask layer on the protective layer; Etching the stacked structure located in the first region using the first mask layer as a mask includes: using the first mask layer as a mask, etching the protection layer located in the first region to transfer the first pattern to the protection layer; removing the first mask layer and continuing to etch the stack with the patterned protective layer. A method for manufacturing the memory according to claim 6.

9. Removing a portion of the active layer located in the second region to form a plurality of step-shaped connection layers at an end of the second region away from the first region includes: forming a second mask layer over the active layer, the second mask layer in the second region having a second pattern; using the second mask layer as a mask, etching the active layer located in the second region to form a plurality of the connection layers in a stepped shape at an end of the second region away from the first region; removing the second mask layer. A method for manufacturing the memory according to claim 1 .

10. forming a gate material layer overlying the connection layer and the active pillars; forming a gate dielectric layer covering the connection layer and a surface of the active pillar, wherein there is a gap between each of the connection layers and the gate dielectric layer on the surface of each of the active pillars; depositing a gate conductive layer overlying the gate dielectric layer. A method for manufacturing the memory according to claim 1 .

11. The gate conductive layers on the gate dielectric layers provided in the same layer are communicated with each other, and the gate conductive layers on the gate dielectric layers provided in different layers are isolated from each other. A method for manufacturing the memory according to claim 10.

12. While forming a gate material layer covering the connection layer and the active pillar, the method of manufacturing the memory includes: Further comprising forming the gate material layer on the substrate located in the first region and the second region, the gate material layer on the substrate being isolated from the gate material layer on the active pillars and the gate material layer on the connection layer. A method for manufacturing the memory according to claim 10.

13. The method for manufacturing the memory includes forming the gate material layer covering the connection layer and the active pillar so that the connection layer and the gate material layer formed on the active pillar located at the same hierarchical level are communicated with each other, and the connection layer and the gate material layer formed on the active pillar located at different hierarchical levels are isolated from each other, and then the method for manufacturing the memory includes forming the gate material layer covering the connection layer and the active pillar so that the connection layer and the gate material layer formed on the active pillar located at different hierarchical levels are communicated with each other, and the gate material layer covering the connection layer and the gate material layer formed on the active pillar located at different hierarchical levels are isolated from each other, forming a plurality of spaced apart contact plugs extending in the first direction, each of the contact plugs contacting one of the gate material layers located in the second region; A method for manufacturing the memory according to claim 1 .

14. a memory having a first region, a second region, and a third region; A substrate; a plurality of connection layers located in the second region and spaced apart along a first direction, the plurality of connection layers having ends remote from the first region that are formed in a stepped shape; A plurality of active pillar layers located in the first region and spaced apart along the first direction, each of the active pillar layers being provided in the same layer as one of the connection layers, each of the active pillar layers having a plurality of active pillars spaced apart from each other, and each of the active pillar layers extending along a second direction; a gate material layer located on the connection layer and on the active pillar, the connection layer located at the same hierarchical level and the gate material layer formed on the active pillar being communicated with each other, and the connection layer located at a different hierarchical level and the gate material layer formed on the active pillar being isolated from each other; a plurality of spaced apart capacitors located in the third region; the capacitors extend along the second direction, and each of the capacitors is electrically connected to one of the active pillars; the first direction is a direction perpendicular to the substrate, the second direction is a length direction of the active pillar parallel to the substrate, and the third direction is a direction perpendicular to the second direction parallel to the substrate; The second region is adjacent to the first region in the third direction, and the third region is adjacent to the first region in the second direction. Memory.

15. The memory, the gate material layer includes a first region and a second region, the first region being in contact with the gate material layer, and the second region being in contact with a first region of the gate material layer. The memory of claim 14.

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