Solid-state imaging device and its manufacturing method

Abstract

[Problem] To provide: a solid-state imaging device that can enhance the light blocking effect of a charge accumulation unit; and a method for manufacturing the same. [Solution] A solid-state imaging device according to the present disclosure is provided with: a substrate; a plurality of photoelectric conversion units provided on the substrate; a charge accumulation unit provided between four photoelectric conversion units that are mutually adjacent on the substrate; and a light-blocking film provided in a groove in the substrate. The groove includes: a first portion provided between two photoelectric conversion units that are mutually adjacent; and a second portion provided around the charge accumulation unit. The second portion has a first opening between the charge accumulation unit and at least a first photoelectric conversion unit of the four photoelectric conversion units and passes through the substrate between the charge accumulation unit and at least a second photoelectric conversion unit of the four photoelectric conversion units.

Description

[Technical field]

[0001] The present disclosure relates to a solid-state imaging device and a manufacturing method thereof. [Background technology]

[0002] A solid-state imaging device temporarily stores charges obtained by photoelectric conversion of a photodiode (PD) in a charge storage section such as a floating diffusion section (FD) and then reads out the charges. In such a solid-state imaging device, in order to suppress stray light to the floating diffusion section, the floating diffusion section may be disposed at the cross section of a light-shielding film having a mesh-like planar shape. This makes it possible to shield the floating diffusion section from light by the light-shielding film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-168566 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, if the floating diffusion is not sufficiently light-shielded, the floating diffusion may perform photoelectric conversion in response to stray light, which may result in the floating diffusion generating a false signal.

[0005] In view of this, the present disclosure provides a solid-state imaging device capable of improving the light blocking properties of a charge accumulation section, and a manufacturing method thereof. [Means for solving the problem]

[0006] A solid-state imaging device according to a first aspect of the present disclosure includes a substrate, a plurality of photoelectric conversion units provided in the substrate, a charge accumulation unit provided between four adjacent photoelectric conversion units in the substrate, and a light-shielding film provided in a groove in the substrate, the groove including a first portion provided between two adjacent photoelectric conversion units in the substrate and a second portion provided around the charge accumulation unit, the second portion having a first opening between at least a first photoelectric conversion unit of the four photoelectric conversion units and the charge accumulation unit, and penetrating the substrate between at least a second photoelectric conversion unit of the four photoelectric conversion units and the charge accumulation unit. This allows most of the charge accumulation unit to be shielded from light by the light-shielding film, improving the light-shielding properties of the charge accumulation unit.

[0007] In addition, in this first aspect, the second portion may further penetrate the substrate between a third photoelectric conversion unit of the four photoelectric conversion units and the charge accumulation unit, and between a fourth photoelectric conversion unit of the four photoelectric conversion units and the charge accumulation unit, thereby making it possible to suppress stray light from the second, third, and fourth photoelectric conversion units to the charge accumulation unit and further improve the light blocking property of the charge accumulation unit.

[0008] In the first aspect, the first portion may have a plate-like shape extending vertically within the substrate, thereby making it possible for the plate-like first portion to suppress stray light between the photoelectric conversion units.

[0009] In the first aspect, the second portion may have a cylindrical shape extending vertically within the substrate, whereby stray light from the photoelectric conversion portion to the charge accumulation portion can be suppressed by the cylindrical second portion.

[0010] In the first aspect, the second portion may have a C-shape in a cross section passing through the first opening, thereby making it possible to suppress stray light from photoelectric conversion units other than the first photoelectric conversion unit to the charge accumulation unit.

[0011] In addition, in the first aspect, the light-shielding film may include a metal layer or a semiconductor layer provided in the groove via an insulating film, which makes it possible, for example, for the insulating film to function as an element isolation insulating film, and for the metal layer or the semiconductor layer to function as a light-shielding film.

[0012] In addition, in this first aspect, the second portion may further have a second opening between a third photoelectric conversion unit of the four photoelectric conversion units and the charge accumulation unit, and may penetrate the substrate between a fourth photoelectric conversion unit of the four photoelectric conversion units and the charge accumulation unit. This makes it possible to, for example, suitably dispose a circuit element for the first photoelectric conversion unit near the third photoelectric conversion unit while improving the light blocking property of the charge accumulation unit.

[0013] In addition, in the first aspect, the third photoelectric conversion unit may be provided on the opposite side of the charge accumulation unit to the first photoelectric conversion unit, which makes it possible to suitably arrange a circuit element for the first photoelectric conversion unit on the opposite side of the charge accumulation unit to the first photoelectric conversion unit, for example.

[0014] In the first aspect, the reset transistor for the first photoelectric conversion unit may be provided on the third photoelectric conversion unit side with respect to the charge accumulation unit, which makes it possible to suitably arrange the reset transistor for the first photoelectric conversion unit, for example.

[0015] In the first aspect, the first portion may have a third opening between the two photoelectric conversion units, which makes it possible to suitably arrange a circuit element near the third opening, for example.

[0016] The solid-state imaging device according to the first aspect may further include a charge accumulation section provided in the substrate near the third opening and common to the two photoelectric conversion sections, which allows the charge accumulation section to be preferably disposed.

[0017] The solid-state imaging device according to the first aspect may further include a moth-eye structure provided on the upper surface of the substrate above the photoelectric conversion portion, thereby making it possible to obtain the advantages of the moth-eye structure while suppressing stray light caused by the moth-eye structure with a light-shielding film.

[0018] In addition, in the first aspect, the first opening may be provided on an opposite side of the charge storage section from a center of a pixel array region of the solid-state imaging device. Since a large amount of light is generally incident on each photoelectric conversion section from the center of the pixel array region, this makes it possible to effectively prevent the first opening from becoming a cause of stray light.

[0019] In addition, in the first aspect, the pixel array region may include a first region, a second region provided on an opposite side of the first region with respect to a center of the pixel array region, a third region provided between the first region and the second region, and a fourth region provided on an opposite side of the third region with respect to the center of the pixel array region, and the first opening in the second region may be provided on an opposite side of the first opening in the first region with respect to the center of the pixel array region, and the first opening in the fourth region may be provided on an opposite side of the first opening in the third region with respect to the center of the pixel array region. This makes it possible to provide first openings at suitable positions in each of the first to fourth regions.

[0020] A method for manufacturing a solid-state imaging device according to a second aspect of the present disclosure includes forming a plurality of photoelectric conversion units in a substrate, forming a charge accumulation unit between four adjacent photoelectric conversion units in the substrate, forming a groove in the substrate, and forming a light-shielding film in the groove, the groove including a first portion provided between two adjacent photoelectric conversion units in the substrate and a second portion provided around the charge accumulation unit, the second portion having a first opening between at least a first photoelectric conversion unit of the four photoelectric conversion units and the charge accumulation unit, and formed to penetrate the substrate between at least a second photoelectric conversion unit of the four photoelectric conversion units and the charge accumulation unit. This makes it possible to shield most of the charge accumulation unit from light by the light-shielding film, thereby improving the light-shielding properties of the charge accumulation unit.

[0021] In addition, in this second aspect, the second portion may be formed to penetrate the substrate between a third photoelectric conversion unit of the four photoelectric conversion units and the charge accumulation unit, and between a fourth photoelectric conversion unit of the four photoelectric conversion units and the charge accumulation unit, thereby making it possible to suppress stray light from the second, third, and fourth photoelectric conversion units to the charge accumulation unit and further improve the light blocking property of the charge accumulation unit.

[0022] In addition, in this second aspect, the second portion may further have a second opening between a third photoelectric conversion unit of the four photoelectric conversion units and the charge accumulation unit, and may be formed so as to penetrate the substrate between a fourth photoelectric conversion unit of the four photoelectric conversion units and the charge accumulation unit. This makes it possible to improve the light blocking property of the charge accumulation unit while arranging a circuit element for the first photoelectric conversion unit near the third photoelectric conversion unit, for example.

[0023] In the second aspect, the first portion may be formed to have a third opening between the two photoelectric conversion units, which makes it possible to dispose a circuit element near the third opening, for example.

[0024] The method for manufacturing a solid-state imaging device according to the second aspect may further include forming a moth-eye structure on the upper surface of the substrate above the photoelectric conversion section, thereby making it possible to suppress stray light caused by the moth-eye structure with a light-shielding film while enjoying the advantages of the moth-eye structure.

[0025] In the second aspect, the first opening may be formed on an opposite side of the charge storage section from a center of a pixel array region of the solid-state imaging device. Since a large amount of light is generally incident on each photoelectric conversion section from the center of the pixel array region, this makes it possible to effectively prevent the first opening from becoming a cause of stray light.

[0026] In addition, in this second aspect, the groove may be formed by forming a part of the groove from the front surface of the substrate and forming another part of the groove from the back surface of the substrate, thereby making it possible to form the groove by forming an opening (part of the groove) shallower than the thickness of the substrate multiple times.

[0027] In addition, in the second aspect, the groove may be formed by processing the substrate from only one of the front surface and the back surface of the substrate, which makes it possible to form the groove while reducing the number of times the substrate is processed. [Brief description of the drawings]

[0028] [Figure 1] 1 is a block diagram showing a configuration of a solid-state imaging device according to a first embodiment. [Diagram 2] 1 is a cross-sectional view showing the structure of a solid-state imaging device according to a first embodiment. [Diagram 3] 1 is a longitudinal sectional view showing the structure of a solid-state imaging device according to a first embodiment. [Figure 4] 4 is another vertical sectional view showing the structure of the solid-state imaging device according to the first embodiment. FIG. [Diagram 5] 4 is a longitudinal sectional view (1 / 2) illustrating a method for manufacturing the solid-state imaging device according to the first embodiment. FIG. [Figure 6]4 is a longitudinal sectional view (2 / 2) illustrating a method for manufacturing the solid-state imaging device according to the first embodiment. FIG. [Figure 7] FIG. 4 is a longitudinal sectional view (1 / 2) showing a first example of a method for forming a groove in the first embodiment. [Figure 8] 4 is a vertical cross-sectional view (2 / 2) showing a first example of a method for forming a groove in the first embodiment. FIG. [Figure 9] 6 is a longitudinal sectional view (1 / 2) showing a second example of a method for forming a groove in the first embodiment. FIG. [Figure 10] 6 is a vertical cross-sectional view (2 / 2) showing a second example of a method for forming a groove in the first embodiment. FIG. [Figure 11] 5A to 5C are vertical cross-sectional views showing a third example of the method for forming a groove in the first embodiment. [Figure 12] 6A to 6C are vertical cross-sectional views showing a fourth example of the method for forming a groove in the first embodiment. [Figure 13] FIG. 11 is a cross-sectional view showing the structure of a solid-state imaging device according to a second embodiment. [Figure 14] FIG. 11 is a longitudinal sectional view showing the structure of a solid-state imaging device according to a second embodiment. [Figure 15] 13 is another vertical sectional view showing the structure of the solid-state imaging device according to the second embodiment. FIG. [Figure 16] FIG. 11 is a cross-sectional view showing the structure of a solid-state imaging device according to a third embodiment. [Figure 17] FIG. 11 is a longitudinal sectional view showing the structure of a solid-state imaging device according to a third embodiment. [Figure 18] FIG. 13 is a cross-sectional view showing the structure of a solid-state imaging device according to a fourth embodiment. [Figure 19] FIG. 13 is a longitudinal sectional view showing the structure of a solid-state imaging device according to a fourth embodiment. [Figure 20] 13 is another vertical sectional view showing the structure of the solid-state imaging device according to the fourth embodiment. FIG. [Figure 21] 13A and 13B are a plan view and a cross-sectional view showing the structure of a solid-state imaging device according to a fifth embodiment. [Figure 22] FIG. 1 is a block diagram showing an example of the configuration of an electronic device. [Diagram 23] FIG. 1 is a block diagram showing a configuration example of a mobile object control system. [Figure 24]24 is a plan view showing a specific example of the setting position of the imaging unit in FIG. 23. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0030] (First embodiment) FIG. 1 is a block diagram showing the configuration of a solid-state imaging device according to the first embodiment.

[0031] The solid-state imaging device in FIG. 1 is a CMOS (Complementary Metal Oxide Semiconductor) type solid-state imaging device, and includes a pixel array region 2 having a plurality of pixels 1, a control circuit 3, a vertical drive circuit 4, a plurality of column signal processing circuits 5, a horizontal drive circuit 6, an output circuit 7, a plurality of vertical signal lines 8, and a horizontal signal line 9.

[0032] Each pixel 1 includes a photodiode that functions as a photoelectric conversion unit, and a plurality of pixel transistors, examples of which include MOS transistors such as a transfer transistor, a reset transistor, an amplification transistor, and a selection transistor.

[0033] The pixel array region 2 has a plurality of pixels 1 arranged in a two-dimensional array. The pixel array region 2 includes an effective pixel region that receives light, performs photoelectric conversion, and amplifies and outputs the signal charge generated by the photoelectric conversion, and a black reference pixel region (not shown) for outputting optical black that serves as a reference for the black level. In general, the black reference pixel region is arranged on the periphery of the effective pixel region.

[0034] The control circuit 3 generates various signals that serve as references for the operation of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc., based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock. The signals generated by the control circuit 3 are, for example, clock signals and control signals, and are input to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc.

[0035] The vertical drive circuit 4 includes, for example, a shift register, and sequentially selects and scans each pixel 1 in the pixel array region 2 in the vertical direction on a row-by-row basis. The vertical drive circuit 4 further supplies a pixel signal based on a signal charge generated by each pixel 1 in response to the amount of received light to a column signal processing circuit 5 through a vertical signal line 8.

[0036] The column signal processing circuit 5 is arranged, for example, for each column of pixels 1 in the pixel array region 2, and performs signal processing of signals output from one row of pixels 1 for each column based on signals from the black reference pixel region. Examples of this signal processing include noise removal and signal amplification. A horizontal selection switch (not shown) is provided between the output stage of the column signal processing circuit 5 and the horizontal signal line 9.

[0037] The horizontal drive circuit 6 includes, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in turn, causing each of the column signal processing circuits 5 to output a pixel signal to a horizontal signal line 9.

[0038] The output circuit 7 processes signals sequentially supplied from each of the column signal processing circuits 5 through a horizontal signal line 9, and outputs the processed signals.

[0039] Fig. 2 is a cross-sectional view showing the structure of the solid-state imaging device of the first embodiment. Fig. 2 shows nine pixels 1 included in the pixel array region 2 of Fig. 1, and more specifically, one pixel 1 and its eight neighboring pixels 1.

[0040] FIG. 2 shows X, Y, and Z axes that are perpendicular to each other. The X and Y directions correspond to the lateral (horizontal) direction, and the Z direction corresponds to the longitudinal (vertical) direction. The +Z direction corresponds to the upward direction, and the -Z direction corresponds to the downward direction. The -Z direction may or may not strictly coincide with the direction of gravity.

[0041] Fig. 2 further shows an X' axis tilted relative to the X axis and a Y' axis tilted relative to the Y axis. The X' and Y' directions, like the X and Y directions, correspond to the lateral (horizontal) direction. Fig. 2 further shows line A-A' parallel to the X' direction and line B-B' parallel to the Y' direction.

[0042] Fig. 3 is a vertical cross-sectional view showing the structure of the solid-state imaging device of the first embodiment. Fig. 4 is another vertical cross-sectional view showing the structure of the solid-state imaging device of the first embodiment. Fig. 3 shows a cross-section (X'Z cross-section) along the line A-A' shown in Fig. 2, and Fig. 4 shows a cross-section (Y'Z cross-section) along the line B-B' shown in Fig. 2. Fig. 2 shows a cross-section (XY cross-section) along the line A-A' shown in Fig. 3 or the line B-B' shown in Fig. 4. However, for ease of explanation, Fig. 2 shows not only the components in this XY cross-section, but also some components located lower than this XY cross-section.

[0043] The structure of the solid-state imaging device of this embodiment will be described below with reference to FIGS.

[0044] 2 to 4, the solid-state imaging device of this embodiment includes a plurality of photodiodes PD, a plurality of floating diffusion regions FD, a plurality of transfer transistors TR, and a plurality of reset transistors RST. These photodiodes PD are examples of photoelectric conversion regions of the present disclosure, and these floating diffusion regions FD are examples of charge accumulation regions of the present disclosure.

[0045] The solid-state imaging device of this embodiment further includes a support substrate 11, multiple wiring layers 12, 13, and 14, an interlayer insulating film 15, multiple contact plugs 16, and a gate insulating film 17, a gate electrode 18, and a sidewall insulating film 19 included in each transfer transistor TR.

[0046] The solid-state imaging device of this embodiment further includes a substrate 21, an n-type semiconductor region 22 and a p-type semiconductor region 23 included in each photodiode PD, and an n+ type semiconductor region 24 included in each floating diffusion FD. The n-type semiconductor region 22, the p-type semiconductor region 23, and the n+ type semiconductor region 24 are provided within the substrate 21.

[0047] The solid-state imaging device of this embodiment further includes a groove 31 provided in the substrate 21, an element isolation section 32 provided in the groove 31, an element isolation insulating film 33 and a light-shielding film 34 included in the element isolation section 32, a planarization film 35, a color filter layer 36, and an on-chip lens 37. The groove 31 includes a plurality of linear grooves 31a which are an example of the first part of the present disclosure, and a plurality of annular grooves 31b which are an example of the second part of the present disclosure. Similarly, the element isolation section 32 includes a plurality of linear parts 32a and a plurality of annular parts 32b. In addition, the light-shielding film 34 includes an inner light-shielding film 34a provided in the groove 31 and an outer light-shielding film 34b provided outside the groove 31.

[0048] The substrate 21 is, for example, a semiconductor substrate such as a silicon (Si) substrate. In Fig. 3 and Fig. 4, the surface of the substrate 21 in the -Z direction is the front surface S1 of the substrate 21, and the surface of the substrate 21 in the +Z direction is the back surface S2 of the substrate 21. Since the solid-state imaging device of this embodiment is a back-illuminated type, the back surface S2 of the substrate 21 is the light incidence surface of the substrate 21. The thickness of the substrate 21 is, for example, 1 to 6 µm. The substrate 21 may be, for example, a laminated substrate including a semiconductor substrate and a semiconductor layer formed on the front surface or back surface of the semiconductor substrate.

[0049] The substrate 21 includes an n-type semiconductor region 22 and a p-type semiconductor region 23 included in each photodiode PD, and an n+ type semiconductor region 24 included in each floating diffusion FD. As shown in Figures 2 to 4, the n-type semiconductor region 22 is located approximately in the center of each photodiode PD, and the p-type semiconductor region 23 is located approximately around the n-type semiconductor region 22. The n+ type semiconductor region 24 is located near the surface S1 of the substrate 21.

[0050] In addition, the p-type semiconductor region and the n-type semiconductor region in the substrate 21 of this embodiment may be interchanged. For example, the n-type semiconductor region 22, the p-type semiconductor region 23, and the n+ type semiconductor region 24 may be changed to a p-type semiconductor region, an n-type semiconductor region, and a p+ type semiconductor region, respectively.

[0051] Each photodiode PD includes an n-type semiconductor region 22 and a p-type semiconductor region 23 forming a pn junction, and functions as a photoelectric conversion section that converts received light into electric charges to generate signal charges. Fig. 2 shows nine photodiodes PD provided for nine pixels 1, and more specifically, one photodiode PD and eight photodiodes PD adjacent to it. As shown in Fig. 2, the photodiodes PD of this embodiment are arranged in a two-dimensional array in the shape of a square lattice.

[0052] Each floating diffusion FD includes an n+ type semiconductor region 24 and functions as a charge storage section that stores signal charges generated by the corresponding photodiode PD and a charge-voltage conversion section that converts the signal charges into a voltage signal and outputs it. Figure 2 shows four floating diffusion sections FD. The floating diffusion sections FD of this embodiment are arranged in a two-dimensional array in the shape of a square lattice, as shown in Figure 2.

[0053] Each floating diffusion section FD in this embodiment is provided between four photodiodes PD adjacent to each other. For example, the floating diffusion section FD in the upper left of FIG. 2 is provided between the four photodiodes PD in the upper left, left, upper, and center of FIG. 2. This floating diffusion section FD is used as a charge storage section for the photodiode PD in the center of FIG. 2, as described later. Similarly, each floating diffusion section FD in FIG. 2 is used as a charge storage section for the photodiode PD in the lower right thereof. Note that the floating diffusion section FD in this embodiment is precisely disposed at a position lower than the A-A' line and the B-B' line as shown in FIG. 3 and FIG. 4, but is illustrated in FIG. 2 for ease of understanding.

[0054] Each transfer transistor TR is provided on the surface S1 of the substrate 21, and transfers a signal charge from a corresponding photodiode PD to a corresponding floating diffusion FD. For example, the transfer transistor TR shown in FIG. 3 transfers a signal charge from the photodiode PD shown in FIG. 3 to the floating diffusion FD on the left of it. In FIG. 2, this transfer transistor TR is disposed between the photodiode PD in the center of FIG. 2 and the floating diffusion FD on the upper left thereof. Note that the transfer transistor TR in this embodiment is, to be precise, disposed at a position lower than the A-A' line and the B-B' line, but is illustrated in FIG. 2 for ease of understanding.

[0055] Each reset transistor RST is provided on the surface S1 of the substrate 21, similar to the transfer transistor TR, and initializes the corresponding floating diffusion portion FD, that is, resets the potential of the corresponding floating diffusion portion FD to the power supply potential (VDD potential). For example, the floating diffusion portion FD at the upper left of Fig. 2 is initialized by the reset transistor RST at the upper left thereof. Note that the reset transistor RST in this embodiment is actually disposed at a position lower than the A-A' line and the B-B' line, but is illustrated in Fig. 2 for ease of understanding.

[0056] As described above, the signal charge generated by the photodiode PD in the center of Fig. 2 is accumulated in the floating diffusion region FD in the upper left of Fig. 2 by the transfer transistor TR in the upper left of Fig. 2. This floating diffusion region FD is initialized by the reset transistor RST in the upper left of Fig. 2.

[0057] The support substrate 11 is provided below the substrate 21 with an interlayer insulating film 15 interposed therebetween. The support substrate 11 is, for example, a semiconductor substrate such as a silicon substrate. The support substrate 11 is provided to ensure the strength of the substrate 21. The interlayer insulating film 15 is, for example, an insulating film such as a silicon oxide film.

[0058] The wiring layers 12 to 14 are provided in the interlayer insulating film 15 to form a multilayer wiring structure. The multilayer wiring structure of this embodiment includes three wiring layers 12 to 14, but may include four or more wiring layers. Each of the wiring layers 12 to 14 includes various wirings, and pixel transistors such as the transfer transistor TR and the reset transistor RST are driven using these wirings. The wiring layers 12 to 14 include metal layers such as a tungsten (W) layer, a copper (Cu) layer, and an aluminum (Al) layer. The wiring layers 12 to 14 may include wirings M that function as a reflective film or a light-shielding film.

[0059] The contact plug 16 is formed on the wiring layer 14 in the interlayer insulating film 15. The contact plug 16 is in contact with, for example, the lower surface of the n+ type semiconductor region 24 of the floating diffusion portion FD or the lower surface of the gate electrode 18 of the transfer transistor TR.

[0060] The gate insulating film 17, gate electrode 18, and sidewall insulating film 19 of each transfer transistor TR are provided on the surface S1 of the substrate 21, and are covered with the interlayer insulating film 15. Specifically, the gate insulating film 17 and the gate electrode 18 are formed in this order on the surface S1 of the substrate 21, and the sidewall insulating film 19 is formed on the side surface of the gate electrode 18. In Fig. 3, the gate electrode 18 is provided below the p-type semiconductor region 23 between the n-type semiconductor region 22 and the n+ type semiconductor region 24, with the gate insulating film 17 interposed therebetween.

[0061] The groove 31 is provided in the substrate 21 and extends in the vertical direction (Z direction) within the substrate 21. As shown in Fig. 2, the groove 31 of this embodiment has a generally mesh-like planar shape. More specifically, the groove 31 of this embodiment includes a plurality of linear grooves 31a and a plurality of annular grooves 31b.

[0062] As shown in FIG. 2, each linear groove 31a has a linear planar shape extending in the X-direction or Y-direction. Since each linear groove 31a also extends in the Z-direction, it has a plate-like shape parallel to the XZ plane or YZ plane. In this embodiment, each linear groove 31a penetrates the substrate 21 and extends from the back surface S2 to the front surface S1 of the substrate 21. Each linear groove 31a is provided between two photodiodes PD adjacent to each other. For example, the left linear portion 31a of the center photodiode PD in FIG. 2 is provided between the center and left two photodiodes PD in FIG. 2.

[0063] Each annular groove 31b has a cylindrical shape extending in the Z direction, and has an opening E1 in a part of the cylindrical shape. The opening E1 is a portion in the substrate 21 where the groove 31 is not formed. Therefore, the substrate portion inside each annular groove 31b and the substrate portion outside each annular groove 31b are connected to each other by the substrate portion in the opening E1. As shown in FIG. 3, each annular groove 31b in this embodiment includes a portion penetrating the substrate 21 and a portion not penetrating the substrate 21. The portion not penetrating the substrate 21 extends from the back surface S2 of the substrate 21 but does not reach the front surface S1 of the substrate 21. The opening E1 in this embodiment is located below the portion not penetrating the substrate 21. The opening E1 is an example of a first opening in the present disclosure.

[0064] Each annular groove 31b in this embodiment has an O-shaped (annular) planar shape at its upper part and a C-shaped planar shape at its lower part. Fig. 2 shows the C-shaped planar shape of each annular groove 31b. In other words, each annular groove 31b has a C-shaped shape in a cross section (XY cross section) passing through the opening E1. Each annular groove 31b is provided between four linear grooves 31a and around the corresponding floating diffusion portion FD.

[0065] The element isolation portion 32 includes an element isolation insulating film 33 and a light-shielding film 34 formed in sequence in the trench 31. The element isolation insulating film 33 is formed on the side and bottom surface of the trench 31. The light-shielding film 34 is embedded in the trench 31 via the element isolation insulating film 33. The element isolation portion 32 includes a plurality of linear portions 32a formed in a plurality of linear trenches 31a, and a plurality of annular portions 32b formed in a plurality of annular grooves 31b. Each linear portion 32a includes an element isolation insulating film 33 and a light-shielding film 34 in sequence. Similarly, each annular portion 32b includes an element isolation insulating film 33 and a light-shielding film 34 in sequence.

[0066] The element isolation insulating film 33 functions as an insulating film for electrically isolating the pixels 1 from one another (for example, the photodiodes PD from one another). The element isolation insulating film 33 is, for example, a silicon oxide film. The element isolation insulating film 33 may be a transparent insulating film or an insulating film having a light-shielding property, and when the element isolation insulating film 33 has a light-shielding property, it also functions as a light-shielding film. The element isolation insulating film 33 of this embodiment is a transparent insulating film, and is formed not only in the grooves 31 but also on the rear surface S2 of the substrate 21 above each photodiode PD (see FIGS. 3 and 4). The element isolation insulating film 33 may include a fixed charge film having a negative fixed charge.

[0067] The light-shielding film 34 is a film that blocks light, and is provided to suppress the intrusion of light from one location to another location in the solid-state imaging device. The light-shielding film 34 is, for example, a metal layer such as a tungsten layer, or a compound semiconductor layer with a chalcopyrite structure having a high light absorption coefficient. For example, the light-shielding film 34 in the linear groove 31a can suppress the intrusion of light from one photodiode PD to another photodiode PD, and the light-shielding film 34 in the annular groove 31b can suppress the intrusion of light from the photodiode PD to the floating diffusion portion FD. The light-shielding film 34 of this embodiment includes not only the internal light-shielding film 34a provided in the groove 31, but also the external light-shielding film 34b provided outside the groove 31 (see FIGS. 3 and 4). The external light-shielding film 34b is provided on each annular groove 31a, and can suppress the intrusion of light from the planarization film 35 to the floating diffusion portion FD. The light-shielding film 34 may be an insulating film.

[0068] The planarization film 35 is formed so as to cover the rear surface S2 of the substrate 21, thereby making the surface on the rear surface S2 of the substrate 21 flat. The planarization film 35 is, for example, an organic film such as a resin film. The planarization film 35 may be an insulating film other than an organic film, in which case the upper surface of the insulating film may be planarized by CMP (Chemical Mechanical Polishing).

[0069] The color filter layer 36 is formed on the planarization film 35 for each pixel 1. For example, a color filter layer 36 for red (R), green (G), or blue (B) is disposed above the photodiode PD of the red, green, or blue pixel 1. A color filter layer 36 for infrared light may be disposed above the photodiode PD of the infrared pixel 1. The color filter layer 36 has a property of transmitting light of a predetermined wavelength, and the light transmitted through the color filter layer 36 is incident on the photodiode PD via the planarization film 35 and the element isolation insulating film 33.

[0070] The on-chip lens 37 is formed for each pixel 1 on the color filter layer 36. The on-chip lens 37 has a property of collecting incident light, and the light collected by the on-chip lens 37 is incident on the photodiode PD via the color filter layer 36, the planarization film 35, and the element isolation insulating film 33.

[0071] Next, still with reference to FIGS. 2 to 4, the groove 31 of this embodiment will be described in further detail.

[0072] As described above, the upper left floating diffusion FD in Fig. 2 is provided between the four photodiodes PD at the upper left, left, upper, and center. Also, the signal charge generated by the center photodiode PD in Fig. 2 is accumulated in the upper left floating diffusion FD.

[0073] Therefore, the upper left annular groove 31b in FIG. 2 has an opening E1 only between the central photodiode PD and the floating diffusion portion FD, and does not have an opening E1 between the upper left, left, and upper photodiodes PD and the floating diffusion portion FD. This allows the signal charge to be transferred from the central photodiode PD to the floating diffusion portion FD through the opening E1, and also allows stray light from the other photodiodes PD to the floating diffusion portion FD to be suppressed. The central photodiode PD is an example of the first photoelectric conversion portion of the present disclosure. The upper left, left, and upper photodiodes PD are examples of the second, third, and fourth photoelectric conversion portions of the present disclosure.

[0074] 2 penetrates the substrate 21 between the upper left, left, and top photodiodes PD and the upper left floating diffusion FD. Therefore, stray light from these photodiodes PD to this floating diffusion FD can be effectively suppressed by the light-shielding film 34 in the annular groove 31b.

[0075] On the other hand, the annular groove 31b at the upper left of FIG. 2 is formed so that an opening E1 remains between the central photodiode PD and the upper left floating diffusion FD. Therefore, the signal charge can be easily transferred from the photodiode PD to the floating diffusion FD through the opening E1. This is because if a light-shielding film 34 exists between the photodiode PD and the floating diffusion FD, it becomes difficult to transfer the signal charge. Furthermore, by providing an annular groove 31b that does not penetrate the substrate 21 between the central photodiode PD and the upper left floating diffusion FD, it is possible to suppress stray light from the photodiode PD to the floating diffusion FD to some extent.

[0076] 2 does not have to penetrate the substrate 21 between the upper left photodiode PD and the floating diffusion FD, between the left photodiode PD and the floating diffusion FD, and between the upper photodiode PD and the floating diffusion FD. For example, the upper left annular groove 31b in FIG. 2 may have an opening between the upper left photodiode PD and the floating diffusion FD. Such an opening will be described in the second embodiment.

[0077] The above description of the groove 31 can be similarly applied to annular grooves 31b other than the annular groove 31b in the upper left of FIG.

[0078] 5 and 6 are longitudinal sectional views showing a method for manufacturing the solid-state imaging device according to the first embodiment. A of Fig. 5 to B of Fig. 6 show longitudinal sectional views corresponding to Fig. 3.

[0079] First, as shown in A of FIG. 5, an n-type semiconductor region 22, a p-type semiconductor region 23, and an n+-type semiconductor region 24, as well as a gate insulating film 17, a gate electrode 18, and a sidewall insulating film 19 of the transfer transistor TR are formed in or on the substrate 21. At this stage, a gate insulating film, a gate electrode, and a sidewall insulating film of the reset transistor RST are also formed. In this manner, a photodiode PD, a floating diffusion layer FD, and a pixel transistor are formed. The photodiode PD and the floating diffusion layer FD are arranged in a two-dimensional array as shown in FIG. 2. The transfer transistor TR and the reset transistor RST are also arranged in a layout as shown in FIG. 2. Next, as shown in A of FIG. 5, a contact plug 16, an interlayer insulating film 15, and wiring layers 12 to 14 are formed on the substrate 21. The process of A of FIG. 5 is performed in a state where the front surface S1 of the substrate 21 faces upward and the back surface S2 of the substrate 21 faces downward.

[0080] Next, as shown in Fig. 5B, after the support substrate 11 is attached to the front surface S1 of the substrate 21 via the interlayer insulating film 15, the substrate 21 is turned upside down. Fig. 5B shows a state in which the front surface S1 of the substrate 21 faces downward and the back surface S2 of the substrate 21 faces upward.

[0081] Next, as shown in FIG. 5B, the substrate 21 is thinned from the rear surface S2, and then a groove 31 is formed in the substrate 21 by etching from the rear surface S2. The groove 31 is formed to include the above-mentioned linear groove 31a (not shown) and annular groove 31b. The linear groove 31a of this embodiment is formed to penetrate the substrate 21. On the other hand, the annular groove 31b of this embodiment is formed to include a portion that penetrates the substrate 21 and a portion that does not penetrate the substrate 21. As a result, an opening E1 of the annular groove 31b is formed below the portion that does not penetrate the substrate 21. The groove 31 is formed in a layout as shown in FIGS. 2 to 4. The process of forming the groove 31 will be described in detail later.

[0082] 6A, an element isolation insulating film 33 and a light-shielding film 34 are formed in this order on the rear surface S2 of the substrate 21. As a result, the element isolation insulating film 33 is formed on the side and bottom surface of the trench 31 and on the photodiode PD. Furthermore, the light-shielding film 34 is embedded in the trench 31 via the element isolation insulating film 33, and is formed on the photodiode PD via the element isolation insulating film 33. In this manner, an element isolation portion 32 is formed in the trench 31. More specifically, a linear portion 32a (not shown) is formed in the linear trench 31a, and an annular portion 32b is formed in the annular trench 31b.

[0083] 6B, the light-shielding film 34 outside the groove 31 is processed by etching. As a result, the light-shielding film 34 is processed to include an inner light-shielding film 34a inside the groove 31 and an outer light-shielding film 34b outside the groove 31. The outer light-shielding film 34b is formed on the annular groove 31b.

[0084] Thereafter, a planarization film 36, a color filter layer 37, and an on-chip lens 38 are formed in this order on the photodiode PD via an element isolation insulating film 33. In this manner, the solid-state imaging device of this embodiment is manufactured.

[0085] Next, various examples of the method for forming the groove 31 of this embodiment will be described with reference to Fig. 7 to Fig. 12. Fig. 7A to Fig. 12B show vertical cross sections corresponding to Fig. 5B (or Fig. 6B). However, for ease of understanding, the illustrations of the support substrate 11, the wiring layers 12 to 14, the interlayer insulating film 15, the contact plug 16, the gate insulating film 17, the gate electrode 18, the sidewall insulating film 19, the n-type semiconductor region 22, the p-type semiconductor region 23, and the n+ type semiconductor region 24 are omitted.

[0086] 7 and 8 are vertical cross-sectional views showing a first example of a method for forming the groove 31. In FIG.

[0087] First, a part (upper part) of the groove 31 is formed in the substrate 21 by etching from the rear surface S2 of the substrate 21 (A in FIG. 7). Specifically, each of the linear groove 31a and the annular groove 31b is formed to a position of height H.

[0088] Next, the remaining portion (lower portion) of the groove 31 is formed in the substrate 21 by etching from the rear surface S2 of the substrate 21 (B in FIG. 7). At this time, each linear groove 31a is processed so as to penetrate the substrate 21. Meanwhile, each annular groove 31b is processed so as to include a portion that penetrates the substrate 21 and a portion that does not penetrate the substrate 21. In the step of B in FIG. 7, only the portion of each annular groove 31b that penetrates the substrate 21 is processed, and the portion that does not penetrate the substrate 21 is not processed. As a result, an opening E1 of the annular groove 31b is formed below the portion that does not penetrate the substrate 21. In this manner, the groove 31 is formed.

[0089] 6A and 6B are then performed in this example. As a result, an element isolation portion 32 is formed in the trench 31 (FIG. 8A). The element isolation portion 32 is formed to include an element isolation insulating film 33 and a light shielding film 34 in this order.

[0090] In this example, the lower portion of the groove 31 may be formed in the substrate 21 by etching from the surface S1 of the substrate 21, and then the upper portion of the groove 31 may be formed in the substrate 21 by etching from the back surface S2 of the substrate 21. That is, the step B of FIG. 7 may be performed, and then the step A of FIG. 7 may be performed. In this case, the step B of FIG. 7 is performed before forming the support substrate 11, the wiring layers 12 to 14, the interlayer insulating film 15, the contact plug 16, the gate insulating film 17, the gate electrode 18, and the sidewall insulating film 19 on the surface S1 of the substrate 21. On the other hand, the step A of FIG. 7 may be performed before forming these on the surface S1 of the substrate 21, or may be performed after forming these on the surface S1 of the substrate 21.

[0091] In this case, the element isolation section 32 may be formed as follows. First, the lower part of the trench 31 is formed in the substrate 21 by etching from the front surface S1 of the substrate 21, and the element isolation insulating film 33' and the light-shielding film 34' are formed in the lower part of the trench 31 in that order (B in FIG. 8). Next, the upper part of the trench 31 is formed in the substrate 21 by etching from the rear surface S2 of the substrate 21, and the element isolation insulating film 33 and the light-shielding film 34 are formed in the upper part of the trench 31 in that order (B in FIG. 8). As a result, the element isolation section 32 is formed in the trench 31 so as to include the element isolation insulating films 33, 33' and the light-shielding films 34, 34' in that order. The materials of the element isolation insulating film 33' and the light-shielding film 34' are, for example, the same as the materials of the element isolation insulating film 33 and the light-shielding film 34, respectively.

[0092] 9 and 10 are vertical cross-sectional views showing a second example of a method for forming the groove 31. In FIG.

[0093] First, a trench 31c is formed in the substrate 21 as a part of the trench 31 by etching from the surface S1 of the substrate 21 (A in FIG. 9). Next, an element isolation insulating film 38 is formed in the trench 31c (A in FIG. 9). As a result, an element isolation portion is formed in the trench 31c. This element isolation portion is used, for example, to electrically isolate transistors on the surface S1 of the substrate 21 from each other. The element isolation insulating film 38 may be a transparent insulating film or an insulating film having a light-shielding property, but it is preferable that the insulating film has a light-shielding property here. When the element isolation insulating film 38 has a light-shielding property, it also functions as a light-shielding film. Note that the trench 31c and the element isolation insulating film 38 are formed before the support substrate 11, the wiring layers 12 to 14, the interlayer insulating film 15, the contact plug 16, the gate insulating film 17, the gate electrode 18, and the sidewall insulating film 19 are formed on the surface S1 of the substrate 21.

[0094] Next, a part (upper part) of the groove 31 is formed in the substrate 21 by etching from the rear surface S2 of the substrate 21 (A in FIG. 9). Specifically, each of the linear groove 31a and the annular groove 31b is formed to a position of height H.

[0095] Next, the remaining portion (lower portion) of the groove 31 is formed in the substrate 21 by etching from the rear surface S2 of the substrate 21 (B in FIG. 9). At this time, each linear groove 31a is processed so as to penetrate the substrate 21 alone or to penetrate the substrate 21 together with the groove 31c. That is, the linear groove 31a above the groove 31c (element isolation insulating film 38) is formed so as to reach the groove 21c (element isolation insulating film 38). On the other hand, each annular groove 31b is processed so as to include a portion that penetrates the substrate 21 alone or together with the groove 31c, and a portion that does not penetrate the substrate 21. In the step of B in FIG. 9, only the portion of each annular groove 31b that penetrates the substrate 21 alone or together with the groove 31c is processed, and the portion that does not penetrate the substrate 21 is not processed. As a result, an opening E1 of the annular groove 31b is formed below the portion that does not penetrate the substrate 21. In this manner, the groove 31 including the linear groove 31a, the annular groove 31b, and the groove 31c is formed.

[0096] 6A and 6B are then performed. As a result, an element isolation portion 32 is formed in the trench 31 (the linear trench 31a and the annular trench 31b). The element isolation portion 32 is formed to include an element isolation insulating film 33 and a light-shielding film 34, in that order. In this example, the element isolation portion in the trench 31c also becomes part of the element isolation portion 32.

[0097] The element isolation portion in the trench 31c may be formed to include an element isolation insulating film 38 and a light shielding film 39 in that order (A in FIG. 10). In this case, the materials of the element isolation insulating film 38 and the light shielding film 39 may be the same as the materials of the element isolation insulating film 33 and the light shielding film 34, respectively, for example.

[0098] Also, the bottom surface of the groove 31c may be formed up to the position of the height H described above (B in FIG. 10). In this case, the step of A in FIG. 9 may be performed thereafter, and the step of B in FIG. 9 may be omitted (B in FIG. 10). In this manner, the groove 31 including the linear groove 31a, the annular groove 31b, and the groove 31c is formed. Note that the element isolation portion in the groove 31c in this case may be formed by the method of A in FIG. 10.

[0099] Also, the groove 31 of this example may be formed in the following procedure. First, the groove 31c is formed in the substrate 21 by etching from the surface S1 of the substrate 21. The groove 31c is formed from the surface S1 of the substrate 21 in the same manner as in the process of A in FIG. 9. Next, a part (lower part) of the groove 31 is formed in the substrate 21 by etching from the surface S1 of the substrate 21. The lower part of the groove 31 is formed from the surface S1 of the substrate 21, unlike the process of B in FIG. 9. Next, the element isolation insulating film 33' and the light shielding film 34' are formed in order in the lower part of the groove 31 (the linear groove 31a and the annular groove 31b) in the same manner as in the process of B in FIG. 8, and the element isolation insulating film 38 is formed in the groove 31c. Next, the remaining part (upper part) of the groove 31 is formed in the substrate 21 by etching from the rear surface S2 of the substrate 21. The upper part of the groove 31 is formed from the rear surface S2 of the substrate 21 in the same manner as in the process of A in FIG. 9. Next, an element isolation insulating film 33 and a light shielding film 34 are formed in this order in the upper part of the trench 31 .

[0100] FIG. 11 is a vertical cross-sectional view showing a third example of a method for forming the groove 31. In FIG.

[0101] First, a part of the groove 31 is formed in the substrate 21 by etching from the rear surface S2 of the substrate 21 (A in FIG. 11). Specifically, the entire linear grooves 31a and the part of each annular groove 31b penetrating the substrate 21 are formed. In A in FIG. 11, the entire linear grooves 31a and the part of each annular groove 31b are formed so as to penetrating the substrate 31.

[0102] Next, the remainder of the groove 31 is formed in the substrate 21 by etching from the rear surface S2 of the substrate 21 (B in FIG. 11). Specifically, a portion of each annular groove 31b that does not penetrate the substrate 21 is formed. In B in FIG. 11, the corresponding portion of each annular groove 31b is formed up to a position of height H. As a result, an opening E1 of the annular groove 31b is formed below the portion that does not penetrate the substrate 21. In this manner, the groove 31 is formed.

[0103] 6A and 6B are then performed in this example. As a result, an element isolation portion 32 is formed in the trench 31. The element isolation portion 32 is formed so as to include an element isolation insulating film 33 and a light shielding film 34 in this order.

[0104] 11A, a part of the groove 31 may be formed in the substrate 21 by etching from the surface S1 of the substrate 21. In this case, the step of FIG. 11A is performed before the support substrate 11, the wiring layers 12 to 14, the interlayer insulating film 15, the contact plug 16, the gate insulating film 17, the gate electrode 18, and the sidewall insulating film 19 are formed on the surface S1 of the substrate 21. On the other hand, the step of FIG. 11B may be performed before these are formed on the surface S1 of the substrate 21, or may be performed after these are formed on the surface S1 of the substrate 21.

[0105] In this example, step B in FIG. 11 may be executed first, and then step A in FIG.

[0106] FIG. 12 is a vertical cross-sectional view showing a fourth example of a method for forming the groove 31. In FIG.

[0107] First, a trench 31c is formed in the substrate 21 as a part of the trench 31 by etching from the surface S1 of the substrate 21 (A in FIG. 12). Next, an element isolation insulating film 38 is formed in the trench 31c (A in FIG. 12). As a result, an element isolation portion is formed in the trench 31c. This element isolation portion is used, for example, to electrically isolate transistors on the surface S1 of the substrate 21 from each other. The element isolation insulating film 38 may be a transparent insulating film or an insulating film having a light-shielding property, but it is preferable that the insulating film has a light-shielding property here. When the element isolation insulating film 38 has a light-shielding property, it also functions as a light-shielding film. Note that the trench 31c and the element isolation insulating film 38 are formed before the support substrate 11, the wiring layers 12 to 14, the interlayer insulating film 15, the contact plug 16, the gate insulating film 17, the gate electrode 18, and the sidewall insulating film 19 are formed on the surface S1 of the substrate 21.

[0108] Next, a part of the groove 31 is formed in the substrate 21 by etching from the rear surface S2 of the substrate 21 (A in FIG. 12). Specifically, the entire linear grooves 31a and the part of each annular groove 31b penetrating the substrate 21 are formed. In A in FIG. 12, the entire linear grooves 31a and the part of each annular groove 31b are formed so as to penetrate the substrate 31 alone or to penetrate the substrate 31 together with the groove 31c.

[0109] Next, the remainder of the groove 31 is formed in the substrate 21 by etching from the rear surface S2 of the substrate 21 (B in FIG. 12). Specifically, a portion of each annular groove 31b that does not penetrate the substrate 21 is formed. In B in FIG. 12, the corresponding portion of each annular groove 31b is formed up to a position of height H. As a result, an opening E1 of the annular groove 31b is formed below the portion that does not penetrate the substrate 21. In this manner, the groove 31 including the linear groove 31a, the annular groove 31b, and the groove 31c is formed.

[0110] 6A and 6B are then performed. As a result, an element isolation portion 32 is formed in the trench 31 (the linear trench 31a and the annular trench 31b). The element isolation portion 32 is formed to include an element isolation insulating film 33 and a light-shielding film 34, in that order. In this example, the element isolation portion in the trench 31c also becomes part of the element isolation portion 32.

[0111] In this example, step B in FIG. 12 may be executed first, and then step A in FIG.

[0112] 10A, the element isolation portion in the trench 31c of the present example may be formed to include an element isolation insulating film 38 and a light shielding film 39 in that order. In this case, the materials of the element isolation insulating film 38 and the light shielding film 39 may be the same as the materials of the element isolation insulating film 33 and the light shielding film 34, respectively.

[0113] Also, the groove 31 of this example may be formed by the following procedure. First, the groove 31c is formed in the substrate 21 by etching from the surface S1 of the substrate 21. The groove 31c is formed from the surface S1 of the substrate 21 in the same manner as in the process of A in FIG. 12. Next, a part of the groove 31 is formed in the substrate 21 by etching from the surface S1 of the substrate 21. Specifically, all of the linear grooves 31a and a part of each annular groove 31b penetrating the substrate 21 are formed. The part of the groove 31 is formed from the surface S1 of the substrate 21, unlike the process of A in FIG. 12. Next, the element isolation insulating film 33' and the light shielding film 34' are formed in that part of the groove 31 (the linear groove 31a and the annular groove 31b) in the same order as in the process of B in FIG. 8, and the element isolation insulating film 38 is formed in the groove 31c. Next, the remaining part of the groove 31 is formed in the substrate 21 by etching from the back surface S2 of the substrate 21. Specifically, a portion of each annular groove 31b that does not penetrate the substrate 21 is formed. The remaining portion of the groove 31 is formed from the rear surface S2 of the substrate 21, similar to the step B of Fig. 12. Next, an element isolation insulating film 33 and a light-shielding film 34 are formed in this order in the remaining portion of the groove 31.

[0114] The first to fourth examples are also applicable to the second to fifth embodiments described later.

[0115] As described above, the groove 31 of this embodiment is formed to include a plurality of linear grooves 31a and a plurality of annular grooves 31b, and each annular groove 31b is formed to include a portion that penetrates the substrate 21 and a portion that does not penetrate the substrate 21. As a result, each annular groove 31b of this embodiment is formed to have an opening E1 below the portion that does not penetrate the substrate 21.

[0116] Therefore, according to this embodiment, it is possible to transfer signal charges from a given photodiode PD to the floating diffusion portion FD through the opening E1, while suppressing stray light from other photodiodes PD to the floating diffusion portion FD by the light-shielding film 34 in the annular groove 31b. Also, according to this embodiment, it is possible to suppress stray light from one photodiode PD to another photodiode PD by the light-shielding film 34 in the linear groove 31a. Also, according to this embodiment, it is possible to suppress color mixing between pixels 1 by the element isolation insulating film 33 and the light-shielding film 34 in the groove 31.

[0117] As described above, according to this embodiment, it is possible to improve the light blocking property of the floating diffusion section FD.

[0118] Second embodiment Fig. 13 is a cross-sectional view showing the structure of a solid-state imaging device according to the second embodiment. Like Fig. 2, Fig. 13 shows nine pixels 1 included in the pixel array region 1 of Fig. 1.

[0119] Fig. 14 is a longitudinal sectional view showing the structure of the solid-state imaging device of the second embodiment. Fig. 15 is another longitudinal sectional view showing the structure of the solid-state imaging device of the second embodiment. Fig. 14 shows a cross section (X'Z cross section) along the line A-A' shown in Fig. 13, and Fig. 15 shows a cross section (Y'Z cross section) along the line B-B' shown in Fig. 13. Fig. 13 shows a cross section (XY cross section) along the line A-A' shown in Fig. 14 or the line B-B' shown in Fig. 15. However, for ease of explanation, Fig. 13 shows not only the components in this XY cross section, but also some components at a lower position than this XY cross section.

[0120] The structure of the solid-state imaging device of this embodiment will be described below with reference to FIGS.

[0121] The solid-state imaging device of this embodiment includes the same components as the solid-state imaging device of the first embodiment. However, each annular groove 31b of this embodiment has a cylindrical shape extending in the Z direction, but has an opening E1 and an opening E2 in a part of the cylindrical shape. The opening E2 is a part in which the groove 31 is not formed in the substrate 21, similar to the opening E1. Therefore, the substrate part inside each annular groove 31b and the substrate part outside each annular groove 31b are connected to each other by the substrate part in the opening E2. As shown in FIG. 14 and FIG. 15, each annular groove 31b of this embodiment includes a part penetrating the substrate 21 and a part not penetrating the substrate 21. The part not penetrating the substrate 21 extends from the back surface S2 of the substrate 21 but does not reach the front surface S1 of the substrate 21. The opening E2 of this embodiment is located below the part not penetrating the substrate 21, similar to the opening E1. The opening E2 is an example of a second opening of the present disclosure.

[0122] Next, the groove 31 of this embodiment will be described in further detail.

[0123] The floating diffusion portion FD in the upper left of Fig. 13 is provided between the four photodiodes PD at the upper left, left, upper, and center. The signal charge generated by the photodiode PD at the center of Fig. 13 is accumulated in the floating diffusion portion FD in the upper left. The floating diffusion portion FD in the upper left of Fig. 13 is initialized by the reset transistor RST at the upper left.

[0124] Therefore, the annular groove 31b at the upper left of FIG. 13 has an opening E2 between the floating diffusion portion FD and the reset transistor RST. This allows the floating diffusion portion FD and the reset transistor RST to be easily electrically connected even if the reset transistor RST is disposed at the upper left of the floating diffusion portion FD. The photodiode PD at the center is an example of the first photoelectric conversion portion of the present disclosure, and the photodiode PD at the upper left is an example of the third photoelectric conversion portion of the present disclosure. The photodiodes PD at the left and upper are examples of the second and fourth photoelectric conversion portions of the present disclosure. In FIG. 13, the third photoelectric conversion portion is disposed on the opposite side of the first photoelectric conversion portion with respect to the floating diffusion portion FD, and the reset transistor RST is disposed on the third photoelectric conversion portion side with respect to the floating diffusion portion FD.

[0125] 13 penetrates the substrate 21 between the left and upper photodiodes PD and the upper left floating diffusion FD. Therefore, stray light from these photodiodes PD to the floating diffusion FD can be effectively suppressed by the light-shielding film 34 in the annular groove 31b.

[0126] On the other hand, the annular groove 31b at the upper left of FIG. 13 is formed so that an opening E1 remains between the central photodiode PD and the upper left floating diffusion FD. Therefore, the signal charge can be easily transferred from the photodiode PD to the floating diffusion FD through the opening E1. This is because if a light-shielding film 34 exists between the photodiode PD and the floating diffusion FD, it becomes difficult to transfer the signal charge. Furthermore, by providing an annular groove 31b that does not penetrate the substrate 21 between the central photodiode PD and the upper left floating diffusion FD, it is possible to suppress stray light from the photodiode PD to the floating diffusion FD to some extent.

[0127] 13 is formed so that an opening E2 remains between the upper left photodiode PD and the upper left floating diffusion FD. Therefore, even if the reset transistor RST is disposed at the upper left of the floating diffusion FD, the floating diffusion FD and the reset transistor RST can be easily electrically connected. Furthermore, by providing the annular groove 31b that does not penetrate the substrate 21 between the upper left photodiode PD and the upper left floating diffusion FD, it is possible to suppress stray light from the photodiode PD to the floating diffusion FD to some extent.

[0128] The above description regarding the groove 31 can be similarly applied to annular grooves 31b other than the annular groove 31b in the upper left of FIG.

[0129] The solid-state imaging device of this embodiment can be manufactured by the method shown in Fig. 5 and Fig. 6. However, in step B of Fig. 5, the groove 31 is formed so that an opening E2 of the annular groove 31b is formed similarly to the opening E1 of the annular groove 31b.

[0130] According to this embodiment, it is possible to easily electrically connect the floating diffusion portion FD and the reset transistor RST, and it is also possible to suppress stray light to the floating diffusion portion FD.

[0131] Third embodiment Fig. 16 is a cross-sectional view showing the structure of a solid-state imaging device according to a third embodiment. Like Fig. 2, Fig. 16 shows nine pixels 1 included in the pixel array region 1 of Fig. 1. Fig. 16 further shows line CC' parallel to the X direction.

[0132] Fig. 17 is a vertical cross-sectional view showing the structure of a solid-state imaging device of the third embodiment. Fig. 17 shows a cross section (XZ cross section) taken along line CC' shown in Fig. 16. Fig. 16 shows a cross section (XY cross section) taken along line CC' shown in Fig. 17. However, for ease of understanding, Fig. 16 shows not only components within this XY cross section, but also some components located lower than this XY cross section.

[0133] With regard to the solid-state imaging device of this embodiment, the structure along line A-A' shown in FIG. 16 is the same as the structure shown in FIG. 3, and the structure along line B-B' shown in FIG. 16 is the same as the structure shown in FIG. 4.

[0134] The structure of the solid-state imaging device of this embodiment will be described below with reference to FIGS.

[0135] The solid-state imaging device of this embodiment includes the same components as the solid-state imaging device of the first embodiment. However, the linear groove 31a on the left in FIG. 16 has a plate-like shape extending in the Z direction, but has an opening E3 in a part of the plate-like shape. The opening E3 is a part in the substrate 21 where the groove 31 is not formed, similar to the opening E1. Therefore, the substrate part on the left side of this linear groove 31a and the substrate part on the right side of this linear groove 31a are connected to each other by the substrate part in the opening E3. This linear groove 31a of this embodiment includes a part penetrating the substrate 21 (FIG. 17) and a part not penetrating the substrate 21. The part not penetrating the substrate 21 extends from the back surface S2 of the substrate 21, but does not reach the front surface S1 of the substrate 21. The opening E3 of this embodiment is located below the part not penetrating the substrate 21, similar to the opening E1. The opening E3 is an example of a third opening of the present disclosure.

[0136] The solid-state imaging device of the present embodiment further includes a plurality of floating diffusion parts OFD different from the floating diffusion part FD, and a plurality of transfer transistors OFG different from the transfer transistor TR. Figure 16 shows one of these floating diffusion parts OFD and two of these transfer transistors OFG. The floating diffusion part OFD is an example of a charge storage part different from the above-mentioned charge storage part.

[0137] The solid-state imaging device of this embodiment further includes an n+ type semiconductor region 25 included in each floating diffusion portion OFD. The n+ type semiconductor region 25 is provided in the substrate 21, and is located in the vicinity of the surface S1 of the substrate 21.

[0138] Each floating diffusion portion OFD includes an n+ type semiconductor region 25. Each floating diffusion portion OFD of this embodiment is provided between two photodiodes PD adjacent to each other. For example, the floating diffusion portion OFD of FIG. 16 is provided between the two photodiodes PD in the center and the left of FIG. 16, and is located in the opening portion E3. This floating diffusion portion OFD is used as a charge storage portion common to the photodiodes PD in the center and the left of FIG. 16, as described later. Note that the floating diffusion portion OFD of this embodiment is precisely located at a position lower than the line C-C' as shown in FIG. 17, but is illustrated in FIG. 16 for ease of understanding.

[0139] Each transfer transistor OFG is provided on the surface S1 of the substrate 21 and disposed near the corresponding photodiode PD. The transfer transistor OFG in FIG. 17 includes a gate insulating film 17, a gate electrode 18, and a sidewall insulating film 19, similar to the above-mentioned transfer transistor TR. Each transfer transistor OFG in this embodiment is provided between the corresponding photodiode PD and the floating diffusion part OFD, and is used to discharge the charge overflowing from the corresponding photodiode PD when intense light is incident. Note that the transfer transistor OFG in this embodiment is disposed at a position lower than the line C-C' as shown in FIG. 17, but is illustrated in FIG. 16 for ease of understanding.

[0140] The solid-state imaging device of this embodiment can be manufactured by the method shown in Fig. 5 and Fig. 6. However, in step B of Fig. 5, the groove 31 is formed so that the opening E3 of the linear groove 31a is formed similarly to the opening E1 of the annular groove 31b. In addition, the floating diffusion region OFD, the transfer transistor OFG, and the n+ type semiconductor region 25 are formed in step A of Fig. 5.

[0141] According to this embodiment, by providing the openings E3 in the linear grooves 31a, it becomes possible to use each floating diffusion portion OFD as a charge storage portion common to the two photodiodes PD.

[0142] (Fourth embodiment) Fig. 18 is a cross-sectional view showing the structure of a solid-state imaging device according to the fourth embodiment. Like Fig. 2, Fig. 18 shows nine pixels 1 included in the pixel array region 1 of Fig. 1.

[0143] Fig. 19 is a longitudinal sectional view showing the structure of the solid-state imaging device of the fourth embodiment. Fig. 20 is another longitudinal sectional view showing the structure of the solid-state imaging device of the fourth embodiment. Fig. 19 shows a cross section (X'Z cross section) along the line A-A' shown in Fig. 18, and Fig. 20 shows a cross section (Y'Z cross section) along the line B-B' shown in Fig. 18. Fig. 18 shows a cross section (XY cross section) along the line A-A' shown in Fig. 19 or the line B-B' shown in Fig. 20. However, for ease of explanation, Fig. 18 shows not only the components in this XY cross section, but also some components at a lower position than this XY cross section.

[0144] The structure of the solid-state imaging device of this embodiment will be described below with reference to FIGS.

[0145] The solid-state imaging device of this embodiment includes, in addition to the components of the solid-state imaging device of the first embodiment, a moth-eye structure 26 provided on the upper surface (rear surface S2) of the substrate 21 above each photodiode PD.

[0146] The moth-eye structure 26 is a minute uneven structure provided on the upper surface of the substrate 21, and includes a plurality of convex portions and a plurality of concave portions. These concave portions have, for example, a pyramid shape extending in the -Z direction, and are arranged in a two-dimensional array. The element isolation insulating film 33 and the planarization film 35 are embedded in these concave portions. According to this embodiment, by providing the moth-eye structure 26 on each photodiode PD, it is possible to reduce the reflection of incident light and improve the sensitivity of the solid-state imaging device.

[0147] However, the moth-eye structure 26 may scatter the light incident on the photodiode PD to the floating diffusion FD, causing stray light to the floating diffusion FD. Therefore, in this embodiment, as described in the first embodiment, the floating diffusion FD is generally surrounded by the annular groove 31b, and the connection between the photodiode PD and the floating diffusion FD is limited to the opening E1. Therefore, according to this embodiment, it is possible to suppress stray light to the floating diffusion FD caused by the moth-eye structure 26 while enjoying the advantages of the moth-eye structure 26.

[0148] The moth-eye structure 26 of this embodiment is also applicable to each embodiment other than the first embodiment.

[0149] The solid-state imaging device of this embodiment can be manufactured by the method shown in Figure 5 and Figure 6. However, before performing the step A of Figure 6, a moth-eye structure 26 is formed on the rear surface S2 of the substrate 21.

[0150] Fifth embodiment FIG. 21 is a plan view and a cross-sectional view showing the structure of a solid-state imaging device according to the fifth embodiment.

[0151] A of Fig. 21 is a plan view showing a schematic structure of the pixel array region 2 of Fig. 1. A of Fig. 21 shows four partial regions 2a, 2b, 2c, and 2d included in the pixel array region 2, and a center C of the pixel array region 2. The pixel array region 2 of this embodiment is divided into four partial regions 2a to 2d by boundary lines L1 and L2 that pass through the center C. The center C corresponds to the origin of the four quadrants.

[0152] Partial region 2a is located at the upper left of A in FIG. 21. Partial region 2b is located at the lower right of A in FIG. 21 and is provided on the opposite side of partial region 2a with respect to center C. Partial region 2c is located at the upper right of A in FIG. 21 and is provided between partial region 2a and partial region 2b. Partial region 2d is located at the lower left of A in FIG. 21 and is provided on the opposite side of partial region 2c with respect to center C. Each of partial regions 2a to 2d includes a plurality of pixels 1. Partial regions 2a, 2b, 2c, and 2d are examples of first, second, third, and fourth regions of the present disclosure, respectively.

[0153] The number of pixels 1 in each partial region may be the same as the number of pixels 1 in the other partial regions, or may be different from the number of pixels 1 in the other partial regions. Therefore, the center C of the pixel array region 2 may be located at the exact center of all the pixels 1 in the pixel array region 2, or may be located at a point shifted from the exact center of all the pixels 1 in the pixel array region 2.

[0154] Fig. 21B is a cross-sectional view showing the structure of the pixel array region 2 in Fig. 1, and is a cross-sectional view showing a detail of the plan view of Fig. 21A. Fig. 21B shows nine pixels 1 included in partial region 2a, nine pixels 1 included in partial region 2b, nine pixels 1 included in partial region 2c, and nine pixels 1 included in partial region 2d.

[0155] As shown in FIG. 21B, each of the partial regions 2a to 2d has a structure similar to that shown in FIG. 2. However, the partial region 2a includes a floating diffusion portion FD, a transfer transistor TR, and a reset transistor RST corresponding to the central photodiode PD at the lower right of the central photodiode PD, and the annular groove 31b around the floating diffusion portion FD has an opening E1 at the upper left. The partial region 2b includes a floating diffusion portion FD and the like corresponding to the central photodiode PD at the upper left, and the annular groove 31b around the floating diffusion portion FD has an opening E1 at the lower right. The partial region 2c includes a floating diffusion portion FD and the like corresponding to the central photodiode PD at the lower left, and the annular groove 31b around the floating diffusion portion FD has an opening E1 at the upper right. The partial region 2d includes a floating diffusion portion FD and the like corresponding to the central photodiode PD at the upper right, and the annular groove 31b around the floating diffusion portion FD has an opening E1 at the lower left.

[0156] In this manner, the opening E1 of each annular groove 31b in each partial region is provided on the opposite side of the annular groove 31b from the center C. Thus, the opening E1 in partial region 2a is provided on the opposite side of the center C from the opening E1 in partial region 2b. Similarly, the opening E1 in partial region 2c is provided on the opposite side of the center C from the opening E1 in partial region 2d.

[0157] In the solid-state imaging device of this embodiment, strong light is incident on the vicinity of the center C of the pixel array region 2, and this light is considered to proceed to the partial regions 2a to 2d as shown by the arrows in B of FIG. 21. Therefore, if the opening E1 faces the center C, stray light from the opening E1 to the floating diffusion portion FD is likely to occur. Therefore, each opening E1 of this embodiment faces the opposite side of the center C. This makes it possible to effectively suppress stray light from each opening E1 to the floating diffusion portion FD. The structure of the pixel array region 2 near the boundaries L1 and L2 may be set in a suitable manner depending on the implementation of the solid-state imaging device.

[0158] The solid-state imaging device of this embodiment can be manufactured by the method shown in Figures 5 and 6. However, in the step of Figure 5B, the opening E1 in each partial region is formed in the direction shown in Figure 21B.

[0159] (Application example) 22 is a block diagram showing an example of the configuration of an electronic device. The electronic device shown in FIG.

[0160] Camera 100 includes optical unit 101 including a lens group and the like, imaging device 102 which is a solid-state imaging device according to any one of the first to fifth embodiments, DSP (Digital Signal Processor) circuit 103 which is a camera signal processing circuit, frame memory 104, display unit 105, recording unit 106, operation unit 107, and power supply unit 108. DSP circuit 103, frame memory 104, display unit 105, recording unit 106, operation unit 107, and power supply unit 108 are connected to each other via bus line 109.

[0161] The optical unit 101 takes in incident light (image light) from a subject and forms an image on an imaging surface of the imaging device 102. The imaging device 102 converts the amount of incident light imaged on the imaging surface by the optical unit 101 into an electrical signal on a pixel-by-pixel basis and outputs the electrical signal.

[0162] The DSP circuit 103 performs signal processing on the pixel signals output by the imaging device 102. The frame memory 104 is a memory for storing one screen of a moving image or a still image captured by the imaging device 102.

[0163] The display unit 105 includes a panel-type display device such as a liquid crystal panel or an organic EL panel, and displays moving images or still images captured by the imaging device 102. The recording unit 106 records the moving images or still images captured by the imaging device 102 in a recording medium such as a hard disk or a semiconductor memory.

[0164] An operation unit 107, under the operation of a user, issues operation commands for various functions of the camera 100. A power supply unit 108 appropriately supplies various types of power to the DSP circuit 103, frame memory 104, display unit 105, recording unit 106, and operation unit 107 as operating power sources to these devices.

[0165] By using the solid-state imaging device according to any one of the first to fifth embodiments as the imaging device 102, it is possible to expect acquisition of a good image.

[0166] The solid-state imaging device can be applied to various other products. For example, the solid-state imaging device may be mounted on various moving objects such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility vehicles, airplanes, drones, ships, and robots.

[0167] 23 is a block diagram showing a configuration example of a moving object control system, which is a vehicle control system 200.

[0168] The vehicle control system 200 includes a plurality of electronic control units connected via a communication network 201. In the example shown in Fig. 23, the vehicle control system 200 includes a drive system control unit 210, a body system control unit 220, an outside-vehicle information detection unit 230, an inside-vehicle information detection unit 240, and an integrated control unit 250. Fig. 23 further illustrates, as components of the integrated control unit 250, a microcomputer 251, an audio / video output unit 252, and an in-vehicle network I / F (Interface) 253.

[0169] The drivetrain control unit 210 controls the operation of devices related to the drivetrain of the vehicle according to various programs. For example, the drivetrain control unit 210 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, etc.

[0170] The body system control unit 220 controls the operation of various devices equipped on the vehicle body according to various programs. For example, the body system control unit 220 functions as a control device for a smart key system, a keyless entry system, a power window device, various lamps (e.g., head lamps, back lamps, brake lamps, blinkers, fog lamps), etc. In this case, radio waves transmitted from a portable device that substitutes for a key or signals from various switches may be input to the body system control unit 220. The body system control unit 220 receives input of such radio waves or signals and controls the door lock device, power window device, lamps, etc. of the vehicle.

[0171] The outside-vehicle information detection unit 230 detects information outside the vehicle equipped with the vehicle control system 200. For example, an imaging unit 231 is connected to the outside-vehicle information detection unit 230. The outside-vehicle information detection unit 230 causes the imaging unit 231 to capture an image outside the vehicle, and receives the captured image from the imaging unit 231. The outside-vehicle information detection unit 230 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc., based on the received image.

[0172] The imaging unit 231 is an optical sensor that receives light and outputs an electrical signal according to the amount of the received light. The imaging unit 231 can output the electrical signal as an image, and can also output it as distance measurement information. The light received by the imaging unit 231 may be visible light, or may be invisible light such as infrared light. The imaging unit 231 includes a solid-state imaging device according to any one of the first to fifth embodiments.

[0173] The in-vehicle information detection unit 240 detects information about the inside of the vehicle equipped with the vehicle control system 200. For example, a driver state detection unit 241 that detects the state of the driver is connected to the in-vehicle information detection unit 240. For example, the driver state detection unit 241 includes a camera that captures an image of the driver, and the in-vehicle information detection unit 240 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 241, or may determine whether the driver is dozing. This camera may include any of the solid-state imaging devices of the first to fifth embodiments, and may be, for example, the camera 100 shown in FIG. 22.

[0174] The microcomputer 251 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-of-vehicle information detection unit 230 or the inside-vehicle information detection unit 240, and output a control command to the drive system control unit 210. For example, the microcomputer 251 can perform cooperative control aimed at realizing functions of an ADAS (Advanced Driver Assistance System), such as vehicle collision avoidance, impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, collision warning, lane departure warning, etc.

[0175] In addition, the microcomputer 251 can perform cooperative control for the purpose of automatic driving, in which the vehicle travels autonomously without being operated by the driver, by controlling the driving force generating device, the steering mechanism, or the braking device based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 230 or the inside vehicle information detection unit 240.

[0176] Furthermore, the microcomputer 251 can output a control command to the body system control unit 220 based on the information outside the vehicle acquired by the vehicle exterior information detection unit 230. For example, the microcomputer 251 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 230, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0177] The audio / image output unit 252 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 23, an audio speaker 261, a display unit 262, and an instrument panel 263 are shown as such output devices. The display unit 262 may include, for example, an on-board display or a head-up display.

[0178] FIG. 24 is a plan view showing a specific example of the setting position of the imaging unit 231 in FIG.

[0179] 24 includes imaging units 301, 302, 303, 304, and 305 as the imaging unit 231. The imaging units 301, 302, 303, 304, and 305 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 300.

[0180] The imaging unit 301 provided on the front nose mainly acquires images of the front of the vehicle 300. The imaging unit 302 provided on the left side mirror and the imaging unit 303 provided on the right side mirror mainly acquire images of the sides of the vehicle 300. The imaging unit 304 provided on the rear bumper or the back door mainly acquires images of the rear of the vehicle 300. The imaging unit 305 provided on the upper part of the windshield inside the vehicle cabin mainly acquires images of the front of the vehicle 300. The imaging unit 305 is used to detect, for example, a leading vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, and the like.

[0181] FIG. 24 shows an example of the imaging ranges of the imaging units 301, 302, 303, and 304 (hereinafter referred to as "imaging units 301 to 304"). Imaging range 311 indicates the imaging range of the imaging unit 301 provided on the front nose. Imaging range 312 indicates the imaging range of the imaging unit 302 provided on the left side mirror. Imaging range 313 indicates the imaging range of the imaging unit 303 provided on the right side mirror. Imaging range 314 indicates the imaging range of the imaging unit 304 provided on the rear bumper or the back door. For example, the image data captured by the imaging units 301 to 304 are superimposed to obtain an overhead image of the vehicle 300 viewed from above. Hereinafter, the imaging ranges 311, 312, 313, and 314 are referred to as "imaging ranges 311 to 314".

[0182] At least one of the imaging units 301 to 304 may have a function of acquiring distance information. For example, at least one of the imaging units 301 to 304 may be a stereo camera including a plurality of imaging devices, or may be an imaging device having pixels for detecting a phase difference.

[0183] For example, the microcomputer 251 (FIG. 23) calculates the distance to each solid object in the imaging range 311-314 and the change in this distance over time (relative speed with respect to the vehicle 300) based on the distance information obtained from the imaging units 301-304. Based on these calculation results, the microcomputer 251 can extract, as a preceding vehicle, a solid object that is the closest solid object on the traveling path of the vehicle 300 and travels in approximately the same direction as the vehicle 300 at a predetermined speed (for example, 0 km / h or more). Furthermore, the microcomputer 251 can set a vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, according to this example, cooperative control can be performed for the purpose of automatic driving that travels autonomously without the driver's operation.

[0184] For example, the microcomputer 251 classifies and extracts three-dimensional object data on three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on the distance information obtained from the imaging units 301 to 304, and can use the data for automatic obstacle avoidance. For example, the microcomputer 251 distinguishes obstacles around the vehicle 300 into obstacles that are visible to the driver of the vehicle 300 and obstacles that are difficult to see. Then, the microcomputer 251 determines a collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and there is a possibility of a collision, the microcomputer 251 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 261 or the display unit 262, or by performing forced deceleration or avoidance steering via the drive system control unit 210.

[0185] At least one of the imaging units 301 to 304 may be an infrared camera that detects infrared rays. For example, the microcomputer 251 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured images of the imaging units 301 to 304. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured images of the imaging units 301 to 304 as infrared cameras and a procedure of performing a pattern matching process on a series of feature points that indicate the contour of an object to determine whether or not the object is a pedestrian. When the microcomputer 251 determines that a pedestrian is present in the captured images of the imaging units 301 to 304 and recognizes the pedestrian, the audio / image output unit 252 controls the display unit 262 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio / image output unit 252 may also control the display unit 262 to display an icon or the like indicating a pedestrian at a desired position.

[0186] Although the embodiments of the present disclosure have been described above, these embodiments may be implemented with various modifications without departing from the scope of the present disclosure. For example, two or more embodiments may be implemented in combination.

[0187] The present disclosure may also be configured as follows.

[0188] (1) A substrate; A plurality of photoelectric conversion units provided in the substrate; a charge accumulation unit provided between four adjacent photoelectric conversion units in the substrate; a light-shielding film provided in the groove in the substrate; The groove is a first portion provided between two adjacent photoelectric conversion units in the substrate; a second portion provided around the charge storage portion; A solid-state imaging device, wherein the second portion has a first opening between at least a first photoelectric conversion unit of the four photoelectric conversion units and the charge accumulation unit, and penetrates the substrate between at least a second photoelectric conversion unit of the four photoelectric conversion units and the charge accumulation unit.

[0189] (2) The solid-state imaging device described in (1), wherein the second portion further penetrates the substrate between a third photoelectric conversion unit of the four photoelectric conversion units and the charge accumulation unit, and between a fourth photoelectric conversion unit of the four photoelectric conversion units and the charge accumulation unit.

[0190] (3) The solid-state imaging device according to (1), wherein the first portion has a plate shape extending vertically within the substrate.

[0191] (4) The solid-state imaging device according to (1), wherein the second portion has a cylindrical shape extending vertically within the substrate.

[0192] (5) The solid-state imaging device according to (4), wherein the second portion has a C-shape in a cross section passing through the first opening.

[0193] (6) The solid-state imaging device according to (1), wherein the light-shielding film includes a metal layer or a semiconductor layer provided in the groove via an insulating film.

[0194] (7) The solid-state imaging device described in (1), wherein the second portion further has a second opening between a third photoelectric conversion unit of the four photoelectric conversion units and the charge accumulation unit, and penetrates the substrate between a fourth photoelectric conversion unit of the four photoelectric conversion units and the charge accumulation unit.

[0195] (8) The solid-state imaging device according to (7), wherein the third photoelectric conversion unit is provided on an opposite side of the charge accumulation unit from the first photoelectric conversion unit.

[0196] (9) The solid-state imaging device according to (7), wherein the reset transistor for the first photoelectric conversion unit is provided on the third photoelectric conversion unit side with respect to the charge accumulation unit.

[0197] (10) The solid-state imaging device according to (1), wherein the first portion has a third opening between the two photoelectric conversion units.

[0198] (11) The solid-state imaging device according to (10), further comprising a charge storage section provided in the substrate near the third opening and common to the two photoelectric conversion sections.

[0199] (12) The solid-state imaging device according to (1), further comprising a moth-eye structure provided on the upper surface of the substrate above the photoelectric conversion portion.

[0200] (13) The solid-state imaging device according to (1), wherein the first opening is provided on an opposite side of the charge accumulation section from a center of a pixel array region of the solid-state imaging device.

[0201] (14) the pixel array region includes a first region, a second region provided on an opposite side of the first region with respect to a center of the pixel array region, a third region provided between the first region and the second region, and a fourth region provided on an opposite side of the third region with respect to a center of the pixel array region; the first opening in the second region is provided on an opposite side of the first opening in the first region with respect to a center of the pixel array region; The solid-state imaging device according to (13), wherein the first opening in the fourth region is provided on an opposite side of the center of the pixel array region from the first opening in the third region.

[0202] (15) forming a plurality of photoelectric conversion units within a substrate; forming a charge storage unit between four adjacent photoelectric conversion units in the substrate; forming a groove in the substrate; forming a light-shielding film in the groove; Including, The groove is a first portion provided between two adjacent photoelectric conversion units in the substrate; a second portion provided around the charge storage portion; A method for manufacturing a solid-state imaging device, wherein the second portion has a first opening between at least a first photoelectric conversion unit of the four photoelectric conversion units and the charge accumulation unit, and is formed so as to penetrate the substrate between at least a second photoelectric conversion unit of the four photoelectric conversion units and the charge accumulation unit.

[0203] (16) The method for manufacturing a solid-state imaging device described in (15), wherein the second portion is further formed so as to penetrate the substrate between a third photoelectric conversion unit of the four photoelectric conversion units and the charge accumulation unit, and between a fourth photoelectric conversion unit of the four photoelectric conversion units and the charge accumulation unit.

[0204] (17) The method for manufacturing a solid-state imaging device described in (15), wherein the second portion further has a second opening between a third photoelectric conversion unit of the four photoelectric conversion units and the charge accumulation unit, and is formed so as to penetrate the substrate between a fourth photoelectric conversion unit of the four photoelectric conversion units and the charge accumulation unit.

[0205] (18) The method for manufacturing a solid-state imaging device according to (15), wherein the first portion is formed to have a third opening between the two photoelectric conversion units.

[0206] (19) The method for manufacturing a solid-state imaging device according to (15), further comprising forming a moth-eye structure on the upper surface of the substrate above the photoelectric conversion portion.

[0207] (20) The method for manufacturing a solid-state imaging device according to (15), wherein the first opening is formed on an opposite side of the charge accumulation section from a center of a pixel array region of the solid-state imaging device.

[0208] (twenty one) The method for manufacturing a solid-state imaging device according to (15), wherein the groove is formed by forming a part of the groove from the front surface of the substrate and forming another part of the groove from the back surface of the substrate.

[0209] (twenty two) The method for manufacturing a solid-state imaging device according to (15), wherein the groove is formed by processing the substrate from only one of the front surface and the back surface of the substrate. [Explanation of symbols]

[0210] 1: pixel; 2: pixel array region; 2a, 2b, 2c, 2d: partial regions; 3: control circuit, 4: vertical drive circuit, 5: column signal processing circuit, 6: horizontal drive circuit; 7: output circuit; 8: vertical signal line; 9: horizontal signal line; 11: Support substrate, 12, 13, 14: Wiring layer, 15: interlayer insulating film; 16: contact plug; 17: gate insulating film, 18: gate electrode, 19: sidewall insulating film, 21: substrate, 22: n-type semiconductor region, 23: p-type semiconductor region, 24, 25: n+ type semiconductor region, 26: moth-eye structure, 31: groove, 31a: linear groove, 31b: annular groove, 31c: groove, 32: element isolation portion, 32a: linear portion, 32b: annular portion, 33, 33': element isolation insulating film, 34, 34': light shielding film, 34a: Internal light shielding film, 34b: External light shielding film, 35: Flattening film, 36: color filter layer; 37: on-chip lens; 38: element isolation insulating film, 39: light shielding film

Claims

1. A substrate; A plurality of photoelectric conversion units provided in the substrate; a charge accumulation unit provided between four adjacent photoelectric conversion units in the substrate; a light-shielding film provided in a groove in the substrate; A solid-state imaging device comprising: The groove is a first portion provided between two adjacent photoelectric conversion units in the substrate; a second portion provided around the charge storage portion; the second portion has a first opening between at least a first photoelectric conversion unit of the four photoelectric conversion units and the charge accumulation unit, and penetrates the substrate between at least a second photoelectric conversion unit of the four photoelectric conversion units and the charge accumulation unit, the first opening is provided on an opposite side of a center of a pixel array region of the solid-state imaging device with respect to the charge accumulation section, the pixel array region includes a first region, a second region provided on an opposite side of the first region with respect to a center of the pixel array region, a third region provided between the first region and the second region, and a fourth region provided on an opposite side of the third region with respect to a center of the pixel array region; the first opening in the second region is provided on an opposite side of the center of the pixel array region to the first opening in the first region; the first opening in the fourth region is provided on an opposite side of the center of the pixel array region from the first opening in the third region; Solid-state imaging device.

2. 2. The solid-state imaging device of claim 1, wherein the second portion further penetrates the substrate between a third photoelectric conversion unit of the four photoelectric conversion units and the charge accumulation unit, and between a fourth photoelectric conversion unit of the four photoelectric conversion units and the charge accumulation unit.

3. The solid-state imaging device according to claim 1 , wherein the first portion has a plate shape extending vertically within the substrate.

4. The solid-state imaging device according to claim 1 , wherein the second portion has a cylindrical shape extending vertically within the substrate.

5. The solid-state imaging device according to claim 4 , wherein the second portion has a C-shape in a cross section passing through the first opening.

6. The solid-state imaging device according to claim 1 , wherein the light-shielding film includes a metal layer or a semiconductor layer provided in the groove via an insulating film.

7. 2. The solid-state imaging device of claim 1, wherein the second portion further has a second opening between a third photoelectric conversion unit of the four photoelectric conversion units and the charge accumulation unit, and penetrates the substrate between a fourth photoelectric conversion unit of the four photoelectric conversion units and the charge accumulation unit.

8. The solid-state imaging device according to claim 7 , wherein the third photoelectric conversion unit is provided on an opposite side of the charge storage unit from the first photoelectric conversion unit.

9. The solid-state imaging device according to claim 7 , wherein the reset transistor for the first photoelectric conversion unit is provided on the third photoelectric conversion unit side with respect to the charge accumulation unit.

10. The solid-state imaging device according to claim 1 , wherein the first portion has a third opening between the two photoelectric conversion portions.

11. The solid-state imaging device according to claim 10 , further comprising a charge storage section provided in the substrate near the third opening and common to the two photoelectric conversion sections.

12. The solid-state imaging device according to claim 1 , further comprising a moth-eye structure provided on the upper surface of the substrate above the photoelectric conversion portion.

13. forming a plurality of photoelectric conversion units within a substrate; forming a charge storage unit between four mutually adjacent photoelectric conversion units in the substrate; forming a groove in the substrate; forming a light-shielding film in the groove; A method for manufacturing a solid-state imaging device, comprising: The groove is a first portion provided between two adjacent photoelectric conversion units in the substrate; a second portion provided around the charge storage portion; the second portion has a first opening between at least a first photoelectric conversion unit of the four photoelectric conversion units and the charge accumulation unit, and is formed so as to penetrate the substrate between at least a second photoelectric conversion unit of the four photoelectric conversion units and the charge accumulation unit; the first opening is formed on an opposite side of a center of a pixel array region of the solid-state imaging device with respect to the charge accumulation section; the pixel array region includes a first region, a second region provided on an opposite side of the first region with respect to a center of the pixel array region, a third region provided between the first region and the second region, and a fourth region provided on an opposite side of the third region with respect to a center of the pixel array region; the first opening in the second region is formed on an opposite side of the first opening in the first region with respect to a center of the pixel array region; the first opening in the fourth region is formed on an opposite side of the first opening in the third region with respect to a center of the pixel array region; A method for manufacturing a solid-state imaging device.

14. The method for manufacturing a solid-state imaging device described in claim 13, wherein the second portion is further formed so as to penetrate the substrate between a third photoelectric conversion unit of the four photoelectric conversion units and the charge accumulation unit, and between a fourth photoelectric conversion unit of the four photoelectric conversion units and the charge accumulation unit.

15. The method for manufacturing a solid-state imaging device described in claim 13, wherein the second portion further has a second opening between a third photoelectric conversion unit of the four photoelectric conversion units and the charge accumulation unit, and is formed so as to penetrate the substrate between a fourth photoelectric conversion unit of the four photoelectric conversion units and the charge accumulation unit.

16. The method for manufacturing a solid-state imaging device according to claim 13 , wherein the first portion is formed to have a third opening between the two photoelectric conversion portions.

17. The method for manufacturing a solid-state imaging device according to claim 13 , further comprising forming a moth-eye structure on the upper surface of the substrate above the photoelectric conversion portion.

18. The method for manufacturing a solid-state imaging device according to claim 13 , wherein the groove is formed by forming a part of the groove from the front surface of the substrate and forming another part of the groove from the rear surface of the substrate.

19. The method for manufacturing a solid-state imaging device according to claim 13 , wherein the groove is formed by processing the substrate from only one of the front surface and the back surface of the substrate.

Images