Transient Voltage Absorption Element

Abstract

A transient voltage-absorbing element (11) comprises: a semiconductor substrate (Sub); an epitaxial layer (Epi) formed on a surface of the semiconductor substrate (Sub); and a p+ region and an n+ region formed in the epitaxial layer (Epi). The epitaxial layer (Epi), the p+ region, and the n+ region form a diode for surge absorption. The transient voltage-absorbing element (11) further comprises a trench (TR) that reaches the semiconductor substrate (Sub) from the surface of the epitaxial layer (Epi).

Description

[Technical field]

[0001] The present invention relates to a transient voltage absorbing element that absorbs surges such as transient abnormal voltages caused by ESD (electrostatic discharge) and lightning surges and switching surges. [Background technology]

[0002] In general, when a transient voltage absorbing element is inserted between a transmission line and ground, high-frequency signals leak to the ground due to the stray capacitance of the transient voltage absorbing element, deteriorating the transmission characteristics of the transmission line.

[0003] Patent Document 1 discloses a transient voltage absorbing element with low stray capacitance that eliminates the influence of unnecessary parasitic elements.

[0004] 9 is a cross-sectional view of the transient voltage absorption element disclosed in Patent Document 1. In this example, a first epitaxial layer 210 is formed on a semiconductor substrate 201, a buried layer 220 is formed near the surface of the first epitaxial layer 210, a second epitaxial layer 211 is formed on the buried layer 220, a first deep diffusion layer 250 is formed in the second epitaxial layer 211, a Zener diode is formed in the first deep diffusion layer 250, and a first PN diode is formed at a position away from the Zener diode. The Zener diode is separated by a trench 501, and the first PN diode is separated by a trench 502, and the Zener diode and the first PN diode are connected in series in the reverse direction via the buried layer 220. This structure makes it possible to eliminate the influence of unnecessary parasitic elements and obtain a transient voltage absorption element with low capacitance. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2012-182381 A Summary of the Invention [Problem to be solved by the invention]

[0006] As shown in Fig. 9, the parasitic capacitance in the lateral direction is suppressed by isolating each diode by a trench. However, parasitic capacitance in the vertical direction remains. In Fig. 9, the parasitic capacitance C1 is a parasitic capacitance generated between the anode electrode terminal 121 and the first epitaxial layer 210, and the parasitic capacitance C2 is a parasitic capacitance generated between the cathode electrode terminal 120 and the third diffusion region 232 and the first epitaxial layer 210.

[0007] 10 is an equivalent circuit diagram of the transient voltage absorption element. This transient voltage absorption element has a structure in which a series circuit of a PN junction diode 101 and a Zener diode 110 is connected between a cathode electrode terminal 120 and an anode electrode terminal 121, and a PN junction diode 102 is connected between the cathode electrode terminal 120 and the anode electrode terminal 121. A parasitic capacitance C1 is connected between both ends of the Zener diode 110, and a parasitic capacitance C2 is connected between both ends of the PN junction diode 101.

[0008] In this way, a circuit is formed in which parasitic capacitance is connected to each of the series-connected diodes, so if this transient voltage absorption element is inserted between the transmission line and ground, the stray capacitance of the transient voltage absorption element will cause high-frequency signals to leak to the ground, degrading the transmission characteristics of the transmission line.

[0009] SUMMARY OF THE PRESENT EMBODIMENT An object of the present invention is to provide a transient voltage absorbing element which has reduced stray capacitance and is capable of suppressing degradation of the high frequency passing characteristics of a transmission line. [Means for solving the problem]

[0010] An example of a transient voltage absorbing element according to the present disclosure includes: a semiconductor substrate, an epitaxial layer formed on a surface of the semiconductor substrate, and a p+ region and an n+ region formed in the epitaxial layer, the epitaxial layer, the p+ region and the n+ region forming a surge absorbing diode; The semiconductor device is characterized by comprising a trench extending from the surface of the epitaxial layer to the semiconductor substrate. Effect of the Invention

[0011] According to the present invention, a transient voltage absorbing element having reduced stray capacitance is obtained, and degradation of the high-frequency passing characteristics of the transmission line is suppressed. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a circuit diagram of a transient voltage absorbing element 11 according to the first embodiment. [Diagram 2] FIG. 2A is a plan view of the transient voltage absorbing element 11, and FIG. 2B is a plan view showing the configuration of a trench inside the transient voltage absorbing element 11. [Diagram 3] 3A is a vertical cross-sectional view taken along line AA in FIGS. 2A and 2B, and FIG. 3B is a vertical cross-sectional view taken along line BB in FIGS. 2A and 2B. [Figure 4] FIG. 4 is a circuit diagram of a transient voltage absorbing element 12 according to the second embodiment. [Diagram 5] FIG. 5(A) is a plan view of the transient voltage absorbing element 12, and FIG. 5(B) is a plan view showing the configuration of a trench inside the transient voltage absorbing element 12. [Figure 6] FIG. 6 is a vertical cross-sectional view taken along the line AA in FIGS. 5(A) and 5(B). [Figure 7] FIG. 7 is a cross-sectional view of a transient voltage absorbing element 13 according to the third embodiment. [Figure 8] FIG. 8 is a circuit diagram of a transient voltage absorbing circuit 103 including a transient voltage absorbing element 13. As shown in FIG. [Figure 9] FIG. 9 is a cross-sectional view of the transient voltage absorbing element disclosed in Patent Document 1. [Figure 10] FIG. 10 is an equivalent circuit diagram of the transient voltage absorbing element disclosed in Patent Document 1. [Figure 11] FIG. 11A is a plan view of a transient voltage absorbing element of a comparative example, and FIG. 11B is a plan view showing the configuration of a trench therein. [Figure 12] 12A is a vertical cross-sectional view taken along line AA in FIGS. 11A and 11B, and FIG. 12B is a vertical cross-sectional view taken along line BB in FIGS. 11A and 11B. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, several specific examples will be given with reference to the drawings to show several embodiments for carrying out the present invention. In each drawing, the same reference numerals are given to the same parts. In consideration of the ease of explanation or understanding of the main points, the embodiments are shown divided into several embodiments for convenience of explanation, but partial replacement or combination of the configurations shown in different embodiments is possible. In the second and subsequent embodiments, the description of matters common to the first embodiment will be omitted, and only the differences will be described. In particular, similar actions and effects due to similar configurations will not be mentioned in each embodiment.

[0014] First Embodiment FIG. 1 is a circuit diagram of a transient voltage absorbing element 11 according to a first embodiment. The transient voltage absorbing element 11 includes a first electrode E1 and a second electrode E2. A parallel circuit of a series circuit of diodes D11 and D12 and a series circuit of diodes D21 and D22 is formed between the first electrode E1 and the second electrode E2. The diodes D11, D12, D21, and D22 include depletion layer capacitances Cd11, Cd12, Cd21, and Cd22, respectively. In addition, a series circuit of parasitic capacitances C11, C12, C21, and C22 is formed between the first electrode E1 and the second electrode E2 of the transient voltage absorbing element 11. Furthermore, a series circuit of parasitic capacitances C31 and C32 is formed between the connection point of the parasitic capacitances C12 and C22 and the connection point of the diodes D11 and D12. Similarly, a series circuit of parasitic capacitances C33 and C34 is formed between the connection point of the parasitic capacitances C12 and C22 and the connection point of the diodes D21 and D22.

[0015] Fig. 2(A) is a plan view of the transient voltage absorption element 11, and Fig. 2(B) is a plan view showing the configuration of the trench inside it. Fig. 3(A) is a vertical cross-sectional view of the portion AA in Fig. 2(A) and Fig. 2(B), and Fig. 3(B) is a vertical cross-sectional view of the portion BB in Fig. 2(A) and Fig. 2(B).

[0016] As shown in Figures 3(A) and 3(B), the transient voltage absorption element 11 includes a semiconductor substrate Sub, an epitaxial layer Epi, and an insulator Ins1. The epitaxial layer Epi is formed on the surface of the semiconductor substrate Sub. A p+ region and an n+ region are formed on the surface of the epitaxial layer Epi. Diodes D11 and D12 are formed by the epitaxial layer Epi, the p+ region, and the n+ region, respectively.

[0017] An insulator Ins1 is formed on the surface of the epitaxial layer Epi. A first electrode E1 is formed from the surface of the insulator Ins1 to the p+ region of the diode D11. A second electrode E2 is formed from the surface of the insulator Ins1 to the n+ region of the diode D12. A third electrode E3 is formed from the surface of the insulator Ins1 to the n+ region of the diode D11 and the p+ region of the diode D12. Similarly, as shown in FIG. 2(A), a fourth electrode E4 is formed to the n+ region of the diode D21 and the p+ region of the diode D22.

[0018] The semiconductor substrate Sub may be made of, for example, Si or GaAs. The insulator Ins1 may be made of, for example, SiO2 or SiN. The first electrode E1, the second electrode E2, the third electrode E3, and the fourth electrode E4 may be made of, for example, Al or Cu.

[0019] In Figures 2(B), 3(A), and 3(B), the first trench TR1 is a trench that separates the formation regions of diodes D11, D12, D21, and D22, and the second trench TR2 is a trench that reduces the parasitic capacitance generated between the first electrode E1 and the second electrode E2.

[0020] 3(A) and 3(B), the first trench TR1 and the second trench TR2 are formed from the surface of the epitaxial layer Epi to the semiconductor substrate Sub. The first trench TR1 and the second trench TR2 are formed by forming grooves in the epitaxial layer Epi and the semiconductor substrate Sub, and then covering the side walls and bottom of the grooves with an insulating material such as an oxide film, and the inside of the oxide film may be further filled with another material such as polysilicon.

[0021] As shown in FIG. 3A, a parasitic capacitance C11 is formed between the first electrode E1 and the epitaxial layer Epi, and a parasitic capacitance C21 is formed between the second electrode E2 and the epitaxial layer Epi. A parasitic capacitance C31 is formed between the third electrode E3 and the epitaxial layer Epi. The epitaxial layer Epi and the semiconductor substrate Sub have different impurity polarities. For example, if the epitaxial layer Epi is p-type, the semiconductor substrate Sub is n-type, and if the epitaxial layer Epi is n-type, the semiconductor substrate Sub is p-type. As a result, parasitic capacitances C12, C22, and C32 are formed between the epitaxial layer Epi and the semiconductor substrate Sub.

[0022] The parasitic capacitances C12 and C32, and the parasitic capacitances C22 and C32 are insulated by the second trench TR2. The second trench TR2 is not located directly below the first electrode E1 and the second electrode E2, that is, the second trench TR2 surrounds the first electrode E1 and the second electrode E2 so as to coincide with the outer periphery of the first electrode E1 and the second electrode E2 when viewed in the vertical direction relative to the semiconductor substrate Sub, and is not disposed so as to overlap the first electrode E1 and the second electrode E2.

[0023] Here, the structure of a transient voltage absorbing element as a comparative example of the transient voltage absorbing element 11 will be illustrated. Fig. 11(A) is a plan view of the transient voltage absorbing element of the comparative example, and Fig. 11(B) is a plan view showing the configuration of the trench inside it. Fig. 12(A) is a vertical cross-sectional view at the AA portion in Fig. 11(A) and Fig. 11(B), and Fig. 12(B) is a vertical cross-sectional view at the BB portion in Fig. 11(A) and Fig. 11(B).

[0024] The transient voltage absorption element of the comparative example and the transient voltage absorption element 11 of the first embodiment have different trench configurations. As shown in Fig. 11(A), Fig. 11(B), and Fig. 12(A), even if the first trench TR1 is provided only around the formation region of each diode in order to form the diodes D11, D12, D21, and D22, a current path of [first electrode E1]-[parasitic capacitance C11]-[epitaxial layer Epi]-[parasitic capacitance C21]-[second electrode E2] is generated as shown by the dashed arrow in Fig. 11(A).

[0025] On the other hand, according to this embodiment, the above-mentioned current path does not occur. In this embodiment, as shown in FIG. 3(A), a current path is generated as follows: [first electrode E1]-[parasitic capacitance C11]-[epitaxial layer Epi]-[parasitic capacitance C12]-[semiconductor substrate Sub]-[parasitic capacitance C22]-[epitaxial layer Epi]-[parasitic capacitance C21]-[second electrode E2]. That is, four parasitic capacitances C11, C12, C22, and C21 connected in series exist between the first electrode E1 and the second electrode E2. However, the resistance value of the semiconductor substrate Sub is high, and the values ​​of the parasitic capacitances C12 and C22 are very small. As a result, the combined parasitic capacitance generated between the first electrode E1 and the second electrode E2 is very small.

[0026] According to the transient voltage absorption element 11 of the first embodiment, as shown in FIG. 1, a series circuit of at least four parasitic capacitances C11, C12, C22, C21 is formed between the first electrode E1 and the second electrode E2. A series circuit of at least four parasitic capacitances C31, C32, C12, C11 is formed between the connection point of the diodes D11, D12 and the first electrode E1. Also, a series circuit of at least four parasitic capacitances C31, C32, C22, C21 is formed between the connection point of the diodes D11, D12 and the second electrode E2. Similarly, a series circuit of at least four parasitic capacitances C33, C34, C12, C11 is formed between the connection point of the diodes D21, D22 and the first electrode E1. Also, a series circuit of at least four parasitic capacitances C33, C34, C22, C21 is formed between the connection point of the diodes D21, D22 and the second electrode E2. In this manner, a series circuit of a plurality of parasitic capacitances is connected between the first electrode E1 and the second electrode E2, and a series circuit of a plurality of parasitic capacitances is simply connected in parallel to each diode, so that a transient voltage absorption element with low stray capacitance is obtained.

[0027] The path between the first electrode E1 and the second electrode E2 via the depletion layer capacitance of each diode is as follows: As shown in Fig. 1, the depletion layer capacitance of diode D11 is Cd11, the depletion layer capacitance of diode D12 is Cd12, the depletion layer capacitance of diode D21 is Cd21, and the depletion layer capacitance of diode D22 is Cd22.

[0028] (Path 1) Path of depletion layer capacitance Cd21, parasitic capacitances C33, C34, C22, C21 (Path 2) Path of parasitic capacitances C11, C12, C34, C33, and depletion layer capacitance Cd22 (Path 3) Path of depletion layer capacitance Cd12, parasitic capacitances C31, C32, C12, C11 (Path 4) Path of parasitic capacitances C21, C22, C32, C31, and depletion layer capacitance Cd11 For any of the paths, any of the parasitic capacitances C12, C22, C32, and C34 having a small capacitance value is included in series between the first electrode E1 and the second electrode E2, so that a transient voltage absorbing element having a low stray capacitance can also be obtained.

[0029] In addition, even if the second trench TR2 is arranged so as to overlap the first electrode E1 and the second electrode E2, rather than surrounding the outer periphery of the first electrode E1 and the second electrode E2 as described above, the same effect can be expected in the range surrounded by the second trench TR2. Therefore, the second trench TR2 may be arranged at a position other than the position surrounding the outer periphery of the first electrode E1 and the second electrode E2, and the same effect can be expected. In addition, by using a part of the first trench TR1 to arrange it at a position surrounding the first electrode E1 and the second electrode E2, the arrangement of the first trench TR1 can be simplified and it is possible to correspond to miniaturization. In addition, by making the length of the first trench TR1 in the thickness direction of the semiconductor substrate the same as the length of the second trench TR2 in the thickness direction of the semiconductor substrate, they can be processed at the same time during manufacturing, which leads to cost reduction. In addition, the term "same" here includes the range of manufacturing error, and can also be rephrased as "approximately the same."

[0030] Second Embodiment In the second embodiment, a transient voltage absorbing element 12 having a part of its configuration different from that of the transient voltage absorbing element 11 shown in the first embodiment will be illustrated.

[0031] 4 is a circuit diagram of a transient voltage absorbing element 12 according to a second embodiment. The transient voltage absorbing element 12 includes a first electrode E1 and a second electrode E2. A parallel circuit of a series circuit of diodes D11 and D12 and a series circuit of diodes D21 and D22 is formed between the first electrode E1 and the second electrode E2. The connection point of the diodes D11 and D12 is connected to the connection point of the diodes D21 and D22. The diodes D11, D12, D21, and D22 each include a depletion layer capacitance. In addition, a series circuit of parasitic capacitances C11, C12, C22, and C21 is formed between the first electrode E1 and the second electrode E2 of the transient voltage absorbing element 11. A series circuit of parasitic capacitances C31 and C32 is formed between the connection point of the diodes D11 and D12 and the connection point of the diodes D21 and D22 and the connection point of the parasitic capacitances C12 and C22.

[0032] Fig. 5(A) is a plan view of the transient voltage absorbing element 12, and Fig. 5(B) is a plan view showing the configuration of the trench therein. Fig. 6 is a vertical cross-sectional view of the AA portion in Fig. 5(A) and Fig. 5(B).

[0033] As shown in Fig. 6, the transient voltage absorption element 12 includes a semiconductor substrate Sub, an epitaxial layer Epi, and an insulator Ins1. The epitaxial layer Epi is formed on the surface of the semiconductor substrate Sub. A p+ region and an n+ region are formed on the surface of the epitaxial layer Epi. The epitaxial layer Epi, the p+ region, and the n+ region form diodes D11 and D12, respectively.

[0034] An insulator Ins1 is formed on the surface of the epitaxial layer Epi. A first electrode E1 is formed from the surface of the insulator Ins1 to the p+ region of the diode D11. A second electrode E2 is formed from the surface of the insulator Ins1 to the n+ region of the diode D12. A third electrode E3 is formed from the surface of the insulator Ins1 to the n+ region of the diode D11 and the p+ region of the diode D12.

[0035] The semiconductor substrate Sub may be made of, for example, Si or GaAs. The insulator Ins1 may be made of, for example, SiO2 or SiN. The first electrode E1, the second electrode E2, and the third electrode E3 may be made of, for example, Al or Cu.

[0036] The first trench TR1 and the second trench TR2 shown in FIG. 5B are formed from the epitaxial layer Epi to the semiconductor substrate Sub as shown in FIG.

[0037] As shown in Fig. 6, a parasitic capacitance C11 is formed between the first electrode E1 and the epitaxial layer Epi, and a parasitic capacitance C21 is formed between the second electrode E2 and the epitaxial layer Epi. A parasitic capacitance C31 is formed between the third electrode E3 and the epitaxial layer Epi. The epitaxial layer Epi and the semiconductor substrate Sub have different impurity polarities. For example, if the epitaxial layer Epi is p-type, the semiconductor substrate Sub is n-type, and if the epitaxial layer Epi is n-type, the semiconductor substrate Sub is p-type. As a result, parasitic capacitances C12, C22, and C32 are formed between the epitaxial layer Epi and the semiconductor substrate Sub.

[0038] In the transient voltage absorption element 12 having this structure, similarly to the transient voltage absorption element 11 shown in the first embodiment, the parasitic capacitances C12 and C32, and the parasitic capacitances C22 and C32 are insulated from each other by the second trench TR2.

[0039] In the transient voltage absorption element 12 according to the second embodiment, a first trench TR1 and a second trench TR2 are formed from the surface of the epitaxial layer Epi to the semiconductor substrate Sub, and therefore, similarly to the transient voltage absorption element 11 shown in the first embodiment, only four parasitic capacitances C11, C12, C22, C21 connected in series, four parasitic capacitances C11, C12, C32, C31 connected in series, and four parasitic capacitances C31, C32, C22, C21 connected in series are generated between the first electrode E1 and the second electrode E2.

[0040] According to the transient voltage absorption element 12 of the second embodiment, as shown in FIG. 4, a series circuit of at least four parasitic capacitances C11, C12, C22, C21 is formed between the first electrode E1 and the second electrode E2. A series circuit of at least four parasitic capacitances C31, C32, C12, C11 is formed between the first electrode E1 and the connection point of the diodes D11, D12 and the connection point of the diodes D21, D22. Also, a series circuit of at least four parasitic capacitances C31, C32, C22, C21 is formed between the second electrode E2 and the connection point of the diodes D11, D12 and the connection point of the diodes D21, D22. In this way, a series circuit of a plurality of parasitic capacitances is connected between the first electrode E1 and the second electrode E2, and a series circuit of a plurality of parasitic capacitances is simply connected in parallel to each diode, so that a transient voltage absorption element with low floating capacitance is obtained.

[0041] Third embodiment In the third embodiment, the entire structure of the transient voltage absorbing element including the redistribution layer is illustrated, and also, a transient voltage absorbing circuit including the transient voltage absorbing element is illustrated.

[0042] 7 is a cross-sectional view of a transient voltage absorption element 13 according to a third embodiment. The transient voltage absorption element 13 is composed of a semiconductor substrate portion and a rewiring portion. The semiconductor substrate portion includes a semiconductor substrate Sub, an epitaxial layer Epi, a first trench TR1, a second trench TR2, an insulator Ins1, and conductors Cond11, Cond12, and Cond13. The rewiring portion includes insulators Ins2, Ins3, Ins4, and Ins5, a conductor Cond2, and a pad Pad.

[0043] The pads (Pad) may be made of a multi-layered conductor for forming electrodes, i.e., the pads (Pad) may include, for example, a base layer and a surface layer, and may further include an adhesive layer between the base layer and the surface layer.

[0044] The insulating layer Ins5 may be configured not to cover the pad Pad. For example, if the insulating layer Ins5 is formed first and then the pad Pad is formed in the opening, the insulating layer Ins5 and the side portion of the pad Pad are in contact with each other.

[0045] The semiconductor substrate Sub may be made of, for example, Si or GaAs. The insulators Ins1, Ins2, Ins3, Ins4, and Ins5 may be made of, for example, SiO2, SiN, or solder resist depending on the location where they are formed. The conductors Cond11, Cond12, Cond13, and Cond2 may be made of, for example, Al or Cu. The pads Pad may be made of, for example, Ni, Cr, or an alloy thereof for the underlayer, Ti or W for the adhesion layer, and Au or other precious metals for the surface layer.

[0046] The epitaxial layer Epi is formed on the surface of the semiconductor substrate Sub. A p+ region and an n+ region are formed on the surface of the epitaxial layer Epi. An insulator Ins1 is formed on the surface of the epitaxial layer Epi. Conductors Cond11, Cond12, and Cond13 are formed from the surface of the epitaxial layer Epi to the p+ region and the n+ region. In addition, a first trench TR1 and a second trench TR2 are formed from the insulator Ins1 to the semiconductor substrate Sub.

[0047] The second trench TR2 is formed outside the first trench TR1 surrounding the first electrode E1 and the second electrode E2. This allows the parasitic capacitances generated between the redistribution layer extending to the end of the component and the semiconductor substrate to be connected in series, thereby reducing the combined parasitic capacitance.

[0048] The rewiring portion has a conductor Cond2 formed therein, which is electrically connected to the conductors Cond11 and Cond13. A pad Pad is formed on the conductor Cond2 in the uppermost layer.

[0049] 8 is a circuit diagram of a transient voltage absorbing circuit 103 including a transient voltage absorbing element 13. This transient voltage absorbing circuit 103 includes a first terminal T1, a second terminal T2, and a signal line SL that exists between the first terminal T1 and the second terminal T2. The transient voltage absorbing element 13 is connected between this signal line SL and a reference potential such as ground. Inductors La and Lb are connected in series to the signal line SL, and a capacitor C3 is connected in parallel to the inductors La and Lb. In this way, the capacitor C3 between the first terminal T1 and the second terminal T2 constitutes a high-pass filter.

[0050] The equivalent circuit of the transient voltage absorbing element 13 is the same as that of the transient voltage absorbing element 11 shown in FIG. 1. In this way, as described in the first embodiment, only a capacitance with a small combined parasitic capacitance value is connected between the signal line SL and the ground. That is, four parasitic capacitances C11, C12, C22, and C21 connected in series, four parasitic capacitances C11, C12, C32, and C31 connected in series, and four parasitic capacitances C31, C32, C22, and C21 connected in series are generated between the first electrode E1 and the second electrode E2. Moreover, since the values ​​of the parasitic capacitances C12, C22, C32, and C34 are very small, the combined parasitic capacitance generated between the first electrode E1 and the second electrode E2 is very small.

[0051] According to this embodiment, unlike the comparative example shown in Fig. 10, in which a series circuit of a single parasitic capacitance and a diode is connected between the first electrode E1 and the second electrode E2, the floating capacitance of the transient voltage absorption element 13 connected in shunt between the signal line SL and a reference potential such as the ground is small. Therefore, the amount of high-frequency signal shunted to the reference potential by the floating capacitance is suppressed, and the deterioration of the high-frequency passing characteristic of the transmission line can be suppressed.

[0052] According to this embodiment, since the stray capacitance of the transient voltage absorbing element 13 connected between the signal line SL and the ground is small, a transmission line in which degradation of high-frequency passing characteristics is suppressed can be configured.

[0053] Finally, the present invention is not limited to the above-described embodiments. Appropriate modifications and changes are possible by those skilled in the art. The scope of the present invention is indicated by the claims, not the above-described embodiments. Furthermore, the scope of the present invention includes modifications and changes from the embodiments within the scope of the claims and the equivalent scope. [Explanation of symbols]

[0054] Cond11,Cond12,Cond13,Cond2…Conductor C1…parasitic capacitance C11,C12,C21,C22…parasitic capacitance C2…parasitic capacitance C3: Capacitor C31,C32…parasitic capacitance C33,C34…parasitic capacitance D11, D12, D21, D22...Diodes E1…1st electrode E2…Second electrode E3,E4…electrode La, Lb…Inductor Epi...Epitaxial layer Pad…Pad SL…Signal line Sub: Semiconductor substrate T1: First terminal T2: Second terminal TR1: First trench TR2: Second trench 11, 12, 13...Transient voltage absorbing elements 101, 102...PN junction diode 103...Transient voltage absorption circuit 110...Zener diode 120...Cathode electrode terminal 121...Anode electrode terminal 201...Semiconductor substrate 210...first epitaxial layer 211...Second epitaxial layer 220…Embedding layer 232…Third diffusion region 250…First deep diffusion layer 501,502…Trench

Claims

1. a semiconductor substrate, an epitaxial layer formed on a surface of the semiconductor substrate, and a p+ region and an n+ region formed in the epitaxial layer, the epitaxial layer, the p+ region and the n+ region forming a surge absorbing diode; a trench extending from a surface of the epitaxial layer to the semiconductor substrate; The surge absorbing diode is composed of a plurality of diodes including a first diode and a second diode connected in series, a first electrode formed on a surface of the epitaxial layer and electrically connected to the first diode and a second electrode electrically connected to the second diode; the trenches include a first trench separating the plurality of diode formation regions from each other, and a second trench reducing a parasitic capacitance generated between the first electrode and the second electrode; Transient voltage absorbing element.

2. the second trench has a range surrounding the first electrode and the second electrode when viewed in a direction perpendicular to the semiconductor substrate; 2. The transient voltage absorbing element of claim 1.

3. the second trench is formed so as to surround the outer periphery of the first electrode and the second electrode when viewed in a direction perpendicular to the semiconductor substrate; 2. The transient voltage absorbing element of claim 1.

4. The length of the first trench in the thickness direction of the semiconductor substrate is approximately the same as the length of the second trench in the thickness direction of the semiconductor substrate.

2. The transient voltage absorbing element of claim 1.

5. the second trench includes a portion of the first trench and surrounds the first electrode and the second electrode when viewed in a direction perpendicular to the semiconductor substrate; The transient voltage absorbing element according to claim 2 .

6. the second trench includes an inner portion surrounding the first electrode and the second electrode when viewed in a direction perpendicular to the semiconductor substrate, and an outer portion surrounding the inner portion when viewed in a direction perpendicular to the semiconductor substrate. The transient voltage absorbing element according to claim 2 .

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