Semiconductor Device

Abstract

To provide a semiconductor device capable of improving characteristics such as a turn-on loss.SOLUTION: A semiconductor device that includes a diode part provided on a semiconductor substrate and a transistor part comprises: an emitter electrode provided above an upper surface of the semiconductor substrate; an interlayer insulating film provided between the upper surface and the emitter electrode; a trench part provided to the interior of the semiconductor substrate so as to extend in a predetermined extension direction on the upper surface; and a plurality of electrode contact parts that are portions where the emitter electrode is connected with the semiconductor substrate, and are provided so as to extend in the extension direction. The trench part includes: a gate trench part provided on the transistor part; and a dummy trench part provided on the diode part. In a first cross section parallel to an arrangement direction of the trench part and perpendicular to the upper surface, the plurality of electrode contact parts are electrically connected with each other in the arrangement direction by a semiconductor region of a second conductivity type provided on the diode part.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Conventionally, semiconductor devices such as insulated gate bipolar transistors (IGBTs) are known (see, for example, Patent Documents 1, 2 and 3). Patent Document 1: JP 2007-266133 A Patent Document 2: JP 2008-177297 A Patent Document 3: JP 2016-39215 A Summary of the Invention [Problem to be solved by the invention]

[0003] In semiconductor devices, it is desirable to improve characteristics such as turn-on loss. [Means for solving the problem]

[0004] In one aspect of the present invention, there is provided a semiconductor device including a diode section having a cathode region of a first conductivity type provided on a lower surface of a semiconductor substrate, and a transistor section having a collector region of a second conductivity type provided on the lower surface. The semiconductor device may include an emitter electrode provided above an upper surface of the semiconductor substrate, an interlayer insulating film provided between the upper surface and the emitter electrode, a trench section provided to the inside of the semiconductor substrate so as to extend in a predetermined extension direction on the upper surface, and a plurality of electrode contact sections provided in the extension direction, which are portions where the emitter electrode is connected to the semiconductor substrate. In any of the above semiconductor devices, the trench section may include at least a gate trench section provided in the transistor section, and at least a dummy trench section provided in the diode section. In a first cross section of any of the above semiconductor devices that is parallel to the arrangement direction of the trench sections and perpendicular to the upper surface, the plurality of electrode contact sections may be electrically connected in the arrangement direction by a semiconductor region of a second conductivity type provided in the diode section.

[0005] In any of the above semiconductor devices, the gate trench portion may include a first gate trench portion provided in the transistor portion closest to the diode portion, and a second gate trench portion adjacent to the first gate trench portion across the diode portion in the arrangement direction.In any of the above semiconductor devices, the dummy trench portion may include a first dummy trench portion adjacent to the first gate trench portion, and a second dummy trench portion adjacent to the first dummy trench portion.In any of the above semiconductor devices, a distance between the first gate trench portion and the first dummy trench portion may be narrower than a distance between the first dummy trench portion and the second dummy trench portion.

[0006] Any of the above semiconductor devices may further include a floating region of a second conductivity type provided between the first dummy trench portion and the second dummy trench portion.

[0007] In any of the semiconductor devices described above, the first dummy trench portion and the second dummy trench portion may have a connection portion at which two extension portions extending along the extension direction in a plan view are connected.

[0008] In any of the above semiconductor devices, the gate trench portion may include a first gate trench portion provided closest to the diode portion in the transistor portion, and a second gate trench portion adjacent to the first gate trench portion across the diode portion in the arrangement direction. In any of the above semiconductor devices, the electrode contact portion may be provided in plurality between the first gate trench portion and the second gate trench portion in the first cross section. In any of the above semiconductor devices, the gate trench portion may include a first gate trench portion provided closest to the diode portion in the transistor portion, and a second gate trench portion adjacent to the first gate trench portion across the diode portion in the arrangement direction. In any of the above semiconductor devices, the dummy trench portion may include a first dummy trench portion adjacent to the first gate trench portion, and a second dummy trench portion adjacent to the first dummy trench portion. In any of the above semiconductor devices, the electrode contact portion may be provided between the first gate trench portion and the first dummy trench portion in the first cross section. In any of the above semiconductor devices, the collector region may be provided below and between the first dummy trench portion and the second dummy trench portion.

[0009] In any of the above semiconductor devices, a distance between the first dummy trench portion and the second dummy trench portion may be at least twice as long as a distance between the first gate trench portion and the first dummy trench portion. In any of the above semiconductor devices, the electrode contact portion may be a trench contact.

[0010] The above summary of the invention does not list all of the necessary features of the present invention. Also, subcombinations of these features may also be inventions. [Brief description of the drawings]

[0011] [Figure 1] 1 is a diagram partially illustrating the top surface of a semiconductor device 100 according to an embodiment of the present invention. [Diagram 2] FIG. 2 is an enlarged view of an area A in FIG. [Diagram 3] FIG. 2 is an enlarged view of region B in FIG. [Figure 4] FIG. 2 is a diagram showing an example of a-a' cross section in FIG. [Diagram 5] 1 is a diagram partially illustrating the upper surface of a semiconductor device 150 of a comparative example. [Figure 6] FIG. 6 is a diagram showing an example of a-a' cross section in FIG. [Figure 7] FIG. 5 is an enlarged view of region C in FIG. [Figure 8] FIG. 5 is a diagram showing another example of the region C in FIG. [Figure 9] FIG. 5 is a diagram showing another example of the region C in FIG. [Figure 10] FIG. 8 is an enlarged view of region D in FIG. [Figure 11] FIG. 13 is a diagram showing the relationship between the distance Wfd and the on-voltage Von. [Figure 12] FIG. 13 is a diagram showing the relationship between the distance Wgfd and the on-voltage Von. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0013] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction of attachment to a substrate or the like when mounting a semiconductor device.

[0014] In this specification, technical matters may be described using orthogonal coordinate axes of X, Y, and Z. In this specification, a plane parallel to the top surface of the semiconductor substrate is defined as the XY plane, and the depth direction of the semiconductor substrate is defined as the Z axis.

[0015] In each embodiment, an example is shown in which the first conductivity type is N type and the second conductivity type is P type, but the first conductivity type may be P type and the second conductivity type may be N type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment are opposite polarities.

[0016] FIG. 1 is a diagram partially illustrating the top surface of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 of this example is a semiconductor chip including a transistor section 70 and a diode section 80. The transistor section 70 includes a transistor such as an IGBT. The diode section 80 is provided adjacent to the transistor section 70 on the top surface of the semiconductor substrate, and includes a diode such as an FWD (Free Wheel Diode). A region of the transistor section 70 located at the boundary between the transistor section 70 and the diode section 80 is a boundary section 90. FIG. 1 shows the top surface of the chip around the chip end, and other regions are omitted.

[0017] 1 shows an active region of the semiconductor substrate in semiconductor device 100, but semiconductor device 100 may have an edge termination structure surrounding the active region. The active region refers to a region through which current flows when semiconductor device 100 is controlled to be in an on-state. The edge termination structure relieves electric field concentration on the upper surface side of the semiconductor substrate. The edge termination structure may have, for example, a guard ring, a field plate, a resurf, or a structure that combines these.

[0018] The semiconductor device 100 of this example is provided inside a semiconductor substrate and includes a gate trench portion 40, a dummy trench portion 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 that are exposed on the upper surface of the semiconductor substrate. The semiconductor device 100 of this example also includes an emitter electrode 52 and a gate electrode 50 that are provided above the upper surface of the semiconductor substrate. The emitter electrode 52 and the gate electrode 50 are provided separately from each other.

[0019] An interlayer insulating film is formed between the emitter electrode 52 and the gate electrode 50 and the upper surface of the semiconductor substrate, but is omitted in Fig. 1. In the interlayer insulating film of this example, contact holes 56, 49, and 54 are formed so as to penetrate the interlayer insulating film.

[0020] Moreover, the emitter electrode 52 is connected to a dummy conductive portion in the dummy trench portion 30 through a contact hole 56. A connection portion 25 made of a conductive material such as polysilicon doped with impurities may be provided between the emitter electrode 52 and the dummy conductive portion. An insulating film such as an oxide film is formed between the connection portion 25 and the upper surface of the semiconductor substrate.

[0021] The gate electrode 50 contacts the gate wiring 48 through the contact hole 49. The gate wiring 48 is formed of polysilicon doped with impurities or the like. The gate wiring 48 is connected to the gate conductive portion in the gate trench portion 40 on the upper surface of the semiconductor substrate. The gate wiring 48 is not connected to the dummy conductive portion in the dummy trench portion 30. The gate wiring 48 in this example is formed from below the contact hole 49 to the tip of the gate trench portion 40. An insulating film such as an oxide film is formed between the gate wiring 48 and the upper surface of the semiconductor substrate. At the tip of the gate trench portion 40, the gate conductive portion is exposed to the upper surface of the semiconductor substrate and contacts the gate wiring 48.

[0022] The emitter electrode 52 and the gate electrode 50 are made of a material containing a metal. For example, at least a portion of each electrode is made of aluminum or an aluminum-silicon alloy. Each electrode may have a barrier metal made of titanium or a titanium compound under the region made of aluminum or the like, and may have a plug made of tungsten or the like in the contact hole.

[0023] The gate trench portion 40 in this example may have two extension portions 39 extending along an extension direction (the X-axis direction in this example) parallel to the upper surface of the semiconductor substrate and perpendicular to the arrangement direction, and a connection portion 41 connecting the two extension portions 39. It is preferable that at least a part of the connection portion 41 is formed in a curved shape. By connecting the ends of the two extension portions 39 of the gate trench portion 40, electric field concentration at the ends of the extension portions 39 can be alleviated. The gate wiring 48 may be connected to the gate conductive portion at the connection portion 41 of the gate trench portion 40.

[0024] The dummy trench portion 30 of this example may have a U-shape on the upper surface of the semiconductor substrate, similar to the gate trench portion 40. That is, the dummy trench portion 30 of this example may have two extension portions 29 extending along the extension direction and a connection portion 31 connecting the two extension portions 29.

[0025] The emitter electrode 52 is formed above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The well region 11 is of the second conductivity type, and is formed in a predetermined range from the end of the active region on the side where the gate electrode 50 is provided. The diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. Part of the regions of the gate trench portion 40 and the dummy trench portion 30 on the gate electrode 50 side are formed in the well region 11. The bottom of the end of the dummy trench portion 30 in the extension direction may be covered by the well region 11.

[0026] The contact holes 54 are formed above the contact region 15 and the emitter region 12. In the diode section 80, the contact holes 54 are formed above the contact region 15 and the base region 14. None of the contact holes 54 is located above the base region 14 and the well region 11 located at both ends of the first mesa portion 60 and the second mesa portion 62 in the X-axis direction.

[0027] A mesa portion is provided adjacent to each trench portion in a direction parallel to the top surface of the semiconductor substrate and perpendicular to the extension direction of each trench portion. The mesa portion is a portion of the semiconductor substrate sandwiched between two adjacent trench portions, and may be a portion from the top surface of the semiconductor substrate to the depth of the deepest bottom of each trench portion.

[0028] In the semiconductor device 100 of this example, a first mesa portion 60 is provided adjacent to one sidewall parallel to the extension direction of each trench portion in the transistor portion 70. A second mesa portion 62 is provided adjacent to the other sidewall parallel to the extension direction of each trench portion. A floating region 17 is provided inside the second mesa portion 62. No floating region 17 is provided inside the first mesa portion 60. In FIG. 1, the region where the floating region 17 is provided is indicated by a dashed line when viewed from above the semiconductor substrate.

[0029] As shown in Fig. 1, the first mesa portion 60 and the second mesa portion 62 may be alternately arranged in an arrangement direction perpendicular to the extension direction of each trench portion. As an example, a base region 14 is arranged at both ends in the X-axis direction of each first mesa portion 60 and each second mesa portion 62 (only one end in the X-axis direction is shown in Fig. 1). A boundary mesa portion 64 is provided in a region adjacent to the diode portion 80 of the transistor portion 70. A first conductive type cathode region 82 is provided in a region on the lower surface side of the semiconductor substrate of the diode portion 80. In Fig. 1, the region where the cathode region 82 is provided is indicated by a dashed line when viewed from above the semiconductor substrate.

[0030] The semiconductor device 100 has an accumulation region 16 of a first conductivity type having a doping concentration higher than that of the drift region, below the base region 14 inside the semiconductor substrate, adjacent to one sidewall and the other sidewall parallel to the extension direction of the gate trench portion 40. The accumulation region 16 may be disposed above the lower end of each trench portion. By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be enhanced, and the on-voltage can be reduced. In FIG. 1, the range in which the accumulation region 16 is formed is indicated by a dashed line.

[0031] 2 is an enlarged view of region A in FIG. 1. As shown in FIG. 2, the first mesa portion 60 and the second mesa portion 62 may be alternately provided in an arrangement direction perpendicular to the extension direction of each trench portion. Also, the emitter region 12 and the contact region 15 may be alternately provided in the extension direction of the gate trench portion 40. Inside the second mesa portion 62, a floating region 17 is provided in the region of the dashed line portion in a top view of the semiconductor substrate. That is, the floating region 17 is provided discretely in the second mesa portion 62 along the Y-axis direction in a top view.

[0032] An emitter region 12 is provided on the upper surface of the first mesa portion 60 in contact with the two gate trench portions 40 that sandwich the first mesa portion 60. The emitter region 12 in this example is N+ type. The emitter region 12 may be formed so as to connect the two trenches. When a trench contact is formed at the bottom of the contact hole 54, the emitter region 12 may be formed so as to connect the trench contact and one of the gate trench portions 40.

[0033] Furthermore, a contact region 15 of the second conductivity type having a doping concentration higher than that of the base region 14 is selectively formed on the upper surface of the first mesa portion 60. The contact region 15 may be formed to connect the two trenches. When a trench contact is formed at the bottom of the contact hole 54, the contact region 15 may be formed to connect the trench contact and one of the gate trench portions 40. The contact region 15 may also be formed at the bottom of the trench contact.

[0034] In the first mesa portion 60, the emitter regions 12 and the contact regions 15 may be arranged alternately adjacent to each other in the extension direction of the gate trench portion 40. On the upper surface of the first mesa portion 60, the emitter regions 12 may be provided in contact with the dummy trench portion 30 or may be provided separately from the dummy trench portion 30. The emitter regions 12 in the example of FIG. 2 are provided in contact with the dummy trench portion 30.

[0035] A contact region 15 of a second conductivity type having a higher doping concentration than the base region 14 is formed on the upper surface of the second mesa portion 62. An emitter region 12 may be provided adjacent to the gate trench portion 40 on the upper surface of the second mesa portion 62, but may not be provided. FIG. 2 shows an example in which the emitter region 12 is provided on the upper surface of the second mesa portion 62. When the emitter region 12 is not provided on the upper surface of the second mesa portion 62, the on-voltage Von of the transistor portion 70 can be made smaller than when the emitter region 12 is provided. On the upper surface of the second mesa portion 62, the contact region 15 may be provided in contact with the dummy trench portion 30 or may be provided away from the dummy trench portion 30. The contact region 15 in the example of FIG. 2 is provided in contact with the dummy trench portion 30.

[0036] The width Wfm of the second mesa portion 62 in the arrangement direction of the gate trench portion 40 of the second mesa portion 62 may be larger than the width Wm of the first mesa portion 60 in the arrangement direction of the gate trench portion 40 of the first mesa portion 60. Wfm may be twice or more than Wm. The width Wfm of the second mesa portion 62 is the width of the semiconductor substrate in the Y-axis direction sandwiched between the two trench portions sandwiching the second mesa portion 62 in a plane parallel to the upper surface of the semiconductor substrate. The width Wm of the first mesa portion 60 is the width of the semiconductor substrate in the Y-axis direction sandwiched between the two trench portions sandwiching the first mesa portion 60 in a plane parallel to the upper surface of the semiconductor substrate. By making the width Wfm of the second mesa portion 62 larger than the width Wm of the first mesa portion 60, holes can be extracted well from the lower surface side of the semiconductor substrate. Therefore, a good trade-off between the on-voltage and the turn-off loss can be achieved. Therefore, the turn-on loss of the semiconductor device 100 can be suppressed.

[0037] As shown in FIG. 2, a plurality of floating regions 17 may be provided in the second mesa portion 62 in a direction perpendicular to the extension direction of the gate trench portion 40 in a plane parallel to the upper surface of the semiconductor substrate. By providing a plurality of floating regions 17, holes can be more effectively extracted from the lower surface of the semiconductor substrate. This makes it possible to achieve a better trade-off between the on-voltage and the turn-off loss. In addition, the dummy trench portion 30 is not formed in the second mesa portion 62. As a result, holes are not extracted from the P-type inversion layer formed in the dummy trench portion 30 to the emitter region 12, so that an increase in the turn-on loss can be suppressed.

[0038] 3 is an enlarged view of region B in FIG. 1. In the semiconductor device 100 of this example, a second mesa portion 62 is provided adjacent to the dummy trench portion 30 in the diode portion 80. In the second mesa portion 62 of the diode portion 80 of this example, the emitter region 12 is not formed. In the second mesa portion 62 of the diode portion 80, the contact region 15 or the base region 14 is formed from one dummy trench portion 30 that sandwiches the second mesa portion 62 to the other dummy trench portion 30. In other words, on the upper surface of the semiconductor substrate, the width in the Y-axis direction of the second mesa portion 62 of the diode portion 80 is equal to the width in the Y-axis direction of the contact region 15 or the base region 14 provided in the second mesa portion 62 of the diode portion 80.

[0039] The second mesa portion 62 of the diode portion 80 may be provided with a contact region 15 having a smaller area exposed on the upper surface of the semiconductor substrate than the contact region 15 of the boundary mesa portion 64 of the transistor portion 70. As an example, the second mesa portion 62 of the diode portion 80 is provided with the contact regions 15 at both ends in the X-axis direction of the region sandwiched between the base regions 14, and the base region 14 is provided in the entire region sandwiched between the contact regions 15.

[0040] The diode section 80 has a first conductivity type cathode region 82 in a region on the lower surface side of the semiconductor substrate. In Fig. 3, the region where the cathode region 82 is provided in the top view of the semiconductor substrate is shown by a dashed line. The diode section 80 may be a region where the cathode region 82 is projected onto the top surface of the semiconductor substrate.

[0041] The distance Lc from the boundary between the contact region 15 and the base region 14 formed at both ends in the X-axis direction to the end of the cathode region 82 projected onto the upper surface may be equal to or greater than the diffusion length of holes or electrons. This makes it possible to prevent excessive injection of holes from the contact region 15 through the drift region into the cathode region 82.

[0042] Fig. 4 is a diagram showing an example of the a-a' cross section in Fig. 1. The a-a' cross section is a YZ plane passing through the emitter region 12 and the contact region 15 in the transistor section 70 and the diode section 80. In the a-a' cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24. The emitter electrode 52 is formed on the upper surfaces of the semiconductor substrate 10 and the interlayer insulating film 38.

[0043] Collector electrode 24 is formed on lower surface 23 of semiconductor substrate 10. Emitter electrode 52 and collector electrode 24 are formed of a conductive material such as metal. In this specification, the direction connecting emitter electrode 52 and collector electrode 24 is referred to as the depth direction (Z-axis direction).

[0044] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate such as gallium nitride. The semiconductor substrate 10 in this example is a silicon substrate. The semiconductor substrate 10 includes a drift region 18 of a first conductivity type. The drift region 18 in this example is an N-type. The drift region 18 may be a remaining region without other doping regions being formed.

[0045] The contact region 15 is provided inside the first mesa portion 60 and the second mesa portion 62, between the upper surface 21 of the semiconductor substrate 10 and the drift region 18. The contact region 15 in this example is provided on the upper surface 21 side of the base region 14 in the second mesa portion 62 or the boundary mesa portion 64 that is sandwiched between the dummy trench portions 30. The contact region 15 is also provided on the upper surface 21 side of the base region 14 in the first mesa portion 60 that is sandwiched between the gate trench portions 40.

[0046] In the semiconductor substrate 10, a P-type base region 14 having a lower doping concentration than the contact region 15 is provided between the upper surface 21 and the drift region 18. The gate trench portion 40 and the dummy trench portion 30 are provided from the upper surface 21 through the base region 14 to the inside of the semiconductor substrate 10. In this example, they are provided up to the drift region 18. The base region 14 contacts at least a sidewall of the gate trench portion 40 that is parallel to the XZ plane.

[0047] In the second mesa portion 62, a floating region 17 of a second conductivity type that is electrically floating and spaced apart from the gate trench portion 40 is provided below the base region 14. In the first mesa portion 60, a floating region 17 of a second conductivity type is not provided below the base region 14 at a depth equivalent to that of the floating region 17.

[0048] Since the dummy trench portion 30 is not formed in the second mesa portion 62, the electric field strength distribution in the off state is unlikely to be uniform. By providing the floating regions 17 of this example discretely, the electric field strength can be distributed uniformly, as in the case where the dummy trench portion 30 is formed, and a decrease in the breakdown voltage is prevented. The floating regions 17 may be arranged along the Y-axis direction at the same pitch as the two gate trench portions 40 that contact the first mesa portion.

[0049] In the second mesa portion 62 of the diode portion 80, the base region 14 is provided up to the upper surface 21. In addition, in the second mesa portion of the diode portion 80, neither the contact region 15 nor the emitter region 12 need be provided on the upper surface 21 onto which the cathode region 82 is projected.

[0050] The diode section 80 has an N+ type cathode region 82 below the buffer region 20. The cathode region 82 may be a region provided at approximately the same depth as the collector region 22 of the transistor section 70. As a result, the diode section 80 may function as a free wheel diode (FWD) in a power conversion circuit such as an inverter that passes a free wheel current that conducts in the reverse direction when the transistor section 70 of another semiconductor device 100 is turned off.

[0051] A collector region 22 is provided on the lower surface 23 below the boundary mesa portion 64. The collector region 22 of the transistor portion 70 may extend to the collector region 22. Since the collector region 22 extends to the lower surface 23 side of the boundary mesa portion 64, a distance between the emitter region 12 of the transistor portion 70 and the cathode region 82 of the diode portion 80 can be secured. This makes it possible to prevent electrons injected from the gate structure portion including the emitter region 12 of the transistor portion 70 into the drift region 18 from flowing out to the cathode region 82 of the diode portion 80. In addition, a distance between the contact region 15 of the transistor portion 70 and the cathode region 82 of the diode portion 80 can be secured. This makes it possible to suppress excess holes from flowing from the contact region 15 of the transistor portion 70 into the cathode region 82.

[0052] In this example, the distance between the contact region 15 of the boundary mesa portion 64 and the cathode region 82 of the diode portion 80 can be made longer than in the case where the cathode region 82 is provided up to just below the boundary mesa portion 64. This makes it possible to suppress the injection of holes from the contact region 15, which has a higher doping concentration than the base region 14, into the cathode region 82 when the diode portion 80 is conductive.

[0053] In both the transistor section 70 and the diode section 80, an N+ type buffer region 20 is formed below the drift region 18. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer extending from the lower surface side of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0054] In the transistor section 70, a P+ type collector region 22 is formed below the buffer region 20. The collector region 22 may extend to a region on the lower surface 23 side of the boundary mesa portion 64. In the diode section 80, an N+ type cathode region 82 is formed below the buffer region 20.

[0055] One or more gate trenches 40 and one or more dummy trenches 30 are formed on the upper surface 21 of the semiconductor substrate 10. Each trench reaches the drift region 18 from the upper surface 21 through the base region 14. In a region where at least one of the emitter region 12, the contact region 15, and the accumulation region 16 is provided, each trench also penetrates these regions and reaches the drift region 18. The trench penetrates the doping region is not limited to a case where the trench is manufactured in the order of forming the doping region and then the trench. A case where the trench is formed and then the doping region is formed between the trenches is also included in the case where the trench penetrates the doping region.

[0056] The gate trench portion 40 has a gate trench, a gate insulating film 42, and a gate conductive portion 44 formed on the upper surface 21. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate insulating film 42 within the gate trench. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0057] The gate conductive portion 44 includes a region facing at least the adjacent base region 14 in the depth direction, with the gate insulating film 42 sandwiched therebetween. The gate trench portion 40 in this cross section is covered at the upper surface 21 with the interlayer insulating film 38. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench.

[0058] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the upper surface 21 side. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and is formed further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10.

[0059] The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length in the depth direction as the gate conductive portion 44. The dummy trench portion 30 in the cross section is covered on the upper surface 21 with an interlayer insulating film 38. The bottoms of the dummy trench portion 30 and the gate trench portion 40 may be curved and convex downward (curved in cross section).

[0060] 5 is a diagram partially illustrating the upper surface of a comparative semiconductor device 150 that does not have a second mesa portion 62. In the comparative semiconductor device 150, a portion of a semiconductor substrate sandwiched between two adjacent trench portions is formed of a first mesa portion 60.

[0061] Fig. 6 is a diagram showing an example of a-a' cross section in Fig. 5. In the semiconductor device 150 of the comparative example, none of the first mesa portions 60 has a floating region 17.

[0062] In the semiconductor device 150 of the comparative example in FIG. 6, the dummy trench portion 30 is provided adjacent to the gate trench portion 40. Therefore, a P-type inversion layer is generated at the bottom of the dummy trench portion 30 when the semiconductor device is turned on. When the semiconductor device is turned on, holes are extracted from the P-type inversion layer to the emitter region 12. This increases the turn-on loss. In the semiconductor device 100 of the present example in FIG. 4, the floating region 17 is provided adjacent to the gate trench portion 40. Since the floating region 17 exists, holes can be extracted well from the lower surface 23 side of the semiconductor substrate 10. This makes it possible to achieve a good trade-off between the on-voltage and the turn-off loss. In addition, since the dummy trench portion 30 does not exist at the position of the floating region 17, the turn-on loss caused by holes being extracted from the P-type inversion layer to the emitter region 12 can be suppressed.

[0063] Fig. 7 is an enlarged view of region C surrounded by a dashed line in Fig. 4. As shown in Fig. 7, in a direction parallel to upper surface 21, the distance Wff between adjacent floating regions 17 in the Y-axis direction may be equal to the width Wm of first mesa portion 60. Here, "equal" may include an error range of 10% or less. In this specification, when it is written "equal," "same," "identical," etc., an error range of 10% or less may be included.

[0064] The sum of the width Wm of the first mesa portion 60 and the gate trench width Wg may be equal to the sum of the distance Wff in the Y-axis direction between adjacent floating regions 17 and the floating region width Wf in a plane parallel to the top surface 21. Furthermore, in a plane parallel to the top surface 21, the floating region width Wf of the floating region 17 in the arrangement direction of the gate trench portions 40 may be equal to the gate trench width Wg in the arrangement direction of the gate trench portions 40. By making the floating region width Wf equal to the gate trench width Wg, the floating region 17 can be manufactured with the same mask width as the gate trench portions 40.

[0065] As shown in FIG. 7, the floating region 17 may not be present at least partially below the emitter region 12 provided in the second mesa portion 62 in the depth direction of the semiconductor substrate 10. Moreover, the floating region 17 may not be present below the contact hole 54 formed in the interlayer insulating film 38 provided on the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. Moreover, the floating region 17 may be located at a depth shallower than the gate depth Wgd from the upper surface 21 to the bottom of the gate trench portion 40. Moreover, the distance Wff between the adjacent floating regions 17 in the Y-axis direction may be smaller than the floating region width Wf. By providing the floating region 17 of this example as described above, the electric field strength during the off state can be uniformly distributed, as with the dummy trench portion 30, and a decrease in the breakdown voltage is prevented.

[0066] Fig. 8 is a diagram showing another example of region C in Fig. 4. In the semiconductor device 100 shown in Fig. 8, in a plane parallel to the upper surface 21, the width Wwf in the Y-axis direction of the floating region 17 located toward the center of the second mesa portion 62 is larger than the floating region width Wf in the Y-axis direction of the floating region 17 closest to the gate trench portion 40.

[0067] By making the floating region width Wwf of the floating region 17 located at the center of the second mesa portion 62 larger than the floating region width Wf of the floating region 17 closest to the gate trench portion 40, holes can be more effectively extracted from the lower surface 23 side. This makes it possible to achieve a better trade-off between the on-voltage and the turn-off loss. In addition, the turn-on loss caused by holes being extracted from the P-type inversion layer to the emitter region 12 can be suppressed. Furthermore, the floating region 17 of this example can distribute the electric field strength uniformly, preventing a decrease in the breakdown voltage.

[0068] FIG. 9 is a diagram showing another example of the region C in FIG. 4. In the semiconductor device 100 shown in FIG. 9, the floating region 17 is provided below the accumulation region 16 in the depth direction of the semiconductor substrate 10 in FIG. 7. Here, "below" means that the upper surface 17-1 of the floating region 17 in the direction parallel to the upper surface 21 is at a depth equal to or lower than the lower surface 16-1 of the accumulation region 16. FIG. 9 shows an example in which the upper surface 17-1 of the floating region 17 is provided below the lower surface 16-1 of the accumulation region 16. The lower surface 16-1 of the accumulation region 16 means a boundary showing a doping concentration five times higher than that of the base region 14. The upper surface 17-1 of the floating region 17 may be provided at the same depth as the lower surface 16-1 of the accumulation region 16.

[0069] By providing the upper surface 17-1 of the floating region 17 below the lower surface 16-1 of the accumulation region 16, holes can be more effectively extracted from the lower surface 23 side. This makes it possible to achieve a better trade-off between the on-voltage and the turn-off loss. Also, it is possible to suppress the turn-on loss caused by holes being extracted from the P-type inversion layer to the emitter region 12. Furthermore, the floating region 17 of this example can distribute the electric field strength uniformly, preventing a decrease in the breakdown voltage.

[0070] Also, as in Figure 8, in a plane parallel to the upper surface 21, the floating region width Wwf in the Y-axis direction of the floating region 17 located toward the center of the second mesa portion 62 may be larger than the floating region width Wf in the Y-axis direction of the floating region 17 closest to the gate trench portion 40.

[0071] Fig. 10 is an enlarged view of region D surrounded by a dashed line in Fig. 7. As shown in Fig. 10, the width of floating region 17 in the Z-axis direction is defined as Wft. The depth from upper surface 21 to the peak of the doping concentration in the depth direction of floating region 17 is defined as Wfd. When the doping concentration distribution in the depth direction of floating region 17 is uniform, Wfd may be the depth to the center of floating region 17 in the depth direction.

[0072] The distance from the sidewall of the gate trench portion 40 on the second mesa portion 62 side to the floating region 17 closest to the gate trench portion 40 is defined as Wgf. Wgf may be the distance from the sidewall of the gate trench portion 40 at the same depth as the floating region 17 closest to the gate trench portion 40 to the floating region 17.

[0073] The depth from the upper surface 21 to the bottom of the gate trench portion 40 is defined as Wgd. The difference between Wgd and the depth from the upper surface 21 to the bottom surface of the floating region 17 is defined as Wgfd. The depth from the upper surface 21 to the bottom surface of the contact region 15 is defined as Wc. The bottom surface of the contact region 15 refers to the boundary where the doping concentration in the second mesa portion 62 exhibits a doping concentration equal to the doping concentration in the base region 14 of the first mesa portion 60. In addition, the depth in the Z-axis direction of the base region 14 below the contact region 15 is defined as Wb.

[0074] The depth Wgfd from the lower surface of the floating region 17 to the bottom of the gate trench portion 40 may be greater than the width Wft of the floating region 17 in the Z-axis direction. In addition, the depth Wgfd from the lower surface of the floating region 17 to the bottom of the gate trench portion 40 may be greater than the distance Wgf from the sidewall of the gate trench portion 40 on the second mesa portion 62 side to the floating region 17 adjacent to the gate trench portion 40. By setting the magnitude relationship of Wgfd, Wft, and Wgf in this way, holes can be more effectively extracted from the lower surface 23 side of the semiconductor substrate 10. In particular, by setting Wgfd to a predetermined length, the carrier injection promotion effect (IE effect) can be enhanced while also increasing the extraction of holes. This makes it possible to improve the trade-off between the on-voltage and the turn-off loss. In addition, the turn-on loss caused by holes being extracted from the P-type inversion layer to the emitter region 12 can be suppressed. Furthermore, the floating region 17 of this embodiment allows the electric field strength to be distributed uniformly, preventing a decrease in the breakdown voltage.

[0075] FIG. 11 is a diagram showing a simulation of the relationship between Wfd and the on-voltage Von of the transistor section 70 when, as an example, Wft is 1 μm, Wgf is 0.7 μm, Wf is 1.2 μm, Wgd is 6.0 μm, Wc is 1.7 μm, and Wb is 1.1 μm in FIG. 10. The vertical axis shows the on-voltage Von normalized with the maximum value of the on-voltage Von set to 100%. As can be seen from FIG. 11, when Wfd is 2.3 μm, the on-voltage Von shows the maximum value. When Wfd is increased, the on-voltage Von decreases sharply. When Wfd is 2.9 μm, the on-voltage Von shows the minimum value. When Wfd is further increased, the on-voltage Von increases monotonically.

[0076] In FIG. 11, when Wfd is smaller than 2.9 μm, the floating region 17 is located at a shallower position in the Z-axis direction from the upper surface 21 compared to Wgd, so that the accumulation region 16 is canceled by the floating region 17. As a result, the holes concentrated at the bottom of the gate trench portion 40 are easily extracted by the floating region 17, and the on-voltage becomes high. Also, when Wfd is larger than 2.9 μm, the holes concentrated at the bottom of the gate trench portion 40 are easily extracted by the floating region 17. However, since the distance between the floating region 17 and the emitter region 12 becomes large, the hole extraction ability of the transistor portion 70 as a whole becomes small. Therefore, the accumulation effect of the holes is reduced, and the on-voltage Von becomes large. As can be seen from FIG. 11, when Wfd is 2.6 μm or more and 4.8 μm or less, the on-voltage Von can be increased by 2% or less from the minimum value.

[0077] FIG. 12 is a diagram in which Wfd in FIG. 11 is converted into the distance Wgfd from the lower surface of the floating region 17 to the bottom of the gate trench portion 40. As can be seen from FIG. 12, when Wgfd is 2.2 μm, the on-voltage Von shows a maximum value. When Wgfd is reduced, the on-voltage Von decreases sharply. When Wgfd is 1.6 μm, the on-voltage Von shows a minimum value. When Wgfd is further reduced, Wgfd increases monotonically. As can be seen from FIG. 12, when converted into Wgfd, when Wgfd is -0.3 μm or more and 1.9 μm or less, the on-voltage Von can increase within 2% from the minimum value. Here, negative values ​​are when the floating region 17 is located deeper than the bottom of the gate trench portion 40. In terms of the depth from the lower surface of the floating region 17 to the gate trench portion 40, when Wgfd is 1.9 μm or less, the on-voltage Von can be increased by 2% or less from the minimum value.

[0078] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the claims that such modifications and improvements can also be included in the technical scope of the present invention.

[0079] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and may be realized in any order unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is explained using "first," "next," etc. for convenience, it does not mean that it is essential to perform the process in this order. [Explanation of symbols]

[0080] 10 semiconductor substrate, 11 well region, 12 emitter region, 14 base region, 15 contact region, 16 accumulation region, 16-1 lower surface of accumulation region, 17 floating region, 17-1 upper surface of floating region, 18 drift region, 20 buffer region, 21 upper surface, 22 collector region, 23 lower surface, 24 collector electrode, 25 connection portion, 29 extension portion, 30 dummy trench portion, 31 connection portion, 32 dummy insulating film, 34 dummy mesa conductive portion, 38...interlayer insulating film, 39...extension portion, 40...gate trench portion, 41...connection portion, 42...gate insulating film, 44...gate conductive portion, 48...gate wiring, 49...contact hole, 50...gate electrode, 52...emitter electrode, 54...contact hole, 56...contact hole, 60...first mesa portion, 62...second mesa portion, 64...boundary mesa portion, 70...transistor portion, 80...diode portion, 82...cathode region, 100...semiconductor device, 150...semiconductor device

Claims

1. 1. A semiconductor device including: a diode section having a first conductive type cathode region provided on a lower surface of a semiconductor substrate; and a transistor section having a second conductive type collector region provided on the lower surface, an emitter electrode provided above an upper surface of the semiconductor substrate; an interlayer insulating film provided between the upper surface and the emitter electrode; a trench portion provided on the upper surface to extend into the semiconductor substrate in a predetermined extension direction; a plurality of electrode contact portions extending in the extension direction, the electrode contact portions being portions at which the emitter electrode is connected to the semiconductor substrate; Equipped with the trench portion includes at least a gate trench portion provided in the transistor portion and a dummy trench portion provided in at least the diode portion, in a first cross section parallel to an arrangement direction of the trench portions and perpendicular to the top surface, the electrode contact portions are electrically connected in the arrangement direction by a semiconductor region of a second conductivity type provided in the diode portion; the gate trench portion includes a first gate trench portion provided in the transistor portion closest to the diode portion, and a second gate trench portion adjacent to the first gate trench portion in the arrangement direction with the diode portion interposed therebetween; the dummy trench portion includes a first dummy trench portion adjacent to the first gate trench portion and a second dummy trench portion adjacent to the first dummy trench portion, The distance between the first gate trench portion and the first dummy trench portion is narrower than the distance between the first dummy trench portion and the second dummy trench portion. Semiconductor device.

2. a floating region of a second conductivity type provided between the first dummy trench portion and the second dummy trench portion; The semiconductor device according to claim 1 .

3. The first dummy trench portion and the second dummy trench portion are The connecting portion is connected to two extending portions extending in the extending direction in a plan view.

3. The semiconductor device according to claim 1 or 2.

4. A semiconductor device including: a diode section having a cathode region of a first conductivity type provided on a lower surface of a semiconductor substrate; and a transistor section having a collector region of a second conductivity type provided on the lower surface, an emitter electrode provided above an upper surface of the semiconductor substrate; an interlayer insulating film provided between the upper surface and the emitter electrode; a trench portion provided on the upper surface to extend into the semiconductor substrate in a predetermined extension direction; a plurality of electrode contact portions extending in the extension direction, the electrode contact portions being portions at which the emitter electrode is connected to the semiconductor substrate; Equipped with the trench portion includes at least a gate trench portion provided in the transistor portion and a dummy trench portion provided in at least the diode portion, in a first cross section parallel to an arrangement direction of the trench portions and perpendicular to the top surface, the electrode contact portions are electrically connected in the arrangement direction by a semiconductor region of a second conductivity type provided in the diode portion; the gate trench portion includes a first gate trench portion provided in the transistor portion closest to the diode portion, and a second gate trench portion adjacent to the first gate trench portion in the arrangement direction with the diode portion interposed therebetween; the dummy trench portion includes a first dummy trench portion adjacent to the first gate trench portion and a second dummy trench portion adjacent to the first dummy trench portion, the electrode contact portion is provided between the first gate trench portion and the first dummy trench portion in the first cross section, The distance between the first dummy trench portion and the second dummy trench portion is at least twice the distance between the first gate trench portion and the first dummy trench portion. Semiconductor device.

5. A semiconductor device including: a diode section having a cathode region of a first conductivity type provided on a lower surface of a semiconductor substrate; and a transistor section having a collector region of a second conductivity type provided on the lower surface, an emitter electrode provided above an upper surface of the semiconductor substrate; an interlayer insulating film provided between the upper surface and the emitter electrode; a trench portion provided on the upper surface to extend into the semiconductor substrate in a predetermined extension direction; a plurality of electrode contact portions extending in the extension direction, the electrode contact portions being portions at which the emitter electrode is connected to the semiconductor substrate; Equipped with the trench portion includes at least a gate trench portion provided in the transistor portion and a dummy trench portion provided in at least the diode portion, in a first cross section parallel to an arrangement direction of the trench portions and perpendicular to the top surface, the electrode contact portions are electrically connected in the arrangement direction by a semiconductor region of a second conductivity type provided in the diode portion; the gate trench portion includes a first gate trench portion provided in the transistor portion closest to the diode portion, and a second gate trench portion adjacent to the first gate trench portion in the arrangement direction with the diode portion interposed therebetween; the dummy trench portion includes a first dummy trench portion adjacent to the first gate trench portion and a second dummy trench portion adjacent to the first dummy trench portion, The collector region is provided below and between the first dummy trench portion and the second dummy trench portion. Semiconductor device.

6. A semiconductor device including: a diode section having a cathode region of a first conductivity type provided on a lower surface of a semiconductor substrate; and a transistor section having a collector region of a second conductivity type provided on the lower surface, an emitter electrode provided above an upper surface of the semiconductor substrate; an interlayer insulating film provided between the upper surface and the emitter electrode; a trench portion provided on the upper surface to extend into the semiconductor substrate in a predetermined extension direction; a plurality of electrode contact portions extending in the extension direction, the electrode contact portions being portions at which the emitter electrode is connected to the semiconductor substrate; Equipped with the trench portion includes at least a gate trench portion provided in the transistor portion and a dummy trench portion provided in at least the diode portion, in a first cross section parallel to an arrangement direction of the trench portions and perpendicular to the top surface, the electrode contact portions are electrically connected in the arrangement direction by a semiconductor region of a second conductivity type provided in the diode portion; In the transistor section, at least one mesa portion in contact with the gate trench portion is provided with one of the electrode contact portions. Semiconductor device.

7. the gate trench portion includes a first gate trench portion provided in the transistor portion closest to the diode portion, and a second gate trench portion adjacent to the first gate trench portion in the arrangement direction with the diode portion interposed therebetween; The electrode contact portion is provided in plurality between the first gate trench portion and the second gate trench portion in the first cross section. The semiconductor device according to claim 6.

8. the gate trench portion includes a first gate trench portion provided in the transistor portion closest to the diode portion, and a second gate trench portion adjacent to the first gate trench portion in the arrangement direction with the diode portion interposed therebetween; the dummy trench portion includes a first dummy trench portion adjacent to the first gate trench portion and a second dummy trench portion adjacent to the first dummy trench portion, The electrode contact portion is provided between the first gate trench portion and the first dummy trench portion in the first cross section. The semiconductor device according to claim 6.

9. The distance between the first dummy trench portion and the second dummy trench portion is at least twice the distance between the first gate trench portion and the first dummy trench portion.

9. The semiconductor device according to claim 1, wherein the first insulating layer is a first insulating layer.

10. The electrode contact portion is a trench contact. The semiconductor device according to claim 1 .

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