Silicon carbide semiconductor device

Abstract

In the present invention, an active region includes a first super junction layer and a device layer. The first super junction layer has first regions and second regions in an alternating configuration. A surrounding region includes a second super junction layer, a terminal layer, and an insulation layer. The second super junction layer has third regions and fourth regions in an alternating configuration. The terminal layer is provided upon the second super junction layer in contact therewith, and has fifth regions and sixth regions in an alternating configuration. The fifth regions are provided as respectively corresponding to the third regions, and the sixth regions are provided as respectively corresponding to the fourth regions. The impurity concentration of the sixth regions is greater than the impurity concentration of the fifth regions by a factor equal to or less than 68 times the impurity concentration of the fifth regions.

Description

[Technical field]

[0001] The present disclosure relates to a silicon carbide semiconductor device. This application claims priority to Japanese Patent Application No. 2020-118900, filed on July 10, 2020. The entire contents of the Japanese patent application are incorporated herein by reference. [Background technology]

[0002] Japanese Patent Laid-Open Publication No. 2006-73987 (Patent Document 1) and Japanese Patent Laid-Open Publication No. 2003-273355 (Patent Document 2) describe a metal oxide semiconductor field effect transistor (MOSFET) having a superjunction structure, mainly targeting silicon semiconductors. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2006-73987 A [Patent Document 2] JP 2003-273355 A Summary of the Invention

[0004] A silicon carbide semiconductor device according to the present disclosure includes a substrate, an active region, a peripheral region, and a first electrode. The substrate is made of a silicon carbide semiconductor of a first conductivity type. The active region is provided in a part of a first main surface of the substrate. The peripheral region is provided on the substrate and surrounds the active region in a plan view. The first electrode is provided on a second main surface facing the first main surface of the substrate. The active region includes a first superjunction layer, an element layer, and a second electrode. The first superjunction layer is provided above the substrate and has a first region of a first conductivity type and a second region of a second conductivity type alternately. The element layer is provided above the first superjunction layer. The second electrode is provided on the element layer. The peripheral region includes a second superjunction layer, a termination layer, and an insulating layer. The second superjunction layer is provided above the substrate and has a third region of a first conductivity type and a fourth region of a second conductivity type alternately. The termination layer is provided on and in contact with the second superjunction layer and has alternating fifth regions of the second conductivity type and sixth regions of the second conductivity type. The insulating layer is in contact with each of the upper end surfaces of the fifth region and the sixth region. The fifth region is provided corresponding to the third region, and the sixth region is provided corresponding to the fourth region. The sixth region has an impurity concentration greater than the impurity concentration of the fifth region and not more than 68 times the impurity concentration of the fifth region. [Brief description of the drawings]

[0005] [Figure 1] FIG. 1 is a schematic vertical cross-sectional view showing the configuration of a silicon carbide semiconductor device in accordance with the first embodiment. [Diagram 2] FIG. 2 is a partial cross-sectional schematic view showing the configuration of a silicon carbide semiconductor device in accordance with the second embodiment. [Diagram 3] FIG. 3 is a schematic vertical cross-sectional view taken along line III-III in FIG. [Figure 4] FIG. 4 is a schematic vertical cross-sectional view taken along line IV-IV in FIG. [Diagram 5] FIG. 5 is a schematic vertical cross-sectional view showing the configuration of a silicon carbide semiconductor device in accordance with the third embodiment. [Figure 6]FIG. 6 is a partial cross-sectional schematic view showing the configuration of a silicon carbide semiconductor device in accordance with the fourth embodiment. [Figure 7] FIG. 7 is a schematic vertical cross-sectional view taken along line VII-VII in FIG. [Figure 8] FIG. 8 is a schematic vertical cross-sectional view taken along line VIII-VIII in FIG. [Figure 9] FIG. 9 is a schematic vertical cross-sectional view showing the configuration of a silicon carbide semiconductor device in accordance with the fifth embodiment. [Figure 10] FIG. 10 is a schematic vertical cross-sectional view showing the configuration of a silicon carbide semiconductor device in accordance with the sixth embodiment. [Figure 11] FIG. 11 is a diagram showing the results of a breakdown voltage simulation. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] [Problem that this disclosure aims to solve] An object of the present disclosure is to provide a silicon carbide semiconductor device capable of improving reliability. [Effects of this disclosure] Advantageous Effects of Invention According to the present disclosure, it is possible to provide a silicon carbide semiconductor device capable of improving reliability. [Description of the embodiments of the present disclosure] First, the embodiments of the present disclosure will be listed and described. In the crystallographic description in this specification, an individual orientation is represented by [], a collective orientation by <>, an individual plane by (), and a collective plane by {}. A negative index in crystallography is usually represented by placing a "-" (bar) above the number, but in this specification, a negative index in crystallography is represented by placing a negative sign before the number.

[0007] (1) A silicon carbide semiconductor device 100 according to the present disclosure includes a substrate 90, an active region IR, a peripheral region OR, and a first electrode 61. The substrate 90 is made of a silicon carbide semiconductor of a first conductivity type. The active region IR is provided in a part of a first main surface 1 of the substrate 90. The peripheral region OR is provided on the substrate 90 and surrounds the active region IR in a plan view. The first electrode 61 is provided on a second main surface 2 facing the first main surface 1 of the substrate 90. The active region IR includes a first superjunction layer 10, an element layer 40, and a second electrode 62. The first superjunction layer 10 is provided above the substrate 90 and has first regions 41 of the first conductivity type and second regions 42 of the second conductivity type alternately. The element layer 40 is provided above the first superjunction layer 10. The second electrode 62 is provided on the element layer 40. The peripheral region OR includes a second superjunction layer 20, a termination layer 50, and an insulating layer 7. The second superjunction layer 20 is provided above the substrate 90, and has a third region 43 of a first conductivity type and a fourth region 44 of a second conductivity type alternately. The termination layer 50 is provided on and in contact with the second superjunction layer 20, and has a fifth region 45 of a second conductivity type and a sixth region 46 of a second conductivity type alternately. The insulating layer 7 is in contact with each of the upper end surfaces of the fifth region 45 and the sixth region 46. The fifth region 45 is provided corresponding to the third region 43, and the sixth region 46 is provided corresponding to the fourth region 44. The impurity concentration of the sixth region 46 is greater than the impurity concentration of the fifth region 45, and is 68 times or less than the impurity concentration of the fifth region 45.

[0008] (2) In silicon carbide semiconductor device 100 according to (1) above, sixth region 46 may have a higher impurity concentration than fourth region 44.

[0009] (3) In the silicon carbide semiconductor device 100 relating to (1) or (2) above, the absolute value of the difference between the impurity concentration of the fifth region 45 and the impurity concentration of the sixth region 46 may be substantially equal to the sum of the impurity concentration of the third region 43 and the impurity concentration of the fourth region 44.

[0010] (4) In the silicon carbide semiconductor device 100 according to any one of (1) to (3) above, a first distance D1 between the upper surface of the element layer 40 and the interface between the element layer 40 and the first superjunction layer 10 may be greater than a second distance D2 between the upper surface of the termination layer 50 and the interface between the termination layer 50 and the second superjunction layer 20.

[0011] (5) In silicon carbide semiconductor device 100 according to any one of (1) to (4) above, first region 41 and third region 43 may each have a first portion 71 and a second portion 72 located between first portion 71 and substrate 90. Second region 42 and fourth region 44 may each have a third portion 73 in contact with first portion 71 and a fourth portion 74 in contact with second portion 72 and located between third portion 73 and substrate 90. In a cross section perpendicular to second main surface 2 and parallel to a direction from first region 41 to second region 42, second portion 72 may have a width greater than that of first portion 71, a width greater than that of fourth portion 74, a width less than that of third portion 73, a width less than that of first portion 71, and a width less than that of third portion 73. The impurity concentration of each of the first portion 71 and the third portion 73 may be higher than the impurity concentration of each of the second portion 72 and the fourth portion 74.

[0012] (6) In silicon carbide semiconductor device 100 according to any one of (1) to (5) above, first region 41 and third region 43 each have an impurity concentration of 3×10 16 cm -3 5×10 or more 17 cm -3 The impurity concentration of each of the second region 42 and the fourth region 44 may be 3×10 16 cm -3 5×10 or more 17 cm -3 It may be the following.

[0013] (7) In the silicon carbide semiconductor device 100 according to any one of (1) to (6) above, a first buffer layer 12 of a first conductivity type may be provided between the first superjunction layer 10 and the substrate 90. A second buffer layer 52 of the first conductivity type may be provided between the second superjunction layer 20 and the substrate 90.

[0014] (8) In the silicon carbide semiconductor device 100 according to any one of (1) to (7) above, the element layer 40 may include a first impurity region 14 of the first conductivity type, a second impurity region 23 in contact with the first impurity region 14 and having the second conductivity type, and a third impurity region 30 separated from the first impurity region 14 by the second impurity region 23 and having the first conductivity type. The element layer 40 may be provided with a trench 5 having a side surface 8 formed by each of the first impurity region 14, the second impurity region 23, and the third impurity region 30, and a bottom 9 continuing to the side surface 8 and formed by the first impurity region 14. The first electrode 61 may be a source electrode. The second electrode 62 may be a drain electrode. A gate electrode 63 may be provided inside the trench 5.

[0015] (9) In silicon carbide semiconductor device 100 according to any one of (1) to (8) above, first main surface 1 may be a {0001} plane or a plane inclined at an angle of 8° or less with respect to the {0001} plane. [Details of the embodiment of the present disclosure] Hereinafter, the details of the embodiments of the present disclosure will be described. In the following description, the same or corresponding elements are denoted by the same reference numerals, and the same description thereof will not be repeated.

[0016] (First embodiment) First, a description will be given of the configuration of silicon carbide semiconductor device 100 in accordance with the first embodiment. Fig. 1 is a schematic vertical cross-sectional view showing the configuration of silicon carbide semiconductor device 100 in accordance with the first embodiment.

[0017] As shown in FIG. 1, the silicon carbide semiconductor device 100 according to the first embodiment is a planar MOSFET. The silicon carbide semiconductor device 100 according to the first embodiment mainly includes, for example, a substrate 90, an active region IR, a peripheral region OR, and a first electrode 61. The substrate 90 is made of a silicon carbide semiconductor of a first conductivity type. The first conductivity type is, for example, an n-type. The substrate 90 contains an n-type impurity capable of imparting an n-type, such as N (nitrogen). The substrate 90 has a first main surface 1 and a second main surface 2. The second main surface 2 faces the first main surface 1. The second main surface 2 is the surface opposite to the first main surface 1.

[0018] Substrate 90 is made of, for example, hexagonal silicon carbide of polytype 4H. First main surface 1 may be, for example, a {0001} plane or a plane inclined at an angle of 8° or less with respect to the {0001} plane. Specifically, first main surface 1 may be a (0001) plane or a plane inclined at an angle of 8° or less with respect to the (0001) plane. First main surface 1 may be a (000-1) plane or a plane inclined at an angle of 8° or less with respect to the (000-1) plane. Substrate 90 has a first substrate portion 11 and a second substrate portion 51.

[0019] The active region IR is provided in a part of a first main surface 1 of a substrate 90. The first main surface 1 has a first area 91 and a second area 92. The active region IR is on the first area 91. The active region IR mainly includes a first buffer layer 12, a first superjunction layer 10, an element layer 40, a second electrode 62, a gate electrode 63, a gate insulating film 6, and an isolation insulating film 64. The first buffer layer 12 is located between the first superjunction layer 10 and the substrate 90. The first buffer layer 12 has, for example, an n-type (first conductivity type). The first buffer layer 12 contains an n-type impurity capable of imparting an n-type, such as N (nitrogen). The first buffer layer 12 is in contact with the first area 91.

[0020] The first superjunction layer 10 is provided above the substrate 90. The first superjunction layer 10 is in contact with, for example, the first buffer layer 12. The first superjunction layer 10 has first regions 41 and second regions 42 arranged alternately. The first regions 41 and the second regions 42 are arranged alternately, for example, along a direction parallel to the first main surface 1. From another perspective, the first regions 41 and the second regions 42 are arranged alternately, for example, along a direction intersecting the thickness direction of the substrate 90.

[0021] The first region 41 has an n-type (first conductivity type). The first region 41 contains an n-type impurity capable of imparting an n-type conductivity, such as N (nitrogen). The second region 42 has a p-type (second conductivity type). The second region 42 contains a p-type impurity capable of imparting a p-type conductivity, such as Al (aluminum).

[0022] The element layer 40 is provided above the first superjunction layer 10. The element layer 40 is, for example, a switching element portion. The element layer 40 has, for example, a first impurity region 14, a second impurity region 23, a third impurity region 30, and a fourth impurity region 24. The first impurity region 14 is, for example, a drift region. The first impurity region 14 has an n-type (first conductivity type). The first impurity region 14 contains an n-type impurity capable of imparting an n-type, such as N (nitrogen). The first impurity region 14 is in contact with the first region 41.

[0023] The second impurity region 23 is, for example, a body region. The second impurity region 23 is in contact with the first impurity region 14. The second impurity region 23 has p-type (second conductivity type). The second impurity region 23 contains p-type impurities capable of imparting p-type, such as Al (aluminum). The second impurity region 23 is in contact with the first region 41 and the second region 42. The concentration of the p-type impurity contained in the second impurity region 23 may be higher than the concentration of the n-type impurity contained in the first impurity region 14.

[0024] The third impurity region 30 is, for example, a source region. The third impurity region 30 is separated from the first impurity region 14 by the second impurity region 23. The third impurity region 30 has an n-type (first conductivity type). The third impurity region 30 contains an n-type impurity capable of imparting an n-type, such as P (phosphorus). The concentration of the n-type impurity contained in the third impurity region 30 may be higher than the concentration of the p-type impurity contained in the second impurity region 23.

[0025] The fourth impurity region 24 is, for example, a contact region. The fourth impurity region 24 is in contact with the second impurity region 23 and the third impurity region 30. The fourth impurity region 24 has p-type (second conductivity type). The fourth impurity region 24 contains p-type impurities capable of imparting p-type conductivity, such as Al (aluminum). The concentration of the p-type impurity contained in the fourth impurity region 24 may be higher than the concentration of the p-type impurity contained in the second impurity region 23.

[0026] The gate insulating film 6 is provided on the element layer 40. The gate insulating film 6 is made of, for example, silicon dioxide. The gate insulating film 6 is in contact with, for example, each of the first impurity region 14, the second impurity region 23, and the third impurity region 30. In the second impurity region 23 in contact with the gate insulating film 6, a channel can be formed.

[0027] The gate electrode 63 is provided on the gate insulating film 6. The gate electrode 63 is in contact with the gate insulating film 6. The gate electrode 63 is made of a conductor such as polysilicon doped with impurities.

[0028] The second electrode 62 is, for example, a source electrode. The second electrode 62 is provided on the element layer 40. The second electrode 62 is in contact with the third impurity region 30 and the fourth impurity region 24. The second electrode 62 may cover the isolation insulating film 64.

[0029] The isolation insulating film 64 is provided so as to cover the gate electrode 63. The isolation insulating film 64 is in contact with each of the gate electrode 63 and the gate insulating film 6. The isolation insulating film 64 is made of, for example, an NSG (None-doped Silicate Glass) film or a PSG (Phosphorus Silicate Glass) film. The isolation insulating film 64 electrically insulates the gate electrode 63 from the second electrode 62.

[0030] The first electrode 61 is, for example, a drain electrode. The first electrode 61 is provided on a second main surface 2 of the substrate 90. The second main surface 2 has a third region 93 and a fourth region 94. The third region 93 is located opposite the first region 91. The fourth region 94 is located opposite the second region 92. The first electrode 61 is in contact with each of the third region 93 and the fourth region 94.

[0031] The peripheral region OR is provided on the substrate 90. The peripheral region OR is on the second area 92 of the first main surface 1. The peripheral region OR surrounds the active region IR in a plan view. The plan view is a field of view in which the silicon carbide semiconductor device 100 is viewed in a direction perpendicular to the first main surface 1. The peripheral region OR mainly includes a second buffer layer 52, a second superjunction layer 20, a termination layer 50, and an insulating layer 7.

[0032] The second buffer layer 52 is located between the second superjunction layer 20 and the substrate 90. The second buffer layer 52 has, for example, an n-type (first conductivity type). The second buffer layer 52 contains an n-type impurity capable of imparting an n-type conductivity, such as N (nitrogen). The second buffer layer 52 is in contact with a second region 92 of the first main surface 1. The second buffer layer 52 is electrically connected to the first buffer layer 12.

[0033] The second superjunction layer 20 is provided above the substrate 90. The second superjunction layer 20 is in contact with, for example, the second buffer layer 52. The second superjunction layer 20 has third regions 43 and fourth regions 44 alternately arranged. The third regions 43 and the fourth regions 44 are alternately arranged, for example, along a direction parallel to the first main surface 1. From another perspective, the third regions 43 and the fourth regions 44 are alternately arranged, for example, along a direction intersecting the thickness direction of the substrate 90. The arrangement direction of the third regions 43 and the fourth regions 44 is the same as the arrangement direction of the first regions 41 and the second regions 42.

[0034] The third region 43 has an n-type (first conductivity type). The third region 43 contains an n-type impurity capable of imparting an n-type conductivity, such as N (nitrogen). The fourth region 44 has a p-type (second conductivity type). The fourth region 44 contains a p-type impurity capable of imparting a p-type conductivity, such as Al (aluminum).

[0035] The termination layer 50 is provided on and in contact with the second superjunction layer 20. The termination layer 50 has a fifth region 45 and a sixth region 46 arranged alternately. The fifth region 45 is provided corresponding to the third region 43, and the sixth region 46 is provided corresponding to the fourth region 44. The fifth region 45 is in contact with the third region 43. The sixth region 46 is in contact with the fourth region 44. The fifth region 45 and the sixth region 46 are arranged alternately along a direction parallel to the first main surface 1, for example. From another perspective, the fifth region 45 and the sixth region 46 are arranged alternately along a direction intersecting the thickness direction of the substrate 90, for example.

[0036] Each of the fifth region 45 and the sixth region 46 has a p-type (second conductivity type). Each of the fifth region 45 and the sixth region 46 contains a p-type impurity capable of imparting a p-type, such as Al (aluminum). The impurity concentration of the sixth region 46 is greater than the impurity concentration of the fifth region 45 and is 68 times or less than the impurity concentration of the fifth region 45. The lower limit of the impurity concentration of the sixth region 46 is not particularly limited, but may be, for example, 1.09 times or more, or 1.58 times or more than the impurity concentration of the fifth region 45. The upper limit of the impurity region of the sixth region 46 is not particularly limited, but may be, for example, 20 times or less, 33.3 times or less, or 55 times or less than the impurity concentration of the fifth region 45.

[0037] The fifth region 45 is formed, for example, by implanting a p-type impurity into the third region 43. Similarly, the sixth region 46 is formed, for example, by implanting a p-type impurity into the fourth region 44. In this case, the impurity concentration of the sixth region 46 is greater than the impurity concentration of the fourth region 44. The absolute value of the difference between the impurity concentrations of the fifth region 45 and the sixth region 46 may be substantially equal to the sum of the impurity concentrations of the third region 43 and the fourth region 44. Specifically, the value obtained by dividing the absolute value of the difference between the impurity concentrations of the fifth region 45 and the sixth region 46 by the sum of the impurity concentrations of the third region 43 and the fourth region 44 is, for example, 0.8 or more and 1.2 or less.

[0038] The impurity concentration of the first region 41 is substantially the same as the impurity concentration of the third region 43. The impurity concentrations of the first region 41 and the third region 43 are, for example, 3×10 16 cm -3 5×10 or more 17 cm -3 The lower limit of the impurity concentration of each of the first region 41 and the third region 43 is not particularly limited, but may be, for example, 4×10 16 cm -3 May be more than 5 x 10 16 cm -3The upper limit of the impurity concentration of each of the first region 41 and the third region 43 is not particularly limited, but may be, for example, 4×10 17 cm -3 It may be less than or equal to 3 x 10 17 cm -3 It may be the following.

[0039] The impurity concentration of the second region 42 is substantially the same as the impurity concentration of the fourth region 44. The impurity concentrations of each of the second region 42 and the fourth region 44 are, for example, 3×10 16 cm -3 5×10 or more 17 cm -3 The lower limit of the impurity concentration of each of the second region 42 and the fourth region 44 is not particularly limited, but may be, for example, 4×10 16 cm -3 It may be more than 5 x 10 16 cm -3 The upper limit of the impurity concentration of each of the second region 42 and the fourth region 44 is not particularly limited, but may be, for example, 4×10 17 cm -3 It may be less than or equal to 3 x 10 17 cm -3 It may be the following.

[0040] The insulating layer 7 is provided on the termination layer 50. The termination layer 50 has a third main surface 3. The third main surface 3 is in contact with the insulating layer 7. The third main surface 3 has a first upper end surface 3a and a second upper end surface 3b. The insulating layer 7 is in contact with each of the upper end surface (first upper end surface 3a) of the fifth region 45 and the upper end surface (second upper end surface 3b) of the sixth region 46. The fifth region 45 is located between the third region 43 and the insulating layer 7. The sixth region 46 is located between the fourth region 44 and the insulating layer 7. The insulating layer 7 is composed of an oxide film such as a low temperature oxide (LTO) film, a high temperature oxide (HTO) film, an NSG film, or a PSG film. A thermal oxide film may be formed on the base of the insulating layer 7.

[0041] 1, a first distance D1 between an upper end surface (fourth main surface 4) of the element layer 40 and an interface (first interface 81) between the element layer 40 and the first superjunction layer 10 is greater than a second distance D2 between an upper end surface (third main surface 3) of the termination layer 50 and an interface (second interface 82) between the termination layer 50 and the second superjunction layer 20. A value obtained by subtracting the second distance D2 from the first distance D1 may be 0.5 μm or more, or may be 1 μm or more. A thickness (fourth thickness T4) of the second superjunction layer 20 is greater than a thickness (third thickness T3) of the first superjunction layer 10.

[0042] Second embodiment Next, the configuration of the silicon carbide semiconductor device 100 according to the second embodiment will be described. The configuration of the silicon carbide semiconductor device 100 according to the second embodiment differs from that of the silicon carbide semiconductor device 100 according to the first embodiment mainly in that the peripheral region OR has a plurality of peripheral region portions, and is otherwise similar to that of the silicon carbide semiconductor device 100 according to the first embodiment. Below, the configuration different from that of the silicon carbide semiconductor device 100 according to the first embodiment will be mainly described.

[0043] FIG. 2 is a partial cross-sectional schematic diagram showing a configuration of a silicon carbide semiconductor device 100 according to a second embodiment. As shown in FIG. 2, in a plan view, the peripheral region OR surrounds the active region IR. The peripheral region OR has a first peripheral region portion OR1, a second peripheral region portion OR2, and a third peripheral region portion OR3. In a plan view, the first peripheral region portion OR1 surrounds the active region IR. The first peripheral region portion OR1 is continuous with the active region IR. In a plan view, the second peripheral region portion OR2 surrounds the first peripheral region portion OR1. The second peripheral region portion OR2 is continuous with the first peripheral region portion OR1.

[0044] The silicon carbide semiconductor device 100 has a first superjunction layer 10 and a second superjunction layer 20. The first superjunction layer 10 has a first region 41 and a second region 42. The first regions 41 and the second regions 42 are alternately arranged along a first direction 101. In a plan view, the longitudinal direction of each of the first region 41 and the second region 42 is the second direction 102. In a plan view, the lateral direction of each of the first region 41 and the second region 42 is the first direction 101.

[0045] Each of the first direction 101 and the second direction 102 is parallel to the first main surface 1. The first direction 101 is a direction perpendicular to the second direction 102. The first direction 101 is, for example, the <1-100> direction. The second direction 102 is, for example, the <11-20> direction. The first direction 101 may be, for example, the <1-100> direction projected onto the first main surface 1. The second direction 102 may be, for example, the <11-20> direction projected onto the first main surface 1.

[0046] The second superjunction layer 20 has a third region 43 and a fourth region 44. The third region 43 and the fourth region 44 are alternately arranged along a first direction 101. In a plan view, the longitudinal direction of each of the third region 43 and the fourth region 44 is the second direction 102. In a plan view, the lateral direction of each of the third region 43 and the fourth region 44 is the first direction 101.

[0047] In a plan view, the third peripheral region portion OR3 surrounds the second peripheral region portion OR2. The third peripheral region portion OR3 is continuous with the second peripheral region portion OR2. The third peripheral region portion OR3 has, for example, a channel stopper 66. In a plan view, the channel stopper 66 surrounds the second peripheral region portion OR2. The channel stopper 66 has, for example, an n-type (first conductivity type). The impurity concentration of the channel stopper 66 is, for example, higher than the impurity concentrations of the first region 41 and the third region 43.

[0048] 2, the channel stopper 66 has a first channel stopper region 66a extending along a first direction 101 and a second channel stopper region 66b extending along a second direction 102. The second channel stopper region 66b may be provided along the third region 43. The first channel stopper region 66a may cross the third region 43 and the fourth region 44. The first channel stopper region 66a may cross the first region 41 and the second region 42.

[0049] FIG. 3 is a schematic vertical cross-sectional view taken along line III-III in FIG. 2. As shown in FIG. 3, the first peripheral region portion OR1 has a first termination layer 56. The first termination layer 56 has a fifth region 45 and a sixth region 46. The second peripheral region portion OR2 has a second termination layer 55. The second termination layer 55 has a seventh region 47 and an eighth region 48. The seventh region 47 corresponds to the third region 43, and the eighth region 48 corresponds to the fourth region 44. The seventh region 47 is in contact with the third region 43. The eighth region 48 is in contact with the fourth region 44. The insulating layer 7 is in contact with, for example, the first termination layer 56, the second termination layer 55, and the channel stopper 66.

[0050] The impurity concentration of second termination layer 55 may be lower than the impurity concentration of first termination layer 56. Specifically, the impurity concentration of seventh region 47 may be lower than the impurity concentration of fifth region 45. Similarly, the impurity concentration of eighth region 48 may be lower than the impurity concentration of sixth region 46. Although a two-stage JTE (Junction Termination Extension) having two termination layers has been described above, a three-stage JTE having three termination layers may also be adopted.

[0051] 3, in a cross section that crosses the first region 41 and the second region 42, the height of the first region 41 in the third direction 103 may be greater than the width of the first region 41 in the first direction 101. Similarly, in a cross section that crosses the first region 41 and the second region 42, the height of the second region 42 in the third direction 103 may be greater than the width of the second region 42 in the first direction 101. The third direction 103 is a direction perpendicular to each of the first direction 101 and the second direction 102. The third direction 103 is, for example, <0001> The third direction 103 is, for example, <0001> The direction may be inclined with respect to the direction.

[0052] 3, in a cross section transverse to the third region 43 and the fourth region 44, the height of the third region 43 in the third direction 103 may be greater than the width of the third region 43 in the first direction 101. Similarly, in a cross section transverse to the third region 43 and the fourth region 44, the height of the fourth region 44 in the third direction 103 may be greater than the width of the fourth region 44 in the first direction 101.

[0053] In a cross section that crosses the first region 41 and the third region 43, the height of the third region 43 in the third direction 103 may be greater than the height of the first region 41 in the third direction 103. Similarly, in a cross section that crosses the second region 42 and the fourth region 44, the height of the fourth region 44 in the third direction 103 may be greater than the height of the second region 42 in the third direction 103.

[0054] 3, in a cross-sectional view, a plurality of gate electrodes 63 may be arranged along the first direction 101. Similarly, a plurality of first impurity regions 14, second impurity regions 23, third impurity regions 30 and fourth impurity regions 24 may be arranged along the first direction 101. The fourth impurity region 24 may penetrate the third impurity region 30 and be in contact with the first region 41.

[0055] 4 is a schematic vertical cross-sectional view taken along line IV-IV in FIG. 2. As shown in FIG. 4, the peripheral region OR has a plurality of JTE regions. The first peripheral region portion OR1 has a first JTE region 53. The second peripheral region portion OR2 has a second JTE region 54. The second JTE region 54 is continuous with the first JTE region 53. Each of the first JTE region 53 and the second JTE region 54 has, for example, p-type. The impurity concentration of the second JTE region 54 is, for example, smaller than the impurity concentration of the first JTE region 53. The value obtained by dividing the impurity concentration of the second JTE region 54 by the impurity concentration of the first JTE region 53 is, for example, 0.5.

[0056] As shown in FIG. 4, the first region 41 may extend in the peripheral region OR along the second direction 102. In the peripheral region OR, the first region 41 may be in contact with the first JTE region 53, the second JTE region 54, and the channel stopper 66. In the present embodiment, the peripheral region OR has two JTE regions, but the number of JTE regions is not limited to two. The peripheral region OR may have, for example, three or more JTE regions. In this case, the impurity concentration of the JTE region may decrease outward as viewed from the active region IR.

[0057] Third embodiment Next, the configuration of the silicon carbide semiconductor device 100 according to the third embodiment will be described. The configuration of the silicon carbide semiconductor device 100 according to the third embodiment differs from that of the silicon carbide semiconductor device 100 according to the first embodiment mainly in that the active region IR is a trench MOSFET, and is otherwise similar to that of the silicon carbide semiconductor device 100 according to the first embodiment. The following description will focus on the configuration that differs from that of the silicon carbide semiconductor device 100 according to the first embodiment.

[0058] Fig. 5 is a schematic vertical cross-sectional view showing a configuration of a silicon carbide semiconductor device 100 according to the third embodiment. As shown in Fig. 5, a trench 5 is provided in an element layer 40. The shape of the trench 5 is, for example, V-shaped. The trench 5 is defined by a side surface 8 and a bottom 9. The side surface 8 is formed of each of a first impurity region 14, a second impurity region 23 and a third impurity region 30. The bottom 9 is continuous with the side surface 8. The bottom 9 is formed of the first impurity region 14.

[0059] At least a portion of the gate insulating film 6 is provided, for example, inside the trench 5. The gate insulating film 6 contacts the first impurity region 14, the second impurity region 23, and the third impurity region 30 at a side surface 8. The gate insulating film 6 contacts the first impurity region 14 at a bottom 9. At least a portion of the gate electrode 63 is provided, for example, inside the trench 5.

[0060] (Fourth embodiment) Next, the configuration of the silicon carbide semiconductor device 100 according to the fourth embodiment will be described. The configuration of the silicon carbide semiconductor device 100 according to the fourth embodiment differs from that of the silicon carbide semiconductor device 100 according to the second embodiment mainly in that the active region IR is a trench MOSFET, and is otherwise similar to that of the silicon carbide semiconductor device 100 according to the second embodiment. The following description will focus on the configuration that differs from that of the silicon carbide semiconductor device 100 according to the second embodiment.

[0061] FIG. 6 is a partial cross-sectional schematic diagram showing a configuration of a silicon carbide semiconductor device 100 according to a fourth embodiment. As shown in FIG. 6, in a plan view, the peripheral region OR surrounds the active region IR. The peripheral region OR has a first peripheral region portion OR1, a second peripheral region portion OR2, and a third peripheral region portion OR3. The channel stopper 66 has a first channel stopper region 66a extending along a first direction 101 and a second channel stopper region 66b extending along a second direction 102. The second channel stopper region 66b may be provided along the fourth region 44. The first channel stopper region 66a may cross the third region 43 and the fourth region 44. The first channel stopper region 66a may cross the first region 41 and the second region 42.

[0062] Fig. 7 is a schematic vertical cross-sectional view taken along line VII-VII in Fig. 6. As shown in Fig. 7, a trench 5 is provided in the element layer 40. The trench 5 is defined by a side surface 8 and a bottom 9. The side surface 8 is composed of the first impurity region 14, the second impurity region 23, and the third impurity region 30. The bottom 9 is continuous with the side surface 8. The bottom 9 is composed of the first impurity region 14.

[0063] At least a portion of the gate insulating film 6 is provided, for example, inside the trench 5. The gate insulating film 6 contacts the first impurity region 14, the second impurity region 23, and the third impurity region 30 at its side surface 8. The gate insulating film 6 contacts the first impurity region at its bottom portion 9. At least a portion of the gate electrode 63 is provided, for example, inside the trench 5. At least a portion of the isolation insulating film 64 is provided, for example, inside the trench 5.

[0064] The active region IR may have, for example, a sixth impurity region 67. The sixth impurity region 67 has, for example, a p-type (second conductivity type). The sixth impurity region 67 faces the bottom 9 of the trench 5. The sixth impurity region 67 is in contact with, for example, the first region 41, the second region 42, and the first impurity region 14. The sixth impurity region 67 is located between the second region 42 and the first impurity region 14 in the third direction 103. In the first direction 101, the width of the sixth impurity region 67 may be larger than the width of the second region 42. In the first direction 101, the width of the sixth impurity region 67 may be larger than the width of the bottom 9 of the trench 5.

[0065] Fig. 8 is a schematic vertical cross-sectional view taken along line VIII-VIII in Fig. 6. As shown in Fig. 8, the sixth impurity region 67 may extend along the second direction 102. The width of the sixth impurity region 67 in the second direction 102 may be greater than the width of the sixth impurity region 67 in the first direction 101. Similarly, the first impurity region 14 may extend along the second direction 102. The width of the first impurity region 14 in the second direction 102 may be greater than the width of the first impurity region 14 in the first direction 101.

[0066] 8, the second region 42 may extend in the peripheral region OR along the second direction 102. In the peripheral region OR, the second region 42 may be in contact with the first JTE region 53, the second JTE region 54, and the channel stopper 66.

[0067] Fifth embodiment Next, the configuration of the silicon carbide semiconductor device 100 according to the fifth embodiment will be described. The configuration of the silicon carbide semiconductor device 100 according to the fifth embodiment differs from that of the silicon carbide semiconductor device 100 according to the first embodiment mainly in that the active region IR is a PN diode, and is otherwise similar to that of the silicon carbide semiconductor device 100 according to the first embodiment. The following description will focus on the configuration that differs from that of the silicon carbide semiconductor device 100 according to the first embodiment.

[0068] FIG. 9 is a schematic vertical cross-sectional view showing a configuration of a silicon carbide semiconductor device 100 according to a fifth embodiment. As shown in FIG. 9, the element layer 40 may be, for example, a rectifying element portion. The element layer 40 has, for example, p-type (second conductivity type). The second electrode 62 is in contact with the element layer 40. The second electrode 62 is provided on the element layer 40. The element layer 40 is provided on the first superjunction layer 10. The element layer 40 is in contact with, for example, each of the first region 41 and the second region 42. The first electrode 61 is, for example, a cathode electrode. The second electrode 62 is, for example, an anode electrode.

[0069] Sixth embodiment Next, the configuration of the silicon carbide semiconductor device 100 according to the sixth embodiment will be described. The configuration of the silicon carbide semiconductor device 100 according to the sixth embodiment is mainly different from the configuration of the silicon carbide semiconductor device 100 according to the third embodiment in that the first region 41 and the third region 43 each have a first portion 71 and a second portion 72, and the second region 42 and the fourth region 44 each have a third portion 73 and a fourth portion 74, and is otherwise similar to the configuration of the silicon carbide semiconductor device 100 according to the third embodiment. Hereinafter, the configuration different from the configuration of the silicon carbide semiconductor device 100 according to the third embodiment will be mainly described.

[0070] FIG. 10 is a schematic vertical cross-sectional view showing a configuration of a silicon carbide semiconductor device 100 according to a sixth embodiment. As shown in FIG. 10, each of the first region 41 and the third region 43 has a first portion 71 and a second portion 72. The second portion 72 is continuous with the first portion 71. The second portion 72 is located between the first portion 71 and the substrate 90. The first portion 71 may be in contact with the first impurity region 14. The first portion 71 may be in contact with the fifth region 45. The second portion 72 may be in contact with the first buffer layer 12. The second portion 72 may be in contact with the second buffer layer 52.

[0071] As shown in FIG. 10 , each of the second region 42 and the fourth region 44 has a third portion 73 and a fourth portion 74. The third portion 73 is in contact with the first portion 71. The fourth portion 74 is in contact with the second portion 72. The fourth portion 74 is continuous with the third portion 73. The fourth portion 74 is located between the third portion 73 and the substrate 90. The third portion 73 may be in contact with the first impurity region 14. The third portion 73 may be in contact with the sixth region 46. The fourth portion 74 may be in contact with the first buffer layer 12. The fourth portion 74 may be in contact with the second buffer layer 52.

[0072] The third portion 73 and the first portion 71 are adjacent to each other in the first direction 101. The third portion 73 and the first portion 71 are arranged alternately in the first direction 101. The fourth portion 74 and the second portion 72 are adjacent to each other in the first direction 101. The fourth portion 74 and the second portion 72 are arranged alternately in the first direction 101.

[0073] The impurity concentration in the third portion 73 may be higher than the impurity concentration in the fourth portion 74. The impurity concentration in the first portion 71 is substantially the same as the impurity concentration in the second portion 72. The impurity concentration in the first portion 71 is substantially the same as the impurity concentration in the third portion 73. The impurity concentration in the fourth portion 74 may be lower than the impurity concentration in the second portion 72.

[0074] The impurity concentration of each of the first portion 71 and the third portion 73 is, for example, 3×10 16 cm -3 5×10 or more 17 cm -3 The lower limit of the impurity concentration of each of the first portion 71 and the third portion 73 is not particularly limited, but may be, for example, 4×10 16 cm -3 May be more than 5 x 10 16 cm -3 The upper limit of the impurity concentration of each of the first portion 71 and the third portion 73 is not particularly limited, but may be, for example, 4×10 17 cm -3It may be less than or equal to 3 x 10 17 cm -3 It may be the following.

[0075] 10, in a cross section perpendicular to the second main surface 2 and parallel to the direction from the first region 41 to the second region 42, the width of the second portion 72 is larger than the width of the first portion 71 (first width W1). The width of the second portion 72 may monotonically increase from the first portion 71 toward the first main surface 1. The width (second width W2) of the second portion 72 in contact with the buffer layer 49 is larger than the first width W1.

[0076] 10, in a cross section perpendicular to the second main surface 2 and parallel to the direction from the first region 41 to the second region 42, the width of the fourth portion 74 is smaller than the width of the third portion 73 (third width W3). The width of the fourth portion 74 may monotonically decrease from the third portion 73 toward the first main surface 1. The width (fourth width W4) of the fourth portion 74 in contact with the buffer layer 49 is smaller than the third width W3.

[0077] 10, the sum of the width (first width W1) of the first portion 71 and the width (third width W3) of the third portion 73 is, for example, 0.5 μm or more and 4 μm or less. The sum of the width (first width W1) of the first portion 71 and the width (third width W3) of the third portion 73 is the pitch P of each of the first superjunction layer 10 and the second superjunction layer 20. The height (third height) of each of the first region 41 and the second region 42 is, for example, 2 μm or more.

[0078] 10, in a cross section perpendicular to the second main surface 2 and parallel to the direction from the first region 41 to the second region 42, the width of the first portion 71 (first width W1) may be smaller than the height (first height T1) of the first portion 71. The height (first height T1) of the first portion 71 may be larger than the height (second height T2) of the second portion 72.

[0079] 10, in a cross section perpendicular to the second main surface 2 and parallel to the direction from the first region 41 to the second region 42, the width of the third portion 73 (third width W3) may be smaller than the height (first height T1) of the third portion 73. The height (first height T1) of the third portion 73 may be larger than the height (second height T2) of the fourth portion 74.

[0080] Next, a method for forming the superjunction layer will be described. First, a buffer layer 49 is formed on a substrate 90. The buffer layer 49 is formed, for example, by epitaxial growth. Next, a first region 41 and a third region 43 are formed on the buffer layer 49. The first region 41 and the third region 43 are formed, for example, by epitaxial growth. Each of the buffer layer 49, the first region 41, and the third region 43 has an n-type (first conductivity type). The impurity concentration of the buffer layer 49 may be the same as each of the impurity concentrations of the first region 41 and the third region 43, or may be lower than each of the impurity concentrations of the first region 41 and the third region 43. Next, a mask layer (not shown) is formed on the first region 41 and the third region 43.

[0081] Next, a channeling ion implantation process is performed. Specifically, in a state where a mask layer is disposed on the first region 41 and the third region 43, impurity ions capable of imparting p-type (second conductivity type), such as aluminum, are implanted into the first region 41 and the third region 43. The implantation energy is, for example, 960 keV. The implantation temperature is, for example, room temperature. As a result, the second region 42 is formed in a part of the first region 41. The second region 42 is provided so as to be spaced apart in the first direction 101. Similarly, the fourth region 44 is formed in a part of the third region 43. The fourth region 44 is provided so as to be spaced apart in the first direction 101. As a result, the first superjunction layer 10 in which the first region 41 and the second region 42 are alternately arranged, and the second superjunction layer 20 in which the third region 43 and the fourth region 44 are alternately arranged are formed (see FIG. 10).

[0082] In the channeling ion implantation process, the crystal axis of silicon carbide is <0001> The impurity ions are implanted in a direction substantially parallel to the direction of the impurity ions. <0001> The third direction 103 may be inclined at an angle of, for example, 0.5° or less with respect to the off direction. Specifically, the implantation direction of the impurity ions may be a direction in which the third direction 103 is inclined toward the off direction. The off direction may be, for example, the first direction 101 or the second direction 102. This reduces scattering between the impurity ions and the silicon carbide, thereby making it possible to implant the impurity ions deeply. As a result, the second region 42 and the fourth region 44 are formed (see FIG. 10 ). Each of the second region 42 and the fourth region 44 has a third portion 73 and a fourth portion 74. The width of the fourth portion 74 is formed to be smaller than the width of the third portion 73.

[0083] Next, a method for measuring the p-type impurity concentration and the n-type impurity concentration in each impurity region will be described.

[0084] The concentration of p-type impurities and the concentration of n-type impurities in each impurity region can be measured using SIMS (Secondary Ion Mass Spectrometry). The measurement device is, for example, a secondary ion mass spectrometer manufactured by Cameca. The measurement pitch is, for example, 0.01 μm. When the n-type impurity to be detected is nitrogen, the primary ion beam is cesium (Cs). The primary ion energy is 14.5 keV. The secondary ion polarity is negative. When the p-type impurity to be detected is aluminum or boron, the primary ion beam is oxygen (O2). The primary ion energy is 8 keV. The secondary ion polarity is positive.

[0085] Next, a method for distinguishing between p-type and n-type regions will be described. A scanning capacitance microscope (SCM) is used to distinguish between p-type and n-type regions. The measuring device is, for example, a NanoScope IV manufactured by Bruker AXS. The SCM is a method for visualizing the carrier concentration distribution in a semiconductor. Specifically, a metal-coated silicon probe is used to scan the surface of a sample. At that time, a high-frequency voltage is applied to the sample. The majority carriers are excited to modulate the capacitance of the system. The frequency of the high-frequency voltage applied to the sample is 100 kHz, and the voltage is 4.0 V. A scanning nonlinear dielectric microscopy (SNDM) or scanning microwave microscopy (SMM) may be used to distinguish between p-type and n-type regions.

[0086] In the above description, the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. The impurity concentration of an impurity region having n-type is the concentration of n-type impurities. The impurity concentration of an impurity region having p-type is the concentration of p-type impurities.

[0087] Next, the effects of silicon carbide semiconductor device 100 according to the above embodiment will be described. Silicon has a lower dielectric breakdown strength than silicon dioxide. Therefore, in the case of a Si-MOSFET, reliability can be improved by designing the MOSFET so that the electric field strength in the peripheral region OR is higher than the electric field strength in the active region IR. On the other hand, silicon carbide has a higher dielectric breakdown strength than silicon dioxide. Therefore, in the case of a SiC-MOSFET, if the MOSFET is designed so that the electric field strength in the peripheral region OR is higher than the electric field strength in the active region IR, the insulating layer 7 breaks down before the semiconductor layer, making it difficult to sufficiently improve reliability.

[0088] The inventors therefore came up with a design idea of ​​suppressing the concentration of the electric field at the interface between the semiconductor layer and the insulating layer 7 by lowering the electric field strength in the peripheral region OR, and actively generating an avalanche in the active region IR by increasing the electric field strength in the active region IR.

[0089] The inventors have conducted extensive research into a specific structure for realizing the above-mentioned design concept, and have found that the reliability of silicon carbide semiconductor device 100 can be improved by configuring silicon carbide semiconductor device 100 as follows, compared to a structure in which an electric field is concentrated in the peripheral region OR.

[0090] Specifically, the silicon carbide semiconductor device 100 according to the present disclosure includes a substrate 90, an active region IR, a peripheral region OR, and a first electrode 61. The substrate 90 is made of a silicon carbide semiconductor of a first conductivity type. The active region IR is provided in a part of a first main surface 1 of the substrate 90. The peripheral region OR is provided on the substrate 90 and surrounds the active region IR in a plan view. The first electrode 61 is provided on a second main surface 2 facing the first main surface 1 of the substrate 90. The active region IR includes a first superjunction layer 10, an element layer 40, and a second electrode 62. The first superjunction layer 10 is provided above the substrate 90 and has first regions 41 of the first conductivity type and second regions 42 of the second conductivity type alternately. The element layer 40 is provided above the first superjunction layer 10. The second electrode 62 is provided on the element layer 40. The peripheral region OR includes a second superjunction layer 20, a termination layer 50, and an insulating layer 7. The second superjunction layer 20 is provided above the substrate 90, and has a third region 43 of a first conductivity type and a fourth region 44 of a second conductivity type alternately. The termination layer 50 is provided on and in contact with the second superjunction layer 20, and has a fifth region 45 of a second conductivity type and a sixth region 46 of a second conductivity type alternately. The insulating layer 7 is in contact with each of the upper end surface of the fifth region 45 and the upper end surface of the sixth region 46. The fifth region 45 is provided corresponding to the third region 43, and the sixth region 46 is provided corresponding to the fourth region 44. The impurity concentration of the sixth region 46 is higher than the impurity concentration of the fifth region 45 and is 68 times or less than the impurity concentration of the fifth region 45. This can improve the reliability of the silicon carbide semiconductor device 100. EXAMPLES

[0091] A breakdown voltage simulation was performed to investigate the relationship between the impurity concentration of the sixth region 46 relative to the impurity concentration of the fifth region 45, and the reliability of the silicon carbide semiconductor device 100. First, a simulation model (1200V design element) with different impurity concentrations in the superjunction layer was created. As shown in Table 1, in the first simulation model (conditions 2 to 8), the impurity concentration in the superjunction layer (in other words, the impurity concentration of each of the third region 43 and the fourth region 44: see FIG. 1) was 1×10 17 cm -3 In the second simulation model (condition 1), the impurity concentration in the superjunction layer was 3×10 16 cm -3 The thickness of the superjunction layer was 7.5 μm. A p-type impurity having the same impurity concentration was added to each of the third region 43 and the fourth region 44 to form a fifth region 45 and a sixth region 46, respectively.

[0092] [Table 1]

[0093] As shown in Table 1, in the first simulation model, the value obtained by dividing the impurity concentration in the sixth region 46 by the impurity concentration in the fifth region 45 was in the range of 1.48 to 67.7. In the second simulation model, the value obtained by dividing the impurity concentration in the sixth region 46 by the impurity concentration in the fifth region 45 was 1.11.

[0094] Fig. 11 is a diagram showing the results of a breakdown voltage simulation. As shown in Fig. 11 and Table 1, it was shown that a high breakdown voltage of about 1.2 kV or more can be realized when the impurity concentration of the sixth region 46 is in the range of 1.11 times or more and 67.7 times or less than the impurity concentration of the fifth region 45. In particular, it was shown that a higher breakdown voltage can be realized when the impurity concentration of the sixth region 46 is in the range of more than 1.48 times and less than 33.3 times the impurity concentration of the fifth region 45.

[0095] The embodiments disclosed herein are illustrative in all respects and should not be considered as limiting. The scope of the present invention is defined by the claims, not the above description, and is intended to include the meaning equivalent to the claims and all modifications within the scope. [Explanation of symbols]

[0096] 1 first main surface, 2 second main surface, 3 third main surface, 3a first upper end surface, 3b second upper end surface, 4 fourth main surface, 5 trench, 6 gate insulating film, 7 insulating layer, 8 side surface, 9 bottom, 10 first superjunction layer, 11 first substrate portion, 12 first buffer layer, 14 first impurity region, 20 second superjunction layer, 23 second impurity region, 24 fourth impurity region, 30 third impurity region, 40 element layer, 41 first region, 42 second region, 43 third region, 44 fourth region, 45 fifth region, 46 sixth region, 47 seventh region, 48 eighth region, 49 buffer layer, 50 termination layer, 51 second substrate portion, 52 second buffer layer, 53 first JTE region, 54 second JTE region, 55 second termination layer, 56 first termination layer, 61 first electrode, 62 second electrode, 63 gate electrode, 64 isolation insulating film, 66 channel stopper, 66a first channel stopper region, 66b second channel stopper region, 67 sixth impurity region, 71 first portion, 72 second portion, 73 third portion, 74 fourth portion, 81 first boundary surface, 82 second boundary surface, 90 substrate, 91 first area, 92 second area, 93 third area, 94 fourth area, 100 silicon carbide semiconductor device, 101 first direction, 102 second direction, 103 third direction, D1 first distance, D2 second distance, IR active region, OR peripheral region, OR1 first peripheral region portion, OR2 second peripheral region portion, OR3 third peripheral region portion, P pitch, T1 first height, T2 second height, T3 third thickness, T4 fourth thickness, W1 first width, W2 second width, W3 third width, W4 fourth width.

Claims

1. a substrate made of a first conductivity type silicon carbide semiconductor; an active region provided on a portion of a first main surface of the substrate; a peripheral region provided on the substrate and surrounding the active region in a plan view; a first electrode provided on a second main surface of the substrate opposite to the first main surface, The active region comprises: a first superjunction layer provided above the substrate and having alternating first regions of the first conductivity type and second regions of the second conductivity type; an element layer provided above the first superjunction layer; a second electrode provided on the element layer; The peripheral region is a second superjunction layer provided above the substrate and having alternating third regions of the first conductivity type and fourth regions of the second conductivity type; a termination layer provided on and in contact with the second superjunction layer, the termination layer having alternating fifth regions of the second conductivity type and sixth regions of the second conductivity type; an insulating layer in contact with each of an upper end surface of the fifth region and an upper end surface of the sixth region; the fifth region is provided corresponding to the third region, and the sixth region is provided corresponding to the fourth region; the sixth region has an impurity concentration greater than the impurity concentration of the fifth region and is equal to or less than 68 times the impurity concentration of the fifth region; A silicon carbide semiconductor device, wherein a first distance between an upper end surface of the element layer and an interface between the element layer and the first superjunction layer is greater than a second distance between an upper end surface of the termination layer and an interface between the termination layer and the second superjunction layer.

2. a substrate made of a first conductivity type silicon carbide semiconductor; an active region provided on a portion of a first main surface of the substrate; a peripheral region provided on the substrate and surrounding the active region in a plan view; a first electrode provided on a second main surface of the substrate opposite to the first main surface, The active region comprises: a first superjunction layer provided above the substrate and having alternating first regions of the first conductivity type and second regions of the second conductivity type; an element layer provided above the first superjunction layer; a second electrode provided on the element layer; The peripheral region is a second superjunction layer provided above the substrate and having alternating third regions of the first conductivity type and fourth regions of the second conductivity type; a termination layer provided on and in contact with the second superjunction layer and having alternating fifth regions of the second conductivity type and sixth regions of the second conductivity type; an insulating layer in contact with each of an upper end surface of the fifth region and an upper end surface of the sixth region; the fifth region is provided corresponding to the third region, and the sixth region is provided corresponding to the fourth region; the sixth region has an impurity concentration greater than the impurity concentration of the fifth region and is equal to or less than 68 times the impurity concentration of the fifth region; each of the first region and the third region has a first portion and a second portion located between the first portion and the substrate; each of the second region and the fourth region has a third portion in contact with the first portion and a fourth portion in contact with the second portion and located between the third portion and the substrate; In a cross section perpendicular to the second main surface and parallel to a direction from the first region to the second region, The width of the second portion is greater than the width of the first portion, The width of the fourth portion is smaller than the width of the third portion, The width of the first portion is less than the height of the first portion; The width of the third portion is less than the height of the third portion; an impurity concentration of each of the first portion and the third portion is greater than an impurity concentration of each of the second portion and the fourth portion.

3. 3 . The silicon carbide semiconductor device according to claim 1 , wherein an impurity concentration of said sixth region is higher than an impurity concentration of said fourth region.

4. 4. The silicon carbide semiconductor device according to claim 1, wherein an absolute value of a difference between an impurity concentration of said fifth region and an impurity concentration of said sixth region is substantially equal to a sum of an impurity concentration of said third region and an impurity concentration of said fourth region.

5. The impurity concentration of each of the first region and the third region is 3×10 16 cm -3 Above 5 x 10 17 cm -3 is as follows: The impurity concentration of each of the second region and the fourth region is 3×10 16 cm -3 Above 5 x 10 17 cm -3 The silicon carbide semiconductor device according to claim 1 , wherein:

6. a first buffer layer of the first conductivity type is provided between the first superjunction layer and the substrate; The silicon carbide semiconductor device according to claim 1 , further comprising a second buffer layer of the first conductivity type provided between the second superjunction layer and the substrate.

7. the element layer includes a first impurity region of the first conductivity type, a second impurity region in contact with the first impurity region and having the second conductivity type, and a third impurity region separated from the first impurity region by the second impurity region and having the first conductivity type; the element layer is provided with a trench having a side surface formed by each of the first impurity region, the second impurity region, and the third impurity region, and a bottom portion continuing to the side surface and formed by the first impurity region; the first electrode is a source electrode and the second electrode is a drain electrode; The silicon carbide semiconductor device according to claim 1 , further comprising a gate electrode provided inside said trench.

8. 8. The silicon carbide semiconductor device according to claim 1, wherein the first main surface is a {0001} plane or a plane inclined at an angle of 8° or less with respect to the {0001} plane.

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