Solid-state imaging device, driving method for solid-state imaging device, and electronic device

Abstract

To provide a solid-state imaging device, a method of driving the same, and electronic equipment capable of reading out a small signal at low illuminance with low noise while maintaining sensitivity and the number of saturated charges, and of reducing a pixel size.SOLUTION: In a solid-state imaging device 10, a pixel circuit 200 has a reading pixel 210, a comparator 220, and a selection counter circuit 230. The reading pixel 210 includes an overflow path to a floating diffusion FD11, performs photoelectric conversion with a photodiode PD11, and reads out a signal corresponding to an illuminance condition of incident light. The comparator 220 compares a voltage signal read out from the reading pixel 210 with a reference signal Vref, and outputs a signal depending on the comparison result. The selection counter circuit 230 includes a selection circuit that selects any one of an external clock and comparator output, and a counter circuit that counts output from the selection circuit.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a solid-state imaging device, a driving method for a solid-state imaging device, and an electronic device. [Background technology]

[0002] 2. Description of the Related Art Complementary Metal Oxide Semiconductor (CMOS) image sensors are in practical use as solid-state imaging devices (image sensors) that use photoelectric conversion elements that detect light and generate electric charges. CMOS image sensors are widely used as part of various electronic devices, such as digital cameras, video cameras, surveillance cameras, medical endoscopes, personal computers (PCs), and portable terminal devices (mobile devices) such as mobile phones.

[0003] CMOS image sensors have a photodiode (photoelectric conversion element) and a floating diffusion (FD) amplifier with a floating diffusion layer for each pixel, and the mainstream readout method is the column-parallel output type, which selects a row in the pixel array and reads out the pixels simultaneously in the column output direction.

[0004] Furthermore, a wide variety of pixel signal readout (output) circuits have been proposed for column-parallel output CMOS image sensors. Among these, one of the most advanced circuits is a circuit that includes an analog-to-digital converter (ADC) for each column and extracts pixel signals as digital signals (see, for example, Patent Documents 1 and 2).

[0005] In this CMOS image sensor with column-parallel ADC (column AD type CMOS image sensor), the comparator compares the so-called RAMP wave with the pixel signal (voltage signal), and performs AD conversion by performing digital CDS in the downstream counter.

[0006] However, although this type of CMOS image sensor is capable of high-speed signal transfer, it has the disadvantage that it cannot perform global shutter readout.

[0007] In response to this, a digital pixel sensor has been proposed that places an ADC (and even a memory section) including a comparator in each pixel, making it possible to realize a global shutter that starts and ends exposure at the same timing for all pixels in the pixel array section (see, for example, Patent Documents 3 and 4).

[0008] In a CMOS image sensor equipped with the conventional digital pixel sensor described above, it is possible to realize a global shutter function, and by arranging an ADC including a comparator in each pixel, it is possible to achieve a wide dynamic range by using a specified readout mode.

[0009] Known methods for expanding the dynamic range include, for example, reading out two types of signals with different accumulation times from the same pixel of an image sensor and combining these two types of signals to expand the dynamic range, and combining a signal with a small dynamic range from a high-sensitivity pixel with a signal with a low-sensitivity pixel that has an expanded dynamic range.

[0010] Patent document 5 presents a unit pixel structure for infrared imaging that has two input stages covering both low and high light levels and an internal automatic input selection circuit to extend the dynamic range. Patent Document 5 describes a technique in which a pulse frequency modulation (PFM) ADC is applied to a unit pixel as a feasible digital implementation.

[0011] Moreover, Patent Document 6 describes a digital readout pixel circuit equipped with a PFM function and an extended counter that achieves excellent quantization noise performance.

[0012] Here, the basic configuration and functions of the PFM will be described with reference to FIGS. FIG. 1 is a diagram showing a first configuration example of a digital readout pixel circuit having a PFM function. FIG. 2 is a diagram showing a second configuration example of a digital readout pixel circuit having a PFM function.

[0013] The pixel circuit 1 in FIG. 1 includes a photodiode PD1, a reset transistor RST-Tr, a comparator 2, and a counter 3.

[0014] In the pixel circuit 1, a comparator 2 compares the voltage of a charge storage node ND1 of the photodiode PD1 with a reference voltage Vref1 (=VSA1) that corresponds to a saturation voltage VSA1 of the photodiode PD1. As a result of the comparison, when the node voltage ND1 reaches the saturation voltage VSA1, the output of the comparator 2 is fed back to the gate of the reset transistor RST-Tr as a feedback reset signal FRST, causing the reset transistor RST-Tr to enter a conductive state. That is, the charge stored in the photodiode PD1 is reset by the feedback reset operation. The number of times the photodiode PD1 is reset is counted by the counter 3.

[0015] In the pixel circuit 1A in FIG. 2, a transfer transistor TG-Tr whose conduction state is controlled by a control signal TG is connected between a charge storage node ND1 of a photodiode PD1 and a floating diffusion FD1 serving as an output node. In addition, in the pixel circuit 1A, a logic circuit 4 is arranged in the feedback path of the feedback reset signal FRST, and delay circuits 5-1 and 5-2 are arranged on the output side of the comparator 2 and the input side of the logic circuit 4 to take into account the delay of the logic circuit 4.

[0016] In the pixel circuit 1A, the transfer transistor TG-Tr is controlled to a conductive state (on state) during an exposure period, and is controlled to a non-conductive state (off state) during the reset phase of the floating diffusion FD1. [Prior art documents] [Patent documents]

[0017] [Patent Document 1] JP 2005-278135 A [Patent Document 2] JP 2005-295346 A [Patent Document 3] US 7164114 B2 FIG, 4 [Patent Document 4] US 2010 / 0181464 A1 [Patent Document 5] US 9324745 B2 [Patent Document 6] US 9197834 B2 Summary of the Invention [Problem to be solved by the invention]

[0018] However, the pixel circuits 1 and 1A in FIGS. 1 and 2 described above have the following disadvantages.

[0019] In the pixel circuit 1 of FIG. 1, since the transfer transistor TG-Tr is not included, the dark current of the photodiode PD1 becomes a major problem, and it is difficult to read out a small signal from the photodiode PD1 under low illuminance conditions with the above-described operation.

[0020] 2, the pixel circuit 1A includes a transfer transistor TG-Tr, but the dark current of the photodiode PD1 at the silicon interface below the transfer transistor TG-Tr remains a significant problem, and it is difficult to read out a small signal from the photodiode PD1 under low illumination with the above-mentioned operation. Furthermore, since the pixel circuit 1A includes the logic circuit (NAND, NOR) 4 that controls the transfer transistor TG-Tr, it is difficult to reduce the pixel size.

[0021] The present invention aims to provide a solid-state imaging device that is capable of reading out small signals under low illuminance with low noise while maintaining sensitivity and saturation charge number, and that also enables pixel size to be reduced, a method for driving a solid-state imaging device, and electronic equipment. [Means for solving the problem]

[0022] A solid-state imaging device according to a first aspect of the present invention has a readout pixel capable of performing photoelectric conversion and reading out a signal corresponding to an illuminance condition of incident light, a comparator that compares a voltage signal read out from the readout pixel with a reference signal and outputs a comparison result signal corresponding to the comparison result, a selection circuit capable of selecting either an external clock or an output from the comparator, and a selection counter circuit including a counter circuit that counts outputs from the selection circuit, wherein the readout pixel has a photoelectric conversion element that accumulates a charge corresponding to an amount of incident light during an exposure period, a transfer element that is held in a non-conductive state during the exposure period and held in a conductive state during a transfer period to transfer the charge accumulated in the photoelectric conversion element, a floating diffusion that holds the charge transferred by the transfer element so as to be read out as a voltage signal, and a reset circuit that discharges the accumulated charge in the floating diffusion. and an overflow path capable of overflowing the charge overflowing from the photoelectric conversion element toward the floating diffusion region, and the readout pixel, the comparator, the selection circuit, and the counter circuit perform a pulse frequency modulation (PFM) mode operation in which, under high illuminance conditions, when a voltage signal corresponding to the held charge of the floating diffusion reaches the reference voltage, the floating diffusion is self-reset by a feedback reset operation of the comparison result signal of the comparator, and the reset frequency of the floating diffusion is counted by the selection counter circuit in response to the comparison result signal, and under low illuminance conditions, a double sampling readout mode operation is performed using the accumulated charge and overflow charge of the photoelectric conversion element.

[0023] A second aspect of the present invention is a method for manufacturing a semiconductor device comprising: a readout pixel capable of performing photoelectric conversion and reading out a signal corresponding to an illuminance condition of incident light; a comparator that compares a voltage signal read out from the readout pixel with a reference signal and outputs a comparison result signal corresponding to the comparison result; a selection circuit that can select either an external clock or an output from the comparator; and a selection counter circuit including a counter circuit that counts outputs from the selection circuit, wherein the readout pixel includes a photoelectric conversion element that accumulates a charge corresponding to an amount of incident light during an exposure period; a transfer element that is held in a non-conductive state during the exposure period and in a conductive state during a transfer period and transfers the charge accumulated in the photoelectric conversion element; a floating diffusion that holds the charge transferred by the transfer element so as to be read out as a voltage signal; and a drain electrode that drains the accumulated charge in the floating diffusion. a reset element capable of performing a reset process to output a reset signal to the photoelectric conversion element and an overflow path capable of overflowing the charge overflowing from the photoelectric conversion element toward the floating diffusion region, wherein under high illuminance conditions, when a voltage signal corresponding to the charge held in the floating diffusion reaches the reference voltage, the floating diffusion is self-reset by a feedback reset operation of a comparison result signal of the comparator, and a pulse frequency modulation (PFM) mode operation is performed in which the reset frequency of the floating diffusion is counted by the selection counter circuit in response to the comparison result signal, and under low illuminance conditions, a double sampling readout mode operation is performed using the accumulated charge and overflow charge of the photoelectric conversion element.

[0024] An electronic device according to a third aspect of the present invention comprises a solid-state imaging device and an optical system for forming an image of a subject on the solid-state imaging device, the solid-state imaging device comprising: a readout pixel capable of performing photoelectric conversion and reading out a signal corresponding to an illuminance condition of incident light; a comparator for comparing a voltage signal read out from the readout pixel with a reference signal and outputting a comparison result signal corresponding to the comparison result; a selection circuit capable of selecting either an external clock or an output from the comparator; and a selection counter circuit including a counter circuit for counting outputs from the selection circuit, the readout pixel comprising: a photoelectric conversion element for accumulating a charge corresponding to an amount of incident light during an exposure period; a transfer element that is held in a non-conductive state during the exposure period and held in a conductive state during a transfer period to transfer the charge accumulated in the photoelectric conversion element; a floating diffusion for holding the charge transferred by the transfer element so as to be read out as a voltage signal; and The pixel includes at least one reset element capable of performing a reset process to drain the accumulated charge in the diffusion, and an overflow path capable of overflowing the charge overflowing from the photoelectric conversion element toward the floating diffusion region, and the readout pixel, the comparator, the selection circuit, and the counter circuit perform a pulse frequency modulation (PFM) mode operation in which, under high illuminance conditions, when a voltage signal corresponding to the held charge in the floating diffusion reaches the reference voltage, the floating diffusion is self-reset by a feedback reset operation of the comparison result signal of the comparator, and the reset frequency of the floating diffusion is counted by the selection counter circuit in response to the comparison result signal, and under low illuminance conditions, a double sampling readout mode operation is performed using the accumulated charge and overflow charge of the photoelectric conversion element. Effect of the Invention

[0025] According to the present invention, it is possible to read out small signals under low illuminance with low noise while maintaining the sensitivity and the number of saturation charges, and furthermore it is possible to miniaturize the pixel size. [Brief description of the drawings]

[0026] [Figure 1] FIG. 2 is a diagram showing a first configuration example of a digital readout pixel circuit having a PFM function. [Diagram 2] FIG. 13 is a diagram showing a second configuration example of a digital readout pixel circuit having a PFM function. [Diagram 3] 1 is a block diagram showing an example of the configuration of a solid-state imaging device according to a first embodiment of the present invention. [Figure 4] 1 is a block diagram showing an example of a basic configuration of a pixel circuit of a solid-state imaging device according to a first embodiment of the present invention. [Diagram 5] 1 is a circuit diagram showing an example of the configuration of a readout pixel in a pixel circuit according to a first embodiment of the present invention. [Figure 6] 1 is a circuit diagram illustrating a configuration example of a comparator according to a first embodiment of the present invention. [Figure 7] 1 is a simplified cross-sectional view showing an example of the configuration of a readout pixel according to a first embodiment of the present invention. [Figure 8] 5 is a timing chart for explaining an example of a readout sequence in a PFM mode and a double sampling readout mode for a pixel circuit under a high illuminance condition in the solid-state imaging device according to the first embodiment of the present invention. [Figure 9] 5A to 5C are diagrams illustrating an operation sequence and potential transitions for explaining operations in a PFM mode and a double sampling readout mode for a pixel circuit under high illuminance conditions in the solid-state imaging device according to the first embodiment of the present invention. [Figure 10] 5 is a timing chart for explaining an example of a readout sequence in a PFM mode and a double sampling readout mode for a pixel circuit under a low illuminance condition in the solid-state imaging device according to the first embodiment of the present invention. [Figure 11] 5A to 5C are diagrams illustrating an operation sequence and potential transitions for explaining operations in a PFM mode and a double sampling readout mode for a pixel circuit in a low illuminance condition of the solid-state imaging device according to the first embodiment of the present invention. [Figure 12]5 is a diagram showing linearity of a composite signal of readout signals in a double sampling readout mode of the solid-state imaging device according to the first embodiment of the present invention. FIG. [Figure 13] FIG. 11 is a circuit diagram showing an example of the configuration of a readout pixel in a pixel circuit according to a second embodiment of the present invention. [Figure 14] 10 is a simplified cross-sectional view showing an example of the configuration of a charge accumulation and transfer system having a shutter gate transistor which is a main part of a pixel circuit according to a second embodiment of the present invention. FIG. [Figure 15] 13 is a timing chart for explaining an example of a readout sequence in a PFM mode and a double sampling readout mode for a pixel circuit under a high illuminance condition in a solid-state imaging device according to a second embodiment of the present invention. [Figure 16] 13 is a timing chart for explaining an example of a readout sequence in a PFM mode and a double sampling readout mode for a pixel circuit under a low illuminance condition in a solid-state imaging device according to a second embodiment of the present invention. [Figure 17] FIG. 11 is a circuit diagram showing an example of the configuration of a pixel circuit according to a third embodiment of the present invention. [Figure 18] FIG. 13 is a circuit diagram showing an example of the configuration of a pixel circuit of a solid-state imaging device according to a fourth embodiment of the present invention. [Figure 19] FIG. 13 is a circuit diagram showing an example of the configuration of a pixel circuit of a solid-state imaging device according to a fifth embodiment of the present invention. [Figure 20] FIG. 1 is a diagram for explaining an example of an application device of a solid-state imaging device according to an embodiment of the present invention. [Figure 21] FIG. 21 is a timing diagram illustrating the operation principle of the application device of FIG. 20. [Figure 22] 1 is a diagram showing an example of a configuration of an electronic device to which a solid-state imaging device according to an embodiment of the present invention is applied; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0028] (First embodiment) FIG. 3 is a block diagram showing an example of the configuration of the solid-state imaging device according to the first embodiment of the present invention. FIG. 4 is a block diagram showing an example of a basic configuration of a pixel circuit of a solid-state imaging device according to the first embodiment of the present invention. In this embodiment, the solid-state imaging device 10 is formed of, for example, a CMOS image sensor.

[0029] As shown in FIG. 3, the solid-state imaging device 10 has as its main components a pixel section 20 as an imaging section, a vertical scanning circuit (row scanning circuit) 30, a readout circuit (column readout circuit) 40, a horizontal scanning circuit (column scanning circuit) 50, and a timing control circuit 60. Of these components, for example, the vertical scanning circuit 30, the readout circuit 40, the horizontal scanning circuit 50, and the timing control circuit 60 constitute a pixel signal readout section 70.

[0030] In the first embodiment, the solid-state imaging device 10, as will be described in detail later, includes pixel circuits 200 arranged in a matrix in the pixel section 20, which perform photoelectric conversion using a photodiode PD11 as a photoelectric conversion element and are capable of reading out a signal according to the illuminance conditions of the incident light, and which include an overflow path to a floating diffusion FD (Floating Diffusion) 11, a comparator 220 which compares a voltage signal (SFout) read out from the readout pixel 210 with a reference signal Vref and outputs a comparison result signal Vout according to the comparison result, a selection counter circuit 230 which receives the comparison result signal Vout from the comparator 220, selects a count clock for the counter, and performs a count operation synchronized with the selected clock, and a memory circuit 240 which stores digitized data by the selection counter circuit 230 according to the comparison result signal Vout of the comparator 220.

[0031] The read pixel 210, the comparator 220, and the selection counter circuit 230 operate in PFM (pulse frequency modulation) mode under high illuminance conditions, and operate in double sampling readout (e.g., LOFIC) mode using the accumulated charge and overflow charge of the photoelectric conversion element under low illuminance conditions.

[0032] In PFM mode operation under high illumination conditions, when a voltage signal corresponding to the charge held in the floating diffusion FD11 reaches the reference voltage of the comparator, the floating diffusion FD11 is self-reset by the feedback reset operation FRST11 of the comparison result signal Vout of the comparator 220, and the number of times (frequency) the floating diffusion FD11 is reset is counted by the selection counter circuit 230 according to the comparison result signal Vout of the comparator 220.

[0033] In the solid-state imaging device 10 according to the first embodiment of the present invention, the pixel circuit 210 is provided with a structure called a lateral overflow integration capacitor (hereinafter, "LOFIC (Lateral Overflow Integration Capacitor)"), as will be described in detail later, and operates in a double sampling readout mode (LOFIC mode) using a dual gain related to the accumulated charge and overflow charge of the photodiode PD11, which is a photoelectric conversion element, under low illuminance conditions.

[0034] In the pixel circuit 200, the read pixel 210 and the selection counter circuit 230 are selectively operable in a PFM mode or a double sampling read mode in response to a mode selection signal SMS.

[0035] In the PFM mode, the readout pixel 210 uses the first comparison result signal Vout11 as a feedback reset signal FRST11 to make the reset element conductive and reset the floating diffusion FD11 to a predetermined potential VAAPIX.

[0036] In the PFM mode, the comparator 220 is supplied with a constant (fixed) first reference signal (reference voltage) Vref11 equivalent to the saturation voltage of the photodiode PD11, which is a photoelectric conversion element, and when a voltage signal corresponding to the charge held in the floating diffusion FD11 reaches the first reference signal level Vref11, the comparator 220 reads out a first comparison result signal Vout11 and outputs it to the pixel 210 and the selection counter circuit 230. In the double sampling readout mode, the comparator 220 is supplied with a ramp-like second reference signal Vref12 that can change continuously, and outputs the comparison result between the voltage signal corresponding to the charge held in the floating diffusion FD11 and the second reference signal Vref12 to the selection counter circuit 230 as a second comparison result signal Vout12.

[0037] The selection counter circuit 230 counts the first comparison result signal Vout11 by the comparator 220 in the PFM mode, and latches the second comparison result signal Vout12 in synchronization with a clock of a predetermined frequency in the double sampling read mode.

[0038] In the example of FIG. 4, the selection counter circuit 230 includes a selector 231 and a counter 232 . The selector 231 has an input terminal A connected to the output line of the comparison result signal Vout of the comparator 220, an input terminal B connected to a supply line of the clock pulse CP, and an output terminal C connected to an input terminal (e.g., a clock terminal) of the counter 232. The selector 231 selectively connects the output terminal C to the input terminal A or B in response to the mode selection signal SMS, thereby selecting a signal to be input to the counter 232 . Specifically, when the mode selection signal SMS designates the PFM mode, the selector 231 connects the input terminal A to the output terminal C and supplies the comparison result signal Vout 11 of the comparator 220 to the counter 232 . When the mode selection signal MSM designates the double sampling read mode, the selector 231 connects the input terminal B to the output terminal C and supplies a clock pulse CP of a predetermined frequency to the counter 232 . The counter 232 counts the first comparison result signal Vout11 of the comparator 220 in the PFM mode, and latches the second comparison result signal Vout12 in synchronization with the clock pulse CP in the double sampling read mode.

[0039] In the first embodiment, the PFM mode is specified under high illuminance conditions during the exposure period PEXP after resetting the photoelectric conversion elements, photodiode PD11 and floating diffusion FD11, and the double sampling readout mode is specified following the PFM mode. In the PFM mode, during the exposure period PEXP, the following operations are repeatedly performed: charge overflow from the photodiode PD11 to the floating diffusion FD11; a self-reset operation on the floating diffusion FD11 due to a feedback reset operation of the comparison result signal Vout of the comparator 220; and the selection count circuit 230 counts the number of times (frequency) the floating diffusion FD11 is reset. In this embodiment, the actual generated charge can be counted by counting the number of resets, so that erroneous detection can be prevented even when non-steady light such as pulsed light is incident during the exposure period.

[0040] Furthermore, in this first embodiment, the readout unit 70 is configured to be capable of performing a first conversion gain mode readout in which pixel signals are read out with a first conversion gain corresponding to a first capacitance during a readout period, and a second conversion gain mode readout in which pixel signals are read out with a second conversion gain corresponding to a second capacitance (different from the first capacitance). In other words, the solid-state imaging device 10 of the first embodiment outputs a signal by switching between a first conversion gain (e.g., high conversion gain: HCG) mode and a second conversion gain (low conversion gain: LCG) mode within the pixel during a readout period for charges (electrons) photoelectrically converted during a single exposure period (accumulation period), and is provided as a solid-state imaging device with a wide dynamic range that outputs both bright signals and dark signals.

[0041] Hereinafter, a specific configuration example of the readout pixel 210 of the solid-state imaging device 10 will be described, and then a detailed description will be given of a structure example of a buried diode (PPD) portion and an overflow path. Here, a configuration example of the readout pixel 210 having the LOFIC structure will be described.

[0042] (Specific Configuration Example of Readout Pixel 210) FIG. 5 is a circuit diagram showing an example of the configuration of a readout pixel in a pixel circuit according to the first embodiment of the invention.

[0043] The pixel section 20 has a plurality of pixel circuits 200, each having a readout pixel 210 including a photodiode (photoelectric conversion element) and an in-pixel amplifier, arranged in a two-dimensional matrix of N rows and M columns.

[0044] As shown in FIG. 5, for example, this readout pixel 210 has a photodiode PD11 as a photoelectric conversion element, a transfer transistor TG11-Tr as a charge transfer gate unit (transfer element), a reset transistor RST11-Tr as a reset element, a reset transistor RST12-Tr for self-reset, an AND gate AD11, a storage transistor SG11-Tr as a storage element, and a storage capacitor CS11 as a storage capacitance element. In the first embodiment, the source follower transistor SF11-Tr serving as a source follower element is also used as one of the transistors of the differential transistor pair of the comparator 220, as will be described later.

[0045] The photodiode PD11 generates and accumulates a signal charge (here, electrons) in an amount corresponding to the amount of incident light. In the following, a case will be described in which the signal charges are electrons and each transistor is an n-type transistor, but the signal charges may be holes and each transistor may be a p-type transistor.

[0046] In each readout pixel 210, a buried photodiode (PPD) is used as the photodiode (PD). The surface of the substrate on which the photodiode (PD) is formed has interface states due to defects such as dangling bonds, so there is a risk that a large amount of charge (dark current) will be generated by thermal energy, making it impossible to read out the correct signal. In a buried photodiode (PPD), the charge storage section of the photodiode (PD) is embedded in a substrate, making it possible to reduce the inclusion of dark current in a signal.

[0047] The transfer transistor TG11-Tr is connected between the buried photodiode (PPD) and the floating diffusion FD11, and is controlled via a control signal TG. The transfer transistor TG11-Tr is selected and turned on while the control signal TG is at high level (H), and transfers the charges (electrons) photoelectrically converted by the photodiode PD11 and stored in the storage node ND10 to the floating diffusion FD11.

[0048] In the example of FIG. 5, the reset transistor RST11-Tr is connected between the power supply potential VAAPIX and the storage transistor SG11-Tr connected to the floating diffusion FD11, and is controlled via a control signal RST. The reset transistor RST11-Tr is selected and turned on while the control signal RST is at H level, and resets the floating diffusion FD11 to the power supply potential VAAPIX when the storage transistor SG11-T is in the conductive state.

[0049] In the example of FIG. 5, the self-reset reset transistor RST12-Tr is connected in parallel with the reset transistor RST11-Tr between the power supply potential VAAPIX and the storage transistor SG11-Tr connected to the floating diffusion FD11, and is controlled via the output control signal SRST of the AND gate AD11. The self-reset reset transistor RST12-Tr is selected and turned on while the control signal SRST is at H level, and resets the floating diffusion FD11 to the power supply potential VAAPIX when the storage transistor SG11-Tr is turned on.

[0050] In the first embodiment, in the PFM mode, during the self-reset operation, the reset transistor RST12-Tr for self-reset and the storage transistor SG11-Tr are held in a conductive state, and the floating diffusion FD11 and the storage capacitor CS11 are reset.

[0051] Furthermore, in this first embodiment, by selectively connecting the floating diffusion FD11 and the storage capacitor CS11 through the storage transistor SG11-Tr, the capacitance of the floating diffusion FD11 can be changed to a first capacitance or a second capacitance, and the conversion gain can be switched to a first conversion gain (high conversion gain: HCG) determined by the first capacitance or a second conversion gain (low conversion gain: LCG) determined by the second capacitance.

[0052] The storage transistor SG11-Tr has, for example, a source connected to the floating diffusion FD11. The storage capacitor CS11 has a first electrode EL1 connected to a reference potential VSS (for example, a ground potential GND) and a second electrode EL2 connected to the drain of the storage transistor SG11-Tr as a capacitive connection node ND11. The storage transistor SG11-Tr is controlled by a control signal SG applied to its gate through a control line. The storage transistor SG11-Tr is selected and turned on while the control signal SG is at H level, connecting the floating diffusion FD11 and the storage capacitor CS11.

[0053] During the first conversion gain (high conversion gain: HCG) signal read process in the double sampling read mode, the storage transistor SG11-Tr is held in a non-conductive state, and the read process is performed by separating the charge of the floating diffusion FD11 and the charge of the storage capacitor CS11. During the second conversion gain (low conversion gain: LCG) signal read process in the double sampling read mode, the storage transistor SG11-Tr is held in a conductive state, and the read process is performed by sharing (mixing) the charge of the floating diffusion FD11 and the charge of the storage capacitor CS11.

[0054] 5, the storage transistor SG11-Tr is connected between the floating diffusion FD11 and the reset transistors RST11-Tr, RST12-Tr, and the storage capacitor CS11 is connected between the connection node ND11 and the reference potential VSS. However, the connection form is not limited to this. For example, the reset transistor RST11-Tr and the storage transistor SG11-Tr may be directly connected to the floating diffusion FD11 individually.

[0055] One input terminal of the AND gate AD11 is connected to the supply line of the reset count signal RCNT, the other input terminal is connected to the supply line of the comparison result signal Vout by the comparator 220, and the output terminal of the control signal SRST is connected to the gate of the self-reset reset transistor RST12-Tr. The reset count signal RCNT is synchronized with the mode selection signal SMS, and is supplied at a high level for the same period when the mode selection signal SMS is at a high level indicating a PFM mode period, and is supplied at a low level for the same period when the mode selection signal SMS is at a low level indicating a double sampling read mode period. Therefore, the AND gate AD11 takes the logical product of the reset count signal RCNT supplied at a high level during the PFM mode period and the comparison result signal Vout by the comparator 220, and outputs the control signal SRST at a high level while the comparison result signal Vout is at a high level. As a result, while the control signal SRST is at a high level, the self-reset reset transistor RST12-Tr is held in a conductive state.

[0056] In the first embodiment, the source follower transistor SF11-Tr serving as a source follower element is shared as one of the transistors of the differential transistor pair of the comparator 220. Here, a specific example of the configuration of the comparator 220 will be described.

[0057] Example of the configuration of the comparator 220 The comparator 220 of the first embodiment includes a differential transistor pair in which a signal voltage VSL is supplied to the gate of one transistor and a fixed voltage as a first reference signal Vref11 or a ramp signal RAMP as a second reference signal Vref12 is supplied to the gate of the other transistor, and which performs a comparison operation between the signal voltage VSL and the reference voltage Vref or the ramp signal RAMP, and an active load circuit connected to the drain side of one transistor and the drain side of the other transistor to form a current mirror.

[0058] FIG. 6 is a circuit diagram showing an example of the configuration of a comparator according to the first embodiment.

[0059] The comparator 220 in FIG. 6 includes PMOS transistors PT21 and PT22, NMOS transistors NT21 and NT22, a current source I21, and nodes ND21 and ND22.

[0060] The source of the PMOS transistor PT21 and the source of the PMOS transistor PT22 are connected to each other, and the connection node thereof is connected to the power supply potential VDD. The source of the NMOS transistor PT21 and the source of the NMOS transistor PT22 are connected to each other, and the connection node thereof is connected to a current source I21 that is connected to a reference potential VSS.

[0061] The drain of the PMOS transistor PT21 and the drain of the NMOS transistor N21 are connected together, and their connection point forms a node ND21. The drain of the PMOS transistor PT22 and the drain of the NMOS transistor NT22 are connected together, and their connection point forms a node ND22. The node ND21 is connected to the gates of the PMOS transistors PT21 and PT22, and the node ND22 is connected to an output node ND221.

[0062] Of these components, a differential transistor pair 221 is formed by NMOS transistors NT21 and NT22 whose sources are connected to each other. One transistor 221-1 is formed by the NMOS transistor NT21, and the other transistor 221-2 is formed by the NMOS transistor NT22. A voltage signal VSL is supplied to the gate of the NMOS transistor NT21 that forms one of the transistors 221-1, and a fixed voltage as the first reference signal Vref11 or a ramp signal RAMP as the second reference signal Vref12 is supplied to the gate of the NMOS transistor NT22 that forms the other transistor 221-2.

[0063] An active load circuit 222 in which a current mirror is formed by PMOS transistors PT21 and PT22 is disposed on the drain side of the NMOS transistor NT21 as one transistor and on the drain side of the NMOS transistor NT22 as the other transistor.

[0064] In the comparator 220 having such a configuration, a connection node ND22 between the drain of the NMOS transistor NT22 as the other transistor and the drain of the PMOS transistor PT22 constituting the active load circuit 222 is connected to an output node ND221 of the comparison result signal Vout. That is, the comparator 220 outputs the comparison result signal Vout from the drain side of the NMOS transistor NT22, which serves as the other transistor.

[0065] For example, the comparator 220 performs a comparison operation between the voltage signal VSL and the first reference signal Vref11 or the second reference signal Vref12, and when the voltage signal VSL and the first reference signal Vref11 or the second reference signal Vref12 become equal in level, it inverts the output level of the comparison result signal Vout from an inactive level (e.g., a low level) to an active level (a high level).

[0066] A source follower transistor SF11-Tr shared with one of the differential transistors of the comparator 220 outputs a column output read signal (voltage signal) obtained by converting the charge of the floating diffusion FD11 into a voltage signal with a gain according to the capacitance. These operations are performed simultaneously in parallel for each pixel in one row, since the gates of the transfer transistors TG11-Tr, reset transistors RST11-Tr, RST12-Tr, and storage transistors SG1-Tr are connected on a row-by-row basis.

[0067] In the pixel section 20, the pixel circuits 200 are arranged in N rows and M columns, and therefore there are N control lines and M vertical signal lines. In FIG. 3, each control line is represented as one row scan control line.

[0068] The vertical scanning circuit 30 drives pixels in the shutter row and the readout row through row scanning control lines under the control of the timing control circuit 60 . Furthermore, the vertical scanning circuit 30 outputs a row selection signal of the row address of a read row for reading out a signal and a shutter row for resetting the charge accumulated in the photodiode PD11 in accordance with the address signal.

[0069] The readout circuit 40 may include a plurality of column signal processing circuits (not shown) arranged corresponding to each column output of the pixel section 20, and may be configured to enable column parallel processing by the plurality of column signal processing circuits.

[0070] The horizontal scanning circuit 50 scans the signals processed by the multiple column signal processing circuits of the readout circuit 40, transfers them in the horizontal direction, and outputs them to a signal processing circuit (not shown).

[0071] The timing control circuit 60 generates timing signals necessary for signal processing in the pixel section 20, the vertical scanning circuit 30, the readout circuit 40, the horizontal scanning circuit 50, and the like.

[0072] The configuration and function of each part of the solid-state imaging device 10 have been outlined above. Next, the configuration and functions of the readout pixels and the like according to the first embodiment will be described in detail.

[0073] (Specific Configuration Example of Readout Pixel 210) FIG. 7 is a simplified cross-sectional view showing an example of the configuration of a readout pixel according to the first embodiment of the present invention. In this case, the readout pixel including a buried photodiode (PPD) is denoted by reference numeral 2100.

[0074] The readout pixel 2000 in Figure 7 has a semiconductor substrate (hereinafter simply referred to as substrate) 2100 having a first substrate surface 2110 side (e.g., the back side) onto which light L is irradiated, and a second substrate surface 2120 side (front side) opposite the first substrate surface 2110 side. The readout pixel 2000 includes a first conductivity type (n type in this embodiment) semiconductor layer (n layer) 2210 formed so as to be embedded in the substrate 2100, and has a photoelectric conversion unit 2200 as a photodiode PD11 having a photoelectric conversion function of received light and a charge storage function, and a second conductivity type (p type in this embodiment) semiconductor layer 2300 formed on at least a side portion of the n layer (first conductivity type semiconductor layer) 2210 of the photoelectric conversion unit 2200. Furthermore, the n-layer (first conductive type semiconductor layer) 2210 of the photoelectric conversion section 2200 is formed with a concentration gradient such that the impurity concentration of n-ions increases stepwise from the first substrate surface 2110 side toward the second substrate surface 2120 side.

[0075] Furthermore, the readout pixel 2000 has a transfer transistor TG11-Tr capable of transferring charges accumulated in the photoelectric conversion unit 2200, a floating diffusion FD11 to which charges are transferred through the transfer transistor TG11-Tr, a storage transistor SG11-Tr whose source is connected to the floating diffusion FD11, and a storage capacitor CS11 as a storage capacitance element that accumulates charges from the floating diffusion FD11 via the drain side of the storage transistor SG11-Tr. In the readout pixel 2000, the storage capacitor CS11, which is a storage capacitance element, is formed on the second substrate surface 2120 side so as to have a spatial overlap with the photoelectric conversion section 2200 in a direction perpendicular to the substrate surface (the Z direction of the Cartesian coordinate system in the figure).

[0076] Furthermore, in the photoelectric conversion section 220, a second conductivity type semiconductor region (p+ region) 2230 having a higher impurity concentration than the side p layer (second conductivity type semiconductor layer) 2300 is formed on the surface of the n layer (first conductivity type semiconductor layer) 2220 on the second substrate surface 2120 side. In addition, the storage capacitor CS11, which is a storage capacitance element, shares the n+ region (first conductivity type semiconductor region) 2240 formed on the surface of the p-layer (second conductivity type semiconductor layer) 2300 on the second substrate surface 2120 side as a first electrode EL1.

[0077] That is, in this first embodiment, the storage capacitor CS11, which is a storage capacitance element, is configured to include a first electrode EL1 formed by an n+ region (first conductivity type semiconductor region) 2240 formed on the surface of the second substrate surface 2120 of the substrate 2100, and a second electrode EL2 formed on the second substrate surface 2120 so as to face the first electrode EL1 at a predetermined interval in a direction perpendicular to the substrate surface.

[0078] In the first embodiment, a flat layer 2250 is formed on the surfaces of the n-layer (first conductive type semiconductor layer) 2210 and p-layer (second conductive type semiconductor layer) 2300 of the photoelectric conversion section 2200 on the first substrate surface 2110 side. A color filter section CF is formed on the light incident side of this flat layer 2250, and further, a microlens MCL is formed on the light incident side of the color filter section so as to correspond to the photoelectric conversion section 2200 as the photodiode PD11 and the p-layer (second conductivity type semiconductor layer) 2300.

[0079] In the first embodiment, a transfer transistor TG11-Tr, a floating diffusion FD11, and a storage transistor SG11-Tr are formed in a p-layer (first conductivity type semiconductor layer) 2320 in the right region of the second substrate surface 2120 of the substrate 2100 in the figure.

[0080] The floating diffusion FD11 is formed on the surface of the second substrate surface 2120 of the substrate 2100 as an n+ region (first conductive type semiconductor region) 2330 having a higher impurity concentration than the n layers (first conductive type semiconductor layers) 2210, 2220 of the photoelectric conversion section 2200.

[0081] The capacitive connection node ND11 between the storage capacitor CS11 of the storage transistor SG11-Tr is formed on the surface of the second substrate surface 2120 of the substrate 2100 as an n+ region (first conductive type semiconductor region) 2340 having a higher impurity concentration than the n layers (first conductive type semiconductor layers) 2210, 2220 of the photoelectric conversion section 2200. The n+ region 2340 serving as the node ND11 is connected to the second electrode EL2 of the storage capacitor CS1 via a wiring layer WR1.

[0082] The transfer transistor TG11-Tr is formed to include a gate electrode 2510 arranged on the second substrate surface 2120 of the substrate 2100 between the p+ region (second conductive type semiconductor region) 2230 and the n+ region (first conductive type semiconductor region) 2330 as the floating diffusion FD11.

[0083] The storage transistor SG11-Tr is formed to include a gate electrode 2520 arranged on the second substrate surface 2120 of the substrate 2100 between an n+ region (first conductive type semiconductor region) 2330 as the floating diffusion FD11 and an n+ region (first conductive type semiconductor region) 2340 as the capacitance connection node ND11.

[0084] In this first embodiment, an embedded overflow path 2600 is formed, which is connected to the upper layer side (p+ layer 2230 side) of the n layer 2220 of the photoelectric conversion unit 2200 and can transfer the overflow charge of the photoelectric conversion unit 2200 to the floating diffusion FD11 and further to the capacitive connection node ND11 with the storage capacitor CS11. The buried overflow path 2600 is formed so as to interconnect the lower layer of the channel formation under the gate electrode 2510 of the transfer transistor TG11-Tr, the lower layer of the n+ region (first conductivity type semiconductor region) 2330 as the floating diffusion FD11, the lower layer of the channel formation region under the gate electrode 2520 of the storage transistor SG11-Tr, and the lower portion of the n+ region (first conductivity type semiconductor region) 2340 as the capacitance connection node ND11. The buried overflow path 2600 is formed by the n− layer of the n layer 2220 of the photoelectric conversion section 2200, which has a low impurity concentration.

[0085] In this manner, in the readout pixel 2000 of the first embodiment, an embedded overflow path 2600 is formed, which is connected to the upper layer side (p+ layer 2230 side) of the n layer 2220 of the photoelectric conversion unit 2200 and can transfer the overflow charge of the photoelectric conversion unit 2200 to the floating diffusion FD11 and further to the capacitive connection node ND11 with the storage capacitor CS11. Therefore, during the exposure period, the transfer transistor TG11-Tr is always turned off (non-conductive state), so that the charge can overflow while suppressing the generation of dark current at the silicon interface below the transfer transistor TG11-Tr.

[0086] Furthermore, in the readout pixel 2000 of this first embodiment, the storage capacitor CS11, which is a storage capacitance element, is configured to include, on the second substrate surface 2120 side, a first electrode EL1 formed by an n+ region (first conductivity type semiconductor region) 2240 formed on the surface of the second substrate surface 2120 of the substrate 2100 so as to have a spatial overlapping portion with the photoelectric conversion unit 2200 in a direction perpendicular to the substrate surface (the Z direction of the Cartesian coordinate system in the figure), and a second electrode EL2 formed on the second substrate surface 2120 so as to face the first electrode EL1 at a predetermined interval in a direction perpendicular to the substrate surface. Therefore, even if the capacitance of the storage capacitor CS11 is set large, it is possible to prevent the aperture of the photodiode PD11 from lowering and the sensitivity from decreasing. Moreover, even if the light receiving area of ​​the photodiode PD11 is set large, the area occupied by the storage capacitor CS11 becomes small, and as a result, it is possible to prevent a decrease in the dynamic range. That is, according to the first embodiment, it is possible to achieve both a wide dynamic range and high sensitivity.

[0087] As described above, in this first embodiment, the PFM mode is specified under high illuminance conditions during the exposure period PEXP after resetting the photoelectric conversion elements, the photodiode PD11 and the floating diffusion FD11, and the double sampling readout mode is specified following the PFM mode.

[0088] When the double sampling read mode is specified following the PFM mode, the read unit 70 holds the storage transistor SG11-Tr in a non-conductive state to separate the storage capacitor CS11 from the floating diffusion FD11, floating The charge of the diffusion FD11 and the charge of the storage capacitor CS11 are separated to switch the conversion gain to a first conversion gain HCG determined by a first capacitance. Then, during the first reset read period after the reset processing, the readout section 70 reads out the first read reset signal HCGRST(ADC) converted with a first conversion gain determined by the first capacitance of the floating diffusion FD11 from the source follower transistor SF11-Tr serving as an output buffer section, and performs a first conversion gain reset readout process HCGRRD to perform a predetermined process on this first readout reset signal HCGRST(ADC). Furthermore, during the first read period following the first transfer period after the first reset read period, the read section 70 reads out a first read signal HCGSIG(ADC) converted with a first conversion gain determined by the first capacitance of the floating diffusion FD11 from the source follower transistor SF11-Tr as an output buffer section, and performs a first conversion gain read process HCGSRD to perform a predetermined process on this first read signal HCGSIG(ADC).

[0089] Then, the readout section 70 holds the reset level and the signal level, or performs a CDS calculation based on the difference between the reset level and the signal level. Next, after the first conversion gain read process HCGSRD, the readout section 70 switches the storage transistor SG11-Tr to a conductive state to connect the storage capacitor CS11 to the floating diffusion FD11, floating The charge of the diffusion FD11 and the charge of the storage capacitor are shared to switch the conversion gain to a second conversion gain LCG determined by a second capacitance. Then, during a second read period following the second transfer period after the first read period, the read section 70 reads out a second read signal LCGSIG(ADC) converted with a second conversion gain determined by the second capacitance of the floating diffusion FD11 from the source follower transistor SF11-Tr as an output buffer section, and performs a second conversion gain read process LCGSRD to perform a predetermined process on the second read signal LCGSIG(ADC). Then, the readout unit 70 resets the floating diffusion FD11 using the reset transistor RST11-Tr, and then reads out a second readout reset signal LCGRST(ADC) converted with a second conversion gain LCG determined by the second capacitance of the floating diffusion FD11 from the source follower transistor SF11-Tr as an output buffer unit, and performs a second conversion gain reset readout process LCGRRD that performs a predetermined process on the second readout reset signal LCGRST(ADC).

[0090] Then, the readout section 70 holds the reset level and the signal level, or performs a DDS calculation based on the difference between the reset level and the signal level. When the subject is in high illuminance, the reset level of the source follower is acquired by resetting the floating diffusion FD11 after the signal level of the source follower is acquired, and therefore an incomplete differential signal (also called a DDS (Double Data Sampling) signal or a DRS (Delta Reset Sampling) signal) that is not correlated with the reset noise is obtained. Although such reset noise is noticeable in a normal CMOS image sensor, in the readout method in the first embodiment, this DDS signal is a signal on the high illuminance (high brightness) side read out by the source follower readout operation, for example, and is not used in low illuminance, and is buried in the shot noise of the signal, making it difficult to see and therefore inconspicuous.

[0091] The readout section 70 can perform the first conversion gain reset readout process HCGRRD during the exposure period PEXP. Moreover, under an extremely low illuminance condition, the readout section 70 performs, for example, a second conversion gain reset readout process LCGRRD and a second conversion gain readout process LCGSRD as normal readout operations. Under a medium illuminance condition, the readout section 70 performs a first conversion gain reset readout process HCGRRD, a first conversion gain readout process HCGSRD, a second conversion gain readout process LCGSRD, and a second conversion gain reset readout process LCGRRD.

[0092] Thus, in this first embodiment, the device has a storage transistor SG11-Tr and a storage capacitor CS11, and is configured such that the capacitance of the floating diffusion FD11 can be changed to a first capacitance or a second capacitance to switch the conversion gain to a first conversion gain determined by the first capacitance (e.g., high conversion gain: HCG) or a second conversion gain determined by the second capacitance (e.g., low conversion gain: LCG). As a result, the FWC (Full Well Capacity) becomes small at the time of high conversion gain (HCG), and the FWC becomes large at the time of low conversion gain (LCG).

[0093] Here, an example of a readout sequence for the pixel circuits in the solid-state imaging device according to the first embodiment will be described.

[0094] 8A to 8H are timing charts for explaining an example of a readout sequence in the PFM mode and the double sampling readout mode for a pixel circuit under high illuminance conditions in the solid-state imaging device according to the first embodiment of the present invention. 9A to 9N are diagrams showing operation sequences and potential transitions for explaining operations in the PFM mode and the double sampling readout mode for the pixel circuit under high illuminance conditions of the solid-state imaging device according to the first embodiment of the present invention. 10A to 10H are timing charts for explaining an example of a readout sequence in the PFM mode and the double sampling readout mode for a pixel circuit under a low illuminance condition of the solid-state imaging device according to the first embodiment of the present invention. 11A to 11N are diagrams showing operation sequences and potential transitions for explaining operations in the PFM mode and the double sampling readout mode for the pixel circuit in the solid-state imaging device according to the first embodiment of the present invention under low illuminance conditions.

[0095] 8(A) and 10(A) show the reset count signal RCNT which indicates the PFM mode period and the double sampling read mode period in synchronization with the mode selection signal SMS, FIGS. 8(B) and 10(B) show the control signal RST of the reset transistor RST11-Tr, FIGS. 8(C) and 10(C) show the control signal SG of the storage transistor SG11-Tr, FIGS. 8(D) and 10(D) show the control signal TG of the transfer transistor TG11-Tr, FIGS. 8(E) and 10(E) show the potential of the floating diffusion FD11, FIGS. 8(F) and 10(F) show the output voltage SFout of the source follower transistor SF11-Tr and the reference signal Vref(1,2) of the comparator 220, FIGS. 8(G) and 8(G) show the digitized output voltage Vout of the comparator 220, and FIGS. 8(H) and 10(H) show the clock signal CLK used in the double sampling read mode.

[0096] (Operation in high light conditions) Under high illumination conditions, before the PFM mode is started, the control signal RST is set to a high level and the reset transistor RST11-Tr is held in a conductive state, and then the control signal TG is set to a high level and the transfer transistor TG11-Tr is held in a conductive state with the floating diffusion FD11 and photodiode PD11 connected, and the control signal SG is switched from a low level to a high level and the storage transistor SG11-Tr is switched from a non-conductive state to a conductive state. As a result, the photodiode PD11 and the floating diffusion FD11 are reset to the fixed potential VAAPIX, that is, a global reset is performed (FIG. 9(A)). Subsequently, the control signal TG is switched from high level to low level, and the transfer transistor TG11-Tr is switched from a conductive state to a non-conductive state.

[0097] The exposure time PEXP starts at the timing when the transfer transistor TG11-Tr is switched from the conductive state to the non-conductive state (FIG. 9B). After the exposure period PEXP starts, the control signal RST is switched from high to low to switch the reset transistor RST11-Tr from a conductive state to a non-conductive state, while the PFM mode is activated by the reset count signal RCNT synchronized with the mode selection signal SMS.

[0098] In PFM mode operation under high illumination conditions, when a voltage signal according to the charge held in the floating diffusion FD11 reaches the reference signal Vref11, the reset transistor RST12-Tr is held in a conductive state for a predetermined period by the feedback reset operation FRST11 of the comparison result signal Vout of the comparator 220, and the floating diffusion FD11 is self-reset (FIGS. 9(C), (D), (E)). Then, the number of resets (frequency) of the floating diffusion FD11 is counted by the selection counter circuit 230 according to the comparison result signal Vout of the comparator 220. In PFM mode operation under high illumination conditions, during the exposure period PEXP, the following operations are repeatedly performed: charge overflow from the photodiode PD11 to the floating diffusion FD11; self-reset operation of the floating diffusion FD11 due to the feedback reset operation of the comparison result signal Vout of the comparator; and counting the number of resets (frequency) of the floating diffusion FD11 by the selection count circuit 230 (Figures 9(C), (D), and (E)).

[0099] Next, in order to switch from the PFM mode to the double sampling (LOFIC) read mode, the reset count signal RCNT, which is synchronized with the mode selection signal SMS, is switched from high level to low level. In parallel with this, the control signal SG is switched from high to low, the storage transistor SG11-Tr is held in a non-conductive state, and the storage capacitor CS11 is disconnected from the floating diffusion FD11.

[0100] This means: floating The charge of the diffusion FD11 and the charge of the storage capacitor CS11 are separated, and the gain of the floating diffusion FD11 is switched to a first conversion gain HCG determined by the first capacitance.

[0101] Then, during the first reset read period after the reset process, a first read reset signal HCGRST(ADC) converted with a first conversion gain HCG determined by the first capacitance of the floating diffusion FD11 is read out from the source follower transistor SF11-Tr (Figure 9(G)), and a first conversion gain reset read process HCGRRD is performed to perform a predetermined process on this first read reset signal HCGRST(ADC). Next, in the first transfer period after the first reset readout period, the control signal TG is switched to a high level, the transfer transistor TG11-Tr is held in a conductive state, and the accumulated charge of the photodiode PD11 is transferred to the floating diffusion FD11. After the first transfer period, the control signal TG is switched back to a low level, and the transfer transistor TG11-Tr is switched to a non-conductive state.

[0102] Next, during the first read period following the first transfer period, a first read signal HCGSIG(ADC) converted with a first conversion gain determined by the first capacitance of the floating diffusion FD11 is read out from the source follower transistor SF11-Tr, and a first conversion gain read process HCGSRD is performed to perform a predetermined process on this first read signal HCGSIG(ADC).

[0103] Then, the reset level HCGRSTADC and the signal level HCGSIGADC are held, or the CDS calculation is performed based on the difference between the reset level and the signal level.

[0104] Next, after the first conversion gain read process HCGSRD, the control signal SG is switched from low level to high level, the storage transistor SG11-Tr is switched to the conductive state, and the storage capacitor CS11 is connected to the floating diffusion FD11. As a result, the charge of the floating diffusion FD11 and the charge of the storage capacitor are shared, and the gain of the floating diffusion FD11 is switched to the second conversion gain LCG determined by the second capacitance.

[0105] Then, in the second transfer period after the second readout period, the control signal TG is switched to a high level, the transfer transistor TG11-Tr is held in a conductive state, and the accumulated charge of the photodiode PD11 is transferred to the floating diffusion FD11. After the second transfer period, the control signal TG is switched to a low level, and the transfer transistor TG11-Tr is switched to a non-conductive state. Then, during the second read period following the second transfer period after the first read period, a second read signal LCGSIG(ADC) converted with a second conversion gain LCG determined by the second capacitance of the floating diffusion FD11 is read out from the source follower transistor SF11-Tr (Figure 9(L)), and a second conversion gain read process LCGSRD is performed to perform a predetermined process on this second read signal LCGSIG(ADC).

[0106] Next, during a second reset read period following the second transfer period, a second read reset signal LCGRST(ADC) converted with a second conversion gain LCG determined by the second capacitance of the floating diffusion FD11 is read out from the source follower transistor SF11-Tr, and a second conversion gain reset read process LCGRRD is performed to perform a predetermined process on this second read reset signal LCGRST(ADC).

[0107] Then, the reset level LCGRSTADC and the signal level LCGSIGADC are held, or the DDS calculation is performed based on the difference between the reset level LCGRSTADC and the signal level LCGSIGADC.

[0108] (Operation in low light conditions) Under low illuminance conditions, in the PFM mode, the reference signal Vref11 corresponding to the charge held in the floating diffusion FD11 is never reached. Therefore, in PFM mode operation under low illuminance conditions, during the exposure period PEXP, the overflow of charge from the photodiode PD11 to the floating diffusion FD11, the self-reset operation on the floating diffusion FD11 due to the feedback reset operation of the comparison result signal Vout of the comparator, and the count operation of the number of resets (frequency) of the floating diffusion FD11 by the selection count circuit 230 are not repeated.

[0109] Moreover, the operation in the double sampling (LOFIC) readout mode under low illumination conditions is similar to the operation under high illumination conditions described above. Therefore, a detailed description thereof will be omitted here.

[0110] As described above, according to the first embodiment, the pixel circuit 200 is configured to include a readout pixel 210 that performs photoelectric conversion using a photodiode PD11 as a photoelectric conversion element and is capable of reading out a signal according to the illuminance conditions of the incident light, a comparator 220 that compares a voltage signal SFout read out from the readout pixel 210 with a reference signal Vref and outputs a comparison result signal Vout according to the comparison result, a selection counter circuit 230 that receives the comparison result signal Vout from the comparator 220, selects a count clock for the counter, and performs a count operation synchronized with the selected clock, and a memory circuit 240 that stores digitized data by the selection counter circuit 230 according to the comparison result signal Vout of the comparator 220. The pixel circuit 200 is formed with an overflow path 2600 that allows the charge overflowing from the photodiode PD11 to overflow to the floating diffusion FD11 and further to the connection node with the storage capacitor CS11. The read pixel 210, the comparator 220, and the selection counter circuit 230 operate in PFM (pulse frequency modulation) mode under high illuminance conditions, and operate in double sampling readout (e.g., LOFIC) mode using the accumulated charge and overflow charge of the photoelectric conversion element under low illuminance conditions. Specifically, in PFM mode operation under high illuminance conditions, when a voltage signal corresponding to the charge held in the floating diffusion FD11 reaches the saturation voltage of the photodiode PD11, which is a photoelectric conversion element, the floating diffusion FD11 is self-reset by a feedback reset operation FRST11 of the comparison result signal Vout of the comparator 220, and the number of times (frequency) the floating diffusion FD11 is reset is counted by the selection counter circuit 230 according to the comparison result signal Vout of the comparator 220. Under low illumination conditions, the device operates in a double sampling readout mode (LOIC mode) using dual gain associated with the accumulated charge and overflow charge of the photodiode PD11, which is a photoelectric conversion element.

[0111] Therefore, according to the first embodiment, at least an overflow path is embedded from the photodiode PD11 to the formation region of the floating diffusion FD11, so that the transfer transistor TG11-Tr can be controlled to a non-conductive state (off) during the exposure period, thereby allowing charge to overflow while suppressing the dark current generated at the silicon interface below the transfer transistor TG11-Tr. That is, according to the first embodiment, it is possible to read out a small signal in a saturated state while maintaining the sensitivity and the number of saturated charges, and furthermore, it is possible to miniaturize the pixel size.

[0112] Furthermore, according to the first embodiment, it is possible to expand the dynamic range with a small pixel size by using a predetermined readout mode. According to the first embodiment, it is possible to substantially achieve a high dynamic range and a high frame rate. Furthermore, according to the first embodiment, as shown in Fig. 12, an ultra-high dynamic range signal can be read by the linear response of PFM readout, and a high sensitivity / low noise signal can be read by HCG readout. It is also possible to prevent signal variations at pixel connection points due to saturation variations. Furthermore, according to the first embodiment, the actual generated charge can be counted by counting the number of times the floating diffusion FD11 is reset, so that erroneous detection can be prevented even when non-stationary light such as pulsed light is incident during the exposure period.

[0113] Second Embodiment FIG. 13 is a circuit diagram showing an example of the configuration of a readout pixel in a pixel circuit according to the second embodiment of the present invention. FIG. 14 is a simplified cross-sectional view showing an example of the configuration of a charge accumulation and transfer system having a shutter gate transistor which is a main part of a pixel circuit according to the second embodiment of the present invention. 15A to 15H are timing charts for explaining an example of a readout sequence in the PFM mode and the double sampling readout mode for a pixel circuit under high illuminance conditions in a solid-state imaging device according to the second embodiment of the present invention. 16A to 16I are timing charts for explaining an example of a readout sequence in the PFM mode and the double sampling readout mode for a pixel circuit under a low illuminance condition in a solid-state imaging device according to the second embodiment of the present invention.

[0114] The pixel circuit 200A of the solid-state imaging device 10A according to the second embodiment differs from the pixel circuit 200 of the solid-state imaging device 10 according to the first embodiment described above in the following points.

[0115] In the pixel circuit 200A of the solid-state imaging device 10A according to the second embodiment, an anti-blooming transistor AB11-Tr is provided between the charge storage region of the photodiode PD11 and a fixed potential (e.g., a power supply potential) VAAPIX, as a gate element capable of discharging the charge of the photodiode PD11 to the fixed potential VAAPIX outside the floating diffusion FD11 region.

[0116] In the solid-state imaging device 10A according to the second embodiment, as shown in FIG. 14 (and FIG. 7), the overflow barrier of the transfer transistor TG11-Tr is lower than the overflow barrier of the anti-blooming transistor AB11-Tr because an overflow path 2600 is embedded therein. As a result, the charge of the photodiode PD11 overflows only in the direction of the floating diffusion FD11.

[0117] (Configuration of the left separation layer 2310 in the X direction (column direction)) An n+ layer 2340 that will become the drain of the anti-blooming AB11-Tr is formed on the second substrate surface 2120 side of the p-type isolation layer 2310 on the left side in the X direction (column direction) of FIG. A gate electrode 2540 of the anti-blooming transistor AB11-Tr is formed on the second substrate surface 2120 side via a gate insulating film. An overflow path 2600 is formed below the transfer transistor TG11-Tr, extending from the photodiode PD11 to the floating diffusion FD11 and further to the connection node 2340 with the storage capacitor CS11. The potential of the overflow path 2600 can also be controlled by gate control, for example.

[0118] In such a structure, when the intensity (amount) of incident light is very high, charges exceeding the PD saturation charge amount overflow into the floating diffusion FD11 as overflow charges through the overflow path 2600 below the transfer transistor TG11-Tr.

[0119] In addition, in the solid-state imaging device 10A according to the second embodiment, the accumulated charge of the photodiode PD11 is reset by holding the anti-blooming transistor AB11-Tr in a conductive state for a predetermined period of time, as shown in FIG. 15(E) and FIG. 16(E). The exposure period PEXP starts from the point in time when the control signal AB for the anti-blooming transistor AB11-Tr is switched from high level to low level.

[0120] The other configurations are the same as those of the first embodiment described above. According to the second embodiment, in addition to the same effects as those of the first embodiment described above, the following effects can be obtained.

[0121] That is, according to the second embodiment, it is possible to prevent a signal (overflow charge) exceeding the accumulated charge of a given photodiode PD from flowing into an adjacent pixel and causing charge mixing (resulting in a false signal).

[0122] (Third embodiment) FIG. 17 is a circuit diagram showing an example of the configuration of a pixel circuit of a solid-state imaging device 10B according to the third embodiment of the present invention.

[0123] A pixel circuit 200B of a solid-state imaging device 10B according to the third embodiment differs from the pixel circuit 200A of the solid-state imaging device 10A according to the second embodiment described above in the configuration of a comparator 220B.

[0124] In the pixel circuit 200B of the solid-state imaging device 10B according to the third embodiment, the comparator 220B receives a voltage signal VSL output from the source-side output node of the source follower transistor SF11-Tr of the readout pixel 210B at its inverting input terminal (-) as a first input terminal, and receives a reference signal (reference voltage) Vref(11,12) at its non-inverting input terminal (+) as a second input terminal, and performs AD conversion processing (comparison processing) to compare the voltage signal VST with the reference signal Vref and output a digitized comparison result signal SCMP.

[0125] The comparator 220B has a coupling capacitor CC1 connected to its inverting input terminal (-) serving as a first input terminal, and is configured to achieve low noise and a high SNR at low illuminance by AC-coupling the output node of the source follower transistor SF11-Tr serving as the output buffer section of the readout pixel 210B on the first substrate 2110 side with the input section of the comparator 220B on the second substrate 2120 side.

[0126] In addition, the comparator 220B is configured such that an auto-zero switch SW-AZ serving as a reset switch is connected between the output terminal and an inverting input terminal (-) serving as a first input terminal, so that the offset of the comparator 220B can be removed.

[0127] For example, in the comparator 220B, the analog signal (potential VSL) read out from the source follower transistor SF11-Tr serving as the output buffer section of the readout pixel 210B is compared in the comparator 220B with a reference signal Vref12, for example, a ramp signal RAMP, which is a slope waveform that changes linearly with a certain gradient. At this time, a counter (not shown) arranged for each column, similar to comparator 220B, operates, and converts voltage signal VSL into a digital signal by changing the counter value in one-to-one correspondence with a ramp signal RAMP having a ramp waveform. Basically, the AD conversion unit converts the change in the reference signal Vref (for example, the ramp signal RAMP) into a change in voltage into a change in time, and converts that time into a digital value by counting it over a certain period (clock). Then, when the analog signal VSL and the ramp signal RAMP (reference signal Vref) intersect, the output of the comparator 220B is inverted, and the input clock of the counter is stopped, or the clock that had been stopped is input to the counter, and the counter value (data) at that time is stored in the memory unit 230, completing the AD conversion.

[0128] As described above, according to the third embodiment, it is possible to remove the offset of the comparator 220B, and further to achieve low noise, thereby making it possible to achieve a high SNR at low illuminance.

[0129] (Fourth embodiment) FIG. 18 is a circuit diagram showing an example of the configuration of a pixel circuit of a solid-state imaging device 10C according to the fourth embodiment of the present invention.

[0130] The pixel circuit 200C of the solid-state imaging device 10C according to the fourth embodiment differs from the pixel circuit 200 of the solid-state imaging device 10 according to the first embodiment described above in that a specific configuration example of the selection counter circuit 230C is shown.

[0131] In the pixel circuit 200C of the solid-state imaging device 10C according to the fourth embodiment, the selection counter circuit 230C has as its main components an up / down (U / D) counter 233 and a selector 234 that selects a signal to be input to the clock terminal of the up / down counter 231 in accordance with the output comparison result signal of the comparator 220.

[0132] The selector 234 has a first input terminal A connected to a reference potential VSS, a second input terminal B set to a fixed potential in the PFM mode and connected to a supply line of a clock signal SCLK set as a clock pulse of a predetermined frequency in the double sampling readout mode, and an output terminal C connected to a clock terminal CK of the up / down counter 233. The selector 234 switches the connection with the output terminal C from the first input terminal A to the second input terminal B when the output of the comparator 220 is flipped (inverted) in the PFM mode. The selector 234 switches the connection with the output terminal C from the second input terminal B to the first input terminal A when the output of the comparator 220 flips during the double sampling readout mode.

[0133] When an up / down counter is used as in the fourth embodiment, no memory for the reset signals HCGRST and LCGRST is required. That is, it is sufficient for the memory circuit 240 to include a total of three memories: a memory 241 for PFM, a memory 242 for the HCG read signal HCGSIG, and a memory 243 for the LCG read signal LCGSIG.

[0134] Therefore, according to the fourth embodiment, it is possible to obtain the same effects as the first to third embodiments described above, and also to reduce the size of the memory.

[0135] Fifth embodiment FIG. 19 is a circuit diagram showing an example of the configuration of a pixel circuit of a solid-state imaging device 10D according to the fifth embodiment of the present invention.

[0136] A pixel circuit 200D of a solid-state imaging device 10D according to the fifth embodiment differs from the pixel circuit 200 of the solid-state imaging device 10 according to the above-described first embodiment in the configuration of a selection counter circuit 230D.

[0137] In a pixel circuit 200D of a solid-state imaging device 10D according to the fifth embodiment, a selection counter circuit 230D has a counter 235 and a latch 236 as main components. In the selective count circuit 230D, the counter 235 counts the first comparison result signal Vout11 by the comparator 220 in the PFM mode. In the selection counter circuit 223D, in the double sampling read mode, the latch 236 latches the second comparison result signal Vout12 in synchronization with a clock of a predetermined frequency.

[0138] According to the fifth embodiment, it is possible to obtain the same effects as those of the first to third embodiments described above.

[0139] (Applications of solid-state imaging devices) FIG. 20 is a diagram for explaining an example of an application device of the solid-state imaging device according to the embodiment of the present invention. FIG. 21 is a timing diagram showing the operation principle of the application device of FIG.

[0140] The application device 300 in FIG. 20 includes an image sensor 310 to which the solid-state imaging device 10 (10A to 10D) according to the first to fifth embodiments described above is applied, a light emitter 320, and a control unit 333.

[0141] The application device 300 is configured to detect the presence or absence of an object (event) OBJ within a specified range by utilizing the fact that, in PFM mode, during the exposure period PEXP, the pixel circuit included in the image sensor 310 repeatedly performs the following operations: charge overflow operation from the photodiode PD11 to the floating diffusion FD11, a self-reset operation on the floating diffusion FD11 due to a feedback reset operation of the comparison result signal Vout of the comparator, and a count operation of the number of resets (frequency) of the floating diffusion FD11 by the selection count circuit 230.

[0142] As a specific example, under an extremely high illuminance condition, the light emitter 310 projects the detection light DL toward the designated region RGN. In this state, if no object OBJ exists within the designated region RGN, the operation of counting the number of times (frequency) the floating diffusion FD11 is reset is repeatedly performed at a prescribed cycle. Here, when an object OBJ enters the designated region RGN, the detection light DL is reflected by the object OBJ and received by the pixel unit 20 including the pixel circuit 200. As a result, the intensity of the received light changes compared to when the object OBJ is not present, and the time until the potential of the floating diffusion FD11 attenuates to the reference signal Vout11 becomes longer. That is, when an object (event) OBJ is detected, the pulse frequency (number of times) according to the output of the comparator 220 changes, and the control unit 330 judges whether or not an event has been detected depending on the presence or absence of this change.

[0143] (Examples of application to electronic devices) Furthermore, the above-described solid-state imaging devices 10, 10A, 10B, 10C, and 10D can be applied as imaging devices to electronic devices such as digital cameras, video cameras, mobile terminals, surveillance cameras, and medical endoscope cameras.

[0144] FIG. 22 shows a camera system to which the solid-state imaging device according to the embodiment of the present invention is applied. FIG. 13 is a diagram illustrating an example of a configuration of an electronic device.

[0145] As shown in FIG. 22, the electronic device 400 includes a CMOS image sensor 410 to which the solid-state imaging devices 10, 10A, 10B, 10C, and 10D according to the present embodiment can be applied. Furthermore, the electronic device 400 has an optical system (lens or the like) 420 that guides incident light to the pixel region of the CMOS image sensor 410 (forming an image of a subject). The electronic device 400 includes a signal processing circuit (PRC) 430 that processes an output signal from the CMOS image sensor 410 .

[0146] The signal processing circuit 430 performs predetermined signal processing on the output signal of the CMOS image sensor 410 . The image signal processed by the signal processing circuit 430 can be displayed as a moving image on a monitor such as an LCD display, or output to a printer. It can also be recorded directly on a recording medium such as a memory card, and various other forms are possible.

[0147] As described above, by mounting the above-mentioned solid-state imaging devices 10, 10A, 10B, 10C, and 10D as the CMOS image sensor 410, it is possible to provide a high-performance, small-sized, low-cost camera system. This makes it possible to realize electronic devices such as surveillance cameras and medical endoscope cameras that are used in applications where the camera installation requirements include constraints such as mounting size, number of connectable cables, cable length, and installation height. [Explanation of symbols]

[0148] 10, 10A, 10B, 10C, 10D... solid-state imaging device, 20... pixel unit, 200... pixel circuit, PD11... photodiode, FD11... floating diffusion, TG11-Tr... transfer transistor, RST11-Tr, RST12-Tr... reset transistor, SF11-Tr... source follower transistor, SG11-Tr... storage transistor, CS11... storage capacitor, AB11-Tr... anti-blooming transistor, 220 , 220B, 220D... comparator, 230, 230C, 230D... selection counter circuit, 231... selector, 232... counter, 233... up / down counter, 234... selector, 235... counter, 236... latch, 300... application device (event detection device), 310... image sensor, 320... light emitter, 330... control unit, 400... electronic device, 410... CMOS image sensor, 420... optical system, 430... signal processing circuit (PRC).

Claims

1. a readout pixel capable of performing photoelectric conversion and reading out a signal corresponding to an illuminance condition of incident light; a comparator that compares a voltage signal read from the read pixel with a reference signal and outputs a comparison result signal according to the comparison result; a selection counter circuit including a selection circuit capable of selecting either an external clock or a comparator output, and a counter circuit for counting outputs from the selection circuit; having The readout pixel is a photoelectric conversion element that accumulates electric charges according to the amount of incident light during an exposure period; a transfer element that is held in a non-conductive state during the exposure period and held in a conductive state during a transfer period to transfer the charges stored in the photoelectric conversion element; a floating diffusion that holds the charges transferred by the transfer element so as to be read out as a voltage signal; At least one reset element capable of performing a reset process to discharge accumulated charges in the floating diffusion; an overflow path that allows charges overflowing from the photoelectric conversion element to overflow toward the floating diffusion region; Including, The readout pixel, the comparator, the selection circuit, and the counter circuit are Under high illumination conditions, when a voltage signal corresponding to the charge held in the floating diffusion reaches a reference voltage, the floating diffusion is self-reset by a feedback reset operation of the comparison result signal of the comparator, and a pulse frequency modulation (PFM) mode operation is performed in which the number of resets (frequency) of the floating diffusion is counted by the selection counter circuit according to the comparison result signal; Under low illuminance conditions, a double sampling readout mode operation is performed using the accumulated charge and overflow charge of the photoelectric conversion element. Solid-state imaging device.

2. The readout pixel and the selection counter circuit include: The PFM mode or the double sampling readout mode can be selectively operated in response to a mode selection signal; The comparator is In the PFM mode, a constant first reference signal is supplied, and when a voltage signal corresponding to the charge held in the floating diffusion reaches the first reference signal level, a first comparison result signal is output to the readout pixel and the selection counter circuit; In the double sampling readout mode, a second reference signal having a ramp shape that can be continuously changed is supplied, and a comparison result between a voltage signal corresponding to the charge held in the floating diffusion and the second reference signal is outputted to the selection counter circuit as a second comparison result signal; The selection counter circuit includes: In the PFM mode, the first comparison result signal by the comparator is counted; In the double sampling read mode, the second comparison result signal is latched in synchronization with a clock having a predetermined frequency; The readout pixel is In the PFM mode, the first comparison result signal is used as a feedback reset signal to make the reset element conductive and reset the floating diffusion.

2. The solid-state imaging device according to claim 1.

3. The PFM mode is The high illuminance condition is specified during an exposure period after resetting the photoelectric conversion element and the floating diffusion, The double sampling readout mode is specified following the PFM mode.

3. The solid-state imaging device according to claim 1.

4. In the PFM mode, During the exposure period, an overflow operation of charges from the photoelectric conversion element to the floating diffusion, a self-reset operation for the floating diffusion by a feedback reset operation of the comparison result signal of the comparator, and a count operation of the reset frequency of the floating diffusion by the selection counter circuit are repeatedly performed.

4. The solid-state imaging device according to claim 1.

5. When an event occurs, the reset pulse frequency changes.

5. The solid-state imaging device according to claim 4.

6. The readout pixel is a storage element connected to the floating diffusion; a storage capacitance element that stores the charge of the floating diffusion through the storage element; The storage element is disposed between the floating diffusion and the reset element.

6. The solid-state imaging device according to claim 1.

7. In PFM mode, During the self-resetting operation, the reset element and the storage element are maintained in a conductive state, and the floating diffusion and the storage capacitance element are reset.

7. The solid-state imaging device according to claim 6.

8. a source follower element serving as an output buffer unit that converts the charge of the floating diffusion into a voltage signal corresponding to the amount of charge and outputs the converted voltage signal; By selectively connecting the floating diffusion and the storage capacitance element through the storage element, The capacitance of the floating diffusion can be changed to a first capacitance or a second capacitance, so that the conversion gain can be switched to a first conversion gain determined by the first capacitance or a second conversion gain determined by the second capacitance.

8. The solid-state imaging device according to claim 6.

9. a pixel section in which the readout pixels are arranged; a readout unit configured to read out pixel signals from the readout pixels of the pixel unit; The readout unit is When the double sampling read mode is designated following the PFM mode, the storage element is held in a non-conductive state to separate the storage capacitance element from the floating diffusion, and the charge of the floating diffusion and the charge of the storage capacitance element are separated to switch the gain of the floating diffusion to a first conversion gain determined by the first capacitance, a first conversion gain reset readout process for reading out a first readout reset signal converted by a first conversion gain determined by a first capacitance of the floating diffusion from the source follower element as the output buffer unit during a first reset readout period after the reset process, and performing a predetermined process on the first readout reset signal; a first conversion gain readout process for reading out a first readout signal converted with a first conversion gain determined by a first capacitance of the floating diffusion from the source follower element as the output buffer unit during a first readout period following a first transfer period after the first reset readout period, and performing a predetermined process on the first readout signal; After the first conversion gain readout process, the storage element is switched to a conductive state to connect the storage capacitance element to the floating diffusion, and the charge of the floating diffusion and the charge of the storage capacitance element are shared to switch the gain of the floating diffusion to a second conversion gain determined by the second capacitance, a second conversion gain readout process for reading out a second readout signal converted with a second conversion gain determined by a second capacitance of the floating diffusion from the source follower element as the output buffer unit during a second readout period following a second transfer period after the first readout period, and performing a predetermined process on the second readout signal; After resetting the floating diffusion by the reset element, a second readout reset signal converted with a second conversion gain determined by a second capacitance of the floating diffusion as an output node is read out from the source follower element as the output buffer unit, and a second conversion gain reset readout process is performed to perform a predetermined process on the second readout reset signal.

9. The solid-state imaging device according to claim 8.

10. The readout unit is The first conversion gain reset readout process is performed during the exposure period.

10. The solid-state imaging device according to claim 9.

11. The readout unit is Under an extremely low illuminance condition, the second conversion gain reset read process and the second conversion gain read process are performed.

11. The solid-state imaging device according to claim 9.

12. The readout unit is Under a medium illumination condition, the first conversion gain reset readout process, the first conversion gain readout process, the second conversion gain readout process, and the second conversion gain reset readout process are performed.

11. The solid-state imaging device according to claim 9.

13. the source follower element is formed by a source follower transistor having a gate connected to the floating diffusion and a drain connected to a predetermined potential; The comparator is one input terminal is connected to the source of the source follower transistor via a coupling capacitor, and the other input terminal is connected to the input line of the reference signal; An auto-zero switch is connected between the one input terminal and the output terminal.

13. The solid-state imaging device according to claim 8.

14. The selection counter circuit includes: A counter; a selector that selects a signal to be input to the counter in response to a mode selection signal; The selector: When the mode selection signal designates the PFM mode, a comparison result signal of the comparator is supplied to the counter; When the mode selection signal designates a double sampling read mode, a clock pulse having a predetermined frequency is supplied to the counter; The counter is Counting the comparison result signal of the comparator in the PFM mode; A second comparison result signal is latched in synchronization with the clock pulse during a double sampling read mode. The solid-state imaging device according to claim 1 .

15. The selection counter circuit includes: An up / down counter, a selector for selecting a signal to be input to a clock terminal of the up-down counter in response to an output comparison result signal of the comparator; The selector: The first input terminal is connected to a reference potential; a second input terminal is connected to a supply line of a signal which is set to a fixed potential in the PFM mode and is set as a clock pulse of a predetermined frequency in the double sampling readout mode; an output terminal connected to a clock terminal of the up-down counter; When the output of the comparator flips during a PFM mode, the connection with the output terminal is switched from the first input terminal to the second input terminal; When the output of the comparator flips during a double sampling readout mode, the connection with the output terminal is switched from the second input terminal to the first input terminal. The solid-state imaging device according to claim 1 .

16. The selection counter circuit includes: A counter; a latch; In the PFM mode, the counter counts the first comparison result signal by the comparator; In the double sampling read mode, the latch latches the second comparison result signal in synchronization with a clock having a predetermined frequency.

3. The solid-state imaging device according to claim 2.

17. A gate element capable of transferring the accumulated charge of the photoelectric conversion element to the outside of the floating diffusion region.

17. The solid-state imaging device according to claim 1.

18. a readout pixel capable of performing photoelectric conversion and reading out a signal corresponding to an illuminance condition of incident light; a comparator that compares a voltage signal read from the read pixel with a reference signal and outputs a comparison result signal according to the comparison result; a selection counter circuit including a selection circuit capable of selecting either an external clock or a comparator output, and a counter circuit for counting outputs from the selection circuit; having The readout pixel is a photoelectric conversion element that accumulates electric charges according to the amount of incident light during an exposure period; a transfer element that is held in a non-conductive state during the exposure period and held in a conductive state during a transfer period to transfer the charges stored in the photoelectric conversion element; a floating diffusion that holds the charges transferred by the transfer element so as to be read out as a voltage signal; At least one reset element capable of performing a reset process to discharge accumulated charges in the floating diffusion; an overflow path capable of causing the charge overflowing from the photoelectric conversion element to overflow toward the floating diffusion region. A method for driving a solid-state imaging device, comprising: Under high illuminance conditions, when a voltage signal corresponding to the charge held in the floating diffusion reaches a reference voltage, the floating diffusion is self-reset by a feedback reset operation of the comparison result signal of the comparator, and a pulse frequency modulation (PFM) mode operation is performed in which the reset frequency of the floating diffusion is counted by the selection counter circuit according to the comparison result signal; Under low illuminance conditions, a double sampling readout mode operation is performed using the accumulated charge and overflow charge of the photoelectric conversion element. A method for driving a solid-state imaging device.

19. A solid-state imaging device; an optical system that forms a subject image on the solid-state imaging device; The solid-state imaging device includes: a readout pixel capable of performing photoelectric conversion and reading out a signal corresponding to an illuminance condition of incident light; a comparator that compares a voltage signal read from the read pixel with a reference signal and outputs a comparison result signal according to the comparison result; a selection counter circuit including a selection circuit capable of selecting either an external clock or a comparator output, and a counter circuit for counting outputs from the selection circuit; having The readout pixel is a photoelectric conversion element that accumulates electric charges according to the amount of incident light during an exposure period; a transfer element that is held in a non-conductive state during the exposure period and held in a conductive state during a transfer period to transfer the charges stored in the photoelectric conversion element; a floating diffusion that holds the charges transferred by the transfer element so as to be read out as a voltage signal; At least one reset element capable of performing a reset process to discharge accumulated charges in the floating diffusion; an overflow path that allows charges overflowing from the photoelectric conversion element to overflow toward the floating diffusion region; Including, The readout pixel, the comparator, the selection circuit, and the counter circuit are Under high illuminance conditions, when a voltage signal corresponding to the charge held in the floating diffusion reaches a reference voltage, the floating diffusion is self-reset by a feedback reset operation of the comparison result signal of the comparator, and a pulse frequency modulation (PFM) mode operation is performed in which the reset frequency of the floating diffusion is counted by the selection counter circuit according to the comparison result signal; Under low illuminance conditions, a double sampling readout mode operation is performed using the accumulated charge and overflow charge of the photoelectric conversion element. electronic equipment.

Images