Method for forming a semiconductor structure

Abstract

An embodiment of the present disclosure provides a semiconductor structure and a method for forming the same, the method for forming the semiconductor structure includes the steps of: providing a substrate, the substrate including a first isolation trench extending along a first direction and a plurality of active pillars arranged in an array along the first direction and a third direction, the first isolation trench dividing the substrate into a first region and a second region in a second direction, the active pillars being supported by a support structure, any two of the first direction, the second direction and the third direction being perpendicular to each other, and the first direction and the second direction being parallel to a top surface of the substrate; forming a semi-capacitor structure located in the first region and a gate-all-around structure located in the second region in a gap between the active pillars; processing the active pillars and the semi-capacitor structure in the first region to form a capacitor structure extending along the second direction; and forming a first connection structure connecting the gate-all-around structure and the capacitor structure in the first isolation trench.

Description

[Technical field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This disclosure is based on and claims priority to a Chinese patent application having application number 202210686849.3, filing date June 16, 2022, and title "Semiconductor structure and method for forming same," the entire contents of which are incorporated herein by reference.

[0002] TECHNICAL FIELD This disclosure relates to the field of semiconductor technology, including but not limited to semiconductor structures and methods of forming same. [Background technology]

[0003] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers, which consists of many duplicated memory cells, each of which typically includes a capacitor and a transistor.

[0004] In the DRAM of the related art, the transistor is horizontal and the capacitor is vertical to the transistor. With the continuous development of the technology node, the integration density of the DRAM is continuously improved, the size is continuously reduced, the aspect ratio of the capacitor becomes larger and larger, the size of the transistor becomes smaller and smaller, and the process complexity and manufacturing cost of the DRAM gradually increase. Summary of the Invention [Means for solving the problem]

[0005] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same.

[0006] According to a first aspect, embodiments of the present disclosure provide a method of forming a semiconductor structure, the method comprising: providing a substrate, the substrate including a first isolation groove extending along a first direction and a plurality of active pillars arranged in an array along the first direction and a third direction, the first isolation groove dividing the substrate into a first region and a second region in a second direction, the active pillars being supported by a support structure, any two of the first direction, the second direction, and the third direction being perpendicular to each other, and the first direction and the second direction being parallel to a top surface of the substrate; forming a semi-capacitor structure located in the first region and a gate-all-around structure located in the second region in the gaps between the active pillars; processing the active pillars and the semi-capacitor structure in the first region to form a capacitor structure extending along the second direction; forming a first connection structure in the first isolation groove to connect the gate-all-around structure and the capacitor structure.

[0007] According to a second aspect, embodiments of the present disclosure provide a semiconductor structure, the semiconductor structure being formed by the method for forming a semiconductor structure described above, the semiconductor structure comprising: A substrate, the substrate including a first region and a second region arranged along a second direction, the second region including active pillars arranged in an array along a first direction and a third direction, where any two of the first direction, the second direction, and the third direction are perpendicular to each other, and the first direction and the second direction are parallel to an upper surface of the substrate; a capacitor structure located in the first region; a gate-all-around structure located in the second region surrounding a surface of the active pillar; a first connection structure connecting the capacitor structure and the gate-all-around structure; a support structure supporting the capacitor structure and the gate-all-around structure.

[0008] In the semiconductor structure and method for forming the same provided in the embodiments of the present disclosure, the capacitor structure is horizontal, and therefore the horizontal capacitor structure is less likely to tip over or break compared to a vertical capacitor structure with a high aspect ratio, thereby improving the stability of the capacitor structure; and a stacked structure formed by stacking multiple capacitor structures in a third direction can form a three-dimensional semiconductor structure, which can further improve the integration density and miniaturization of the semiconductor structure. [Brief description of the drawings]

[0009] [Figure 1] 1 is a schematic flow chart of a method for forming a semiconductor structure according to an embodiment of the present disclosure. [Figure 2a] 1A-1D are structural schematic diagrams illustrating a process for forming a semiconductor structure according to an embodiment of the present disclosure. [Figure 2b] 1A-1D are structural schematic diagrams illustrating a process for forming a semiconductor structure according to an embodiment of the present disclosure. [Figure 2c] 1A-1D are structural schematic diagrams illustrating a process for forming a semiconductor structure according to an embodiment of the present disclosure. [Figure 2d] 1A-1D are structural schematic diagrams illustrating a process for forming a semiconductor structure according to an embodiment of the present disclosure. [Figure 2e] 1A-1D are structural schematic diagrams illustrating a process for forming a semiconductor structure according to an embodiment of the present disclosure. [Figure 2f] 1A-1D are structural schematic diagrams illustrating a process for forming a semiconductor structure according to an embodiment of the present disclosure. [Figure 2g] 1A-1D are structural schematic diagrams illustrating a process for forming a semiconductor structure according to an embodiment of the present disclosure. [Figure 2h] 1A-1D are structural schematic diagrams illustrating a process for forming a semiconductor structure according to an embodiment of the present disclosure. [Figure 2i] 1A-1D are structural schematic diagrams illustrating a process for forming a semiconductor structure according to an embodiment of the present disclosure. [Figure 2j] 1A-1D are structural schematic diagrams illustrating a process for forming a semiconductor structure according to an embodiment of the present disclosure. [Figure 2k]1A-1D are structural schematic diagrams illustrating a process for forming a semiconductor structure according to an embodiment of the present disclosure. [Figure 2l] 1A-1D are structural schematic diagrams illustrating a process for forming a semiconductor structure according to an embodiment of the present disclosure. [Figure 2m] 1A-1D are structural schematic diagrams illustrating a process for forming a semiconductor structure according to an embodiment of the present disclosure. [Figure 2n] 1A-1D are structural schematic diagrams illustrating a process for forming a semiconductor structure according to an embodiment of the present disclosure. [Figure 3a] 1A-1D are structural schematic diagrams illustrating a process for forming a semiconductor structure according to an embodiment of the present disclosure. [Figure 3b] 1A-1D are structural schematic diagrams illustrating a process for forming a semiconductor structure according to an embodiment of the present disclosure. [Figure 3c] 1A-1D are structural schematic diagrams illustrating a process for forming a semiconductor structure according to an embodiment of the present disclosure. [Figure 3d] 1A-1D are structural schematic diagrams illustrating a process for forming a semiconductor structure according to an embodiment of the present disclosure. [Figure 3e] 1A-1D are structural schematic diagrams illustrating a process for forming a semiconductor structure according to an embodiment of the present disclosure. [Figure 3f] 1A-1D are structural schematic diagrams illustrating a process for forming a semiconductor structure according to an embodiment of the present disclosure. [Figure 3g] 1A-1D are structural schematic diagrams illustrating a process for forming a semiconductor structure according to an embodiment of the present disclosure. [Figure 3h] 1A-1D are structural schematic diagrams illustrating a process for forming a semiconductor structure according to an embodiment of the present disclosure. [Figure 3i] 1A-1D are structural schematic diagrams illustrating a process for forming a semiconductor structure according to an embodiment of the present disclosure. [Figure 3j] 1A-1D are structural schematic diagrams illustrating a process for forming a semiconductor structure according to an embodiment of the present disclosure. [Figure 3k] 1A-1D are structural schematic diagrams illustrating a process for forming a semiconductor structure according to an embodiment of the present disclosure. [Figure 3l] 1A-1D are structural schematic diagrams illustrating a process for forming a semiconductor structure according to an embodiment of the present disclosure. [Figure 3m]1A-1D are structural schematic diagrams illustrating a process for forming a semiconductor structure according to an embodiment of the present disclosure. [Figure 4] 1 is a cross-sectional view of a semiconductor structure according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In the drawings, which are not necessarily drawn to scale, like reference numbers may indicate like parts in different views. Like reference numbers with different alphabetical suffixes may represent different instances of like parts. The drawings illustrate embodiments described herein by way of example, not by way of limitation.

[0011] The exemplary embodiments disclosed in the present disclosure will be described in more detail below with reference to the drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be realized in various forms and should not be limited to the specific embodiments described herein. On the contrary, these embodiments are provided so that the present disclosure may be more fully understood and the scope of the present disclosure may be fully conveyed to those skilled in the art.

[0012] In the following description, many details are described to provide a more complete understanding of the present disclosure. However, it is clear to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, some known technical features in the art are omitted so as not to obscure the present disclosure. That is, this specification does not describe all the features of the actual embodiment, and does not describe well-known functions and structures in detail.

[0013] For clarity, in the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated. Like numbers in all drawings represent like elements.

[0014] When an element or layer is described as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it should be understood that it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or that there may be intervening elements or layers. Conversely, when an element is described as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, it is meant that there are no intervening elements or layers. Although terms such as first, second, and third may be used to describe various elements, components, regions, layers, and / or sections, it should be understood that these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, without departing from the teachings of this disclosure, a first element, component, region, layer, or section described below may be described as a second element, component, region, layer, or section. The description of a second element, component, region, layer or section does not imply that the first element, component, region, layer or section is necessarily present in the present disclosure.

[0015] The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the disclosure. Unless otherwise specified herein, the singular forms "a", "one" and "the" are intended to include the plural forms. It is also to be understood that the terms "comprise" and / or "comprise" as used herein are used to clarify the presence of the overstated features, integers, steps, operations, elements and / or components, and do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or sets. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0016] Before introducing the embodiments of the present disclosure, first, three directions representing a three-dimensional structure that may be used in the following embodiments are defined. Taking the Cartesian coordinate system as an example, the three directions can include the X-axis, Y-axis, and Z-axis directions. The substrate can include a top surface on the front side and a bottom surface on the back side opposite to the front side. When the flatness of the top and bottom surfaces is ignored, a direction perpendicular to the top and bottom surfaces of the substrate is defined as a third direction. In the directions of the top and bottom surfaces of the substrate (i.e., the plane on which the substrate is located), two directions that intersect with each other (e.g., perpendicular to each other) are defined. For example, the direction in which the first isolation trench extends can be defined as a first direction, and the direction in which the third isolation trench extends can be defined as a second direction, and the planar direction of the semiconductor base can be determined by the first direction and the second direction. Here, any two of the first direction, the second direction, and the third direction are perpendicular to each other. In the embodiments of the present disclosure, the first direction is defined as the X-axis direction, the second direction is defined as the Y-axis direction, and the third direction is defined as the Z-axis direction.

[0017] An embodiment of the present disclosure provides a method for forming a semiconductor structure, and FIG. 1 is a schematic flow chart of the method for forming a semiconductor structure according to an embodiment of the present disclosure. As shown in FIG. 1, the method for forming a semiconductor structure includes the following steps:

[0018] In step S101, a substrate is provided, the substrate including a first isolation groove extending along a first direction and a plurality of active pillars arranged in an array along the first direction and a third direction, where the first isolation groove divides the substrate into a first region and a second region in the second direction, and the active pillars are supported by a support structure.

[0019] In embodiments of the present disclosure, the substrate includes at least a semiconductor base, which may be silicon-based, or may include other semiconductor elements such as germanium (Ge), or may include semiconductor compounds such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or may include other semiconductor alloys such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (GaInAs), indium gallium phosphide (GaInP), and / or indium gallium arsenide phosphide (GaInAsP), or combinations thereof.

[0020] In an embodiment of the present disclosure, the first isolation trench divides the substrate in the second direction into a first region and a second region, and the first region and the second region may be used to form different functional structures, for example, the first region may be used to form a capacitor structure, and the second region may be used to form a gate-all-around structure, a bit line structure, or a stepped word line structure.

[0021] In an embodiment of the present disclosure, the substrate includes a plurality of active pillars and support structures arranged in an array along a first direction and a third direction, with the active pillars being supported by the support structures between them, and each active pillar is used to form one transistor.

[0022] The supporting structure extends along the first direction and the third direction, and the supporting structure may be located on the surface of the semiconductor base or may extend into the interior of the semiconductor base, thereby achieving a better supporting effect.

[0023] In the embodiments of the present disclosure, the active pillar may be a quadrilateral pillar (eg, a square pillar, a hexagonal pillar, an octagonal pillar) or a circular pillar.

[0024] In step S102, a semi-capacitor structure located in a first region and a gate-all-around structure located in a second region are formed in the gaps between the active pillars.

[0025] In the embodiment of the present disclosure, the first region is used to form a capacitor structure, and the second region is used to form a gate-all-around structure. A semi-capacitor structure is not a complete capacitor structure, but a part of a capacitor structure, such as a capacitor structure that includes only one electrode layer, or a capacitor structure that includes only a dielectric layer and one electrode layer.

[0026] In embodiments of the present disclosure, the gate-all-around structure formed has a wide channel region, which can reduce short channel effects and improve gate controllability, thereby improving the performance of the semiconductor structure formed.

[0027] In step S103, the active pillars and semi-capacitor structures in the first region are processed to form capacitor structures extending along a second direction.

[0028] In embodiments of the present disclosure, the active pillars in the first region can be processed to convert a semi-capacitor structure into a full capacitor structure, for example, by forming an electrode layer in the first region, or by forming a dielectric layer and an electrode layer in the first region.

[0029] In the embodiments of the present disclosure, the capacitor structures formed are arranged at intervals along a first direction and a third direction and extend along a second direction, i.e., the capacitor structures formed in the embodiments of the present disclosure are arranged horizontally, and the horizontal capacitor structures can reduce the likelihood of tipping or breaking, thereby improving the stability of the capacitor structures.

[0030] In step S104, a first connection structure is formed in the first isolation trench to connect the gate-all-around structure and the capacitor structure.

[0031] When implemented, a wire can be epitaxially grown on a channel surface in the gate-all-around structure as a first connecting structure, the first connecting structure extending along a second direction and electrically connected to an electrode layer of the capacitor structure.

[0032] In the embodiment of the present disclosure, first, a first isolation trench extending along a first direction and a plurality of active pillars arranged in an array along the first direction and the third direction are formed on a substrate, the substrate is divided into a first region and a second region in the first direction by the first isolation trench, thereby realizing the manufacture of different functional devices in different regions, then, in the gap between the active pillars, a semi-capacitor structure located in the first region and a gate-all-around structure located in the second region are formed, and further, the active pillars and the semi-capacitor structure in the first region are processed to form a capacitor structure extending along the second direction, the capacitor structure including a semi-capacitor structure, and finally, a first connection structure connecting the gate-all-around structure and the capacitor structure in the first isolation trench is formed. Since the gate-all-around structure and the semi-capacitor structure constituting the capacitor structure are formed simultaneously, the manufacturing process flow of the semiconductor structure can be simplified and the manufacturing cost of the semiconductor structure can be reduced. In addition, the capacitor structure in the embodiment of the present disclosure extends along a second direction, i.e., the capacitor structure in the embodiment of the present disclosure is horizontal, and compared to a vertical capacitor structure with a high aspect ratio, the horizontal capacitor structure can be less likely to tip over or break, thereby improving the stability of the capacitor structure, and a stacked structure formed by stacking multiple capacitor structures in a third direction can form a three-dimensional semiconductor structure, further improving the integration density and miniaturization of the semiconductor structure.

[0033] 2a-2n and 3a-3m are structural schematic diagrams in a process of forming a semiconductor structure according to an embodiment of the present disclosure, where FIG. 2a is a three-dimensional structural schematic diagram, FIG. 2b is a cross-sectional view along a-a' and b-b' of the stacked structure in FIG. 2a, and in order to facilitate detailed description of the internal structure of the formed semiconductor structure, FIG. 2c-2n and FIG. 3a-3m in the subsequent forming process are all shown at the viewing angles of the cross-sectional views along a-a' and b-b'. Next, the process of forming a semiconductor structure according to an embodiment of the present disclosure will be described in detail with reference to FIG. 2a-2n and FIG. 3a-3m.

[0034] 2a to 2n, step S101 may be performed. In step S101, a substrate is provided, the substrate including a first isolation groove 12 extending along a first direction and a plurality of active pillars 110 arranged in an array along the first direction and the third direction, where the first isolation groove 12 divides the substrate into a first region A and a second region B in the second direction, and the active pillars 110 are supported by a support structure 14.

[0035] In some embodiments, a substrate can be formed by providing a semiconductor base 10, forming a laminate structure 11 on the semiconductor base 10, the laminate structure 11 including a first semiconductor layer 111 and a second semiconductor layer 112 stacked alternately, etching the laminate structure 11 to form a first isolation groove 12, and removing the first semiconductor layer 111 in the laminate structure 11.

[0036] As shown in FIG. 2a-FIG. 2b, a laminated structure 11 is formed on a semiconductor base 10 by alternately stacking a first semiconductor layer 111 and a second semiconductor layer 112. The material of the first semiconductor layer 111 may be germanium, silicon germanium, silicon carbide, silicon-on-insulator (SOI) or germanium-on-insulator (GOI). The second semiconductor layer 112 may be a silicon layer, or may contain other semiconductor elements, such as germanium, or may contain semiconductor compounds, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide or indium antimonide, or may contain other semiconductor alloys, such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, indium gallium arsenide, indium gallium phosphide, and / or indium gallium arsenide phosphide, or combinations thereof.

[0037] In the embodiment of the present disclosure, since it is necessary to subsequently etch and remove the first semiconductor layer 111 and leave the second semiconductor layer 112, the first semiconductor layer 111 has a high etching selectivity with respect to the second semiconductor layer 112, that is, under the same etching conditions, the first semiconductor layer 111 is more likely to be etched and removed than the second semiconductor layer 112. For example, the first semiconductor layer 111 may be a silicon germanium layer, and the second semiconductor layer 112 may be a silicon layer.

[0038] In the embodiment of the present disclosure, the first semiconductor layer 111 and the second semiconductor layer 112 can be formed by an epitaxial process. The first semiconductor layer 111 and the second semiconductor layer 112 can be alternately stacked to form a semiconductor superlattice, and the thickness of each semiconductor layer varies from a few atoms to several tens of atoms, and the main semiconductor properties of each layer, such as band gap and doping level, can be controlled independently. The number of layers of the first semiconductor layer 111 and the second semiconductor layer 112 in the stacked structure 11 can be set according to the required capacitor density (or memory density), and the more the number of layers of the first semiconductor layer 111 and the second semiconductor layer 112, the higher the integration degree and the higher the capacitor density of the formed three-dimensional memory. For example, the number of layers of the first semiconductor layer 111 and the second semiconductor layer 112 can be 2 to 2000 layers.

[0039] In some embodiments, before forming the first isolation trench 12 , the method for forming a semiconductor structure further includes etching the stacked structure 11 and a portion of the semiconductor base 10 to form a third isolation trench 13 .

[0040] As shown in Figures 2c and 2d, the third isolation groove 13 can be formed by the following steps: first, a first mask layer 151, a first anti-reflective layer 311, and a first photoresist layer 161 having a specific pattern H are sequentially formed on the surface of the laminated structure 11; then, the first anti-reflective layer 311 and the first mask layer 151 are sequentially etched by the first photoresist layer 161 to transfer the specific pattern H to the first mask layer 151; finally, the laminated structure 11 and a part of the semiconductor base 10 are etched by the first mask layer having the specific pattern H to form the third isolation groove 13. In the embodiment of the present disclosure, the bottom of the formed third isolation groove 13 is located in the semiconductor base 10; in other embodiments, the third isolation groove 13 may not extend into the semiconductor base 10, but may only be located in the laminated structure 11.

[0041] In the embodiment of the present disclosure, the first anti-reflective layer 311 is used to absorb the reflected light on the surface of the laminated structure 11, and avoid the occurrence of interference between the reflected light and the incident light. The material of the first anti-reflective layer 311 may be silicon oxynitride or a spin-coated carbon layer. The material used for the first mask layer 151 may be one or more of silica, silicon nitride, silicon carbide, and silicon oxynitride. The first mask layer 151 and the first anti-reflective layer 311 may be formed by any one suitable deposition process.

[0042] In an embodiment of the present disclosure, the third isolation trench 13 divides the second region B in the first direction into a first portion B-1 and a second portion B-2, where the first portion B-1 may be used to form a gate-all-around structure and the second portion B-2 may be used to form a stepped word line structure.

[0043] In some embodiments, after forming the third isolation grooves 13, the method for forming a semiconductor structure further includes removing the first photoresist layer 161, the first anti-reflective layer 311, and the first mask layer 151. In embodiments of the present disclosure, a dry etching technique (e.g., a plasma etching technique, a reactive ion etching technique, or an ion milling technique) or a wet etching technique can be used to remove the first photoresist layer 161, the first anti-reflective layer 311, and the first mask layer 151 to expose the surface of the stacked structure 11 (as shown in FIG. 2d).

[0044] FIG. 2e is an overhead view of the first region. As shown in FIG. 2e, after forming the third isolation trench 13 and before forming the first isolation trench 12, the method of the semiconductor structure further includes the steps of etching the stacked structure to form a fifth isolation trench 31 extending along the second direction, where the fifth isolation trench 31 divides the second semiconductor layer 112 into a plurality of active pillars 110 arranged along the first direction, and forming an isolation structure 311 in the fifth isolation trench 31.

[0045] In the embodiment of the present disclosure, the material forming the isolation structures 311 may be silica, silicon nitride, or silicon oxynitride. The isolation structures 311 are used to fill the voids between adjacent active pillars 110, facilitating the subsequent formation of other structures between the active pillars 110 and the isolation structures 311.

[0046] In some embodiments, after forming the isolation structure 311 and before forming the first isolation trench 12, the method for forming the semiconductor structure further includes the steps of etching away a portion of the isolation structure 311 and a portion of the first semiconductor layer 111 to form a plurality of etching holes 141 extending along a first direction, where the etching holes 141 expose the active pillars 110, and filling the etching holes 141 with a support material to form a support structure 14 surrounding the active pillars 110.

[0047] In the embodiment of the present disclosure, as shown in FIGS. 2f to 2h, the support structure 14 may be formed by the following steps. First, a second mask layer 152, a second anti-reflective layer 312, and a second photoresist layer 162 having a specific pattern I are sequentially formed on the surface of the stacked structure 11, where the specific pattern I may be a plurality of openings extending along the X-axis direction; then, the second anti-reflective layer 312 and the second mask layer 152 are sequentially etched by the second photoresist layer 162 to transfer the specific pattern I to the second mask layer 152; further, a part of the isolation structure 311 and a part of the first semiconductor layer 111 are etched and removed by the second mask layer having the specific pattern I to form a plurality of etching holes 141 extending along the X-axis direction; and finally, the etching holes 141 are filled with a support material to form the support structure 14 surrounding the active pillars 110. The material used for the second mask layer 152 may be one or more of silica, silicon nitride, silicon carbide, and silicon oxynitride. The material of the second anti-reflective layer 312 may be silicon oxynitride or spin-coated carbon. The supporting material may be silicon nitride or silicon carbonitride.

[0048] In the embodiment of the present disclosure, the support structure 14 may extend into the semiconductor base 10 to achieve a more stable supporting effect.

[0049] In the embodiments of the present disclosure, the support structure 14 may be used to support the active pillars 110, and for subsequently forming a capacitor structure and a gate-all-around structure between adjacent active pillars 110, the support structure 14 may further be used to support the capacitor structure and the gate-all-around structure, thereby improving the stability of the formed semiconductor structure.

[0050] In some embodiments, after forming the etching holes 141, the method for forming a semiconductor structure further includes removing the second photoresist layer 162, the second anti-reflective layer 312, and the second mask layer 152. When performed, a dry etching technique or a wet etching technique can be used to remove the second photoresist layer 162, the second anti-reflective layer 312, and the second mask layer 152 to expose the surface of the laminate structure 11 (as shown in FIG. 2h).

[0051] As shown in Figures 2i and 2j, the first isolation groove 12 can be formed by the following steps. First, a third mask layer 153 and a third photoresist layer 163 having a specific pattern C are sequentially formed on the surface of the laminated structure 11, the specific pattern C may be an opening extending along the X-axis direction, and the projection of the specific pattern C on the semiconductor base 10 is adjacent to one of the projections of the specific pattern I on the semiconductor base 10 in the Y-axis direction. Then, the third mask layer 153 is etched by the third photoresist layer 163 to transfer the specific pattern C to the third mask layer 153, and the laminated structure 11 and the isolation structure 311 are etched by the third mask layer having the specific pattern C to form the first isolation groove 12, and the adjacent support structure 14 is exposed by the first isolation groove 12. In the embodiment of the present disclosure, the first isolation groove 12 extends into the semiconductor base 10 to achieve a better isolation effect.

[0052] In the embodiment of the present disclosure, the first isolation trench 12 divides the substrate in the Y-axis direction into a first region A and a second region B, where the first region A is used to form a capacitor structure, and the second region B is used to form a gate-all-around structure, a bit line structure and a stepped word line structure.

[0053] In another embodiment, the first isolation grooves 12 may further be located only on the surface of the semiconductor base 10 .

[0054] In an embodiment of the present disclosure, after forming the first isolation grooves 12, the method for forming a semiconductor structure further includes removing the third mask layer 153 and the third photoresist layer 163. When performed, the third mask layer 153 and the third photoresist layer 163 can be removed using a dry etching technique or a wet etching technique.

[0055] In some embodiments, after forming the first isolation trenches 12, the method for forming a semiconductor structure further includes filling the first isolation trenches 12 with a sacrificial material to form a sacrificial layer 121, as shown in FIG. 2k.

[0056] In an embodiment of the present disclosure, the sacrificial layer 121 may be silicon oxynitride, which is used to protect the cross section of the second semiconductor layer 112 from damage during the subsequent removal of the first semiconductor layer 111, and is convenient for the subsequent epitaxial formation of a connecting structure connecting the gate-all-around structure and the stepped word line structure to the cross section of the second semiconductor layer 112.

[0057] As shown in FIG. 2l, the first semiconductor layer 111 in the laminated structure 11 is removed.

[0058] In the embodiment of the present disclosure, the first semiconductor layer 111 in the laminate structure 11 may be removed by wet etching (e.g., etching using a strong acid such as concentrated sulfuric acid, hydrofluoric acid, concentrated nitric acid, etc.) or dry etching technology. Since the first semiconductor layer 111 has a high etching selectivity with respect to the second semiconductor layer 112, the second semiconductor layer 112 is not damaged when the first semiconductor layer 111 is removed.

[0059] 2l, in some embodiments, after removing the first semiconductor layer 111, the method of forming a semiconductor structure further includes removing the sacrificial layer 121, the protective layer 131, and the isolation structures 311. For example, the sacrificial layer 121, the protective layer 131, and the isolation structures 311 may be removed using a wet etching technique.

[0060] In some embodiments, as shown in FIG. 2m, the method for forming a semiconductor structure further includes performing a thinning process on the active pillars 110. In the embodiments of the present disclosure, the thinning process is performed on the active pillars 110, so that the gap between two adjacent active pillars 110 is increased, which on the one hand can improve the effective area of ​​the capacitor structure, thereby improving the capacitance of the capacitor structure, and on the other hand can provide a larger space in advance for the subsequent formation of the capacitor structure and the gate-all-around structure, thereby reducing the process complexity.

[0061] In the embodiment of the present disclosure, the active pillars 110 can be thinned in the following two ways.

[0062] In method 1, dry etching is performed directly on the active pillars 110, and the etching is stopped after a required thickness is formed.

[0063] In Method 2, the active pillars 110 are subjected to an in-situ oxidation process, a part of the active pillars 110 is oxidized to a silica layer, and the silica layer is removed by wet etching or dry etching technology.

[0064] It should be noted that in other embodiments, the active pillars 110 may not require a thinning process.

[0065] Next, referring to FIG. 2n, step S102 can be performed, in which a semi-capacitor structure 18 located in the first region A and a gate-all-around structure 17 located in the second region B are formed in the gaps between the active pillars 110.

[0066] In some embodiments, the semi-capacitor structure 18 and the gate-all-around structure 17 are provided on the surfaces of the active pillars 110 in the first region A and the second region B. medium It may be formed by sequentially forming a layer 171 and a first metal layer 173 .

[0067] In some embodiments, medium The layer 171 may be a single layer or multiple layers. For example, in the embodiment of the present disclosure, medium Layer 171 is the first medium Layer 1711 and 2 medium layer 1712. Here, the first medium The material of the layer 1711 may be silica or another suitable material. medium The material of layer 1712 may be one or any combination of high-k materials, such as lanthanum oxide, aluminum oxide, hafnium oxide, hafnium oxynitride, niobium oxide, hafnium silicate, or zirconium oxide, and the material of the first metal layer may be any one of a number of well-conductive materials, such as titanium nitride.

[0068] In the embodiment of the present disclosure, the second medium When the layer 1712 can be a dielectric layer of a capacitor structure, the second layer located in the first region A medium Layer 1712 and first metal layer 173 form semi-capacitor structure 18. In another embodiment, medium If the layer 1712 cannot be a dielectric layer of the capacitor structure, the semi-capacitor structure 18 includes a first metal layer 173. medium Layer 1711, 2nd medium The layer 1712 and the first metal layer 173 form a gate-all-around structure.

[0069] In the embodiment of the present disclosure, the first medium Layer 1711, 2nd medium Layer 1712 and first metal layer 173 may be formed by any of a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a spin coating process, a coating process, or a thin film process, etc.

[0070] In the embodiment of the present disclosure, the first metal layer 173 located in the first region A constitutes the lower electrode layer of the capacitor structure, and the medium The layer 171 and the first metal layer 173 are the gates of the gate-all-around structure 17. medium In the embodiment of the present disclosure, the gate-all-around structure 17 and the lower electrode layer of the capacitor structure are simultaneously formed, which simplifies the manufacturing process flow of the semiconductor structure and reduces the manufacturing cost of the semiconductor structure.

[0071] In the embodiments of the present disclosure, the gate-all-around structure 17 has a wide channel region, which can reduce short channel effects and improve gate controllability, thereby improving the performance of the formed semiconductor structure.

[0072] It should be noted that, at the same time as forming the gate-all-around structure 17 and the semi-capacitor structure 18, the inner walls of the first isolation trench 12 and the third isolation trench 13 are also medium A layer 171 and a first metal layer 173 are formed.

[0073] Continuing to refer to FIG. 2n, after forming the first metal layer 173, the method for forming the semiconductor structure further includes filling a surface of the first metal layer 173 and gaps between the first metal layers 173 with a first isolation material to form a first isolation layer 19.

[0074] In the embodiments of the present disclosure, the first isolation layer 19 may be used to isolate adjacent first metal layers 173 and prevent electrical leakage of the first metal layers 173. The first isolation material may be silica, silicon nitride, silicon oxynitride, or other suitable material.

[0075] Next, referring to FIGS. 3a-3c, step S103 may be performed, in which the active pillars 110 and the semi-capacitor structures in the first region A are processed to form capacitor structures 20 extending along the second direction.

[0076] In some embodiments, the second medium When the layer 1712 can be a dielectric layer of the capacitor structure 20, step S103 can be formed by the following steps: As shown in FIGS. 3a to 3c, a first opening 21 extending along the X-axis direction is formed in the first region A, the first opening 21 exposes the semiconductor base 10, and the first opening 21 exposes the active pillar 110 and the first insulating layer 112 in the first region A. medium The layer 1711 is removed to form the first gap 22 , and a second metal material is deposited in the first opening 21 and the first gap 22 to form the second metal layer 174 .

[0077] In another embodiment, the second medium If the layer 1712 cannot be the dielectric layer of the capacitor structure 20, step S103 can further include the following steps: forming a first opening 21 extending along the X-axis direction in the first region A, exposing the semiconductor base 10 through the first opening 21, and forming an active pillar 110 and a capacitor structure 20 in the first region A through the first opening 21. mediumLayer 171 is removed to form first gap 22, and a dielectric material and a second metal material are sequentially deposited in first opening 21 and first gap 22 to form dielectric layer 172 and second metal layer 174. At this time, second metal layer 174 constitutes the upper electrode of capacitor structure 20, and first metal layer 173, dielectric layer 172 and second metal layer 174 located in first region A constitute capacitor structure 20.

[0078] 3a and 3b, in some embodiments, the first opening 21 can be formed by the following steps: forming a fourth photoresist layer 164 having a specific pattern D on the surface of the first isolation layer 19, in which the first isolation layer 19 can be a mask layer for forming the first opening 21, etching the first isolation layer 19 through the fourth photoresist layer 164 to transfer the specific pattern D to the first isolation layer 19, and etching the stacked structure 11 through the first isolation layer 19 having the specific pattern D until the semiconductor base 10 is exposed, thereby forming the first opening 21.

[0079] In the embodiment of the present disclosure, the material of the dielectric layer is a high-k medium For example, lanthanum oxide (La2O3), aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), niobium oxide (NbO), hafnium silicate (HfSiO X The second metal material may be one or any combination of titanium, tungsten, molybdenum, a metal nitride, or a metal silicide. The dielectric material and the second metal material may be formed by any one deposition process.

[0080] Finally, referring to FIGS. 3d to 3f, step S104 can be performed, in which a first connection structure 23 is formed to connect the gate-all-around structure 17 and the capacitor structure 20 in the first isolation trench 12.

[0081] In some embodiments, the first connection structure 23 can be formed by the following steps: removing the first isolation layer 19 located in the first isolation groove 12, and forming a first insulating layer 19 on the sidewall of the second region B located in the first isolation groove 12. medium the layer 171 and the first metal layer 173 are removed to form a second isolation trench 12a extending along a first direction, where the second isolation trench 12a exposes the active pillar 110 in the second region B and the first metal layer 173 on the sidewall of the first region A, and a first connection structure 23 is epitaxially grown on the exposed surface of the active pillar 110, where the first connection structure 23 contacts the first metal layer 173 in the first region.

[0082] 3d-3f, the first connection structure 23 can be formed by the following steps: forming a fifth photoresist layer 165 having a specific pattern E on the surface of the first isolation layer 19, in which the first isolation layer 19 can be used as a mask layer for forming the second isolation groove 12a, etching the first isolation layer 19 by the fifth photoresist layer 165, transferring the specific pattern E to the first isolation layer 19, and forming the first isolation layer 19 located in the first isolation groove 12 by the first isolation layer having the specific pattern E; medium layer 171 and first metal layer 173 are etched away to form second isolation trenches 12a extending along the X-axis direction, which expose the active pillars 110 in the second region B and the first metal layer 173 on the sidewalls of the first region A through the second isolation trenches 12a, and a first semiconductor material is epitaxially grown on the exposed surfaces of the active pillars 110 to form a first connection structure 23, which contacts the first metal layer 173 in the first region A.

[0083] In the embodiment of the present disclosure, the first connection structure 23 can be a heteroepitaxial layer, so that the first semiconductor material can be silicon germanium, and the germanium content in the silicon germanium can be 5% to 50%. The thickness of the first connection structure 23 is 20 angstroms (Å) to 200 Å.

[0084] In embodiments of the present disclosure, the epitaxial growth may be vapor phase epitaxial, liquid phase epitaxial, molecular beam epitaxial, or metal organic chemical vapor deposition. The selectivity of the epitaxial growth process can be exploited to achieve self-aligned connection of the gate-all-around structure 17 and the capacitor structure 20. Continuing to refer to FIG. 3f, after forming the first connection structure 23, the method for forming the semiconductor structure further includes filling the gaps in the second isolation grooves 12a and between the first connection structures 23 with a second isolation material to form a second isolation layer 24, where the surface of the second isolation layer 24 is flush with the surface of the first isolation layer 19.

[0085] In the embodiment of the present disclosure, the second isolation layer 24 may be used to isolate adjacent first connection structures 23. The material of the second isolation layer 24 may be silica, silicon nitride, silicon oxynitride, or other suitable material.

[0086] In some embodiments, referring to Figures 3g to 3m, after forming the second isolation layer 24, the method of forming the semiconductor structure further includes forming a bit line structure 25 and a stepped word line structure 26 connected to the gate-all-around structure 17.

[0087] In some embodiments, the bitline structure 25 may be formed by the following steps: etching one end of the active pillar 110 away from the capacitor structure 20 to form a bitline trench extending along a first direction, exposing the semiconductor base 10 in the second region through the bitline trench, and filling the bitline trench with a bitline metal material to form the bitline structure 25.

[0088] As shown in Figures 3g and 3h, a sixth photoresist layer 166 having a specific pattern F is formed on the surface of the first isolation layer 19, at this time, the first isolation layer 19 and the second isolation layer 24 can be used as a mask layer for forming a bit line groove, the first isolation layer 19 is etched by the sixth photoresist layer 166 to transfer the specific pattern E to the first isolation layer 19, one end of the active pillar 110 away from the capacitor structure 20 is etched by the first isolation layer 19 having the specific pattern F to form a bit line groove (not shown) extending along the X-axis direction, the semiconductor base 10 in the second region B is exposed by the bit line groove, and the bit line groove is filled with a bit line metal material to form a bit line structure 25.

[0089] In embodiments of the present disclosure, the bitline metal material includes tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), a titanium-containing metal layer, polycrystalline silicon, or any combination thereof.

[0090] In some embodiments, the relationship between the bit line structure 25, the gate-all-around structure 17, and the support structure 14 includes the following two: In the first case, the support structure 14 is located in the middle of the gate-all-around structure 17, and the gate-all-around structure 17 contacts the bit line structure 25, as shown in FIG. 3h; In the second case, the support structure 14 is located at one end of the gate-all-around structure away from the capacitor structure (i.e., at the rightmost end of the gate-all-around structure 17), and in this case, the support structure contacts the bit line structure 25, and the bit line structure 25 and the gate-all-around structure 17 are isolated by the support structure 14.

[0091] In some embodiments, before forming the stepped word line structure 26, the method of forming the semiconductor structure includes forming the first isolation layer 19 located in the third isolation trench 13, mediumThe method further includes the steps of removing the layer 171 and the first metal layer 173 to form a fourth isolation groove 13a extending along the second direction, where the fourth isolation groove 13a exposes the first metal layer 173 of the first portion and the active pillar 110 of the second portion, and forming a second connection structure 27 in the fourth isolation groove 13a to connect the second portion and the gate-all-around structure 17.

[0092] In some embodiments, as shown in FIGS. 3i to 3j, the fourth isolation trench 13a can be formed by the following steps: forming a seventh photoresist layer 167 having a specific pattern G on the surface of the first isolation layer 19, in which the first isolation layer 19 and the second isolation layer 24 can be used as mask layers for forming the fourth isolation trench 13a, etching the first isolation layer 19 by the seventh photoresist layer 167 to transfer the specific pattern G to the first isolation layer 19, etching and removing the first isolation layer 19 located in the third isolation trench 13 by the first isolation layer 19 having the specific pattern G, and forming a fourth isolation trench 13a on the sidewall of the second portion B-2 located in the third isolation trench 13. medium The layer 171 and the first metal layer 173 are removed to form a fourth isolation trench 13a extending along the Y-axis direction, where the fourth isolation trench 13a exposes the first metal layer 173 on the sidewall of the first portion B-1 and the active pillar 110 of the second portion B-2.

[0093] In the embodiment of the present disclosure, the fourth isolation trench 13a is used to form a second connection structure 27 connecting the second portion B-2 and the gate-all-around structure 17. As shown in Fig. 3k, the second connection structure 27 is formed by the following steps: epitaxially growing a second semiconductor material on the exposed surface of the active pillar 110 of the second portion B-2 to form the second connection structure 27, where the second connection structure 27 contacts the first metal layer 173 in the first portion B-1.

[0094] In the embodiment of the present disclosure, the second connecting structure 27 can be a homoepitaxial layer, so that the second semiconductor material can be silicon, and the thickness of the second connecting structure 27 is between 20 Å and 200 Å.

[0095] In embodiments of the present disclosure, epitaxial growth may be vapor phase epitaxial, liquid phase epitaxial, molecular beam epitaxial, or metal organic chemical vapor deposition.

[0096] In some embodiments, still referring to FIG. 3k, after forming the second connecting structure 27, the method of forming the semiconductor structure may further include: medium Forming an insulating layer 175 medium The surface of layer 175 is medium A step flush with the surface of layer 171 and an insulating medium The method further includes a step of forming a third metal layer 176 on the surface of layer 175, the surface of which is flush with the surface of the first metal layer 173, and a step of filling the surface of the third metal layer 176 and the gap between the third metal layer 176 with a third isolation material to form a third isolation layer 28, the surface of which is flush with the surface of the first isolation layer 19.

[0097] In the embodiment of the present disclosure, insulation medium The material of the layer 175 may be silica, silicon nitride, or silicon oxynitride, for example, silica. The third isolation layer 28 may be used to isolate adjacent third metal layers 176 and prevent electrical leakage of the third metal layers 176. The material of the third isolation layer 28 may be silica, silicon nitride, silicon oxynitride, or other suitable material. The material of the third metal layer 176 may be any one of the well-conductive materials, such as tungsten.

[0098] In some embodiments, the gate-all-around structure 17 is divided in the X-axis direction into a first portion B-1 and a second portion B-2 by the third isolation trench 13, and the stepped word-line structure 26 is formed by the following steps: forming a photoresist layer having a second opening on a surface of the second portion, exposing an end of the second portion away from the first portion through the second opening, and etching the second portion multiple times through the photoresist layer to form the stepped word-line structure 26, where the size of the second opening in the first direction is successively increased during the multiple etching processes.

[0099] In some embodiments, the stepped wordline structure 26 may be formed by the following steps. First, a photoresist layer having a second opening is formed on a surface of the second portion B-2, one end of the second portion away from the first portion is exposed by the second opening, and the second portion B-2 is etched by the photoresist layer having the second opening to form a first step structure, where the first step structure includes one step; next, a photoresist layer having a third opening is formed on the surface of the first step structure, a portion of the first step structure is exposed by the third opening, and the first step structure is etched by the photoresist layer having the third opening to form a second step structure, where the second step structure includes two steps, and the size of the third opening in the X-axis direction is larger than the size of the second opening; further, a photoresist layer having a fourth opening is formed on the surface of the second step structure, a portion of the second step structure is exposed by the fourth opening, and the second step structure is etched by the photoresist layer at the fourth opening to form a third step structure, where the third step structure includes three steps, and the size of the fourth opening in the X-axis direction is larger than the size of the third opening. The above steps are repeated and through multiple etching processes, a stepped word line structure 26 is finally formed.

[0100] As shown in FIG. 3l, in an embodiment of the present disclosure, a stepped word line structure 26 is formed in the semiconductor base 10 extending along the X-axis direction, and the stepped word line structure 26 has a length that decreases from bottom to top for each layer along the Z-axis direction.

[0101] In another embodiment, the stepped word line structure 26 may further be formed by the following steps: firstly, forming a first word line having a first length on a base surface of the second portion B-2, where the first word line is electrically connected to the gate-all-around structure 17 of the first layer that is the lowest in the third direction; then forming a first isolation unit having a second length on a surface of the first word line; forming a second word line having a second length on a surface of the first isolation unit; and electrically connecting the second word line to the gate-all-around structure 17 of the second layer that is the second lowest in the third direction, where the first length is greater than the second length, and the first isolation unit is electrically connected to the adjacent first word line and the second word line. a third isolation unit having a third length on the surface of the second word line, and a third word line having a third length on the surface of the second isolation unit, where the third word line is electrically connected to the third layer gate-all-around structure 17 from below along the third direction, where the second length is greater than the third length, and the second isolation unit is arranged to isolate adjacent second and third word lines; and by repeating the above steps and going through multiple formation processes, a stepped word line structure 26 consisting of multiple word lines is formed.

[0102] In some embodiments, after forming the stepped word line structure 26, the method of forming a semiconductor structure further includes forming a first metal line 291, which is connected to the capacitor structure 20, a second metal line 292, which is connected to the bit line structure 25, and a third metal line 293, which is connected to the stepped word line structure 26.

[0103] In some embodiments, as shown in FIG. 3m, the first metal line 291, the second metal line 292, and the third metal line 293 are formed by the following steps: forming a barrier layer 30 on the surface of the stepped wordline structure 26, the surfaces of the first isolation layer 19, the second isolation layer 24, and the third isolation layer 28, etching the barrier layer 30, forming a first via hole (not shown) exposing the second metal layer 174, a second via hole (not shown) exposing the bitline structure 25, and a third via hole (not shown) exposing the stepped wordline structure 26, forming the first metal line 291 connected to the capacitor structure 20 in the first via hole, forming the second metal line 292 connected to the bitline structure 25 in the second via hole, and forming the third metal line 293 connected to the stepped wordline structure 26 in the third via hole.

[0104] In the embodiment of the present disclosure, the material of the first metal line 291, the second metal line 292 and the third metal line 293 may be formed by any one conductive metal material, for example, titanium nitride, etc. In other embodiments, the material of the first metal line 291, the second metal line 292 and the third metal line 293 may further be copper, aluminum, copper-aluminum alloy, tungsten, or other conductive metals.

[0105] In the embodiment of the present disclosure, the gate-all-around structure and the semi-capacitor structure are simultaneously formed, which simplifies the manufacturing process flow of the semiconductor structure and reduces the manufacturing cost of the semiconductor structure. In addition, since the capacitor structure in the embodiment of the present disclosure extends along the second direction, i.e., the capacitor structure in the embodiment of the present disclosure is horizontal, compared with a vertical capacitor structure with a high aspect ratio, the horizontal capacitor structure is less likely to tip over or break, thereby improving the stability of the capacitor structure. In addition, a stacked structure formed by stacking multiple capacitor structures in a third direction can form a three-dimensional semiconductor structure, which can further improve the integration degree and miniaturization of the semiconductor structure.

[0106] In addition, an embodiment of the present disclosure further provides a semiconductor structure, and FIG. 4 is a cross-sectional view of a semiconductor structure according to an embodiment of the present disclosure. As shown in FIG. 4, the semiconductor structure 100 includes a substrate, the substrate includes a first region A and a second region B arranged along a Y-axis direction, the second region B includes a first portion B-1 and a second portion B-2 arranged along an X-axis direction, and the second region B includes active pillars 110 arranged in an array along the X-axis direction and the Z-axis direction. The semiconductor structure 100 further includes a capacitor structure 20 located in the first region A and extending along the Y-axis direction, and a gate-all-around structure 17 located in the second region B, where the gate-all-around structure 17 surrounds a surface of the active pillars 110.

[0107] In some embodiments, the capacitor structure 20 includes a first metal layer 173 and a second metal layer 174. medium layer 1712 and a second metal layer 174, and the gate-all-around structure 17 medium layer 171 and a first metal layer 173, where medium Layer 171 is the first medium Layer 1711 and the second medium layer 1712.

[0108] In the embodiments of the present disclosure, the gate-all-around structure 17 has a wide channel region, which can reduce short channel effects and improve gate controllability, thereby improving the performance of the formed semiconductor structure.

[0109] In some embodiments, the semiconductor structure 100 further includes a first isolation layer 19 located between adjacent first metal layers 173 and on the surface of the first metal layers 173, where the first isolation layer 19 is used to isolate adjacent first metal layers 173 and prevent electrical leakage of the first metal layers 173.

[0110] In some embodiments, the semiconductor structure 100 further includes a first connecting structure 23 connecting the capacitor structure 20 and the gate-all-around structure 17, and a supporting structure 14 supporting the capacitor structure 20 and the gate-all-around structure 17. The supporting structure 14 is embedded in the semiconductor base 10, thereby achieving a more stable supporting effect.

[0111] In some embodiments, the semiconductor structure 100 further includes a bit line structure 25 located in the second region B and extending along the first direction.

[0112] In some embodiments, the semiconductor structure 100 further includes a second connecting structure 27 and a stepped word line structure 26, where the gate-all-around structure 17 and the stepped word line structure 26 are connected by the second connecting structure 27.

[0113] In some embodiments, the semiconductor structure 100 further includes a first isolation layer 19 located between the first metal layers 173 and on the surface of the first metal layers 173, where the first isolation layer 19 is used to isolate adjacent first metal layers 173.

[0114] In some embodiments, the semiconductor structure 100 further includes a second isolation layer 24 located between adjacent first connection structures 23, where the second isolation layer 24 is used to isolate adjacent first connection structures 23.

[0115] In some embodiments, the semiconductor structure 100 further includes a second isolation layer 24 located between adjacent second connection structures 27, where the second isolation layer 24 is used to isolate adjacent second connection structures 27.

[0116] In some embodiments, the semiconductor structure 100 may include an insulating layer located on the surface of the second connecting structure 27. medium layer 175, where insulating medium The surface of layer 175 is medium It is flush with the surface of layer 171 .

[0117] In some embodiments, the semiconductor structure 100 is an insulating medium It further includes a third metal layer 176 located on a surface of layer 175 , where the surface of third metal layer 176 is flush with the surface of first metal layer 173 .

[0118] In some embodiments, the semiconductor structure 100 further includes a third isolation layer 28 located between and on the surface of the third metal layer 176, where the third isolation layer 28 is used to isolate adjacent third metal layers 176.

[0119] In some embodiments, the semiconductor structure 100 further includes a first metal line 291, a second metal line 292, and a third metal line 293, where the first metal line 291 is located on a surface of the capacitor structure 20 and is electrically connected to the capacitor structure 20. The second metal line 292 is located on a surface of the bitline structure 25 and is electrically connected to the bitline structure 25. The third metal line 293 is located on a surface of the stepped wordline structure 26 and is electrically connected to the stepped wordline structure 26.

[0120] In an embodiment of the present disclosure, the semiconductor structure 100 further includes a barrier layer 30 , where the first metal line 291 , the second metal line 292 and the third metal line 293 are located within the barrier layer 30 .

[0121] The semiconductor structure according to the embodiments of the present disclosure is similar to the method for forming the semiconductor structure according to the above-mentioned embodiments, and the technical features not disclosed in detail in the embodiments of the present disclosure can be understood by referring to the above-mentioned embodiments, and the description thereof will be omitted here.

[0122] In the semiconductor structure according to the embodiment of the present disclosure, the capacitor structures extend along the second direction, i.e., the capacitor structures are arranged horizontally, so that the horizontal capacitor structures can reduce the possibility of tipping or breaking, thereby improving the stability of the capacitor structures. In addition, the capacitor structures are arranged in an array along the first direction and the third direction, and a stacked structure formed by stacking a plurality of capacitor structures in the third direction can form a three-dimensional semiconductor structure, which can further improve the integration density of the semiconductor structure and realize miniaturization.

[0123] In some embodiments provided in the present disclosure, it should be understood that the disclosed apparatus and method may be realized in a non-targeted manner. The above-described apparatus embodiments are only illustrative, for example, the division of the units is only a logical functional division, and there may be other division modes when actually realized, for example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not implemented.

[0124] The features disclosed in any method or apparatus embodiment provided in this disclosure may be combined in any non-inconsistent manner to yield new method or apparatus embodiments.

[0125] The above are merely some embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present disclosure, and all of these changes or replacements should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be subject to the scope of protection of the claims. [Industrial Applicability]

[0126] In the semiconductor structure and method for forming the same provided in the embodiments of the present disclosure, the capacitor structure is horizontal, and therefore the horizontal capacitor structure is less likely to tip over or break compared to a vertical capacitor structure with a high aspect ratio, thereby improving the stability of the capacitor structure; and a stacked structure formed by stacking multiple capacitor structures in a third direction can form a three-dimensional semiconductor structure, which can further improve the integration density and miniaturization of the semiconductor structure. [Explanation of symbols]

[0127] 10 Semiconductor-based 11 Laminated structure 111 First semiconductor layer 112 Second semiconductor layer 110 Active Pillar 12 1st isolation groove 12a 2nd isolation groove 121 Sacrificial Layer 13 Third isolation groove 13a 4th isolation groove 131 Protective layer 14 Support structure 151 First mask layer 152 Second Mask Layer 153 3rd mask layer 161 First photoresist layer 162 Second Photoresist Layer 163 Third Photoresist Layer 164 4th photoresist layer 165 5th photoresist layer 166 6th photoresist layer 167 7th photoresist layer 17 Gate-all-around structure 171 medium layer 1711 No. 1 medium layer 1712 No. 2 medium layer 172 Dielectric Layer 173 1st metal layer 174 2nd metal layer 175 Insulation medium layer 176 Third metal layer 18 Semi-capacitor structure 19 First isolation layer 20 Capacitor structure 21 First opening 22 1st cavity 23 First connection structure 24 Second isolation layer 25 bit line structure 26 Stepped word line structure 27 Second connection structure 28 Third isolation layer 291 First Metal Wire 292 Second Metal Wire 293 Third Metal Wire 30 Barrier Layer 31 5th isolation groove 311 Isolation structure 100 Semiconductor Structure

Claims

1. 1. A method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first isolation groove extending along a first direction and a plurality of active pillars arranged in an array along the first direction and a third direction, the first isolation groove dividing the substrate into a first region and a second region in a second direction, the active pillars being supported by a support structure, any two of the first direction, the second direction, and the third direction being perpendicular to each other, the first direction and the second direction being parallel to an upper surface of the substrate; forming a semi-capacitor structure located in the first region and a gate-all-around structure located in the second region in the gaps between the active pillars; processing the active pillars and the semi-capacitor structures in the first region to form capacitor structures extending along the second direction; forming a first connection structure connecting the gate-all-around structure and the capacitor structure in the first isolation trench; The semi-capacitor structure and the gate-all-around structure are: the first metal layer located in the first region constitutes the semi-capacitor structure, and the medium layer and the first metal layer located in the second region constitute the gate-all-around structure. A method for forming a semiconductor structure.

2. The substrate further comprises a semiconductor base, the active pillars and the support structure are formed in the semiconductor base, and the step of treating the active pillars and the semi-capacitor structure in the first region comprises: forming a first opening in the first region extending along the first direction, the first opening exposing the semiconductor base; removing the active pillars and the medium layer in the first region through the first opening to form a first gap; sequentially forming a dielectric layer and a second metal layer in the first opening and the first gap, the first metal layer, the dielectric layer and the second metal layer located in the first region forming the capacitor structure; After forming the first metal layer, forming a first isolation layer between the first metal layers and in the first isolation trenches; A method for forming the semiconductor structure of claim 1.

3. The first connection structure is removing a first isolation layer located in the first isolation trench, and removing the medium layer and the first metal layer on a sidewall of a second region located in the first isolation trench to form a second isolation trench extending along the first direction, wherein the second isolation trench exposes the active pillar in the second region and the first metal layer on a sidewall of the first region; epitaxially growing the first connection structure on the exposed surface of the active pillar, the first connection structure contacting a first metal layer in the first region; After forming the first connection structure, forming a second isolation layer in the second isolation groove and between the first connection structure, the surface of the second isolation layer being flush with the surface of the first isolation layer; A method for forming the semiconductor structure of claim 2.

4. The method for forming a semiconductor structure includes: forming a bit line structure and a stepped word line structure connected to the gate-all-around structure; The bit line structure includes: etching an end of the active pillar remote from the capacitor structure to form a bit line groove extending along the first direction, the bit line groove exposing a semiconductor base of the second region; filling the bit line grooves with a bit line metal material to form the bit line structures, the bit line structures and the gate-all-around structures being isolated by the support structure. A method for forming a semiconductor structure according to claim 3.

5. The substrate further includes a third isolation trench extending along the second direction, the third isolation trench dividing the gate-all-around structure in the first direction into a first portion and a second portion, and the stepped word line structure includes: forming a photoresist layer having a second opening on a surface of the second portion, the second opening exposing one end of the second portion away from the first portion; and etching the second portion through the photoresist layer multiple times to form the stepped word line structure, wherein in multiple etching processes, the size of the second opening in the first direction successively increases. A method for forming a semiconductor structure according to claim 4.

6. Prior to forming the stepped word line structure, the method of forming the semiconductor structure includes: removing a first isolation layer located in the third isolation trench, removing the medium layer and the first metal layer on a sidewall of the second portion located in the third isolation trench, and forming a fourth isolation trench extending along the second direction, wherein the fourth isolation trench exposes the first metal layer on a sidewall of the first portion and the active pillar of the second portion; forming a second connection structure connecting the second portion and the gate-all-around structure in the fourth isolation trench; The second connection structure is epitaxially growing the second connection structure on the exposed surface of the active pillar of the second portion, the second connection structure contacting the first metal layer on the sidewall of the first portion.

6. A method for forming a semiconductor structure according to claim 5.

7. After forming the second connection structure, the method for forming the semiconductor structure includes: forming an insulating medium layer on a surface of the second connection structure, the surface of the insulating medium layer being flush with the surface of the medium layer; forming a third metal layer on a surface of the insulating medium layer, the surface of the third metal layer being flush with the surface of the first metal layer; filling a third isolation material between and on a surface of the third metal layer to form a third isolation layer, the surface of the third isolation layer being flush with the surface of the first isolation layer. A method for forming a semiconductor structure according to claim 6.

8. After forming the third isolation layer, the method of forming the semiconductor structure includes: forming a first metal line connected to the capacitor structure, a second metal line connected to the bit line structure, and a third metal line connected to the stepped word line structure; The first metal line, the second metal line, and the third metal line are forming a barrier layer on a surface of the stepped word line structure, the first isolation layer, the second isolation layer, and the third isolation layer; etching the barrier layer to form a first via hole exposing the second metal layer, a second via hole exposing the bit line structure, and a third via hole exposing the stepped word line structure; forming the first metal wire in the first through hole, forming the second metal wire in the second through hole, and forming the third metal wire in the third through hole. A method for forming a semiconductor structure according to claim 7.

9. The substrate is providing the semiconductor base; forming a laminate structure on the semiconductor base, the laminate structure including first and second semiconductor layers alternately stacked; Etching the stacked structure to form the first isolation trench; removing the first semiconductor layer in the stacked structure; A method for forming a semiconductor structure according to claim 5.

10. Before forming the first isolation trench, the method for forming the semiconductor structure includes: a step of etching the stacked structure to form a fifth isolation trench extending along the second direction, the fifth isolation trench dividing the second semiconductor layer into a plurality of the active pillars arranged along the first direction; forming an isolation structure in the fifth isolation trench; Before forming the first isolation trench, the method for forming the semiconductor structure includes: etching away a portion of the isolation structure and a portion of the first semiconductor layer to form a plurality of etching holes extending along the first direction, the etching holes exposing the active pillars; filling the etching holes with a support material to form the support structure surrounding the active pillars; After forming the first isolation trench and before removing the first semiconductor layer in the stacked structure, the method for forming the semiconductor structure includes: filling the first isolation trench with a sacrificial material to form a sacrificial layer; A method for forming a semiconductor structure according to claim 9.

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