Semiconductor Device

Abstract

This semiconductor device comprises: a semiconductor substrate of a first conductivity type having a first main surface on one side and a second main surface on the other side; a well region of a second conductivity type which is formed in a surface layer portion of the first main surface and divides the semiconductor substrate into an active region and an external region; an IGBT including a collector region of the second conductivity type formed in the active region on a surface layer portion of the second main surface and a FET structure formed in the active region on the first main surface; and a diode which includes a cathode region of the first conductivity type formed only in the external region on the surface layer portion of the second main surface and has the well region as an anode region.

Description

[Technical field]

[0001] The present invention relates to a semiconductor device including an IGBT (Insulated Gate Bipolar Transistor) and a diode. [Background technology]

[0002] Patent Document 1 discloses an RC-IGBT (Reverse Conducting - IGBT). The RC-IGBT includes an IGBT and a diode that are integrated on a semiconductor substrate. The IGBT includes a FET structure and a collector region. The diode includes a cathode region and an anode region.

[0003] The FET structure includes a p-type base region formed in a surface layer portion on the front side of the semiconductor substrate, an emitter region formed in a surface layer portion of the base region, a gate insulating layer covering the base region and the emitter region, and a gate electrode covering the gate insulating layer. The collector region is formed in the entire surface layer portion on the back side of the semiconductor substrate. The cathode region is formed in a region directly below the FET structure in the surface layer portion on the back side of the semiconductor substrate. The anode region consists of the base region of the IGBT. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2010 / 090248 Summary of the Invention [Problem to be solved by the invention]

[0005] In a structure in which a cathode region is formed directly under a FET structure, electrons injected from the emitter region flow into the cathode region during the start-up operation of the IGBT, resulting in a snapback phenomenon and a deterioration in switching characteristics.

[0006] An embodiment of the present invention provides a semiconductor device capable of suppressing degradation of switching characteristics caused by the snapback phenomenon. [Means for solving the problem]

[0007] One embodiment of the present invention provides a semiconductor device including a semiconductor substrate of a first conductivity type having a first main surface on one side and a second main surface on the other side, a well region of a second conductivity type formed in a surface layer portion of the first main surface and dividing the semiconductor substrate into an active region and an outer region, a collector region of the second conductivity type formed in the active region in the surface layer portion of the second main surface, and an IGBT including a FET structure formed in the active region in the first main surface, and a diode including a cathode region of the first conductivity type formed only in the outer region in the surface layer portion of the second main surface and having the well region as an anode region.

[0008] According to this semiconductor device, it is possible to suppress the degradation of switching characteristics caused by the snapback phenomenon.

[0009] The above and other objects, features and advantages of the present invention will become apparent from the following detailed description of the embodiments with reference to the accompanying drawings. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention. [Diagram 2] FIG. 2 is a plan view showing the structure of a first main surface of the semiconductor substrate shown in FIG. [Diagram 3] FIG. 3 is an enlarged view of a main portion of the first main surface shown in FIG. [Figure 4] FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. [Diagram 5] FIG. 5 is a cross-sectional view taken along line VV in FIG. [Figure 6] FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. [Figure 7]FIG. 7 is a plan view showing the structure of the second main surface of the semiconductor substrate shown in FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. [Figure 9] FIG. 9 is a graph showing current-voltage characteristics. [Figure 10] FIG. 10 is a diagram corresponding to FIG. 7 and is a plan view showing the structure of the second main surface of the semiconductor device according to the second embodiment of the present invention. [Figure 11] FIG. 11 is a diagram corresponding to FIG. 7 and is a plan view showing the structure of the second main surface of the semiconductor device according to the third embodiment of the present invention. [Figure 12] FIG. 12 is a plan view showing a semiconductor device according to a fourth embodiment of the present invention. [Figure 13] FIG. 13 is an enlarged view of a main portion of the first main surface of the semiconductor device shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] FIG. 1 is a plan view showing a semiconductor device 1 according to a first embodiment of the present invention. FIG. 2 is a plan view showing a structure of a first main surface 4 of a semiconductor substrate 2 shown in FIG. 1. FIG. 3 is an enlarged view of a main part of the first main surface 4 shown in FIG. 2. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 3. FIG. 5 is a cross-sectional view taken along line VV in FIG. 3. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 3. FIG. 7 is a plan view showing a structure of a second main surface 5 of the semiconductor substrate 2 shown in FIG. 1. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 1.

[0012] 1 to 8, a semiconductor device 1 is a semiconductor switching device including an RC-IGBT (Reverse Conducting-IGBT) having an IGBT (Insulated Gate Bipolar Transistor) and a diode.

[0013] The semiconductor device 1 includes an n-type semiconductor substrate 2 made of silicon and formed into a rectangular parallelepiped shape. The semiconductor substrate 2 functions as a drift region 3. The semiconductor substrate 2 is made of an FZ substrate formed through an FZ (Floating Zone) method, or a CZ substrate formed through a CZ (Czochralski) method. In this embodiment, the semiconductor substrate 2 is made of an FZ substrate. The n-type impurity concentration of the semiconductor substrate 2 is 1.0×10 13 cm -3 Above 1.0×10 15 cm -3 It may be the following.

[0014] The semiconductor substrate 2 includes a first main surface 4 on one side, a second main surface 5 on the other side, and four side surfaces 6A, 6B, 6C, and 6D connecting the first main surface 4 and the second main surface 5. The side surfaces 6A to 6D include a first side surface 6A, a second side surface 6B, a third side surface 6C, and a fourth side surface 6D.

[0015] The first main surface 4 and the second main surface 5 are each formed in a quadrangular shape in a plan view (hereinafter simply referred to as "plan view") seen from their normal direction Z. The first side surface 6A and the second side surface 6B extend along the first direction X and face a second direction Y intersecting the first direction X. The third side surface 6C and the fourth side surface 6D extend along the second direction Y and face the first direction X. The second direction Y is specifically perpendicular to the first direction X.

[0016] The semiconductor device 1 includes an n-type buffer region 7 formed in a surface layer portion of the second main surface 5. In this embodiment, the buffer region 7 is formed over the entire surface layer portion of the second main surface 5. The buffer region 7 has an n-type impurity concentration that exceeds the n-type impurity concentration of the semiconductor substrate 2. The n-type impurity concentration of the buffer region 7 is 1.0×10 14 cm -3 Above 1.0×10 18 cm -3 It may be the following.

[0017] The semiconductor device 1 includes a p-type well region 10 formed in a surface layer portion of the first main surface 4. The well region 10 has a p-type impurity concentration that exceeds the n-type impurity concentration of the semiconductor substrate 2. The p-type impurity concentration of the well region 10 is 1.0×10 15 cm -3 Above 1.0×10 18 cm -3 The well region 10 may be a common emitter region.

[0018] Well region 10 is formed in a line shape that divides the inner portion of first main surface 4 from multiple directions at intervals inward from side surfaces 6A-6D in plan view. Well region 10 in this embodiment is formed endlessly so as to surround the inner portion of first main surface 4 in plan view. Well region 10 is specifically formed in a ring shape (a quadrangular ring shape in this embodiment) having four sides parallel to side surfaces 6A-6D.

[0019] The well region 10 includes a pad well region 11 and a line well region 12. The pad well region 11 is a region in which a p-type impurity is introduced in a relatively wide island shape. In this embodiment, the pad well region 11 is formed in a region on the first side surface 6A side in the surface layer portion of the first main surface 4. Specifically, the pad well region 11 is formed in a quadrangular shape in a region along the center of the first side surface 6A at an interval from the first side surface 6A to the second side surface 6B side in the surface layer portion of the first main surface 4.

[0020] The line well region 12 is a region where a p-type impurity is introduced in a relatively narrow line shape. The line well region 12 has a width smaller than that of the pad well region 11, and is drawn out in a line shape from the pad well region 11. The line well region 12 extends along the side surfaces 6A to 6D in a plan view, and is formed in a line shape that divides the inner part of the first main surface 4 from multiple directions. In this embodiment, the line well region 12 is formed in an endless shape that surrounds the inner part of the first main surface 4 in a plan view. Specifically, the well region 10 is formed in a ring shape (a square ring shape in this embodiment) having four sides parallel to the side surfaces 6A to 6D.

[0021] The width W1 of the line well region 12 may be 5 μm or more and 100 μm or less. The width W1 is defined by the width in a direction perpendicular to the direction in which the line well region 12 extends. The width W1 may be 5 μm or more and 25 μm or less, 25 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, or 75 μm or more and 100 μm or less.

[0022] Well region 10 divides semiconductor substrate 2 into active region 13 and outer region 14. Active region 13 is divided by the inner periphery of well region 10 in a plan view. Outer region 14 is divided into a region between side surfaces 6A-6D and the inner periphery of well region 10 in a plan view.

[0023] The thickness of the well region 10 may be 1 μm or more and 20 μm or less. The thickness of the well region 10 may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, or 15 μm or more and 20 μm or less.

[0024] The semiconductor device 1 includes an IGBT formed in the active region 13. The IGBT includes a p-type collector region 20 formed in a surface layer portion of the second main surface 5, and a FET structure 21 (Field Effect Transistor structure) formed on the first main surface 4.

[0025] Specifically, the collector region 20 is formed in the surface layer portion of the buffer region 7 on the second main surface 5 side. The collector region 20 is formed over the entire surface layer portion of the second main surface 5. The collector region 20 has a p-type impurity concentration that exceeds the n-type impurity concentration of the semiconductor substrate 2. The p-type impurity concentration of the collector region 20 is 1.0×10 15 cm -3 Above 1.0×10 18 cm -3 It may be the following.

[0026] The FET structure 21 includes a p-type base region 22 formed in a surface layer portion of the first main surface 4. The base region 22 has a p-type impurity concentration that exceeds the n-type impurity concentration of the semiconductor substrate 2. The p-type impurity concentration of the base region 22 is preferably lower than the p-type impurity concentration of the well region 10. The p-type impurity concentration of the base region 22 is preferably 1.0×10 15 cm -3 Above 1.0×10 17 cm -3 It may be the following.

[0027] The base region 22 is formed over the entire active region 13 and is connected to the inner periphery of the well region 10. The base region 22 has a thickness less than that of the well region 10. The thickness of the base region 22 is preferably equal to or less than half the thickness of the well region 10. The thickness of the base region 22 may be 1 μm or more and 5 μm or less. The thickness of the base region 22 may be 1 μm or more and 2 μm or more, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, or 4 μm or more and 5 μm or less.

[0028] The FET structure 21 includes a plurality of trench gate structures 23 formed on the first main surface 4. The plurality of trench gate structures 23 are formed in lines extending along a first direction X and spaced apart in a second direction Y. The plurality of trench gate structures 23 are formed in stripes extending along the first direction X.

[0029] Each of the trench gate structures 23 includes a gate trench 24, a gate insulating layer 25, and a gate electrode 26. The gate trench 24 is formed by digging down the first main surface 4 toward the second main surface 5. The gate trench 24 penetrates the base region 22 and reaches the drift region 3. The bottom wall of the gate trench 24 is formed at a depth position between the bottom of the well region 10 and the bottom of the base region 22. A portion of the gate trench 24 adjacent to the well region 10 may be partially covered by the well region 10.

[0030] The gate insulating layer 25 is formed in a film shape along the inner wall of the gate trench 24. The gate insulating layer 25 includes at least one of a silicon oxide layer and a silicon nitride layer. In this embodiment, the gate insulating layer 25 is made of a silicon oxide layer. The gate electrode 26 is embedded in the gate trench 24 with the gate insulating layer 25 in between. The gate electrode 26 includes conductive polysilicon.

[0031] The FET structure 21 includes a plurality of n-type emitter regions 27 formed in a surface layer portion of the base region 22. The emitter regions 27 have an n-type impurity concentration that exceeds the n-type impurity concentration of the semiconductor substrate 2. The n-type impurity concentration of the emitter regions 27 is 1.0×10 16 cm -3 Above 5.0×10 20 cm -3 It may be the following.

[0032] The plurality of emitter regions 27 are formed in regions between the plurality of trench gate structures 23 in a surface layer portion of the base region 22. The plurality of emitter regions 27 are formed in strip shapes extending along the trench gate structures 23. The plurality of emitter regions 27 face the gate electrode 26 with the gate insulating layer 25 interposed therebetween. The bottoms of the plurality of emitter regions 27 are formed at a depth position between the first main surface 4 and the bottom of the base region 22. The plurality of emitter regions 27 define a channel of the IGBT between the bottoms of the base region 22.

[0033] The FET structure 21 includes a plurality of emitter trenches 28 formed in the first main surface 4. The plurality of emitter trenches 28 are formed by digging down the first main surface 4 toward the second main surface 5 in a region between the plurality of trench gate structures 23. Each emitter trench 28 is formed in a strip shape extending along the trench gate structure 23. Each emitter trench 28 penetrates the emitter region 27 and reaches the base region 22. The bottom wall of each emitter trench 28 is formed at a depth position between the bottom of the emitter region 27 and the bottom of the base region 22.

[0034] The FET structure 21 includes a plurality of p-type contact regions 29 formed in a surface layer portion of the base region 22. The contact regions 29 have a p-type impurity concentration that exceeds the p-type impurity concentration of the base region 22. The p-type impurity concentration of the contact regions 29 is 1.0×10 16 cm -3 Above 1.0×10 20 cm -3 It may be the following.

[0035] Specifically, each contact region 29 is formed in a region along the bottom wall of the emitter trench 28 in a region between the multiple trench gate structures 23. Each contact region 29 may cover a side wall of the emitter trench 28. Each contact region 29 is formed at an interval from the bottom of the base region 22 toward the bottom wall of the emitter trench 28. Each contact region 29 is formed in a strip shape extending along the trench gate structure 23.

[0036] In this embodiment, the FET structure 21 includes a plurality of n-type carrier storage regions 30 formed in a surface layer portion of the first main surface 4. The carrier storage regions 30 have an n-type impurity concentration that exceeds the n-type impurity concentration of the semiconductor substrate 2. The n-type impurity concentration of the carrier storage regions 30 is less than the n-type impurity concentration of the emitter region 27. The n-type impurity concentration of the carrier storage regions 30 is 1.0×10 16 cm -3 Above 1.0×10 18 cm -3 It may be the following.

[0037] Each carrier storage region 30 is formed on the bottom wall side of the trench gate structure 23 with respect to the base region 22, in a region between the multiple trench gate structures 23. The bottom of each carrier storage region 30 is formed at a depth position between the bottom of the base region 22 and the bottom wall of the trench gate structure 23. Each carrier storage region 30 is formed in a strip shape extending along the trench gate structure 23 in a plan view. Each carrier storage region 30 faces the gate electrode 26 with the gate insulating layer 25 sandwiched therebetween.

[0038] The carrier storage region 30 suppresses carriers (holes) supplied to the drift region 3 from being discharged to the base region 22. As a result, holes are accumulated in the drift region 3 in a region directly below the FET structure 21, reducing the on-resistance. The carrier storage region 30 may be removed as necessary.

[0039] The semiconductor device 1 includes a diode formed in the outer region 14. The diode includes an n-type cathode region 31 formed in a surface layer portion of the second main surface 5, and a p-type anode region 32 formed in a surface layer portion of the first main surface 4. The anode region 32 is formed by the well region 10. That is, the diode includes the well region 10 as the anode region 32.

[0040] 4 to 7 (particularly FIG. 7), cathode region 31 is formed in a surface layer portion of second main surface 5 in a manner such that the p-type impurity in collector region 20 is offset by n-type impurity. Cathode region 31 has an n-type impurity concentration that exceeds the n-type impurity concentration of semiconductor substrate 2. The n-type impurity concentration of cathode region 31 preferably exceeds the n-type impurity concentration of buffer region 7. The n-type impurity concentration of cathode region 31 is 1.0×10 16 cm -3 Above 5.0×10 20 cm -3 It may be the following.

[0041] The cathode region 31 is formed only in the outer region 14 in the surface layer portion of the second main surface 5. The cathode region 31 is not formed in the region directly below the FET structure 21 in the surface layer portion of the second main surface 5. The cathode region 31 is formed in the region directly below the well region 10 in the surface layer portion of the second main surface 5. As a result, the cathode region 31 faces the well region 10 with the drift region 3 interposed therebetween in the thickness direction (normal direction Z) of the semiconductor substrate 2.

[0042] The cathode region 31 is formed in a line shape extending along the well region 10 in a plan view. The cathode region 31 divides the active region 13 from multiple directions in a plan view. In this embodiment, the cathode region 31 extends along the side faces 6A to 6D, and divides the active region 13 from four directions in a plan view. The cathode region 31 is preferably formed at intervals inward from the inner and outer peripheries of the well region 10 in a plan view. The cathode region 31 is preferably formed only in a region overlapping the well region 10 in a plan view.

[0043] Specifically, the cathode region 31 is formed in a region immediately below the line well region 12 in the surface layer portion of the second main surface 5, and exposes the pad well region 11. The occupancy rate of the cathode region 31 in the region immediately below the line well region 12 preferably exceeds the occupancy rate of the collector region 20 in the region immediately below the line well region 12.

[0044] On the other hand, the occupancy rate of the cathode region 31 in the region immediately below the pad well region 11 is preferably less than the occupancy rate of the collector region 20 in the region immediately below the pad well region 11. In this embodiment, the cathode region 31 is formed only in the region immediately below the line well region 12 in the surface layer portion of the second main surface 5, and is not formed in the region immediately below the pad well region 11 in the surface layer portion of the second main surface 5.

[0045] More specifically, the cathode region 31 is formed in a line shape having ends including a first end 33 on one side, a second end 34 on the other side, and a line portion 35 extending through a region between the first end 33 and the second end 34. The first end 33, the second end 34, and the line portion 35 of the cathode region 31 are each formed in a region directly below the line well region 12.

[0046] The first end 33 is formed at a distance from the pad well region 11 on one side (the third side surface 6C side) along the first direction X. The second end 34 is formed at a distance from the pad well region 11 on the other side (the fourth side surface 6D side) along the first direction X. The second end 34 faces the first end 33 across the pad well region 11. The second end 34 forms a gap portion 36 that exposes the pad well region 11 in a region between the second end 34 and the first end 33. The line portion 35 extends along the line well region 12 in a plan view, and divides the active region 13 from multiple directions (four directions in this embodiment).

[0047] The width W2 of the cathode region 31 may be 5 μm or more and 100 μm or less. The width W2 may be 5 μm or more and 25 μm or less, 25 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, or 75 μm or more and 100 μm or less. The width W2 is preferably less than the width W1 of the line well region 12.

[0048] The area ratio RS of the plane area of ​​the cathode region 31 to the plane area of ​​the active region 13 is preferably 1% or more and 10% or less. The area ratio RS may be 1% or more and 2% or less, 2% or more and 4% or less, 4% or more and 6% or less, 6% or more and 8% or less, or 8% or more and 10% or less. The area ratio RS is particularly preferably 1% or more and 5% or less.

[0049] 2 and 8, the semiconductor device 1 includes an FL structure 40 (Field Limiting structure) formed in a surface layer portion of the first main surface 4 in the outer region 14. The FL structure 40 is formed in a region between the side surfaces 6A-6D and the outer periphery of the well region 10 with a gap therebetween and from the side surfaces 6A-6D and the well region 10. The FL structure 40 is formed with a gap therebetween in a direction opposite to the active region 13 from the cathode region 31. The FL structure 40 does not overlap the cathode region 31 in a plan view.

[0050] The FL structure 40 includes one or more (four in this embodiment) p-type FL regions 41A, 41B, 41C, 41D (field limiting regions). The FL regions 41A to 41D are formed in an electrically floating state. The FL regions 41A to 41D have a p-type impurity concentration that exceeds the n-type impurity concentration of the semiconductor substrate 2. The p-type impurity concentration of the FL regions 41A to 41D preferably exceeds the p-type impurity concentration of the base region 22. The p-type impurity concentration of the FL regions 41A to 41D is 1.0×10 15 cm -3 Above 1.0×10 18 cm -3 It may be the following.

[0051] The FL regions 41A to 41D are formed in this order at intervals in a direction away from the well region 10. That is, the FL regions 41A to 41D are formed at intervals from the cathode region 31 toward the peripheral edge (side surfaces 6A to 6D) of the semiconductor substrate 2 in a plan view, and do not overlap the cathode region 31. The FL regions 41A to 41D extend in a line along the well region 10 in a plan view. Specifically, the FL regions 41A to 41D are formed in a ring shape (quadratic ring shape) surrounding the well region 10 in a plan view. As a result, the FL regions 41A to 41D are formed as FLR regions (Field Limiting Ring regions).

[0052] The FL regions 41A to 41D have a thickness greater than the thickness of the base region 22. The bottoms of the FL regions 41A to 41D are located in a region on the second main surface 5 side with respect to the bottom of the base region 22. The FL regions 41A to 41D are preferably formed to a constant thickness.

[0053] The thickness of the FL regions 41A to 41D may be 1 μm or more and 20 μm or less. The thickness of the FL regions 41A to 41D may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, or 15 μm or more and 20 μm or less. The thickness of the FL regions 41A to 41D is preferably equal to the thickness of the well region 10.

[0054] The width of the FL regions 41A to 41D may be 5 μm or more and 50 μm or less. The width of the FL regions 41A to 41D may be 5 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less. The width of the FL regions 41A to 41D is preferably 10 μm or more and 30 μm or less.

[0055] The distance between adjacent FL regions 41A to 41D may be 5 μm or more and 50 μm or less. The distance between FL regions 41A to 41D may be 5 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less. The distance between FL regions 41A to 41D may increase in order in the direction away from well region 10.

[0056] The distance between the well region 10 and the FL region 41A may be 5 μm or more and 50 μm or less. The distance between the well region 10 and the FL region 41A may be 5 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.

[0057] The semiconductor device 1 includes an n-type CS region 42 (Channel Stop region) formed in the surface layer portion of the first main surface 4 in the outer region 14. The CS region 42 has an n-type impurity concentration that exceeds the n-type impurity concentration of the semiconductor substrate 2. The n-type impurity concentration of the CS region 42 is 1.0×10 15 cm -3 Above 1.0×10 18 cm -3 It may be the following.

[0058] The CS region 42 is formed in a region between the side surfaces 6A to 6D and the FL structure 40 with a gap therebetween. The CS region 42 may be exposed from the side surfaces 6A to 6D. The CS region 42 extends in a line shape along the FL structure 40 in a plan view. Specifically, the CS region 42 is formed in a ring shape (quadrangle) surrounding the FL structure 40 in a plan view. The CS region 42 is formed in an electrically floating state.

[0059] The width of the CS region 42 may be 50 μm or more and 150 μm or less. The width of the CS region 42 is the width in a direction perpendicular to the extension direction of the CS region 42. The width of the CS region 42 may be 50 μm or more and 75 μm or less, 75 μm or more and 100 μm or less, 100 μm or more and 125 μm or less, or 125 μm or more and 150 μm or less.

[0060] The semiconductor device 1 includes an insulating layer 50 covering the first main surface 4. The insulating layer 50 has a laminated structure including a first insulating layer 51 and a second insulating layer 52. The first insulating layer 51 covers almost the entire area of ​​the first main surface 4. Specifically, the first insulating layer 51 selectively covers the FET structure 21 in the active region 13, and selectively covers the well region 10, the FL structure 40, and the CS region 42 in the outer region 14. The first insulating layer 51 is continuous with the gate insulating layer 25 in the active region 13. The second insulating layer 52 covers almost the entire area of ​​the first insulating layer 51.

[0061] The first insulating layer 51 may have a laminated structure in which a plurality of insulating layers are laminated, or may have a single-layer structure made of a single insulating layer 50. The first insulating layer 51 may include at least one of a silicon oxide layer and a silicon nitride layer. The first insulating layer 51 may have a laminated structure in which a silicon oxide layer and a silicon nitride layer are laminated in any order. The first insulating layer 51 may have a single-layer structure made of a silicon oxide layer or a silicon nitride layer.

[0062] The second insulating layer 52 may have a laminated structure in which a plurality of insulating layers are laminated, or may have a single-layer structure made of a single insulating layer 50. The second insulating layer 52 may include at least one of a silicon oxide layer and a silicon nitride layer. The second insulating layer 52 may have a laminated structure in which a silicon oxide layer and a silicon nitride layer are laminated in any order. The second insulating layer 52 may have a single-layer structure made of a silicon oxide layer or a silicon nitride layer.

[0063] 4 to 6, semiconductor device 1 includes a gate wiring layer 53 embedded in a portion of insulating layer 50 covering well region 10. Gate wiring layer 53 is specifically formed on a portion of first insulating layer 51 covering well region 10. Gate wiring layer 53 faces well region 10 with first insulating layer 51 in between, and is covered by second insulating layer 52. Gate wiring layer 53 is preferably made of the same electrode material as gate electrode 26. In this embodiment, gate wiring layer 53 is made of conductive polysilicon.

[0064] The gate wiring layer 53 includes a line wiring portion 54 and a plurality of connection wiring portions 55. The line wiring portion 54 extends in a line shape along the well region 10 in a plan view. The line wiring portion 54 includes a portion covering the pad well region 11 and a portion covering the line well region 12. The portion of the line wiring portion 54 covering the pad well region 11 does not overlap the cathode region 31 in a plan view. The portion of the line wiring portion 54 covering the line well region 12 overlaps the cathode region 31 in a plan view.

[0065] It is preferable that the line wiring portion 54 defines the active region 13 from multiple directions in a plan view. In this embodiment, the line wiring portion 54 extends along the side surfaces 6A to 6D in a plan view, and defines the active region 13 from four directions. The line wiring portion 54 may be formed in an endless shape (annular shape) or in a shape with ends.

[0066] The line wiring portion 54 has a width less than the width W1 of the line well region 12. The line wiring portion 54 is formed at intervals inward from the inner and outer peripheries of the well region 10. As a result, the entire area of ​​the line wiring portion 54 faces the well region 10 with the first insulating layer 51 sandwiched therebetween.

[0067] The width of the line wiring portion 54 is arbitrary. The line wiring portion 54 may be formed with a uniform width. The width of the portion of the line wiring portion 54 that covers the line well region 12 may be less than the width of the portion of the line wiring portion 54 that covers the pad well region 11.

[0068] The multiple connection wiring parts 55 are drawn out from the line wiring part 54 toward both ends of the multiple trench gate structures 23, respectively (see FIG. 5). Specifically, the multiple connection wiring parts 55 are drawn out from a portion of the line wiring part 54 extending along the third side surface 6C (fourth side surface 6D) toward the multiple gate electrodes 26. The multiple connection wiring parts 55 are drawn out in a one-to-one correspondence with the multiple gate electrodes 26, and are respectively connected to the corresponding gate electrodes 26. As a result, the gate wiring layer 53 is electrically connected to the gate electrodes 26.

[0069] The semiconductor device 1 includes a plurality of emitter openings 61 formed in the insulating layer 50. The plurality of emitter openings 61 expose the plurality of emitter trenches 28 in a one-to-one correspondence in the active region 13. The plurality of emitter openings 61 are in communication with the plurality of emitter trenches 28, respectively.

[0070] The semiconductor device 1 includes one or more (multiple in this embodiment) first well openings 62 formed in the insulating layer 50. The multiple first well openings 62 selectively expose the inner periphery of the well region 10 in the outer region 14. In this embodiment, the multiple first well openings 62 are each formed at intervals along the inner periphery of the well region 10 so as to surround the active region 13. The multiple first well openings 62 may each be formed in a line extending along the inner periphery of the well region 10.

[0071] The semiconductor device 1 includes one or more (one in this embodiment) second well openings 63 formed in the insulating layer 50. The second well openings 63 selectively expose the outer periphery of the well region 10 in the outer region 14. In this embodiment, the second well openings 63 are formed in a line shape extending along the outer periphery of the well region 10 so as to surround the active region 13. In this embodiment, the second well openings 63 are formed in a ring shape (quadrangle shape) that exposes the outer periphery of the well region 10. The second well openings 63 may be formed in an endless shape or in a shape with ends.

[0072] The semiconductor device 1 includes a plurality of FL openings 64 formed in the insulating layer 50. The plurality of FL openings 64 selectively expose the plurality of FL regions 41A-41D in the outer region 14 in a one-to-one correspondence. The plurality of FL openings 64 are each formed in a line extending along the plurality of FL regions 41A-41D. In this embodiment, the plurality of FL openings 64 are formed in a ring shape (quadrangle shape) that exposes the plurality of FL regions 41A-41D. The plurality of FL openings 64 may be formed in an endless shape or may be formed in an ended shape.

[0073] The semiconductor device 1 includes one or more (one in this embodiment) CS openings 65 formed in the insulating layer 50. The CS openings 65 selectively expose the CS region 42 in the outer region 14. The CS openings 65 are formed in a line shape extending along the CS region 42. In this embodiment, the CS openings 65 are formed in a ring shape (quadrangle shape) that exposes the CS region 42 and communicates with the side surfaces 6A to 6D. The CS openings 65 may be formed in an endless shape or may be formed in an ended shape.

[0074] The semiconductor device 1 includes one or more (one in this embodiment) gate openings 66 formed in the insulating layer 50. The gate opening 66 selectively exposes the gate wiring layer 53 in the outer region 14. The gate opening 66 is formed in a line shape extending along the gate wiring layer 53. The gate opening 66 may be formed in an endless shape or in a shape with ends.

[0075] 4 to 6, semiconductor device 1 includes a plurality of emitter plug electrodes 67 embedded in a plurality of emitter trenches 28 via a plurality of emitter openings 61. Each of the plurality of emitter plug electrodes 67 is electrically connected to an emitter region 27 and a contact region 29 in a corresponding emitter trench 28. Each of the plurality of emitter plug electrodes 67 has a layered structure including a barrier electrode 68 and a main electrode 69.

[0076] The barrier electrode 68 is formed in the form of a film along the inner walls of the emitter trench 28 and the emitter opening 61. The barrier electrode 68 may have a single-layer structure including a titanium layer or a titanium nitride layer. The barrier electrode 68 may have a laminated structure including a titanium layer and a titanium nitride layer in any order. The main electrode 69 is embedded in the emitter trench 28 and the emitter opening 61 with the barrier electrode 68 in between. The main electrode 69 may include tungsten.

[0077] 1 to 8, the semiconductor device 1 includes a gate principal surface electrode 71 formed on the first principal surface 4. Specifically, the gate principal surface electrode 71 is formed on a portion of the insulating layer 50 covering the well region 10. The gate principal surface electrode 71 enters the gate opening 66 from above the insulating layer 50 and is electrically connected to the gate wiring layer 53. More specifically, the gate principal surface electrode 71 integrally includes a gate pad electrode 72 and a gate finger electrode 73.

[0078] The gate pad electrode 72 is an external terminal portion that is externally connected to a conductive wire (e.g., a bonding wire) or the like. The gate pad electrode 72 is formed on a portion of the insulating layer 50 that covers the pad well region 11. As a result, the gate pad electrode 72 faces the pad well region 11 with the insulating layer 50 in between. The gate pad electrode 72 does not overlap the cathode region 31 in a plan view. With this structure, current concentration occurring in the semiconductor substrate 2 due to the arrangement of the gate pad electrode 72 and the cathode region 31 can be suppressed.

[0079] The gate pad electrode 72 preferably covers the entire pad well region 11. The gate pad electrode 72 is formed in a quadrangular shape that matches the pad well region 11 in a plan view. The gate pad electrode 72 may have any planar shape. The gate pad electrode 72 enters the gate opening 66 from above the insulating layer 50 and is electrically connected to the gate wiring layer 53.

[0080] The gate finger electrode 73 is drawn out from the gate pad electrode 72 onto a portion of the insulating layer 50 that covers the line well region 12. As a result, the gate finger electrode 73 faces the line well region 12 with the insulating layer 50 in between. The gate finger electrode 73 overlaps the cathode region 31 in a planar view. The gate finger electrode 73 extends in a line shape along the line well region 12 in a planar view, and divides the active region 13 from multiple directions.

[0081] In this embodiment, the gate finger electrodes 73 extend along the side surfaces 6A to 6D in a plan view, and divide the active region 13 from four directions. The gate finger electrodes 73 are formed in a line shape with ends having a first end 74 and a second end 75. In this embodiment, the first end 74 and the second end 75 are formed in a region along the second side surface 6B. The region between the first end 74 and the second end 75 faces the gate pad electrode 72 in the second direction Y. The positions of the first end 74 and the second end 75 are arbitrary. The gate finger electrodes 73 enter the gate opening 66 from above the insulating layer 50, and are electrically connected to the gate wiring layer 53.

[0082] The semiconductor device 1 includes an emitter principal surface electrode 76 formed on the first principal surface 4 at a distance from the gate principal surface electrode 71. The emitter principal surface electrode 76 also serves as an anode electrode of the diode. The emitter principal surface electrode 76 is formed on a region of the insulating layer 50 outside the gate principal surface electrode 71.

[0083] The emitter main surface electrode 76 is electrically connected to a plurality of emitter plug electrodes 67. The emitter main surface electrode 76 further extends from above the insulating layer 50 into the first well opening 62 and the second well opening 63, and is electrically connected to the well region 10. Specifically, the emitter main surface electrode 76 integrally includes an emitter pad electrode 77 and an emitter finger electrode 78.

[0084] The emitter pad electrode 77 is an external terminal portion that is externally connected to a conductive wire (e.g., a bonding wire) or the like. The emitter pad electrode 77 is formed on a portion of the insulating layer 50 that covers the active region 13, and faces the FET structure 21 with the insulating layer 50 in between. The emitter pad electrode 77 is formed in a polygonal shape that follows the inner edge of the gate pad electrode 72 and the inner edge of the gate finger electrode 73. The emitter pad electrode 77 is electrically connected to a plurality of emitter plug electrodes 67.

[0085] The emitter pad electrode 77 has a peripheral portion 79 that covers the inner peripheral edge of the well region 10. The peripheral portion 79 of the emitter pad electrode 77 overlaps the cathode region 31 in a plan view. The peripheral portion 79 of the emitter pad electrode 77 may be formed at a distance from the cathode region 31 toward the active region 13 in a plan view. The peripheral portion 79 of the emitter pad electrode 77 extends from above the insulating layer 50 into the first well opening 62 and is electrically connected to the inner peripheral edge of the well region 10.

[0086] Emitter finger electrode 78 crosses the region between first end 74 and second end 75 of gate finger electrode 73 on insulating layer 50 and is drawn out to a region outside gate finger electrode 73. Emitter finger electrode 78 is formed on a portion of insulating layer 50 covering the outer periphery of well region 10, and extends in a line along well region 10.

[0087] The emitter finger electrodes 78 define the active region 13 from multiple directions in a plan view. In this embodiment, the emitter finger electrodes 78 extend along the side surfaces 6A to 6D in a plan view, and define the active region 13 from four directions. Specifically, the emitter finger electrodes 78 are formed in an endless shape surrounding the gate finger electrodes 73. The emitter finger electrodes 78 may be formed in a shape with ends.

[0088] The emitter finger electrode 78 includes a portion covering the pad well region 11 and a portion covering the line well region 12. The portion of the emitter finger electrode 78 covering the pad well region 11 does not overlap the cathode region 31 in a plan view. The portion of the emitter finger electrode 78 covering the line well region 12 overlaps the cathode region 31 in a plan view. The emitter finger electrode 78 may be formed at an interval from the cathode region 31 toward the side faces 6A to 6D in a plan view. The emitter finger electrode 78 enters the second well opening 63 from above the insulating layer 50 and is electrically connected to the outer periphery of the well region 10.

[0089] 1 and 8, the semiconductor device 1 includes a plurality of (four in this embodiment) field electrodes 80A-80D formed on the first main surface 4 in the outer region 14. Specifically, the field electrodes 80A-80D are each formed on an insulating layer 50.

[0090] The field electrodes 80A-80D are formed in a one-to-one correspondence with the FL regions 41A-41D. The field electrodes 80A-80D are formed in lines extending along the corresponding FL regions 41A-41D. In this embodiment, the field electrodes 80A-80D are formed in rings extending along the corresponding FL regions 41A-41D. The field electrodes 80A-80D enter the corresponding FL openings 64 from above the insulating layer 50 and are electrically connected to the corresponding FL regions 41A-41D. The field electrodes 80A-80D are formed in an electrically floating state.

[0091] The outermost field electrode 80D may include a plate portion 81 extending toward the side surfaces 6A to 6D. The width of the field electrode 80D including the plate portion 81 may be 20 μm or more and 100 μm or less. The width of the field electrode 80D is the width in a direction perpendicular to the direction in which the field electrode 80D extends. The width of the field electrode 80D may be 20 μm or more and 40 μm or less, 40 μm or more and 60 μm or less, 60 μm or more and 80 μm or less, or 80 μm or more and 100 μm.

[0092] 1 and 8, the semiconductor device 1 includes an equipotential electrode 82 formed on the first main surface 4 in the outer region 14. Specifically, the equipotential electrode 82 is formed on the insulating layer 50. The equipotential electrode 82 is formed in a line shape extending along the CS region 42. In this embodiment, the equipotential electrode 82 is formed in a ring shape extending along the CS region 42.

[0093] The equipotential electrodes 82 extend into the corresponding CS openings 65 from above the insulating layer 50, and are electrically connected to the CS regions 42. The outer periphery of the equipotential electrodes 82 is formed at a distance from the side surfaces 6A to 6D toward the inner portion (FL structure 40 side) of the semiconductor substrate 2, and exposes the peripheral portion of the first main surface 4 (CS region 42). The equipotential electrodes 82 are formed in an electrically floating state.

[0094] The insulation distance between the equipotential electrode 82 and the outermost field electrode 80D may be 20 μm to 100 μm. The insulation distance may be 20 μm to 40 μm, 40 μm to 60 μm, 60 μm to 80 μm, or 80 μm to 100 μm.

[0095] The gate principal surface electrode 71, the emitter principal surface electrode 76, the field electrodes 80A to 80D, and the equipotential electrode 82 each include a barrier electrode 83 and a main electrode 84 laminated in this order from the first principal surface 4 side.

[0096] The barrier electrode 83 is formed in the form of a film on the insulating layer 50 (first main surface 4). The barrier electrode 83 may have a single-layer structure including a titanium layer or a titanium nitride layer. The barrier electrode 83 may have a laminated structure including a titanium layer and a titanium nitride layer in any order. The main electrode 84 is formed in the form of a film on the barrier electrode 83. The main electrode 84 may include at least one of a pure Cu layer (a Cu layer having a purity of 99% or more), a pure Al layer (an Al layer having a purity of 99% or more), an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer.

[0097] The semiconductor device 1 includes a collector electrode 85 connected to the second main surface 5. The collector electrode 85 also serves as a cathode electrode of the diode. The collector electrode 85 covers the entire second main surface 5 and is electrically connected to the collector region 20 and the cathode region 31.

[0098] The collector electrode 85 includes at least one of a Ti layer, a Ni layer, a Pd layer, an Au layer, and an Ag layer. The collector electrode 85 may have a laminated structure in which at least two of a Ti layer, a Ni layer, a Pd layer, an Au layer, and an Ag layer are laminated in any order. The collector electrode 85 may have a single layer structure consisting of a Ti layer, a Ni layer, a Pd layer, an Au layer, and an Ag layer. The collector electrode 85 preferably includes a Ti layer as an ohmic electrode. In this embodiment, the collector electrode 85 has a laminated structure including a Ti layer, a Ni layer, a Pd layer, an Au layer, and an Ag layer laminated in this order from the second main surface 5 side.

[0099] Fig. 9 is a graph showing current-voltage characteristics, where the vertical axis represents collector current IC [A] and the horizontal axis represents collector-emitter voltage VCE [V].

[0100] 9 shows a first characteristic S1 (see dashed line) and a second characteristic S2 (see solid line). The first characteristic S1 shows the current-voltage characteristic of the semiconductor device according to the comparative example. The second characteristic S2 shows the current-voltage characteristic of the semiconductor device 1. The semiconductor device according to the comparative example includes a cathode region 31 formed in a region directly below the FET structure 21 in a surface layer portion of the second main surface 5.

[0101] The first characteristic S1 has a snapback waveform in which the collector-emitter voltage VCE increases, then drops sharply and reaches a low impedance region. On the other hand, the second characteristic S2 does not have a snapback waveform like the first characteristic S1.

[0102] In the semiconductor device according to the comparative example, a cathode region 31 is formed in a region directly below the FET structure 21 in the surface layer portion of the second main surface 5. Therefore, when the IGBT starts up (when the collector-emitter voltage VCE starts up), electrons injected from the emitter region 27 flow into the cathode region 31. As a result, a snapback phenomenon occurs, and the switching characteristics deteriorate.

[0103] In contrast, in the semiconductor device 1, the cathode region 31 is not formed in the region directly below the FET structure 21 in the surface layer portion of the second main surface 5. The cathode region 31 in the semiconductor device 1 is formed only in the outer region 14. Specifically, the cathode region 31 in the semiconductor device 1 is formed only in the region directly below the well region 10.

[0104] With this structure, it is possible to prevent electrons injected from the emitter region 27 from flowing into the cathode region 31 during the rising operation of the IGBT (when the collector-emitter voltage VCE rises). As a result, it is possible to prevent degradation of switching characteristics caused by the snapback phenomenon.

[0105] Fig. 10 is a plan view corresponding to Fig. 7, showing the structure of the second main surface 5 of a semiconductor device 91 according to a second embodiment of the present invention. Hereinafter, structures corresponding to those described with respect to the semiconductor device 1 will be denoted by the same reference numerals, and descriptions thereof will be omitted.

[0106] 10, a semiconductor device 91 includes a plurality of (two or more) cathode regions 31 formed only in the outer region 14 in a surface layer portion of the second main surface 5. The plurality of cathode regions 31 are formed only in regions overlapping with the well region 10 in the surface layer portion of the second main surface 5, as in the first embodiment.

[0107] The multiple cathode regions 31 extend in lines along the well region 10 and are formed at intervals in a direction away from the active region 13. Like the cathode region 31 according to the first embodiment, the multiple cathode regions 31 each include a first end 33, a second end 34 on the other side, and a line portion 35 extending through a region between the first end 33 and the second end 34.

[0108] The area ratio RS of the plane area (total plane area) of the plurality of cathode regions 31 to the plane area of ​​the active region 13 is preferably 1% or more and 10% or less. The area ratio RS may be 1% or more and 2% or less, 2% or more and 4% or less, 4% or more and 6% or less, 6% or more and 8% or less, or 8% or more and 10% or less. The area ratio RS is particularly preferably 1% or more and 5% or less.

[0109] As described above, the semiconductor device 91 can also achieve the same effects as those described for the semiconductor device 1.

[0110] Fig. 11 is a plan view corresponding to Fig. 7, showing the structure of the second main surface 5 of the semiconductor device 101 according to the third embodiment of the present invention. Hereinafter, structures corresponding to those described with respect to the semiconductor device 1 will be denoted by the same reference numerals, and descriptions thereof will be omitted.

[0111] 11, the semiconductor device 101 includes a plurality of cathode regions 31 formed only in the outer region 14 in the surface layer portion of the second main surface 5. The plurality of cathode regions 31 are formed only in the region overlapping the well region 10 in the surface layer portion of the second main surface 5, as in the first embodiment.

[0112] The multiple cathode regions 31 are formed at intervals along the well region 10 in a plan view. In this embodiment, the multiple cathode regions 31 are each formed in a circular shape in a plan view. The multiple cathode regions 31 may have any planar shape. The multiple cathode regions 31 may be formed in a linear, polygonal, or elliptical shape.

[0113] Specifically, the multiple cathode regions 31 are formed in the surface layer portion of the second main surface 5 in a region immediately below the line well region 12, exposing the pad well region 11. The occupancy rate of the multiple cathode regions 31 in the region immediately below the line well region 12 preferably exceeds the occupancy rate of the multiple collector regions 20 in the region immediately below the line well region 12.

[0114] On the other hand, the occupancy rate of the multiple cathode regions 31 in the region immediately below the pad well region 11 is preferably less than the occupancy rate of the collector region 20 in the region immediately below the pad well region 11. In this embodiment, the multiple cathode regions 31 are formed only in the region immediately below the line well region 12 in the surface layer portion of the second main surface 5, and are not formed in the region immediately below the pad well region 11 in the surface layer portion of the second main surface 5.

[0115] That is, the multiple cathode regions 31 are formed at intervals on one side (the third side surface 6C side) and the other side (the fourth side surface 6D side) in the first direction X from the pad well region 11. The multiple cathode regions 31 face each other in the first direction X with the pad well region 11 therebetween, forming a gap portion 36 that exposes the pad well region 11.

[0116] The area ratio RS of the plane area (total plane area) of the plurality of cathode regions 31 to the plane area of ​​the active region 13 is preferably 1% or more and 10% or less. The area ratio RS may be 1% or more and 2% or less, 2% or more and 4% or less, 4% or more and 6% or less, 6% or more and 8% or less, or 8% or more and 10% or less. The area ratio RS is particularly preferably 1% or more and 5% or less.

[0117] As described above, the semiconductor device 101 can also achieve the same effects as those described for the semiconductor device 1.

[0118] Fig. 12 is a plan view showing a semiconductor device 111 according to a fourth embodiment of the present invention. Fig. 13 is an enlarged view of a main part of a first main surface 4 of the semiconductor device 111 shown in Fig. 12. Fig. 12 corresponds to the above-mentioned Fig. 1, and Fig. 13 corresponds to the above-mentioned Fig. 4. Hereinafter, structures corresponding to those described with respect to the semiconductor device 1 will be given the same reference numerals and descriptions thereof will be omitted.

[0119] 12 and 13, emitter main surface electrode 76 of semiconductor device 111 does not have emitter finger electrode 78. Gate finger electrode 73 of semiconductor device 111 is formed endlessly surrounding active region 13 in plan view in this embodiment. Gate finger electrode 73 may be formed with ends as in the first embodiment.

[0120] The gate finger electrode 73 faces the outer periphery of the well region 10 with the insulating layer 50 sandwiched therebetween. In this embodiment, the gate finger electrode 73 is formed at a distance from the cathode region 31 on the outer periphery side of the well region 10 in a plan view, exposing the entire cathode region 31. The gate finger electrode 73 does not overlap the cathode region 31 in a plan view. With this structure, current concentration in the semiconductor substrate 2 due to the arrangement of the gate finger electrode 73 and the cathode region 31 can be suppressed.

[0121] The gate finger electrodes 73 may be formed at intervals from the outer periphery of the well region 10 toward the side faces 6A-6D (FL structure 40) in a plan view, exposing the entire well region 10. With such a structure, current concentration in the semiconductor substrate 2 due to the arrangement of the gate finger electrodes 73 and the cathode region 31 can also be suppressed.

[0122] The gate finger electrode 73 may be formed so as to overlap a part of the cathode region 31 in a plan view. In this case, the gate finger electrode 73 is preferably formed so that the exposed portion of the cathode region 31 exceeds the covered portion of the cathode region 31. This structure also makes it possible to suppress current concentration in the semiconductor substrate 2 due to the arrangement of the gate finger electrode 73 and the cathode region 31.

[0123] As described above, the semiconductor device 111 can also achieve the same effects as those described for the semiconductor device 1. The structure of the semiconductor device 111 can also be incorporated into the second and third embodiments.

[0124] The present invention can be embodied in other forms.

[0125] In each of the above-described embodiments, an example has been described in which the emitter main surface electrode 76 is connected to the emitter region 27 and the contact region 29 via a plurality of emitter plug electrodes 67. However, a configuration in which the emitter plug electrode 67 is omitted and the emitter main surface electrode 76 extends into the emitter trench 28 and the emitter opening 61 and is directly connected to the emitter region 27 and the contact region 29 may be employed.

[0126] In the above-described embodiment, a structure in which the conductivity type of each semiconductor portion is inverted may be adopted, that is, the p-type portion may be made n-type and the n-type portion may be made p-type.

[0127] The semiconductor devices 1, 91, 101, 111 according to the first to fourth embodiments can be incorporated into inverter circuits, power factor correction circuits, resonant circuits, etc. However, in an RC-IGBT incorporated into an inverter circuit, the diode is used as a free wheel diode, so that it is preferable that the area ratio RS of the plane area of ​​the cathode region 31 to the plane area of ​​the active region 13 is set to a value exceeding 10% (for example, 15% to 50%). In this case, it is preferable to form the cathode region 31 in the region directly below the FET structure 21, and to use a part or the whole of the base region 22 as the anode region 32.

[0128] On the other hand, in an RC-IGBT incorporated in a power factor correction circuit, a resonant circuit, or the like, a relatively large area ratio RS is not required because the diode is used as a protective device, and it is not necessary to form the cathode region 31 in the region directly below the FET structure 21. In other words, the area ratio RS may be, for example, 1% to 10% (preferably 1% to 5%). In this case, the protective function of the diode can be appropriately improved by suppressing the snapback phenomenon.

[0129] In this way, the RC-IGBT incorporated in the inverter circuit has a different design concept from the RC-IGBT incorporated in the power factor correction circuit, the resonant circuit, etc. Therefore, the semiconductor devices 1, 91, 101, 111 are preferably incorporated in an electric circuit in which a diode is used as a protection device such as a power factor correction circuit, the resonant circuit, etc. (particularly, an electric circuit in which a diode is not actively used as a freewheeling diode).

[0130] Examples of features extracted from this specification and the drawings are given below. The following [A1] to [A17] provide a semiconductor device capable of suppressing degradation of switching characteristics caused by the snapback phenomenon.

[0131] [A1] A semiconductor device including a first conductivity type semiconductor substrate having a first main surface on one side and a second main surface on the other side, a second conductivity type well region formed in a surface layer portion of the first main surface and dividing the semiconductor substrate into an active region and an outer region, a second conductivity type collector region formed in the active region in the surface layer portion of the second main surface, an IGBT including a FET structure formed in the active region in the first main surface, and a first conductivity type cathode region formed only in the outer region in the surface layer portion of the second main surface, and a diode having the well region as an anode region. This semiconductor device can suppress deterioration of switching characteristics caused by the snapback phenomenon.

[0132] [A2] The semiconductor device described in A1, wherein the collector region is formed over the entire surface portion of the second main surface, and the cathode region is formed in a manner such that the second conductivity type impurities in the collector region are offset by the first conductivity type impurities.

[0133] [A3] The semiconductor device according to A1 or A2, wherein the cathode region is formed in a region overlapping the well region.

[0134] [A4] The semiconductor device according to any one of A1 to A3, wherein the cathode region is formed only in a region overlapping the well region.

[0135] [A5] The semiconductor device according to any one of A1 to A4, wherein the cathode region has a planar area of ​​1% to 10% of the planar area of ​​the active region.

[0136] [A6] The semiconductor device according to any one of A1 to A5, wherein the cathode region has a planar area of ​​1% to 5% of the planar area of ​​the active region.

[0137] [A7] The semiconductor device according to any one of A1 to A6, wherein the well region extends in a line, and the cathode region extends in a line along the well region.

[0138] [A8] The semiconductor device according to any one of A1 to A7, wherein the well region is formed endlessly.

[0139] [A9] The semiconductor device according to any one of A1 to A8, wherein the cathode region is formed to have ends.

[0140] [A10] A semiconductor device according to any one of A1 to A9, wherein the well region includes a pad well region formed in an island shape and a line well region extended in a line shape from the pad well region, and the cathode region is formed in a region overlapping the line well region in a planar view.

[0141] [A11] The semiconductor device according to A10, wherein the cathode region is not formed in a region overlapping the pad well region in a plan view.

[0142] [A12] The semiconductor device according to A10 or A11, wherein the cathode region is formed only in a region overlapping the line well region in a plan view.

[0143] [A13] The semiconductor device according to any one of A10 to A12, further including a gate pad covering the pad well region on the first main surface.

[0144] [A14] The semiconductor device according to any one of A10 to A13, further including an emitter pad covering the active region on the first main surface.

[0145] [A15] The semiconductor device according to any one of A1 to A14, further including a second conductivity type FL region formed in a surface layer portion of the first main surface in the outer region and spaced from the cathode region in a direction opposite to the active region in a planar view.

[0146] [A16] The semiconductor device according to A15, wherein the FL region surrounds the well region in a plan view.

[0147] [A17] The semiconductor device according to any one of A1 to A16, further comprising a buffer region of a first conductivity type formed in a surface layer portion of the second main surface, the collector region and the cathode region being each formed in a surface layer portion of the buffer region on the second main surface side.

[0148] This application corresponds to Japanese Patent Application No. 2019-177614 filed with the Japan Patent Office on September 27, 2019, the entire disclosure of which is incorporated herein by reference. Although the embodiments of the present invention have been described in detail, these are merely specific examples used to clarify the technical content of the present invention, and the present invention should not be interpreted as being limited to these specific examples, and the scope of the present invention is limited only by the scope of the appended claims. [Explanation of symbols]

[0149] 1 Semiconductor device 2. Semiconductor Substrate 4 First main surface 5 Second main surface 10 Well Area 11 Pad Well Area 12 Line Well Region 13 Active Area 14 Outer area 20 Collector Region 21 FET structure 31 Cathode Region 32 Anode Region 41A FL area 41B FL area 41C FL area 41D FL area 72 Gate pad electrode 77 Emitter pad electrode 91 Semiconductor Devices 101 Semiconductor device 111 Semiconductor device

Claims

1. a semiconductor substrate of a first conductivity type having a first main surface on one side and a second main surface on the other side; a well region of a second conductivity type formed in a surface layer portion of the first main surface and dividing the semiconductor substrate into an active region and an outer region; an IGBT including a collector region of a second conductivity type formed in the active region in a surface layer portion of the second main surface, and an FET structure formed in the active region in the first main surface; a diode including a cathode region of a first conductivity type formed only in the outer region in a surface layer portion of the second main surface and having the well region as an anode region; The cathode region is formed only in a region overlapping the well region.

2. the collector region is formed over the entire surface portion of the second main surface, 2. The semiconductor device according to claim 1, wherein said cathode region is formed in such a manner that the second conductivity type impurity in said collector region is offset by the first conductivity type impurity.

3. 3. The semiconductor device according to claim 1, wherein the cathode region has a planar area of ​​1% to 10% of a planar area of ​​the active region.

4. 4. The semiconductor device according to claim 1, wherein the cathode region has a planar area of ​​1% to 5% of a planar area of ​​the active region.

5. The well region extends in a line shape, 5. The semiconductor device according to claim 1, wherein the cathode region extends in a line shape along the well region.

6. 6. The semiconductor device according to claim 1, wherein the well region is formed endlessly.

7. 7. The semiconductor device according to claim 1, wherein the cathode region is formed to have ends.

8. The semiconductor device according to any one of claims 1 to 7, further comprising a second conductivity type FL region formed in a surface layer portion of the first main surface in the outer region and spaced apart from the cathode region in a direction opposite to the active region in a plan view.

9. The semiconductor device according to claim 8 , wherein said FL region surrounds said well region in a plan view.

10. a buffer region of a first conductivity type formed in a surface layer portion of the second main surface, 10. The semiconductor device according to claim 1, wherein the collector region and the cathode region are each formed in a surface layer portion of the buffer region on the second main surface side.

11. A semiconductor substrate of a first conductivity type having a first main surface on one side and a second main surface on the other side; a well region of a second conductivity type formed in a surface layer portion of the first main surface and dividing the semiconductor substrate into an active region and an outer region; an IGBT including a collector region of a second conductivity type formed in the active region in a surface layer portion of the second main surface, and an FET structure formed in the active region in the first main surface; a diode including a cathode region of a first conductivity type formed only in the outer region in a surface layer portion of the second main surface, and having the well region as an anode region; A semiconductor device, wherein the cathode region has a planar area of ​​1% to 10% of the planar area of ​​the active region.

12. The collector region is formed over an entire surface portion of the second main surface, 12. The semiconductor device according to claim 11, wherein said cathode region is formed in such a manner that the second conductivity type impurity in said collector region is offset by the first conductivity type impurity.

13. 13. The semiconductor device according to claim 11, wherein the cathode region is formed in a region overlapping the well region.

14. 14. The semiconductor device according to claim 11, wherein the cathode region is formed only in a region overlapping the well region.

15. A semiconductor substrate of a first conductivity type having a first main surface on one side and a second main surface on the other side; a well region of a second conductivity type formed in a surface layer portion of the first main surface and dividing the semiconductor substrate into an active region and an outer region; an IGBT including a collector region of a second conductivity type formed in the active region in a surface layer portion of the second main surface, and an FET structure formed in the active region in the first main surface; a diode including a cathode region of a first conductivity type formed only in the outer region in a surface layer portion of the second main surface, and having the well region as an anode region; The well region includes a pad well region formed in an island shape, and a line well region extended in a line shape from the pad well region, the cathode region is formed in a region overlapping the line well region in a plan view, The cathode region is formed only in a region that overlaps with the line well region in a plan view.

16. a gate finger electrode covering the line well region on the first major surface; The semiconductor device according to claim 15 , wherein the cathode region includes a portion formed in a region overlapping the gate finger electrode in a plan view.

17. the collector region includes a portion formed in a region immediately below the line well region, 17. The semiconductor device according to claim 15, wherein an occupancy rate of said cathode region in said region immediately below said line well region exceeds an occupancy rate of said collector region in said region immediately below said line well region.

18. 18. The semiconductor device according to claim 15, further comprising a gate pad covering the pad well region on the first main surface.

19. 19. The semiconductor device according to claim 15, further comprising an emitter pad covering the active region on the first main surface.

Images