Semiconductor structure and manufacturing method thereof, and memory

Abstract

The present disclosure provides a semiconductor structure, a manufacturing method thereof, and a memory, which solves the technical problem in the field of semiconductor technology that it is difficult to manufacture a semiconductor structure. The semiconductor structure includes a substrate and a conductive structure located above the substrate, the conductive structure includes a plurality of first conductive structures and a plurality of second conductive structures spaced apart from each other and extending along a first direction, and the lengths of the plurality of first conductive structures and the lengths of the plurality of second conductive structures both change in a stepwise manner. The lengths of the plurality of first conductive structures and the lengths of the plurality of second conductive structures both change in a stepwise manner, and the first conductive structures and the second conductive structures form word lines, which are easy to manufacture and draw out, so that other structures can be easily formed on the word lines, and electrical connection between the word lines and peripheral circuits can be realized.

Description

[Technical field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This disclosure claims priority to a Chinese patent application filed on March 23, 2022, bearing application number 202210289743.X and entitled "Semiconductor structure and manufacturing method thereof, and memory," the entire contents of which are incorporated herein by reference.

[0002] The present disclosure relates to the field of semiconductor technology, and in particular to semiconductor structures and methods of manufacture thereof, and memories. [Background technology]

[0003] 2. Description of the Related Art With the development of semiconductor technology, memories, especially dynamic random access memories (DRAMs), have been widely applied to various electronic devices due to their high storage density and fast read / write speed.

[0004] A DRAM typically includes multiple storage units, each of which includes a transistor and a capacitor. The gate of the transistor is electrically connected to a word line (WL) of the DRAM, and the voltage on the word line controls the transistor to be turned on or off. The source / drain of the transistor is electrically connected to a bit line (BL), and the drain / source is electrically connected to a capacitor, and data information is output via the bit line.

[0005] In order to further reduce the size of the memory and increase the storage density of the memory, the capacitors are generally arranged horizontally and have a large length-to-thickness ratio, but the manufacturing difficulty of such memories is relatively high. Summary of the Invention

[0006] In view of the above problems, embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, and a memory, for reducing the manufacturing difficulty of the semiconductor structure.

[0007] According to some embodiments, a first aspect of the present disclosure provides a semiconductor structure including a substrate and a conductive structure located above the substrate, the conductive structure including a plurality of first conductive structures and a plurality of second conductive structures extending along a first direction and spaced apart from each other, wherein lengths of the plurality of first conductive structures and lengths of the plurality of second conductive structures both vary in a step-like manner.

[0008] The semiconductor structure provided by the embodiments of the present disclosure has at least the following advantages:

[0009] In a semiconductor structure provided by an embodiment of the present disclosure, a plurality of first conductive structures and a plurality of second conductive structures are provided above a substrate, the plurality of first conductive structures and the plurality of second conductive structures all extend along a first direction, and the plurality of first conductive structures, the plurality of second conductive structures, and the first conductive structures and the second conductive structures are all spaced apart to achieve insulation isolation. The lengths of the plurality of first conductive structures and the plurality of second conductive structures all change stepwise, the first conductive structures and the second conductive structures form word lines, and since the word lines are easy to manufacture and draw out, other structures can be easily formed on the word lines, and electrical connection between the word lines and peripheral circuits can be achieved.

[0010] According to some embodiments, a second aspect of the present disclosure provides a memory including a substrate including a device region, a device layer overlying the device region, the device layer including a plurality of spaced apart channel structures, a word line structure including a plurality of spaced apart word lines extending along a first direction, the length of the plurality of word lines varying in a step-like manner, and a bit line structure including a plurality of spaced apart bit lines extending along a second direction, the word lines extending through the device layer and surrounding the channel structure, the bit lines extending through the device layer and electrically connected to the channel structure, the channel structure also electrically connected to a storage node.

[0011] The memory provided by the embodiments of the present disclosure has at least the following advantages:

[0012] In a memory provided by an embodiment of the present disclosure, a device layer is provided above a device region of a substrate, the device layer including a plurality of channel structures spaced apart from one another, a plurality of bit lines are spaced apart from one another and extending along a second direction, the bit lines pass through the device layer and are electrically connected to the channel structures, the channel structures are also electrically connected to storage nodes, and a plurality of word lines are spaced apart from one another and extending along a first direction, the length of which varies in a stepped manner, the word lines pass through the device layer and are electrically connected to the channel structures. By forming the word lines that vary in a stepped manner, the word lines are drawn out, making it easier to manufacture the word lines, and further, other structures can be easily formed on the word lines, realizing electrical connections between the word lines and peripheral circuits.

[0013] According to some embodiments, a third aspect of the present disclosure includes: Providing a substrate; The present invention provides a method for manufacturing a semiconductor structure, the method including: forming a conductive structure above the substrate, the conductive structure including a plurality of first conductive structures and a plurality of second conductive structures extending along a first direction and spaced apart from each other, the lengths of the plurality of first conductive structures and the lengths of the plurality of second conductive structures both varying in a step-like manner.

[0014] The method for fabricating a semiconductor structure provided by the embodiments of the present disclosure has at least the following advantages:

[0015] In a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure, a conductive structure including a plurality of first conductive structures and a plurality of second conductive structures spaced apart from each other and extending along a first direction is formed above a substrate, so that the lengths of the plurality of first conductive structures and the lengths of the plurality of second conductive structures all change in a step-like manner, and the first conductive structures and the second conductive structures form word lines. Since the word lines are easy to manufacture and draw out, other structures can be easily formed on the word lines, and electrical connection between the word lines and peripheral circuits can be realized. [Brief description of the drawings]

[0016] [Figure 1] FIG. 1 is a diagram illustrating an example of a configuration of a semiconductor structure in an embodiment of the present disclosure. [Diagram 2] 1 illustrates a memory architecture according to one embodiment of the present disclosure. [Diagram 3] 1 is a flow chart of a method for manufacturing a semiconductor structure in one embodiment of the present disclosure. [Figure 4] FIG. 2 is a diagram illustrating an example of a configuration after a first stacked structure, a second stacked structure, and a third stacked structure are formed in an embodiment of the present disclosure. [Diagram 5] FIG. 2 is a diagram illustrating an example of a configuration after a first trench is formed in an embodiment of the present disclosure. [Figure 6] FIG. 13 is a diagram illustrating an example of a configuration after a channel structure is formed in one embodiment of the present disclosure. [Figure 7] FIG. 2 is an exemplary diagram illustrating a configuration after removing a portion of the first active layer and a portion of the second active layer in one embodiment of the present disclosure. [Figure 8] FIG. 2 is a diagram illustrating an example of a configuration after forming a first conductive structure and a second conductive structure in an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] In the related art, in order to further increase the storage capacity of the memory, the capacitor is usually fabricated by arranging the capacitor horizontally, that is, by making the extension direction of the capacitor parallel to the substrate. When arranging the capacitor horizontally, it is necessary to rearrange both the bit line structure and the word line structure to fit the capacitor, which makes the memory fabrication relatively difficult.

[0018] In view of this, the present disclosure provides a semiconductor structure and a manufacturing method thereof, and a memory, wherein a plurality of first conductive structures and a plurality of second conductive structures are provided above a substrate, and the lengths of the plurality of first conductive structures and the lengths of the plurality of second conductive structures all change in a step-like manner, the first conductive structures and the second conductive structures form word lines, and since the word lines are easy to manufacture and pull out, other structures can be easily formed on the word lines, and electrical connection between the word lines and peripheral circuits can be realized.

[0019] In order to facilitate a clearer understanding of the above objectives, features and advantages of the embodiments of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, and are not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without incurring creative labor should belong to the protection scope of the present disclosure.

[0020] 1, a first aspect of an embodiment of the present disclosure provides a semiconductor structure, which includes a substrate 10 and a conductive structure located above the substrate 10. Here, the material of the substrate 10 may be a semiconductor, for example, the material of the substrate 10 may be single crystal silicon, polycrystalline silicon, amorphous silicon, germanium, silicon carbide, silicon germanide, germanium on insulator (GOI) or silicon on insulator (SOI), etc., or may be other materials known to those skilled in the art.

[0021] Continuing to refer to FIG. 1, the conductive structure includes a plurality of spaced apart first conductive structures 50 and a plurality of second conductive structures 60, both of which extend along a first direction, and the lengths of the plurality of first conductive structures 50 and the plurality of second conductive structures 60 both vary in a step-like manner.

[0022] The above "a plurality of first conductive structures 50 and a plurality of second conductive structures 60 spaced apart" means that a plurality of first conductive structures 50 and a plurality of second conductive structures 60 are stacked and arranged along the second direction, and the plurality of first conductive structures 50 are arranged at intervals from each other, and a plurality of second conductive structures are arranged at intervals from each other, so as to ensure the insulation and isolation of each first conductive structure 50 and each second conductive structure 60. The second direction can cross the first direction, and preferably, the second direction is perpendicular to the first direction so as to make the arrangement of the plurality of first conductive structures 50 and the plurality of second conductive structures 60 more compact. Exemplarily, the first direction is a direction parallel to the substrate 10 (the X direction in FIG. 1), and the second direction is a direction perpendicular to the substrate 10 (the Y direction in FIG. 1).

[0023] By providing in this manner, the lengths of the plurality of first conductive structures 50 and the plurality of second conductive structures 60 both change in a stepped manner, and the first conductive structures 50 and the second conductive structures 60 form word lines such that each word line has a lead-out end. Because the word lines are easy to manufacture and lead-out, other structures can be easily formed on the word lines, and electrical connection between the word lines and peripheral circuits can be realized.

[0024] Specifically, the first conductive structures 50 and the second conductive structures 60 have a partially overlapping region when orthogonally projected on the substrate 10. To realize the stacking of the first conductive structures 50 and the second conductive structures 60, at least one first conductive structure 50 is located between the second conductive structures 60, or at least one second conductive structure 60 is located between the first conductive structures 50. This arrangement can fully utilize the space above the substrate 10, and the distribution of the lead ends of the first conductive structures 50 and the second conductive structures 60 is uniform.

[0025] Preferably, a plurality of first conductive structures 50 and a plurality of second conductive structures 60 are provided alternately in the second direction. That is, one second conductive structure 60 is provided between each two adjacent first conductive structures 50, or one first conductive structure 50 is provided between each two adjacent second conductive structures 60. By providing them in this manner, the distance between two adjacent first conductive structures 50 and the distance between two adjacent second conductive structures 60 in the second direction are approximately equal, and the distribution of the lead ends of the first conductive structures 50 and the lead ends of the second conductive structures 60 becomes more uniform. In this way, the first conductive structures 50 and the second conductive structures 60 are approximately symmetrical, and the space above the substrate 10 can be fully utilized.

[0026] 1 , the plurality of first conductive structures 50 extend along a first direction, and the lengths of the plurality of first conductive structures 50 change stepwise, and the plurality of second conductive structures 60 extend along the first direction, and the lengths of the plurality of second conductive structures 60 change stepwise. By providing in this manner, each of the first conductive structures 50 and each of the second conductive structures 60 is partially exposed, and the exposed portions can be used as the leading ends of the first conductive structures 50 and each of the second conductive structures 60, so that each of the first conductive structures 50 and each of the second conductive structures 60 can be easily led out and connected to peripheral circuits.

[0027] In one possible implementation, the length of the first conductive structure 50 closer to the substrate 10 is greater than the length of the first conductive structure 50 farther from the substrate 10, such that the lengths of the multiple first conductive structures 50 change in a step-like manner, and the length of the second conductive structure 60 closer to the substrate 10 is greater than the length of the second conductive structure 60 farther from the substrate 10, such that the lengths of the multiple second conductive structures 60 change in a step-like manner.

[0028] Specifically, the lengths of the first conductive structures 50 along the first direction are successively shortened so that the portions of the first conductive structures 50 that are separated from the second conductive structures 60 change in a stepped manner along the direction away from the substrate 10, forming a step at the left end of the first conductive structures 50 as shown in FIG. 1. The lengths of the second conductive structures 60 along the first direction are successively shortened so that the portions of the second conductive structures 60 that are separated from the first conductive structures 50 change in a stepped manner, forming a step at the right end of the second conductive structures 60 as shown in FIG. 1. The ends of each of the first conductive structures 50 and each of the second conductive structures 60 that are spaced apart from each other are all partially exposed, and the ends are all away from the channel structure 23 at the center of the substrate 10, so that the manufacturing space is large and there is little interference with the channel structure 23.

[0029] In some possible embodiments, the substrate 10 includes a device region and a first connection region and a second connection region provided on either side of the device region, where a semiconductor device such as a transistor is provided on the device region, and the first connection region and the second connection region are both used to draw out the semiconductor device in the device region so that the semiconductor device is electrically connected to peripheral circuits.

[0030] The first connection region and the second connection region are provided on both sides facing the device region, and for example, the first connection region, the device region, and the second connection region are arranged in order along a first direction. As shown in Fig. 1, the first direction is the horizontal direction (X direction), the first connection region is the region shown in A of Fig. 1, the device region is the region shown in B of Fig. 1, and the second connection region is the region shown in C of Fig. 1, the first connection region is located on the left side of the device region, and the second connection region is located on the right side of the device region.

[0031] In some possible examples, the substrate 10 located in the device region, the substrate 10 located in the first connection region, and the substrate 10 located in the second connection region are integral, i.e., the substrate 10 located in the device region, the substrate 10 located in the first connection region, and the substrate 10 located in the second connection region are connected to each other. In some other possible examples, the substrate 10 located in the first connection region and / or the substrate 10 located in the second connection region are spaced apart from the substrate 10 located in the device region, i.e., there is a gap between at least one of the substrate 10 located in the first connection region and the substrate 10 located in the second connection region and the substrate 10 located in the device region. Preferably, the substrate 10 located in the first connection region, the substrate 10 located in the second connection region, and the substrate 10 located in the device region are all spaced apart to provide the substrate 10 and subsequently form desired structures on the substrate 10, respectively.

[0032] Based on the above embodiment, i.e., based on the substrate 10 including a device region and a first connection region and a second connection region respectively provided on either side of the device region, in some possible implementations, the first conductive structure 50 is located above the device region and extends to the first connection region, the second conductive structure 60 is located above the device region and extends to the second connection region, the length of the first conductive structure 50 located above the first connection region changes in a step-like manner, and the length of the second conductive structure 60 located above the second connection region changes in a step-like manner.

[0033] As shown in Fig. 1, the first conductive structure 50 is provided above the device region and above the first connection region, and the second conductive structure 60 is provided above the device region and above the second connection region. The length of the first conductive structure 50 located above the first connection region changes stepwise, so that the first conductive structure 50 located above the first connection region forms a first step, and the first conductive structure 50 is drawn out through the step surface of the first step. The length of the second conductive structure 60 located above the second connection region changes stepwise, so that the second conductive structure 60 located above the second connection region forms a second step, and the second conductive structure 60 is drawn out through the step surface of the second step.

[0034] In some possible embodiments, the device region is provided with a plurality of spaced apart channel structures 23, and each of the first conductive structures 50 and each of the second conductive structures 60 located above the device region surrounds the plurality of spaced apart channel structures 23, and a dielectric layer is provided between the first conductive structures 50 and the channel structures 23, and between the second conductive structures 60 and the channel structures 23.

[0035] As shown in FIG. 1, the channel structure 23 may be provided in a plurality, and the plurality of channel structures 23 may be arranged in an array. The plurality of channel structures 23 are arranged at intervals not only along the first direction but also along the second direction, and each channel structure 23 extends along a third direction. The first direction and the second direction cross each other, and are both perpendicular to the third direction. In the embodiment of the present disclosure, the first direction and the second direction are perpendicular to each other. This arrangement method makes the arrangement of the channel structures 23 more compact, makes the arrangement method more suitable, maximizes the number of the channel structures 23, and improves the storage density of the semiconductor structure. Of course, the embodiment of the present disclosure does not limit the angle between the first direction and the second direction, and the user can select according to the actual situation.

[0036] Specifically, a source and a drain are provided at both ends of the channel structure 23, the source, the channel structure 23 and the drain form a source pillar, and the source, the channel structure 23 and the drain are stacked in sequence along the third direction. That is, the extension direction of the active pillar is the third direction, and the subsequently formed transistors are arranged along the third direction, and the third direction is parallel to the substrate 10. The shape of the active pillar may be a cylinder, a prism, a rectangular parallelepiped or other shape, and the embodiments of the present disclosure do not limit the shape of the active pillar, and users can select according to actual situations.

[0037] Each first conductive structure 50 located above the device region surrounds a plurality of spaced apart channel structures 23, and each second conductive structure 60 located above the device region surrounds a plurality of spaced apart channel structures 23. The first conductive structures 50 and the second conductive structures 60 located above the device region each form a gate, and a dielectric layer (not shown) is provided between the first conductive structures 50 and the channel structures 23, and a dielectric layer is provided between the second conductive structures 60 and the channel structures 23. The gate, the dielectric layer and the active pillar form a Gate All Around transistor (GAA), which has a smaller feature size than a planar transistor and can effectively increase the integration density of the semiconductor structure and memory capacity when occupying the same substrate 10 area.

[0038] Continuing to refer to FIG. 1, each first conductive structure 50 located above the first connection region surrounds the first active layer 31, with a first insulating layer (not shown) provided between the first conductive structure 50 and the first active layer 31, and each second conductive structure 60 located above the second connection region surrounds the second active layer 41, with a second insulating layer (not shown) provided between the second conductive structure 60 and the second active layer 41.

[0039] Here, each first conductive structure 50 located above the first connection region is used to draw out its corresponding gate above the device region, and each second conductive structure 60 located above the second connection region is used to draw out its corresponding gate in the device region, i.e., the gate of a transistor above the device region is drawn out by the first conductive structure 50 in the first connection region and the second conductive structure 60 in the second connection region, respectively, and connected to a peripheral circuit.

[0040] Specifically, each first conductive structure 50 located above the first connection region surrounds a first active layer 31, which can be used as a support layer for the first conductive structure 50 for forming the first conductive structure 50 thereon. A first insulating layer is provided between the first conductive structure 50 and the first active layer 31, and the material of the first insulating layer can be the same as the material of the dielectric layer, so that the first insulating layer and the dielectric layer are formed simultaneously, thereby simplifying the manufacturing process of the semiconductor structure, so that the first conductive structure 50 above the first connection region and the first conductive structure 50 above the device region are formed simultaneously.

[0041] Each second conductive structure 60 located above the second connection region surrounds a second active layer 41, which can be used as a support layer for the second conductive structure 60 to be formed thereon. A second insulating layer is provided between the second conductive structure 60 and the second active layer 41, and the material of the second insulating layer can be the same as the material of the dielectric layer, so that the second insulating layer and the dielectric layer are formed simultaneously, thereby the second conductive structure 60 above the second connection region and the second conductive structure 60 above the device region are formed simultaneously, which can simplify the manufacturing process of the semiconductor structure.

[0042] Going one step further, the first insulating layer, the second insulating layer and the dielectric layer may be made of the same material, thereby allowing the first conductive structures 50 and the second conductive structures 60 to be formed simultaneously, further simplifying the manufacturing process of the semiconductor structure. The materials of the first insulating layer, the second insulating layer and the dielectric layer may be oxides such as silicon oxide, hafnium oxide, zirconium oxide, etc.

[0043] In some possible embodiments, a first active layer 31 and multiple channel structures 23 corresponding to the same first conductive structure 50 are provided in the same layer, and a second active layer 41 and multiple channel structures 23 corresponding to the same second conductive structure 60 are provided in the same layer.

[0044] 1, each first conductive structure 50 located above the device region surrounds a plurality of spaced apart channel structures 23, and each first conductive structure 50 located above the first connection region surrounds a first active layer 31. Here, the first active layer 31 and the plurality of channel structures 23 corresponding to the same first conductive structure 50 are provided in the same layer, so that the arrangement of the first conductive structures 50 is more optimized, the occupied space is smaller, the thickness of the first conductive structures 50 is more uniform, and the flatness is better.

[0045] Similarly, each second conductive structure 60 located above the device region surrounds a plurality of spaced apart channel structures 23, and each second conductive structure 60 located above the second connection region surrounds a second active layer 41. Here, the second active layer 41 and the plurality of channel structures 23 corresponding to the same second conductive structure 60 are provided in the same layer, so that the arrangement of the second conductive structure 60 is more optimized, the occupied space is smaller, the thickness of the second conductive structure 60 is more uniform, and the flatness is better.

[0046] 1, the semiconductor structure further includes a plurality of spaced apart contact plugs, the contact plugs including first contact plugs 70 and second contact plugs 80, the plurality of first contact plugs 70 being electrically connected to the plurality of first conductive structures 50 in one-to-one correspondence, and the plurality of second contact plugs 80 being electrically connected to the plurality of second conductive structures 60 in one-to-one correspondence. The plurality of contact plugs are used to electrically connect the first conductive structures 50 and the second conductive structures 60 to peripheral circuits, and the plurality of contact plugs are spaced apart to ensure insulation isolation between the plurality of contact plugs, thereby avoiding mutual interference between the first conductive structures 50 or the second conductive structures 60.

[0047] Specifically, the contact plugs include first contact plugs 70 and second contact plugs 80, and the number of first contact plugs 70 is set to match the number of first conductive structures 50, so that the first contact plugs 70 are electrically connected to the first conductive structures 50 in one-to-one correspondence, thereby electrically connecting all the first conductive structures 50 to the peripheral circuits, and controlling the transistors corresponding to the first conductive structures 50 through the peripheral circuits. The number of second contact plugs 80 is set to match the number of second conductive structures 60, so that the second contact plugs 80 are electrically connected to the second conductive structures 60 in one-to-one correspondence, thereby electrically connecting all the second conductive structures 60 to the peripheral circuits, and controlling the transistors corresponding to the second conductive structures 60 through the peripheral circuits.

[0048] Illustratively, each of the first conductive structures 50 and each of the second conductive structures 60 has a first surface and a second surface disposed opposite to each other, where the first surface is a side away from the substrate 10 and the second surface is a side closer to the substrate 10. A first contact plug 70 contacts the first surface of the first conductive structure 50, and a second contact plug 80 contacts the first surface of the second conductive structure 60.

[0049] As shown in FIG. 1, the first contact plugs 70 and the second contact plugs 80 are both extended along the second direction, and the lengths of the first contact plugs 70 and the second contact plugs 80 are both changed in a step-like manner. The first contact plugs 70 can be arranged along the first direction, and the second contact plugs 80 can be arranged along the first direction. By providing in this manner, the space occupied by the first contact plugs 70 and the second contact plugs 80 is smaller, which is favorable for increasing the number of transistors, thereby increasing the memory density of the semiconductor structure. Preferably, in order to further reduce the space occupied by the first contact plugs 70 and the second contact plugs 80, the first contact plugs 70 and the second contact plugs 80 are located in the same row along the first direction.

[0050] The lengths of the first contact plugs 70 change stepwise, and the lengths of the second contact plugs 80 change stepwise, where the length direction is the second direction. By providing them in this manner, the lengths of the first contact plugs 70 and the second contact plugs 80 are approximately equal, and the paths between the peripheral circuit and the first conductive structure 50 and between the peripheral circuit and the second conductive structure 60 are approximately equal, thereby reducing the difference in the operating state of each transistor in the device region.

[0051] Continuing to refer to FIG. 1, the first contact plug 70 and the second contact plug 80 each include a first conductive portion and a second conductive portion provided on the first conductive portion, and the size of the first conductive portion is smaller than the size of the second conductive portion. Here, the first conductive portion is a portion close to the substrate 10, and the second conductive portion is a portion far from the substrate 10, that is, the second conductive portion is located on one side of the first conductive portion far from the substrate 10. The first conductive portion of the first contact plug 70 contacts the first conductive structure 50, and the first conductive portion of the second contact plug 80 contacts the second conductive structure 60. The size of the first conductive portion may refer to the diameter or cross-sectional area of ​​the first conductive portion, and the size of the second conductive portion may refer to the diameter or cross-sectional area of ​​the second conductive portion. As shown in FIG. 1, the orthogonal projection of the second conductive portion on the substrate 10 covers the orthogonal projection of the first conductive portion on the substrate 10.

[0052] Each of the first conductive portion and the second conductive portion may include a core layer and an outer layer covering the side and bottom surfaces of the core layer. Here, the core layer may be an insulating layer, and the material may be silicon nitride or silicon oxide. The outer layer may be a metal layer, and the material may be tungsten or titanium nitride. By providing them in this way, the thickness of the metal layer can be thinned to reduce costs while ensuring the electrical characteristics of the first conductive portion and the second conductive portion.

[0053] As described above, in the semiconductor structure according to the embodiment of the present disclosure, a plurality of first conductive structures 50 and a plurality of second conductive structures 60 are provided above the substrate 10, and the plurality of first conductive structures 50 and the plurality of second conductive structures 60 all extend along a first direction, and the plurality of first conductive structures 50, the plurality of second conductive structures 60, and the first conductive structures 50 and the second conductive structures 60 are all provided with intervals to be insulated and isolated from each other. The lengths of the plurality of first conductive structures 50 and the plurality of second conductive structures 60 all change stepwise, and the first conductive structures 50 and the second conductive structures 60 form word lines. Since the word lines are easy to manufacture and draw out, other structures can be easily formed on the word lines, and electrical connection between the word lines and peripheral circuits can be realized.

[0054] 1 and 2, an embodiment of the present disclosure further provides a memory, which may include, for example, a dynamic random access memory, a static random access memory (SRAM), a flash memory, an electrically erasable programmable read-only memory (EEPROM), a phase change random access memory (PRAM), or a magnetoresistive random access memory (MRAM), etc. The embodiment of the present disclosure will be described taking the dynamic random access memory as an example.

[0055] 1 and 2, the memory includes a substrate 10, a device layer, a word line structure 2, and a bit line structure 1. Here, the material of the substrate 10 can be a semiconductor substrate, for example, the material of the substrate 10 can be single crystal silicon, polycrystalline silicon, amorphous silicon, germanium, silicon carbide, silicon germanide, germanium on insulator, silicon on insulator, etc.

[0056] The substrate 10 includes a device region, and a device layer is provided above the device region, and the device layer includes a plurality of spaced apart channel structures 23. In some possible embodiments, the substrate 10 further includes a first connection region and a second connection region, and the device region is located between the first connection region and the second connection region, and the first connection region and the second connection region are used to draw out the word line structure 2. Exemplarily, the first connection region, the device region, and the second connection region are sequentially arranged along a first direction. The substrate 10 located in the device region and the substrate 10 located in the first connection region and the second connection region are all spaced apart to provide the substrate 10 and form the necessary structures on the substrate 10, respectively.

[0057] The channel structures 23 may be arranged in an array, in which the channel structures 23 are spaced apart not only in the first direction but also in the second direction, and extend along a third direction, in which the first direction (X direction in FIG. 1) and the second direction (Y direction in FIG. 1) cross each other and are both perpendicular to the third direction (Z direction in FIG. 2). Such an arrangement makes the arrangement of the channel structures 23 more compact and more suitable, maximizing the number of the channel structures 23 arranged, and increasing the storage density of the semiconductor structure.

[0058] A source and a drain are provided at both ends of the channel structure 23, respectively, and the source, the channel structure 23, and the drain form an active pillar, and the source, the channel structure 23, and the drain are stacked in order along a third direction, i.e., the extension direction of the active pillar is the third direction. The shape of the active pillar can be a cylinder, a prism, a rectangular parallelepiped, or other shape. The third direction is a direction parallel to the substrate 10, i.e., the extension direction of the active pillar is parallel to the substrate 10.

[0059] The word line structure 2 includes a plurality of spaced apart word lines extending along a first direction, the length of the plurality of word lines varying stepwise, the word lines penetrating the device layers and surrounding the channel structure 23. The word lines are used to control whether or not the source and the drain are electrically connected. The bit line structure 1 includes a plurality of spaced apart bit lines extending along a second direction, the bit lines penetrating the device layers and electrically connected to the channel structure 23, which is also electrically connected to the storage node. The bit lines are used to read data information of the storage node.

[0060] Specifically, each word line surrounds a plurality of channel structures 23 spaced apart in a first direction, each bit line is connected to one end of a plurality of channel structures 23 spaced apart in a second direction, and the other end of the channel structure 23 is connected to a storage node. Exemplarily, one end of the channel structure 23 is a drain, which contacts a bit line, and the other end of the channel structure 23 is a source, which contacts a storage node, which may be a capacitor 4.

[0061] In an embodiment in which the substrate 10 further includes a first connection region and a second connection region, the lengths of the word lines located above the first connection region vary in a stepwise manner, and the lengths of the word lines located above the second connection region vary in a stepwise manner.

[0062] A part of the word line is located in the device region and extends to the first connection region, and a remaining part of the word line is located in the device region and extends to the second connection region. The word line located in the device region is used as a gate, and a dielectric layer is provided between the word line and the channel structure 23, and the gate, source, drain, channel structure 23 and dielectric layer form a transistor 3, which is a gate-all-around transistor, and compared with a planar transistor, the feature size of the gate-all-around transistor is smaller, and when occupying the same substrate 10 area, it can effectively increase the integration degree of the semiconductor structure and increase the memory capacity.

[0063] The lengths of the word lines located above the first connection region are changed in a stepped manner such that a portion of the word lines forms a step along the second direction. The word lines located above the second connection region are structurally changed such that the portion forms a step along the second direction. To facilitate connection to peripheral circuits, the word lines have portions located above the first and second connection regions as gate pull-out ends.

[0064] In some possible examples, each word line located above the first connection region surrounds a first active layer 31, which can be used as a support layer for the word line for its formation. A first insulating layer is provided between the word line located above the first connection region and the first active layer 31. Each word line located above the second connection region surrounds a second active layer 41, which can be used as a support layer for the word line for its formation. A second insulating layer is provided between the word line located above the second connection region and the second active layer 41.

[0065] In addition, the memory further includes a plurality of support layers and an isolation layer, the plurality of support layers being provided between adjacent transistors 3 along the second direction, and the isolation layers being filled between the word lines. The provision of the support layers, on the one hand, can facilitate stacking of the transistors 3 in the second direction, and, on the other hand, can electrically isolate the adjacent transistors 3. The provision of the isolation layers can electrically isolate the adjacent transistors 3, and can prevent mutual interference between the transistors 3.

[0066] In some possible embodiments, the memory further includes a plurality of contact plugs arranged at intervals, the contact plugs being electrically connected to the word lines in one-to-one correspondence to connect the word lines to the peripheral circuit. The contact plugs include a plurality of first contact plugs 70 located in the first connection region and a plurality of second contact plugs 80 located in the second connection region, the plurality of first contact plugs 70 and the plurality of second contact plugs 80 both extending along the second direction, and the lengths of the plurality of first contact plugs 70 and the plurality of second contact plugs 80 both change stepwise. By providing in this manner, the lengths of the plurality of first contact plugs 70 and the plurality of second contact plugs 80 are approximately equal, and the paths of the peripheral circuit and each word line are approximately equal, thereby reducing the difference in the operating state of each transistor in the device region.

[0067] As described above, in the memory according to the embodiment of the present disclosure, a device layer is provided above a device region of a substrate 10, the device layer includes a plurality of spaced apart channel structures 23, a plurality of bit lines are spaced apart and extend along a second direction, the bit lines penetrate the device layer and are electrically connected to the channel structures 23, the channel structures 23 are further electrically connected to storage nodes, and a plurality of spaced apart word lines are spaced apart and extend along a first direction, the length of which varies stepwise, the word lines penetrate the device layer and are electrically connected to the channel structures 23. By forming the word lines that vary stepwise, the word lines can be drawn out to facilitate the manufacture of the word lines, and further, other structures can be easily formed on the word lines, and electrical connection between the word lines and peripheral circuits is realized.

[0068] Referring to FIG. 3, an embodiment of the present disclosure further provides a method for manufacturing a semiconductor structure, the method including steps S10 to S20.

[0069] In step S10, a substrate is provided.

[0070] 4, the material of the substrate 10 may be a semiconductor substrate, for example, the material of the substrate 10 may be single crystal silicon, polycrystalline silicon, amorphous silicon, germanium, silicon carbide, silicon germanide, germanium-on-insulator, or silicon-on-insulator. In some possible embodiments, the substrate 10 includes a device region and a first connection region and a second connection region provided on both sides of the device region, respectively. Here, a semiconductor device such as a transistor is provided in the device region, and the first connection region and the second connection region are both used to draw out the semiconductor device in the device region in order to electrically connect the semiconductor device to a peripheral circuit.

[0071] Exemplarily, a first connection region (as shown in A of FIG. 4), a device region (as shown in B of FIG. 4), and a second connection region (as shown in C of FIG. 4) are arranged in sequence along a first direction. The first direction is the horizontal direction (X direction) shown in FIG. 1, the first connection region is located on the left side of the device region, and the second connection region is located on the right side of the device region. The substrate 10 located in the device region, the substrate 10 located in the first connection region, and the substrate 10 located in the second connection region may be integral or spaced apart. For example, there is a gap between at least one of the substrate 10 located in the first connection region and the substrate 10 located in the second connection region and the substrate 10 located in the device region. Preferably, the substrate 10 located in the first connection region, the substrate 10 located in the second connection region, and the substrate 10 located in the device region are all spaced apart to provide the substrate 10 and form the required structures on the substrate 10, respectively.

[0072] In step S20, a conductive structure is formed above the substrate, the conductive structure including a plurality of first conductive structures and a plurality of second conductive structures extending along a first direction spaced apart from each other, and the lengths of the plurality of first conductive structures and the plurality of second conductive structures both change in a step-like manner. 5 to 8, the first conductive structures 50 and the second conductive structures 60 are stacked along the second direction, and the first conductive structures 50 are spaced apart, and the second conductive structures 60 are spaced apart, so as to ensure insulation between the first conductive structures 50 and the second conductive structures 60. The second direction can cross the first direction, and is preferably perpendicular to the first direction so as to make the arrangement of the first conductive structures 50 and the second conductive structures 60 more compact. Exemplarily, the first direction is parallel to the substrate 10 (X direction in FIG. 8), and the second direction is perpendicular to the substrate 10 (Y direction in FIG. 8).

[0073] The first conductive structures 50 and the second conductive structures 60 are provided alternately and at intervals in the second direction. That is, one second conductive structure 60 is provided between each two adjacent first conductive structures 50, or one first conductive structure 50 is provided between each two adjacent second conductive structures 60. By providing them in this manner, the distance between two adjacent first conductive structures 50 and the distance between two adjacent second conductive structures 60 are approximately equal along the second direction, the distribution of the lead ends of the first conductive structures 50 and the lead ends of the second conductive structures 60 becomes more uniform, the first conductive structures 50 and the second conductive structures 60 become approximately symmetrical, and the space above the substrate 10 can be fully utilized.

[0074] The multiple first conductive structures 50 extend along a first direction, and the lengths of the multiple first conductive structures 50 change stepwise, and the multiple second conductive structures 60 extend along the first direction, and the lengths of the multiple second conductive structures 60 change stepwise. By providing them in this manner, each of the first conductive structures 50 and each of the second conductive structures 60 is partially exposed, which makes it easy to draw out each of the first conductive structures 50 and each of the second conductive structures 60 and connect them to peripheral circuits.

[0075] Specifically, the first conductive structure 50 is located above the device region and extends to the first connection region, and the second conductive structure 60 is located above the device region and extends to the second connection region, the length of the first conductive structure 50 located above the first connection region changes in a step-like manner, and the length of the second conductive structure 60 located above the second connection region changes in a step-like manner. That is, the first conductive structure 50 is provided above the device region and above the first connection region, and the second conductive structure 60 is provided above the device region and above the second connection region. The length of the first conductive structure 50 located above the first connection region changes in a step-like manner, so that the first conductive structure 50 located above the first connection region forms a first step, and the first conductive structure 50 is drawn out through the step surface of the first step. The length of the second conductive structure 60 located above the second connection region changes stepwise, so that the second conductive structure 60 located above the second connection region forms a second step, and the second conductive structure 60 is pulled out through the step surface of the second step.

[0076] In one specific implementation, forming a conductive structure above the substrate 10 (step S20) includes step S21. In step S21, a first stacked structure, a second stacked structure and a third stacked structure are formed in the device region, the first connection region and the second connection region of the substrate, respectively, where the first stacked structure includes a first sacrificial layer and a device layer that are alternately stacked, the second stacked structure includes a second sacrificial layer and a first active layer that are alternately stacked, and the third stacked structure includes a third sacrificial layer and a second active layer that are alternately stacked, wherein the multiple first active layers correspond one-to-one to the device layers of the first portion, and the multiple second active layers correspond one-to-one to the device layers of the second portion.

[0077] As shown in FIG. 4, a first stacked structure 20 is formed in the device region of the substrate 10, a second stacked structure 30 is formed in the first connection region of the substrate 10, and a third stacked structure 40 is formed in the second connection region of the substrate 10. The first stacked structure 20 includes a plurality of first sacrificial layers 22 and a plurality of device layers 21, and the first sacrificial layers 22 and the device layers 21 are provided by stacking them in order along the second direction. The second stacked structure 30 includes a plurality of second sacrificial layers 32 and a plurality of first active layers 31, and the second sacrificial layers 32 and the first active layers 31 are provided by stacking them in order along the second direction. The third stacked structure 40 includes a plurality of third sacrificial layers 42 and a plurality of second active layers 41, and the third sacrificial layers 42 and the second active layers 41 are provided by stacking them in order along the second direction.

[0078] Here, the first active layers 31 correspond one-to-one to the device layers 21 of the first portion, and the second active layers 41 correspond one-to-one to the device layers 21 of the second portion. Preferably, the first active layers 31 correspond to the odd device layers 21 and are provided in the same layer, and the second active layers 41 correspond to the even device layers 21 and are provided in the same layer. By providing them in this manner, the distance between adjacent first active layers 31 in the second direction is approximately equal to the distance between adjacent second active layers 41 in the second direction, so that the distribution of the structure above the first connection region and the structure above the second connection region is more uniform and symmetrically close, and the space can be fully utilized.

[0079] In some possible examples, the first sacrificial layer 22 is located on the outermost side of the first stacked structure 20, close to the substrate 10, i.e., the first sacrificial layer 22 is located on the substrate 10. By providing in this manner, the device layers 21 of each layer can all subsequently form transistors 3, increasing the number of transistors 3 and thereby increasing the memory density of the semiconductor structure. Correspondingly, the second sacrificial layer 32 and the third sacrificial layer 42 are also located on the substrate 10.

[0080] The material of the first active layer 31 includes N-doped silicon, the material of the first sacrificial layer 22 includes silicon germanide, the materials of the first active layer 31, the second active layer 41 and the third active layer are the same, and the materials of the first sacrificial layer 22, the second sacrificial layer 32 and the third sacrificial layer 42 are the same. The first active layer 31, the second active layer 41, the third active layer, the first sacrificial layer 22, the second sacrificial layer 32 and the third sacrificial layer 42 can all be formed by a deposition process.

[0081] In step S22, the first sacrificial layer and portions of the device layer are removed such that each device layer forms a plurality of spaced apart channel structures.

[0082] 4 and 5, the channel structures 23 may be arranged in an array, the channel structures 23 being spaced apart not only in the first direction but also in the second direction, and extending along a third direction, the first direction intersecting with the second direction and both perpendicular to the third direction. This arrangement makes the arrangement of the channel structures 23 more compact and more suitable, and can maximize the number of the channel structures 23 arranged, thereby increasing the storage density of the semiconductor structure.

[0083] The device layer 21 further forms a source and a drain located at both ends of the channel structure 23, respectively, and the source, the channel structure 23 and the drain form an active pillar, and the source, the channel structure 23 and the drain are stacked in order along a third direction, i.e., the extension direction of the active pillar is the third direction. The shape of the active pillar can be a cylinder, a prism, a rectangular parallelepiped or other shape. The third direction is a direction parallel to the substrate 10, i.e., the extension direction of the active pillar is parallel to the substrate 10.

[0084] In some possible implementations, referring to Figures 5 and 6, removing the first sacrificial layer 22 and a portion of the device layer 21 so that each device layer 21 forms a plurality of spaced apart channel structures 23 includes: A plurality of first trenches 24 are formed in the first stack structure 20 at intervals and extending along a third direction, the first trenches 24 expose the substrate 10, and each device layer 21 is separated into a plurality of active pillars at intervals, and the active pillars include channel structures 23. Specifically, as shown in FIG. 5, a mask layer 90 is first formed on the first stack structure 20, the second stack structure 30, and the third stack structure 40, the mask layer 90 on the first stack structure 20 has a first pattern, the first pattern exposes a portion of the surface of the first stack structure 20, where the mask layer 90 can be a photoresist, and then the first trenches 24 are formed by etching the first stack structure 20 using the mask layer 90 as a mask, and after the first trenches 24 are formed, the mask layer 90 on the first stack structure 20 is removed.

[0085] After forming the first trench 24, the first sacrificial layer 22 is removed using the first trench 24 so that there is a gap between each active pillar provided in different layers. Specifically, as shown in Fig. 6, the first sacrificial layer 22 exposed in the first trench 24 is etched by a selective wet etching process to completely remove the first sacrificial layer 22 and to not remove or to slightly remove the second sacrificial layer 32 and the third sacrificial layer 42. After removing the first sacrificial layer 22, the mask layer 90 on the second stacked structure 30 and the third stacked structure 40 is removed.

[0086] In step S23, a part of the first active layer and a part of the second active layer that are distant from the channel structure are removed so that the lengths of the remaining first active layer and second active layer both change stepwise.

[0087] 6 and 7, the second sacrificial layer 32 and a part of the first active layer 31 away from the channel structure 23 are removed, and the length of the remaining first active layer 31 changes stepwise to form a step, thereby ensuring that the surface of the first active layer 31 of each layer is partially exposed, and other structures can be easily formed thereon. The third sacrificial layer 42 and a part of the second active layer 41 away from the channel structure 23 are removed, and the length of the remaining second active layer 41 changes stepwise to form a step, thereby ensuring that the surface of the second active layer 41 of each layer is partially exposed, and other structures can be easily formed thereon.

[0088] In step S24, a first conductive structure is formed on the first active layer and its corresponding channel structure, and a second conductive structure is formed on the second active layer and its corresponding channel structure.

[0089] 7 and 8, after the first and second conductive layers are formed, the lengths of the plurality of first conductive structures 50 and the plurality of second conductive structures 60 both change in a step-like manner. Specifically, the length of the first conductive structure 50 closer to the substrate 10 is longer than the length of the first conductive structure 50 farther from the substrate 10, so that the lengths of the plurality of first conductive structures 50 change in a step-like manner, and the length of the second conductive structure 60 closer to the substrate 10 is longer than the length of the second conductive structure 60 farther from the substrate 10, so that the lengths of the plurality of second conductive structures 60 change in a step-like manner.

[0090] In some possible embodiments, before forming a first conductive structure 50 in the first active layer 31 and its corresponding channel structure 23 and forming a second conductive structure 60 in the second active layer 41 and its corresponding channel structure 23 (step S24), an insulating material is deposited on the first active layer 31, the second active layer 41 and the channel structure 23, where the insulating material located on the first active layer 31 forms a first insulating layer, the insulating layer material located on the channel structure 23 forms a dielectric layer, and the insulating material located on the second active layer 41 forms a second insulating layer, and the first insulating layer, the dielectric layer and the second insulating layer are all spaced apart.

[0091] That is, before forming the first conductive structure 50 and the second conductive structure 60, a dielectric layer is first formed on the surface of the channel structure 23 to ensure insulation between the channel structure 23 and the first conductive structure 50 and the second conductive structure 60. At the same time, a first insulating layer is formed on the surface of the first active layer 31, and a second insulating layer is formed on the surface of the second active layer 41, and the dielectric layer, the first insulating layer, and the second insulating layer are formed together to ensure the flatness of each of the first conductive structure 50 and the second conductive structure 60.

[0092] Here, the surface of the channel structure 23 refers to the outer peripheral surface of the channel structure 23, and the dielectric layer surrounds the channel structure 23. The surface of the first active layer 31 may refer to the outer peripheral surface of the first active layer 31, or may refer to two surfaces of the first active layer 31 that face each other along the second direction and the surface facing the channel structure 23, i.e., the first insulating layer covers at least two surfaces of the first active layer 31 that face each other along the second direction and the surface facing the channel structure 23. The surface of the second active layer 41 may refer to the outer peripheral surface of the second active layer 41, or may refer to two surfaces of the second active layer 41 that face each other along the second direction and the surface facing the channel structure 23, i.e., the second insulating layer covers at least two surfaces of the second active layer 41 that face each other along the second direction and the surface facing the channel structure 23.

[0093] After forming the first insulating layer, the dielectric layer and the second insulating layer, a conductive material is deposited on the first insulating layer, the dielectric layer and the second insulating layer, where the conductive material located on the first insulating layer and the partial dielectric layer forms a first conductive structure 50, and the conductive material located on the second insulating layer and the other partial dielectric layer forms a second conductive structure 60.

[0094] Specifically, the first conductive structure 50 and the second conductive structure 60 are used as word lines, and each first conductive structure 50 covers the corresponding first insulating layer and the dielectric layer provided in the same layer as the first insulating layer, and is filled between the dielectric layers and between the dielectric layer and the first insulating layer. Each second conductive structure 60 covers the corresponding second insulating layer and the dielectric layer provided in the same layer as the second insulating layer, and is filled between the dielectric layers and between the dielectric layer and the second insulating layer. The first conductive structure 50 and the second conductive structure 60 covering the dielectric layer form a gate, and the gate is a part of the word line, and the first conductive structure 50 covering the first insulating layer and the second conductive structure 60 covering the second insulating layer are both used as the lead-out ends of the gate and connected to the peripheral circuit.

[0095] In some possible embodiments, after forming the conductive structure above the substrate 10, the method further includes a plurality of spaced apart contact plugs, the contact plugs including first contact plugs 70 and second contact plugs 80, the plurality of first contact plugs 70 being electrically connected in one-to-one correspondence with the plurality of first conductive structures 50, the plurality of second contact plugs 80 being electrically connected in one-to-one correspondence with the plurality of second conductive structures 60, and the lengths of the plurality of first contact plugs 70 and the plurality of second contact plugs 80 both vary in a step-like manner.

[0096] A number of contact plugs are used to electrically connect the first conductive structure 50 and the second conductive structure 60 to peripheral circuits, and the contact plugs are spaced apart to ensure isolation between the contact plugs, thereby avoiding mutual interference between the first conductive structures 50 or the second conductive structures 60.

[0097] The number of first contact plugs 70 is set to match the number of first conductive structures 50, and the multiple first contact plugs 70 are electrically connected to the multiple first conductive structures 50 in one-to-one correspondence, thereby allowing all of the first conductive structures 50 to be electrically connected to the peripheral circuitry and the transistors corresponding to the first conductive structures 50 to be controlled by the peripheral circuitry. The number of second contact plugs 80 is set to match the number of second conductive structures 60, and the multiple second contact plugs 80 are electrically connected to the multiple second conductive structures 60 in one-to-one correspondence, thereby allowing all of the second conductive structures 60 to be electrically connected to the peripheral circuitry and the transistors corresponding to the second conductive structures 60 to be controlled by the peripheral circuitry.

[0098] The first contact plugs 70 may be arranged along a first direction, and the second contact plugs 80 may be arranged along the first direction. By providing in this manner, the space occupied by the first contact plugs 70 and the second contact plugs 80 is smaller, which is favorable for increasing the number of transistors, thereby increasing the memory density of the semiconductor structure. Preferably, the first contact plugs 70 and the second contact plugs 80 are located in the same row along the first direction, which further reduces the space occupied by the first contact plugs 70 and the second contact plugs 80.

[0099] The lengths of the first contact plugs 70 change stepwise, and the lengths of the second contact plugs 80 change stepwise, where the length direction is the second direction. By providing them in this manner, the lengths of the first contact plugs 70 and the second contact plugs 80 are approximately equal, and the paths between the peripheral circuit and the first conductive structure 50 and between the peripheral circuit and the second conductive structure 60 are approximately equal, thereby reducing the difference in the operating state of each transistor in the device region.

[0100] The first contact plug 70 and the second contact plug 80 each include a first conductive portion and a second conductive portion provided on the first conductive portion, and the size of the first conductive portion is smaller than the size of the second conductive portion. Here, the first conductive portion is a portion close to the substrate 10, and the second conductive portion is a portion far from the substrate 10, that is, the second conductive portion is located on one side of the first conductive portion far from the substrate 10. The size of the first conductive portion may refer to the diameter or cross-sectional area of ​​the first conductive portion, and the size of the second conductive portion may refer to the diameter or cross-sectional area of ​​the second conductive portion. As shown in FIG. 1, the orthogonal projection of the second conductive portion on the substrate 10 covers the orthogonal projection of the first conductive portion on the substrate 10.

[0101] Each of the first conductive portion and the second conductive portion may include a core layer and an outer layer covering the side and bottom surfaces of the core layer. Here, the core layer may be an insulating layer, and the material may be silicon nitride or silicon oxide. The outer layer may be a metal layer, and the material may be tungsten or titanium nitride. By providing them in this manner, the thickness of the metal layer can be reduced and costs can be reduced, on the premise that the electrical characteristics of the first conductive portion and the second conductive portion are ensured.

[0102] As described above, in the method for manufacturing a semiconductor structure according to an embodiment of the present disclosure, a conductive structure including a plurality of first conductive structures 50 and second conductive structures 60 spaced apart from one another and extending along a first direction is formed above a substrate 10, so that the lengths of the plurality of first conductive structures 50 and the plurality of second conductive structures 60 both change in a step-like manner, and the first conductive structures 50 and the second conductive structures 60 form word lines. Since the word lines are easy to manufacture and lead out, other structures can be easily formed on the word lines, and electrical connection between the word lines and peripheral circuits can be realized.

[0103] Each example or embodiment of the present specification will be described step by step, and each example will be described with emphasis on the differences from other examples, and the same and similar parts between each example may be mutually referred to. Descriptions of terms such as "one embodiment", "several embodiments", "exemplary embodiment", "one example", "specific example", or "several examples" mean that the specific features, structures, materials or features described in combination with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the exemplary expressions of the above terms do not necessarily mean the same embodiment or example. Furthermore, the specific features, structures, materials or features described can be combined in any one or more embodiments or examples in an appropriate manner.

[0104] Finally, the above-mentioned embodiments are intended to illustrate the technical solutions of the present disclosure, but are not intended to limit them. The present disclosure has been described in detail with reference to the above-mentioned embodiments. However, those skilled in the art may modify the technical solutions described in the above-mentioned embodiments, or equivalently replace some or all of the technical features therein, but it should be understood that these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the technical solutions of the embodiments of the present disclosure.

Claims

1. 1. A semiconductor structure comprising: a substrate and a conductive structure overlying the substrate; the conductive structure includes a plurality of first conductive structures and a plurality of second conductive structures that are spaced apart from each other and extend along a first direction, and lengths of the first conductive structures and lengths of the second conductive structures each change stepwise; the substrate includes a device region, and a first connection region and a second connection region provided on both sides of the device region, the first conductive structure is located above the device region and extends to the first connection region, the second conductive structure is located above the device region and extends to the second connection region, the length of the first conductive structure located above the first connection region changes in a step-like manner, and the length of the second conductive structure located above the second connection region changes in a step-like manner; Each of the first conductive structures and each of the second conductive structures located above the device region surrounds a plurality of spaced apart channel structures, and a dielectric layer is provided between the first conductive structures and the channel structures and between the second conductive structures and the channel structures; Each of the first conductive structures located above the first connection region surrounds a first active layer, and a first insulating layer is provided between the first conductive structures and the first active layer; A semiconductor structure, wherein each of the second conductive structures located above the second connection region surrounds a second active layer, and a second insulating layer is provided between the second conductive structures and the second active layer.

2. a length of the first conductive structure closer to the substrate is greater than a length of the first conductive structure farther from the substrate such that the lengths of the first conductive structures change stepwise; a length of the second conductive structure closer to the substrate is greater than a length of the second conductive structure farther from the substrate such that the lengths of the second conductive structures change stepwise; The semiconductor structure of claim 1 .

3. the first conductive structures and the second conductive structures are arranged alternately and spaced apart in a second direction; The semiconductor structure of claim 1 .

4. The semiconductor structure further includes a plurality of spaced apart contact plugs, the contact plugs including a first contact plug and a second contact plug; the first contact plugs are electrically connected to the first conductive structures in one-to-one correspondence, and the second contact plugs are electrically connected to the second conductive structures in one-to-one correspondence; The semiconductor structure of claim 1 .

5. each of the first contact plug and the second contact plug includes a first conductive portion and a second conductive portion provided on the first conductive portion, and a size of the first conductive portion is smaller than a size of the second conductive portion; The semiconductor structure of claim 4.

6. The first active layer and the plurality of channel structures corresponding to the same first conductive structure are provided in the same layer, and the second active layer and the plurality of channel structures corresponding to the same second conductive structure are provided in the same layer. The semiconductor structure of claim 1 .

7. A memory, a substrate including a device region; a device layer overlying the device region, the device layer including a plurality of spaced apart channel structures; a word line structure including a plurality of spaced apart word lines extending along a first direction, the length of the plurality of word lines varying in a stepped manner; a bit line structure including a plurality of spaced apart bit lines extending along a second direction; the word lines extend through the device layer and surround the channel structure, the bit lines extend through the device layer and are electrically connected to the channel structure, the channel structure also being electrically connected to a storage node; the substrate further includes a first connection region and a second connection region, the device region is located between the first connection region and the second connection region, the lengths of the word lines located above the first connection region change stepwise, and the lengths of the word lines located above the second connection region change stepwise; A memory, wherein the substrate located in the device region is spaced apart from the substrate located in the first connection region and the substrate located in the second connection region.

8. Each of the word lines surrounds a plurality of channel structures spaced apart in the first direction, and each of the bit lines is connected to one end of a plurality of channel structures spaced apart in the second direction, and the other end of each of the channel structures is connected to the storage node. The memory of claim 7.

9. 1. A method for manufacturing a semiconductor structure, comprising the steps of: Providing a substrate; forming a conductive structure above the substrate, the conductive structure including a plurality of first conductive structures and a plurality of second conductive structures extending along a first direction and spaced apart from each other, the lengths of the first conductive structures and the lengths of the second conductive structures both varying in a step-like manner; the substrate includes a device region, and a first connection region and a second connection region provided on both sides of the device region, the first conductive structure is located above the device region and extends to the first connection region, the second conductive structure is located above the device region and extends to the second connection region, the length of the first conductive structure located above the first connection region changes in a step-like manner, and the length of the second conductive structure located above the second connection region changes in a step-like manner; Forming a conductive structure above the substrate includes: forming a first stack structure, a second stack structure and a third stack structure in the device region, the first connection region and the second connection region of the substrate, respectively, the first stack structure including a first sacrificial layer and a device layer that are alternately stacked, the second stack structure including a second sacrificial layer and a first active layer that are alternately stacked, the third stack structure including a third sacrificial layer and a second active layer that are alternately stacked, a plurality of the first active layers in one-to-one correspondence with the device layers of a first portion, and a plurality of the second active layers in one-to-one correspondence with the device layers of a second portion; removing the first sacrificial layer and portions of the device layers to form a plurality of spaced apart channel structures in each of the device layers; removing a portion of the first active layer and a portion of the second active layer away from the channel structure such that the lengths of the remaining first active layer and the second active layer both change stepwise; forming a first conductive structure on the first active layer and the channel structure corresponding to the first active layer, and forming a second conductive structure on the second active layer and the channel structure corresponding to the second active layer.

10. the first active layers correspond to the odd-numbered device layers and are provided in the same layers, and the second active layers correspond to the even-numbered device layers and are provided in the same layers. The method of claim 9.

11. Prior to forming a first conductive structure on the first active layer and the channel structure corresponding to the first active layer, and forming a second conductive structure on the second active layer and the channel structure corresponding to the second active layer, the method further comprises: depositing an insulating material over the first active layer, the second active layer and the channel structure, the insulating material over the first active layer forming a first insulating layer, the insulating material over the channel structure forming a dielectric layer, and the insulating material over the second active layer forming a second insulating layer, wherein the first insulating layer, the dielectric layer and the second insulating layer are all spaced apart. The method of claim 9.

Images