Semiconductor device and method for manufacturing the same

Abstract

In the present invention, a metal oxide film 104 is formed on an STO substrate 102. The metal oxide film 104 has a thickness tM that is lower than a specified threshold tTH. A p-type region 106 is formed at the interface of the STO substrate 102 and the metal oxide film 104.

Description

[Technical field]

[0001] The present invention relates to semiconductor devices. [Background technology]

[0002] Semiconductor devices such as transistors, diodes, light-emitting diodes, photosensors, and solar cells are constructed using a junction between n-type and p-type semiconductors. In the currently mainstream silicon (Si) process, impurities are doped into a Si substrate (wafer) to form p-type semiconductors (p-type regions) and n-type semiconductors (n-type regions). The mainstream method of doping impurities is ion implantation, in which a beam of impurity atoms is implanted into the semiconductor substrate.

[0003] In recent years, with the trend toward faster and smaller semiconductor devices, there has been a demand for technology to form shallow, highly-doped n-type and p-type regions.

[0004] Current ion implantation methods destroy the crystals of the silicon substrate by bombarding the substrate with high-energy ions. When the destroyed crystals are repaired by high-temperature heat treatment, the impurities diffuse in the depth direction, which limits the formation of low-resistance n-type and p-type regions. In addition, high-temperature heat treatment is an obstacle to reducing the cost of semiconductor devices.

[0005] In recent years, oxide electronics has been attracting attention in the fields of high-temperature superconducting materials, ferromagnetic oxides, ferroelectrics, high-mobility materials, etc., and among them, STO (strontium titanate: SrTiO3) is used as a standard substrate, and various research results have been reported (see Non-Patent Documents 1 to 4). STO is useful because it has a very high mobility compared to Si and Ge.

[0006] Non-Patent Document 5 reports that a very thin n-type region (i.e., two-dimensional electron gas 2DEG) is formed at the interface between STO and metal by vacuum-evaporating metal on an STO substrate at room temperature. This technology has the advantages of being able to replace expensive ion implantation equipment with inexpensive vacuum evaporation equipment and of not requiring high-temperature processing. [Prior art documents] [Patent documents]

[0007] [Non-Patent Document 1] Mannhart, J. & Schlom, DG, Science 327, pp1607-1611 (2010), “Oxide Interfaces-An Opportunity for Electronics” [Non-Patent Document 2] D. Lu et al, Nature Mater. 15, 1255 (2016) [Non-Patent Document 3] D. Ji et al., Nature 570, pp.87-90 (2019) [Non-Patent Document 4] A. Ohtomo & H. Hwang, Nature 427, pp423-426 (2004) [Non-Patent Document 5] P. Lomker et al., Phys. Rev. Mater. 1, 062001(R) (2017). Summary of the Invention [Problem to be solved by the invention]

[0008] However, there have been no reports to date of forming a p-type region on an STO substrate, and a semiconductor device having a pn junction has not been realized on an STO substrate.

[0009] The present invention has been made in view of the above-mentioned problems, and an exemplary purpose of an embodiment of the present invention is to provide an STO semiconductor device including a p-type region. [Means for solving the problem]

[0010] An embodiment of the present invention relates to an STO (SrTiO3) semiconductor device, comprising an STO substrate, a first metal oxide film formed on the STO substrate and having a thickness less than a predetermined threshold, and a p-type region formed at an interface between the STO substrate and the first metal oxide film.

[0011] Another aspect of the present invention relates to a method for manufacturing an STO (SrTiO3) semiconductor device, comprising the steps of depositing a first metal film having a thickness less than a predetermined threshold on a portion of an STO substrate where a p-type region is to be formed, and oxidizing the first metal film to form a p-type region at an interface between the first metal film and the STO substrate.

[0012] Any combination of the above components and any conversion of the present invention into an apparatus, method, system, etc. are also valid aspects of the present invention. Effect of the Invention

[0013] According to the present invention, p-type regions can be formed on STO semiconductor devices. [Brief description of the drawings]

[0014] [Figure 1] FIG. 1 is a cross-sectional view showing the structure of an STO semiconductor device. [Diagram 2] 2(a) and (b) are diagrams illustrating a method for manufacturing an STO semiconductor device. [Diagram 3] 3(a) and (b) are band diagrams of the interface between an STO semiconductor substrate and a metal oxide film (metal film). [Figure 4]FIG. 4(a) is an in-situ reflection high-energy electron diffraction (RHEED) image of the sample during the manufacturing process, and FIG. 4(b) is a scanning transmission electron microscope (STEM) image of sample A10. [Diagram 5] 5(a) and (b) are diagrams showing the measurement results of samples A20, A40, and A60 by X-ray photoelectron spectroscopy (XPS). [Figure 6] 6(a) to (e) are diagrams showing the measurement results of the Hall effect of samples A10 to A40. [Figure 7] FIG. 13 is a diagram showing the measurement results of the sheet resistance of samples A10 to A40. [Figure 8] FIG. 8(a) is a graph showing the measurement results of the mobility μ of samples A10 to A40, and FIG. 8(b) is a graph showing the measurement results of the film thickness (tFe) dependence of the mobility (left axis) and the sheet carrier density (right axis). [Figure 9] FIG. 9(a) shows the relationship between the inverse of the external magnetic field B-1 and the change in sheet resistance Rxx d2Rxx / dB2 in sample A10, and FIG. 9(b) shows the spectrum when a perpendicular magnetic field B / /

[0001] and an in-plane magnetic field B / /

[0100] are applied. [Figure 10] FIG. 1 is a plot of the work function φ of a representative element M and the enthalpy change ΔHf of oxide formation of the metal element M. [Figure 11] FIG. 2 is an equivalent circuit diagram of the STO semiconductor device of FIG. 1. [Figure 12] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Figure 13] 13A to 13C are diagrams illustrating a method for manufacturing the STO semiconductor device of FIG. 12. [Figure 14] FIG. 11 is a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 15] FIG. 11 is a cross-sectional view of an STO semiconductor device according to a third embodiment. [Figure 16] FIG. 11 is a cross-sectional view of a semiconductor device according to a fourth embodiment. [Figure 17] FIG. 11 is a cross-sectional view of a FET in accordance with a fifth embodiment. [Figure 18]FIG. 18 is a diagram showing an IDS-VGS curve (measurement result) of the FET in FIG. 17. [Figure 19] FIG. 18 is a diagram showing an IDS-VDS curve (measurement result) of the FET of FIG. 17. [Figure 20] FIG. 18 is a diagram showing an IDS-VDS curve (measurement result) of the FET of FIG. 17. [Figure 21] 21(a) to (c) are diagrams showing the IDS-VDS characteristics (measurement results) of the FET of FIG. [Figure 22] FIG. 13 is a cross-sectional view of a FET in accordance with Example 6. [Figure 23] 23(a) to 23(c) are diagrams showing the IDS-VDS characteristics (measurement results) of the FET of FIG. [Figure 24] 24(a) to (d) are diagrams showing the measurement results of the Hall effect of the FET of FIG. [Diagram 25] FIG. 25(a) is a diagram showing the relationship between the backgate voltage VBG and the Hall resistance Ryx, and FIG. 25(b) is a diagram showing the relationship between the backgate voltage VBG and the carrier density. [Figure 26] FIG. 18 is a diagram showing the backgate voltage dependence of the hole mobility μ Hall of the FET of FIG. 17. [Figure 27] FIG. 2 is a band diagram of a FET according to an embodiment. [Figure 28] FIG. 18 is a diagram showing the measurement results of the Hall effect of the FET of FIG. 17. [Figure 29] 29(a) to (c) are diagrams showing the dependence of the backgate voltage VBG of the FET in FIG. [Diagram 30] 30(a) is a graph showing the temperature dependence of the FET in FIG. 17, and FIG. 30(b) is a graph showing the temperature dependence of the FET in FIG. [Diagram 31] 31(a) to (d) are cross-sectional views of FETs according to Examples 7 to 10. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] (Embodiment) The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing are given the same reference numerals, and duplicated descriptions are omitted as appropriate. In addition, the embodiments are illustrative rather than limiting the invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

[0016] In addition, the dimensions of the components in each drawing are shown enlarged or reduced as appropriate to make them easier to understand.

[0017] (Formation of p-type region on STO semiconductor substrate) As mentioned above, although there are reports of forming an n-type region on an STO substrate, there are no reports of forming a p-type region. Therefore, we first explain the basic structure of an STO semiconductor device with a p-type region.

[0018] 1 is a cross-sectional view showing the structure of an STO semiconductor device 100. The STO semiconductor device 100 includes an STO substrate 102, a metal oxide film 104, a p-type region 106, and a cap layer 108. The metal oxide film 104 is formed on the STO substrate 102. The metal oxide film 104 is a dielectric constant layer having a predetermined threshold t TH Smaller thickness t M The p-type region 106 is a two-dimensional hole gas (2DHG) that is formed at the interface between the metal oxide film 104 and the STO substrate 102. The threshold t TH More on this later.

[0019] A capping layer 108 is formed on the metal oxide film 104 to stabilize the chemical properties of the device. For example, the capping layer 108 can be a metal oxide film, similar to the metal oxide film 104. It should be noted that the capping layer 108 is not a necessary component to achieve semiconducting properties.

[0020] 2(a) and (b) are diagrams showing a manufacturing method of the STO semiconductor device 100. As shown in Fig. 2(a), a metal element (Fe in this case) is evaporated on an STO substrate 102 under vacuum to form a metal film 110. Further, another metal element (Al in this case) is evaporated on the metal film 110 to form a metal film 112.

[0021] The metal element (Fe) contained in the metal film 110 has a high oxygen affinity and is oxidized by depriving the STO substrate 102 of oxygen. As a result, the metal film 110 in FIG. 2(a) is oxidized to the metal oxide film 104 (FeO x The metal element (Al) contained in the metal film 112 is also oxidized to form a cap layer 108 of a metal oxide film.

[0022] The above is the basic structure and manufacturing method of the STO semiconductor device 100 having a p-type region. Next, the reason why the p-type region is formed will be explained.

[0023] 3(a) and (b) are band diagrams of the interface between the STO semiconductor device 100 and the metal oxide film 104 (metal film 110).

[0024] The oxidation process is shown in Figure 3(a). When the metal elements in the metal film 110 are oxidized and changed into the metal oxide film 104, they remove oxygen O from the STO substrate 102. As the amount of oxygen increases, the amount of oxygen vacancies in the STO substrate 102 increases. Since oxygen vacancies act as donors that supply electron carriers, increasing the amount of oxygen vacancies forms a two-dimensional electron gas (2DEG), i.e., an n-type region, at the interface between the STO substrate 102 and the metal oxide film 104. The n-type region on the STO substrate reported in non-patent literature is formed by this oxidation process.

[0025] The present inventors have noticed that, with regard to charge transfer at the interface between the STO substrate 102 and the metal film 110, a process (hereinafter referred to as a bonding process) other than the oxidation process occurs.

[0026] As shown in Fig. 3(b), when STO ((001) surface) is bonded to metal M, holes h + is supplied. Also, due to the difference in work function φ between the metal M and STO, the conduction band CB and the valence band VB are bent. The bonding process in Fig. 3(b) occurs prior to the oxidation process in Fig. 3(a). If we ignore the oxidation process of the metal M in Fig. 3(a), a two-dimensional hole gas (2DHG), i.e., a p-type region, should be formed in the STO by the bonding process.

[0027] The present inventors have determined that the bonding process shown in FIG. 3(b) is performed by M On the other hand, the oxidation process in Fig. 3(a) does not depend on the thickness t M Therefore, the thickness of the film t M In the region where t is large, the oxidation process becomes dominant, forming an n-type region, and the thickness t M It has been realized that if t is made small, the junction process becomes dominant and a p-type region is formed. In other words, which of the two processes becomes dominant depends on the thickness t of the metal film 110. M The threshold value t TH It can be said that the STO semiconductor device 100 shown in FIG. M Let t be the threshold value. TH By making it smaller, a p-type region can be formed.

[0028] Film thickness t M The experimental results on the dependence of t Fe A metal film 110 of Fe was evaporated, and a metal film 112 of Al was evaporated thereon to a thickness of 1 nm. The evaporation temperature was T S = 50℃, background pressure is approximately 10 -8 In the experiment, the thickness of the metal film 110 is t FeSix samples A10 to A60 with thicknesses of 0.1, 0.15, 0.2, 0.3, 0.4 and 0.6 nm were fabricated and their characteristics were evaluated. As described above, the metal film 110 and the metal film 112 are oxidized to become the metal oxide film 104 and the cap layer .

[0029] Figure 4(a) shows the in-situ reflection high-energy electron diffraction (RHEED) image during the fabrication process, and Figure 4(b) shows the scanning transmission electron microscope (STEM) image of sample A10. The STO surface is atomically flat.

[0030] 5(a) and (b) are diagrams showing the measurement results of samples A20, A40, and A60 by X-ray photoelectron spectroscopy (XPS). FIG. 5(a) shows the state of Fe, and FIG. 5(b) shows the state of Al. Fe In the sample with a thickness of ≦0.4 nm, Fe and Al are oxidized and become amorphous. 3+ and Al 3+ It is as follows.

[0031] 6(a) to (e) are diagrams showing the measurement results of the Hall effect of samples A10 to A40. The horizontal axis represents the applied magnetic field, and the vertical axis represents the Hall resistance R xy In samples A10, A15, and A20, the Hall resistance R xy shows a straight line that rises to the right, which confirms that a p-type semiconductor has been formed. xy is downward sloping and shows nonlinearity, which indicates that p-type and n-type are mixed. In sample A40, the Hall resistance R xy 6(a) to 6(e), the thickness t Fe It can be seen that the carrier type in the STO substrate 102 can be selectively controlled to p-type or n-type depending on the TH As, t Fe <t TH By setting the p-type region as t Fe >t THBy setting the threshold value t TH It should be noted that depends on the type of element and the deposition conditions.

[0032] 7 is a diagram showing the results of measuring the sheet resistance of samples A10 to A40. Samples A10, A15, and A20, in which a p-type region is formed, and sample A40, in which an n-type region is formed, have roughly similar sheet resistances, while sample A30, in which a p-type region and an n-type region are mixed, has a larger sheet resistance.

[0033] FIG. 8(a) is a diagram showing the measurement results of the mobility μ of samples A10 to A40. Fe For sample A10 with a lattice constant of 0.1 nm, the average wavelength is 24,000 cm at a low temperature of 2 K. 2 It can be seen that a very large hole mobility μ of 1.0 μV / Vs has been achieved.

[0034] Figure 8(b) shows the relationship between mobility (left axis) and sheet carrier density (right axis) as a function of film thickness (t Fe ) dependency measurement results. Fe ≦0.2 nm, p-type, t Fe ≧0.4 nm, n-type characteristics are obtained, and therefore the above-mentioned threshold t TH can be said to lie between 0.2 nm and 0.4 nm.

[0035] FIG. 9(a) shows the reciprocal of the external magnetic field B -1 and sheet resistance R xx Change in d 2 R xx / dB 29(b) shows the spectrum when a perpendicular magnetic field B / /

[0001] and an in-plane magnetic field B / /

[0100] are applied. Shubnikov-de Haas oscillations were observed only when the magnetic field B / /

[0001] was applied in the

[0001] direction, i.e., perpendicular to the surface of the STO substrate, and these oscillations were not observed when the magnetic field B / /

[0100] was applied in the

[0100] direction, i.e., in the in-plane direction of the STO substrate. This measurement result supports the idea that holes are confined in a two-dimensional system of the STO substrate, i.e., that a 2DHG is formed.

[0036] Next, a description will be given of conditions for fabricating the STO semiconductor device 100 in Fig. 1. It should be noted that some of these conditions are not necessarily required depending on the manufacturing method and application of the STO semiconductor device 100.

[0037] (First condition) When fabricating an STO semiconductor device 100 having a p-type region by vacuum deposition, it is desirable to set the temperature of the vacuum deposition to 300° C. or less. This is to prevent oxygen from being released from the STO into the vacuum during deposition, which would cause oxygen vacancies. This condition can be easily met because vacuum deposition can be performed even at room temperature of 30° C.

[0038] (Second condition) The metal element M of the metal oxide film 104 can be selected in consideration of the second condition and the third condition described below.

[0039] As shown in Fig. 3(b), in order to bend the band at the junction between metal M and STO and supply holes to STO, the work function φ of metal M must be smaller than that of STO φ. STO (3.9 V). Furthermore, this band bending must be maintained even after the metal M is oxidized by the oxidation process, so the oxide MO x The work function of STO is also STO = 3.9V.

[0040] (Third condition) As shown in Fig. 2, after a metal film 110 containing a metal M is deposited on an STO substrate 102, the metal M must be oxidized to make it insulating. In order to change the metal M to an oxide MOx by the oxidation process shown in Fig. 3(a), the enthalpy change in oxide formation of the metal element M, ΔH f The absolute value of is required to be greater than the oxygen vacancy formation energy of STO (4.8 eV / oxygen vacancy). On the other hand, the enthalpy change of oxide formation of metal M, ΔH f If the absolute value of is too large, the metal M generates a large amount of oxygen vacancies in STO, generating many electron carriers and preventing the realization of p-type conduction. From this perspective, the metal element M is determined by its oxide formation enthalpy change ΔH f It is advisable to select an element with an optical density of -8 eV / O2 to -4.8 eV / O2.

[0041] Figure 10 shows the work function φ and the enthalpy change of oxide formation ΔH for a representative element M. f In consideration of the second and third conditions, it is advisable to use a metal element M included in the solid line (i). Specifically, in addition to Fe, W (tungsten), Mo (molybdenum), V (vanadium), Mn (manganese), Cr (chromium), Nb (niobium), etc. may be used.

[0042] (Fourth condition) Fig. 11 is an equivalent circuit diagram of the STO semiconductor device 100 in Fig. 1. When the STO semiconductor device 100 is regarded as a two-terminal device, the two-terminal device is expressed as a parallel connection circuit of a metal oxide film 104 and a p-type region 106. Here, the resistance value R M If R is too small, the p-type region 106 is bypassed and the characteristics of the semiconductor device are not observed. M is the resistance value R of the p-type region 106 S It is required to be sufficiently higher than

[0043] Since the sheet resistance of the p-type region 106 is on the order of 10 Ω / □, it is preferable that the sheet resistance of the metal oxide film 104 is more than 10 times the sheet resistance of the p-type region 106, and it is preferable to select a metal M having a sheet resistance of 100 Ω / □ or more.

[0044] Note that actual semiconductor devices are not two-terminal devices as shown in FIG. 11 but have more complicated configurations including pn junctions, and the fourth condition may be relaxed depending on the configuration of the semiconductor device.

[0045] The Fe used in the above sample satisfies all of the first to fourth conditions.

[0046] In practice, it is necessary to form both p and n regions on an STO substrate. Hereinafter, an embodiment of a semiconductor device having p and n regions will be described.

[0047] Example 1 12 is a cross-sectional view of a semiconductor device 200 in accordance with Example 1. The semiconductor device 200 includes an STO substrate 202, a first metal oxide film 204, a second metal oxide film 206, a cap layer 208, a p-type region 210, and an n-type region 212.

[0048] The first metal oxide film 204 is formed on the STO substrate 202 and has a predetermined threshold t TH Smaller thickness t M1 ( <t TH ) is formed at the interface between the STO substrate 202 and the first metal oxide film 204. TH is specific to the metal element constituting the first metal oxide film 204.

[0049] The second metal oxide film 206 is formed on the STO substrate 202 adjacent to the first metal oxide film 204. The second metal oxide film 206 is a junction between the first metal oxide film 204 and the threshold t TH Larger thickness t M2 (t M2 >t THTherefore, an n-type region 212 is formed at the interface between the STO substrate 202 and the second metal oxide film 206.

[0050] The cap layer 208 is configured to cover the first metal oxide film 204 and the second metal oxide film 206 .

[0051] In the first embodiment, the first metal oxide film 204 and the second metal oxide film 206 contain the same metal element, and by controlling the film thickness t, the p-type region 210 and the n-type region 212 can be selectively formed.

[0052] 13 is a diagram illustrating a method for manufacturing the STO semiconductor device 200 of FIG. 12. For example, a mask 252 having an opening in a region 250 including the first metal oxide film 204 and the second metal oxide film 206 on the STO substrate 202 is used to form a first metal oxide film having a thickness of t M1 Then, a metal film 220 is formed by depositing the metal element of Δt=t using a mask 256 in which only the region 254 including the second metal oxide film 206 is opened. M2 -t M1 The metal film 224 may be formed by vapor deposition of the metal element.

[0053] It is understood by those skilled in the art that the method for manufacturing the STO semiconductor device 200 is not limited to that shown in FIG. 13. For example, a first metal oxide film 204 is formed by depositing a first thickness t M1 A metal element having a thickness of t is deposited by using a mask in which only the area including the second metal oxide film 206 is opened. M2 The metal element may be vapor-deposited.

[0054] Example 2 14 is a cross-sectional view of a semiconductor device 300 in accordance with Example 2. The STO semiconductor device 300 includes an STO substrate 302, a first metal oxide film 304, a second metal oxide film 306, a cap layer 308, a p-type region 310, and an n-type region 312.

[0055] The first metal oxide film 304 and the second metal oxide film 306 contain the same metal element. The first metal oxide film 304 has a threshold value tTH Smaller thickness t M1 Thus, a p-type region 310 is formed at the interface between the first metal oxide film 304 and the STO substrate 302.

[0056] The second metal oxide film 306 has the same metal element as the first metal oxide film 304 and has the same thickness t M2 =t M1 However, second metal oxide film 306 contains more oxygen than first metal oxide film 304. The oxygen contained in second metal oxide film 306 is supplied from STO substrate 302, and more oxygen vacancies are generated in the region of STO substrate 302 that overlaps with second metal oxide film 306, and n-type region 312 is formed.

[0057] A method for manufacturing the STO semiconductor device 300 of FIG. 14 will now be described.

[0058] In the first manufacturing method, first, a metal film with a constant thickness is formed in the portions corresponding to first metal oxide film 304 and second metal oxide film 306. In this state, a p-type region is formed at the interface between this metal film and STO substrate 302. Next, only the region corresponding to n-type region 312 is selectively heated by laser irradiation or the like to selectively promote oxidation of the portion of the metal film corresponding to n-type region 312. As a result, the heated portion changes to an n-type region, while the unheated portion maintains the p-type.

[0059] In the second manufacturing method, first, a thin film having a thickness of t M2 The metal film is formed so that the thickness of the metal oxide film becomes t. Then, the metal film is heated in this state to promote oxidation, thereby forming n-type region 312. Next, a metal oxide film having a thickness of t M1 As a result, a p-type region is formed at the interface between the metal film and the STO substrate 302.

[0060] Example 3 15 is a cross-sectional view of an STO semiconductor device 400 according to Example 3. In Examples 1 and 2, the first metal oxide film and the second metal oxide film contain the same metal element, but this is not limited thereto.

[0061] The STO semiconductor device 400 includes an STO substrate 402 , a first metal oxide layer 404 , a second metal oxide layer 406 , a cap layer 408 , a p-type region 410 , and an n-type region 412 .

[0062] The first metal oxide film 404 includes a first metal element, and the second metal oxide film 406 includes a second metal element different from the first metal element. The first metal oxide film 404 has a threshold t TH1 Smaller thickness t M1 Thus, a p-type region 410 is formed at the interface between the first metal oxide film 404 and the STO substrate 402.

[0063] The second metal oxide film 406 has a threshold value t TH2 Larger thickness t M2 Therefore, an n-type region 412 is formed at the interface between the second metal oxide film 406 and the STO substrate 402. M1 and M2 The magnitude relationship is determined according to the type of metal.

[0064] Example 4 In the first to third embodiments, the first metal oxide film and the second metal film are formed on the same surface of the STO substrate, and therefore the p-type region and the n-type region are bonded in the horizontal direction, but this is not limited thereto. Fig. 16 is a cross-sectional view of a semiconductor device 500 according to a fourth embodiment. In this semiconductor device 500, the first metal oxide film 504 and the second metal oxide film 506 are formed on different surfaces of an STO substrate 502. A cap layer 508 is formed on the first metal oxide film 504, and a cap layer 509 is formed on the second metal oxide film 506. Then, the p-type region 510 and the n-type region 512 are bonded in the vertical direction.

[0065] The above are examples of STO semiconductor devices. Those skilled in the art will understand that various devices such as transistors, diodes, light-emitting diodes, photosensors, and solar cells can be configured by combining p-type and n-type regions, and the application of the present invention is not limited to a specific purpose.

[0066] Finally, the advantages of STO semiconductor devices can be summarized as follows: First, they can be manufactured by vacuum deposition, which makes it easy to reduce cost and increase the area.

[0067] Secondly, since no high-temperature process is required, it is also possible to fabricate flexible devices and flexible circuits using plastic substrates, etc.

[0068] Thirdly, it is possible to form multiple transistors and diodes on the same STO substrate and further form the wiring that connects them by vacuum deposition, making it possible to perform all processes by vacuum deposition alone.

[0069] Fourth, it is possible to form very thin p-type and n-type regions with good electrical conductivity, which is anticipated to enable application to smaller devices in the future.

[0070] (Field-Effect Transistor) To demonstrate the above-mentioned semiconductor device, a field effect transistor (FET) was fabricated and its characteristics were evaluated.

[0071] Example 5 17 is a cross-sectional view of a FET 600 according to Example 5. The basic structure of this FET 600 is as described above, and includes an STO substrate 602, a metal oxide film 604, a p-type region 606, and a cap layer 608. Since the objective is to demonstrate the principle, a readily available STO substrate 602 having a thickness of 500 μm was used.

[0072] Thickness t of the metal oxide film 604 M is 0.75 Å, and the above-mentioned threshold t THA p-type region 606 (two-dimensional hole gas 2DHG) is formed below the thinner metal oxide film 604. A cap layer 608 is formed above the metal oxide film 604 and is made of aluminum oxide (AlO x The length of the metal oxide film 604, that is, the channel length (gate length) L, is 0.6 mm, and the width of the metal oxide film 604, that is, the channel width (gate width) W, is 0.1 mm.

[0073] The FET 600 has a back-gate structure and further includes a drain electrode 620, a source electrode 622, and a back-gate electrode 624. The drain electrode 620 and the source electrode 622 are formed in a region of the STO substrate 602 adjacent to the metal oxide film 604. The drain electrode 620 and the source electrode 622 are made of aluminum, for example, and can be formed by metal deposition. Directly below the drain electrode 620 and the source electrode 622, n-type regions (two-dimensional electron gas 2DEG) 626, 628 are formed.

[0074] The back gate electrode 624 is also made of aluminum and can be formed by metal deposition on the back side of the STO substrate 602. Note that in this device, the drain and source are symmetrical, so the names drain and source are merely for convenience.

[0075] FIG. 18 shows the I DS -V GS This is a graph showing the curve (measurement result). The measurement was performed at a cryogenic temperature of 3.5 K and a source voltage of V S With reference potential 0V, V DS (=V D -V S ) = 0.5V. Under these conditions, the threshold voltage V TH The voltage at the output of the transistor is -7V, and the transistor is normally on. This curve shows a hysteresis characteristic, with the subthreshold swing values ​​(S values) being 20.0mV / dec and 38.1mV / dec, and the on-off ratio I ON / I OFF is 10 8 It is clear that the obtained characteristics are comparable to those of the latest MOSFETs at room temperature.

[0076] FIG. 19 shows the I DS -V DS A graph showing the curve (measurement results) of the gate voltage V GS (=V BG -V S The IV characteristics are plotted for gate voltages of 60, 40, 20, 15, 10, 5, 1, -1, -5, and -10 V. The vertical axis on the left is a linear scale, and the vertical axis on the right is a logarithmic scale. Basically, the gate voltage V GS The larger the drain current I DS There is a tendency for this to increase.

[0077] FIG. 20 shows the I DS -V DS A graph showing the curve (measurement results). <V GS Only the range of gate-source voltage V < -4.5V is plotted. GS 17, a PN junction is formed between n-type region 626 directly under drain electrode 620 and p-type region 606, which is the channel region, forming a so-called Esaki diode. Similarly, a PN junction is formed between n-type region 628 directly under source electrode 622 and p-type region 606, which is the channel region, forming an Esaki diode. The negative resistance seen in FIG. 20 can be explained by the fact that FET 600 behaves as a tunnel FET device.

[0078] 21(a) to (c) show the I DS -V DS FIG. 21(c) shows the characteristics (measurement results). GS The characteristics are plotted for =-5.2V, and a clear tunneling effect at reverse bias is observed.

[0079] Example 6 22 is a cross-sectional view of a FET 700 in accordance with Example 6. This FET 700 includes an STO substrate 702, a metal oxide film 704, an n-type region 706, and a cap layer 708. The STO substrate 702 used is a substrate having a thickness of 500 μm, which is easily available.

[0080] Thickness t of the metal oxide film 704 M is 4 Å, and the above threshold t TH The metal oxide film 704 is thicker, and therefore an n-type region 706 (two-dimensional electron gas 2DEG) is formed below the metal oxide film 704. The cap layer 708 formed above the metal oxide film 704 is a 1 nm thick aluminum oxide (AlO x ).

[0081] The FET 700 has a back-gate structure and further includes a drain electrode 720, a source electrode 722, and a back-gate electrode 724. The drain electrode 720 and the source electrode 722 are formed in a region of the STO substrate 702 adjacent to the metal oxide film 704. The drain electrode 720 and the source electrode 722 are made of aluminum, for example, and can be formed by metal deposition. N-type regions (two-dimensional electron gas 2DEG) 726, 728 are formed directly below the drain electrode 720 and the source electrode 722. Therefore, the PN junction described in the fifth embodiment does not exist.

[0082] The back gate electrode 724 is also made of aluminum and can be formed by metal deposition on the back side of the STO substrate 702. Note that in this device, the drain and source are symmetrical, so the names drain and source are merely for convenience.

[0083] 23(a) to (c) show the I DS -V DS 23A and 23B are diagrams showing characteristics (measurement results). As shown in Fig. 23B and Fig. 23C, no tunnel effect is observed. This is consistent with the fact that there is no PN junction between the drain and channel regions and between the source and channel regions in the FET 700 of Fig. 22.

[0084] Next, control of the carrier type of the FET 700 according to the sixth embodiment will be described.

[0085] 24(a) to (d) are diagrams showing the measurement results of the Hall effect of the FET 700 of FIG. 22. The measurements were performed using the gate-source voltage V GS , i.e. the back gate voltage V BG The voltage was changed to 0, 2, 3, 4, 6, 10, 15, 20, 40, 45, 50, and 60V.

[0086] Figure 24(b) shows the back gate voltage V BG 24(c) is a plot of the characteristics when the back-gate voltage V BG 15, 20, 40, and 45V, and Fig. 24(d) shows the plot when the back gate voltage V BG This is a plot at 50 and 60V.

[0087] Figure 25(a) shows the back gate voltage V BG and Hall resistance R yx FIG. 25(b) shows the relationship between the back gate voltage V BG FIG. 13 is a graph showing the relationship between the carrier density and the capacitance.

[0088] As described above, the thickness t of the metal oxide film 704 M is the threshold t TH If the metal oxide film 704 is thicker, it is known that an n-type region is formed directly under the metal oxide film 704, and as shown in FIG. 25(b), BG In the range of 0 to 10 V, the carrier type is n-type. However, when the back gate voltage V BG When the back gate voltage V BG exceeds 50V, the carrier type changes from n-type to p-type.

[0089] In other words, in the conventional technology, when the metal oxide film 704 is thick, only the n-type region can be formed. BGIt has been found that by applying a voltage of 0.1 V to the metal oxide film 704, a p-type region can be formed directly below the metal oxide film 704.

[0090] Returning to Example 5, the measurement results of the Hall effect of the FET 600 in FIG. 17 will now be described. FIG. 26 shows the mobility μ Hall 1 is a graph showing the back gate voltage dependence of the back gate voltage V BG The higher the mobility of holes, which are carriers in the P-type region, μ Hall When the voltage is increased from 0 V to 200 V, the mobility μ Hall This is five times faster, which is expected to enable faster transistor operation.

[0091] FIG. 27 is a band diagram of the FET 600 of FIG. BG When a positive back-gate voltage V is applied, the potential that binds the holes distributed two-dimensionally at a shallow depth becomes steeper, the hole concentration decreases, and the electron correlation becomes weaker. BG Mobility μ depending on Hall This is also thought to be one of the reasons why the number of quantum levels is reduced, which reduces interband scattering and increases the mobility μ Hall This is thought to be one of the reasons why

[0092] FIG. 28 shows the results of measuring the Hall effect of the FET 600 of FIG. 17. The measurement was performed at the back gate voltage V BG The voltage was changed from 0V to 200V.

[0093] 29(a) to (c) show the back gate voltage V BG FIG. 29(a) is a graph showing the dependence of Hall resistance R yx 29(b) shows the carrier density. Back gate voltage V BG Increasing the mobility μ Hall increases, while the carrier density decreases.

[0094] Figure 29(c) shows the sheet resistance, which decreases with the application of gate voltage, which is different from the behavior of a typical transistor.

[0095] Next, the temperature dependence of the FETs 600 and 700 according to the fifth and sixth embodiments will be described. FIG. 30(a) is a diagram showing the temperature dependence of the FET 600 in FIG. 17, and FIG. 30(b) is a diagram showing the temperature dependence of the FET 700 in FIG. 22. Both the FETs 600 and 700 were measured in environments of 3.5, 4, 5, 10, 20, 22, 25, 30, and 50 K. The horizontal axis represents the back gate voltage V BG , the vertical axis is the drain current I DS It is.

[0096] In the fifth and sixth embodiments, the back gate structure is used and the STO substrate is as thick as 500 μm. BG (That is, the gate-source voltage V GS ) is larger, but this can be reduced by using a thinner substrate or by adopting the front gate structure described in Example 7, so this is not a problem in practice. Similarly, the drain voltage V D (That is, the drain-source voltage V DS ) can also be reduced by shortening the channel length.

[0097] Example 7 31(a) to (d) are cross-sectional views of FETs 800A to 800D according to Examples 7 to 10. The FETs 800A to 800D commonly include an STO substrate 802, a metal oxide film 804 (or 805), a cap layer 808, a gate electrode 809, a drain electrode 820, and a source electrode 822. The FETs 800A to 800D have a front gate structure, and the gate electrode 809 is formed on the upper surface of the cap layer 808, not on the rear surface of the substrate 802. The cap layer 808 functions as an oxide insulating film, and therefore the FETs 800A to 800E have a MOS (Metal Oxide Semiconductor) structure.

[0098] Further, n-type regions 826 and 828 are formed directly below the drain electrode 820 and the source electrode 822, respectively.

[0099] The FET 800A in FIG. 31(a) is a front-gated version of the FET 600 in FIG. 17. The thickness of the metal oxide film 804 is set to a value equal to the threshold voltage t TH Thinner and therefore directly beneath it, p-type region 806 is formed.

[0100] The FET 800B in FIG. 31(b) is a front-gated version of the FET 700 in FIG. 22. The thickness of the metal oxide film 805 is 1 / 2 the threshold voltage t TH It is thicker and therefore directly underneath it an n-type region 807 is formed.

[0101] FETs 800C and 800D in Figs. 31(c) and (d) are obtained by adding carrier-type control electrodes 824 and 825 to the FET 800B in Fig. 31(b). The carrier-type control electrodes 824 and 825 are provided to apply a potential to the STO substrate from the outside. In Fig. 31(c), the carrier-type control electrode 824 is formed on the back side of the STO substrate 802, and in Fig. 31(d), the carrier-type control electrode 825 is formed on the front side of the STO substrate 802. As described in the sixth embodiment, the back gate voltage V BG In other words, by increasing the substrate potential, it is possible to switch the carrier type of the channel directly below the gate between n-type and p-type.

[0102] In addition, in the front-gate FETs of FETs 800A and 800B in Figures 31(a) and 31(b), a backgate electrode may be provided in the same manner as in a general front-gate MOSFET, not for the purpose of controlling the carrier type but for the purpose of fixing the substrate potential to the power supply voltage or ground voltage.

[0103] The present invention has been described using specific terms based on the embodiments, but the embodiments merely illustrate the principles and applications of the present invention, and many modifications and changes in arrangement are permitted to the embodiments without departing from the spirit of the present invention as defined in the claims. [Industrial Applicability]

[0104] The present invention relates to semiconductor devices. [Explanation of symbols]

[0105] 100 STO semiconductor devices 102 STO board 104 Metal oxide film 106 p-type region 108 Cap Layer 110,112 Metal film 200 STO semiconductor devices 202 STO board 204 First metal oxide film 206 Second metal oxide film 208 Cap Layer 210 p-type region 212 n-type region 220 Metal Film 224 Metal Film 250 areas 252 Mask 254 areas 256 Mask 300 STO semiconductor devices 302 STO board 304 First metal oxide film 306 Second metal oxide film 308 Cap Layer 310 p-type region 312 n-type region 400 STO semiconductor device 402 STO board 404 First metal oxide film 406 Second metal oxide film 408 Cap Layer 410 p-type region 412 n-type region 500 STO semiconductor devices 502 STO board 504 First metal oxide film 506 Second metal oxide film 508,509 Cap layer 510 p-type region 512 n-type region 600 FET 602 STO board 604 Metal oxide film 606 p-type region 608 Cap Layer 620 Drain electrode 622 Source Electrode 624 Backgate electrode 626 n-type region 628 n-type region 700 FET 702 STO board 704 Metal oxide film 706 n-type region 708 Cap Layer 720 Drain electrode 722 Source Electrode 724 Backgate electrode 800A FET 800B FET 800C FET 800D FET 802 STO board 804 Metal oxide film 805 Metal oxide film 806 p-type region 807 n-type region 808 Cap Layer 809 Gate electrode 820 Drain electrode 822 Source Electrode 824,825 Carrier type control electrode 826,828 n-type region

Claims

1. STO (SrTiO ３ ) substrate; a first metal oxide film formed on the STO substrate and having a thickness smaller than a predetermined threshold; a p-type region formed at an interface between the STO substrate and the first metal oxide film; An STO semiconductor device comprising:

2. The metal element M contained in the first metal oxide film is the metal element M and its oxide MO ｘ 2. The STO semiconductor device of claim 1, wherein the work function is higher than 3.9 eV.

3. The enthalpy change ΔH of oxide formation of the metal element M contained in the first metal oxide film ｆ -8 eV / O ２ ~-4.8 eV / O ２ The STO semiconductor device according to claim 1 or 2, characterized in that the STO semiconductor device is within the range of

4. 4. The STO semiconductor device of claim 3, wherein the metal element M is Fe and the threshold value is 0.3 nm.

5. 5. The STO semiconductor device according to claim 1, further comprising a drain electrode and a source electrode formed on the surface of the STO substrate so as to sandwich the p-type region.

6. a second metal oxide film formed on the STO substrate, having a thickness greater than the threshold value and containing the same metal element as the first metal oxide film; an n-type region formed at an interface between the STO substrate and the second metal oxide film; The STO semiconductor device according to claim 1 , further comprising:

7. a second metal oxide film formed on the STO substrate, containing the same metal element as the first metal oxide film and having the same thickness as the first metal oxide film; an n-type region formed at an interface between the STO substrate and the second metal oxide film; Further equipped with 7. The STO semiconductor device according to claim 1, wherein the second metal oxide film contains more oxygen than the first metal oxide film.

8. a second metal oxide film formed on the STO substrate and including a metal element different from that of the first metal oxide film; an n-type region formed at an interface between the STO substrate and the second metal oxide film; The STO semiconductor device according to claim 1 , further comprising:

9. a second metal oxide film formed on the STO substrate and having a thickness greater than the threshold; a carrier region formed at an interface between the STO substrate and the second metal oxide film; a carrier-type control electrode for controlling the potential of the STO substrate; Further equipped with 6. The STO semiconductor device according to claim 1, wherein the carrier type of the carrier region is controllable in response to a voltage applied to the carrier type control electrode.

10. 9. The STO semiconductor device of claim 6, wherein the first metal oxide film and the second metal oxide film are formed on the same surface of the STO substrate, and the p-type region and the n-type region are laterally bonded.

11. 9. The STO semiconductor device of claim 6, wherein the first metal oxide film and the second metal oxide film are formed on different sides of the STO substrate, and the p-type region and the n-type region are bonded vertically.

12. STO (SrTiO ３ ) substrate; a metal oxide film formed on the STO substrate and having a thickness greater than a predetermined threshold; a carrier region formed at an interface between the STO substrate and the metal oxide film; a carrier-type control electrode for controlling the potential of the STO substrate; Equipped with An STO semiconductor device, characterized in that the carrier type of the carrier region is controllable in response to a voltage applied to the carrier-type control electrode.

13. STO (SrTiO ３ 1.) A method for manufacturing a semiconductor device, comprising the steps of: depositing a first metal film having a thickness smaller than a predetermined threshold on a portion of the STO substrate where a p-type region is to be formed; oxidizing the first metal film to form a p-type region at an interface between the first metal film and the STO substrate; A manufacturing method comprising:

14. depositing a second metal film containing the same metal element as the first metal film and having a thickness greater than the threshold value on a portion of the STO substrate where an n-type region is to be formed; oxidizing the second metal film to form an n-type region at an interface between the second metal film and the STO substrate; The method of claim 13 further comprising:

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