Semiconductor Device

Abstract

Provided is a semiconductor device having a reduced foot print. The semiconductor device comprises: a first transistor having a first oxide semiconductor; a second transistor having a second oxide semiconductor; a capacitive element; a first insulator; and a first electrical conductor in contact with a source or a drain of the second transistor. The capacitive element comprises a second electrical conductor, a third electrical conductor, and a second insulator. The first transistor, the second transistor, and the first electrical conductor are disposed so as to be embedded in the first insulator. The second electrical conductor is disposed in contact with an upper surface of the first electrical conductor and with an upper surface of a gate of the first transistor. The second insulator is disposed on the second electrical conductor and the first insulator. The third electrical conductor is disposed covering the second electrical conductor with the second insulator therebetween.

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the above-mentioned technical fields. The technical fields of the inventions disclosed in this specification relate to products, methods, or manufacturing methods. Alternatively, one aspect of the present invention relates to processes, machines, manufactures, or compositions of matter.

[0003] In this specification and the like, a semiconductor device generally refers to anything that can function by utilizing semiconductor characteristics. Therefore, semiconductor elements such as transistors and diodes, and circuits including semiconductor elements are semiconductor devices. Furthermore, display devices, light-emitting devices, lighting devices, electro-optical devices, memory devices, imaging devices, communication devices, and electronic devices may include semiconductor elements and semiconductor circuits. Furthermore, display devices, light-emitting devices, lighting devices, electro-optical devices, memory devices, imaging devices, communication devices, and electronic devices may also be called semiconductor devices. [Background technology]

[0004] BACKGROUND ART In recent years, transistors using an oxide semiconductor or a metal oxide for a channel formation region (oxide semiconductor transistors, hereinafter referred to as OS transistors) have attracted attention (Patent Document 1).

[0005] OS transistors have an extremely small off-state current. Utilizing this, Patent Documents 2 and 3 disclose nonvolatile memories using OS transistors. Nonvolatile memories using OS transistors have no limit to the number of times data can be rewritten, and consume little power when rewriting data. Patent Document 3 also discloses an example of a nonvolatile memory memory cell constructed using only OS transistors.

[0006] In this specification, nonvolatile memory using OS transistors may be referred to as NOSRAM (registered trademark). NOSRAM is an abbreviation for "Nonvolatile Oxide Semiconductor RAM" and refers to RAM with gain cell type (2T type, 3T type) memory cells. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-151383 [Patent Document 3] Japanese Patent Application Laid-Open No. 2016-115387 Summary of the Invention [Problem to be solved by the invention]

[0008] An object of one embodiment of the present invention is to provide a semiconductor device with a small occupation area.An object of one embodiment of the present invention is to provide a semiconductor device that can be highly integrated.An object of one embodiment of the present invention is to provide a semiconductor device with a large storage capacity.An object of one embodiment of the present invention is to provide a semiconductor device with low manufacturing cost.An object of one embodiment of the present invention is to provide a highly reliable semiconductor device.An object of one embodiment of the present invention is to provide a novel semiconductor device.

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other problems from the description in the specification, drawings, claims, etc. [Means for solving the problem]

[0010] One embodiment of the present invention provides a semiconductor device including a first transistor, a second transistor, a capacitor, a first insulator, and a first conductor. The first transistor has a first oxide semiconductor, a first gate, and a first gate insulator. The second transistor has a second oxide semiconductor, a second gate, and a second gate insulator. The capacitor has a second conductor, a third conductor, and a second insulator. The first insulator is disposed over the first oxide semiconductor and the second oxide semiconductor. A first opening reaching the first oxide semiconductor is formed in the first insulator. A semiconductor device in which a second opening reaching the semiconductor is formed, a third opening reaching one of the source or drain of the second transistor is formed, a first gate insulator and a first gate are disposed in the first opening, a second gate insulator and a second gate are disposed in the second opening, a first conductor is disposed in the third opening, the second conductor is disposed in contact with an upper surface of the first conductor and an upper surface of the first gate, a second insulator is disposed on the second conductor and the first insulator, and a third conductor is disposed to cover the second conductor with the second insulator interposed therebetween.

[0011] In the above, the second conductor is preferably disposed to cover the first gate.

[0012] In the above, a part of the first gate may be exposed from the second conductor and a part of the first gate may be in contact with the second insulator.

[0013] In the above, it is preferable that the channel length direction of the first transistor and the channel length direction of the second transistor are substantially parallel to each other, and that the extending direction of the third conductor is substantially perpendicular to the channel length direction of the first transistor.

[0014] In the above, it is preferable that a fourth conductor be in contact with an upper surface of the second gate, and that the extension direction of the fourth conductor be approximately perpendicular to the channel length direction of the second transistor. In the above, it is preferable that the fourth conductor overlap with the first oxide semiconductor with the first insulator interposed therebetween.

[0015] Another embodiment of the present invention includes first to fourth transistors, a first oxide semiconductor, a second oxide semiconductor, a first capacitor, a second capacitor, a first insulator, a second insulator, a first conductor, and a second conductor. The first transistor and the third transistor are formed using the first oxide semiconductor, and the second transistor and the fourth transistor are formed using the second oxide semiconductor. The first transistor has a first gate and a first gate insulator. The second transistor has a second gate and a the third transistor has a third gate and a third gate insulator; the fourth transistor has a fourth gate and a fourth gate insulator; the first capacitance element has a third conductor and a fourth conductor; the second capacitance element has a fifth conductor and a sixth conductor; the first insulator is disposed on the first oxide semiconductor and the second oxide semiconductor; the first insulator reaches the first oxide semiconductor; and a first opening and a second opening are formed and reach the second oxide semiconductor. a third opening and a fourth opening are formed; a fifth opening reaching one of the source or drain of the second transistor is formed; a sixth opening reaching one of the source or drain of the fourth transistor is formed; a first gate insulator and a first gate are disposed in the first opening; a third gate insulator and a third gate are disposed in the second opening; a second gate insulator and a second gate are disposed in the third opening; a fourth gate insulator and a fourth gate are disposed in the fourth opening; a first conductor is disposed in the fifth opening, a second conductor is disposed in the sixth opening, a third conductor is disposed in contact with an upper surface of the first conductor and an upper surface of the first gate, a fifth conductor is disposed in contact with an upper surface of the second conductor and an upper surface of the third gate, a second insulator is disposed on the third conductor, the fifth conductor and the first insulator, a fourth conductor is disposed covering the third conductor with the second insulator interposed therebetween, and a sixth conductor is disposed covering the fifth conductor with the second insulator interposed therebetween.

[0016] In the above, the first oxide semiconductor and the second oxide semiconductor preferably contain indium, an element M (M is one or more selected from gallium, aluminum, yttrium, and tin), and zinc. [Effects of the Invention]

[0017] According to one embodiment of the present invention, a semiconductor device with a small occupation area can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device which enables high integration can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with a large storage capacity can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device which can be manufactured at low cost can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high reliability can be provided. Alternatively, according to one embodiment of the present invention, a novel semiconductor device can be provided.

[0018] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0019] 1A and 1B are circuit and top views of a semiconductor device according to one embodiment of the present invention. 2A and 2B are top views of a semiconductor device according to one embodiment of the present invention. 3A and 3B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. FIG. 4 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. Figure 5A is a diagram explaining the classification of IGZO crystal structures, Figure 5B is a diagram explaining the XRD spectrum of a CAAC-IGZO film, and Figure 5C is a diagram explaining the electron microbeam diffraction pattern of a CAAC-IGZO film. FIG. 6 is a top view of a semiconductor device according to one embodiment of the present invention. 7A and 7B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. 8A and 8B are circuit diagrams of a semiconductor device according to one embodiment of the present invention. 9A and 9B are block diagrams illustrating a structural example of a semiconductor device according to one embodiment of the present invention, and perspective views illustrating a structural example of a semiconductor device according to one embodiment of the present invention. FIG. 10 is a circuit diagram of a memory cell array according to one embodiment of the present invention. FIG. 11 is a schematic diagram of a memory cell array according to one embodiment of the present invention. 12A and 12B are timing charts of a memory cell array according to one embodiment of the present invention. FIG. 13 is a diagram showing various storage devices by hierarchical level. 14A to 14E illustrate application examples of a memory device according to one embodiment of the present invention. 15A to 15H are diagrams illustrating an electronic device according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0020] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same parts or parts having similar functions will be denoted by the same reference numerals in different drawings, and repeated descriptions thereof will be omitted.

[0021] Furthermore, the position, size, range, etc. of each component shown in the drawings, etc. may not represent the actual position, size, range, etc. in order to facilitate understanding of the invention. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings, etc. For example, in an actual manufacturing process, a resist mask, etc. may be unintentionally eroded by a process such as etching, but this may not be reflected in the drawings in order to facilitate understanding.

[0022] In addition, in the drawings and the like, the illustration of some components may be omitted in order to make the explanation easier to understand.

[0023] Furthermore, the terms "electrode" and "wiring" used in this specification and elsewhere do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0024] In addition, in this specification, a "terminal" in an electric circuit refers to a part where a current is input or output, a voltage is input or output, or a signal is received or transmitted. Therefore, a part of a wiring or an electrode may function as a terminal.

[0025] In this specification, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below, and being in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not necessarily mean that electrode B is formed on insulating layer A in direct contact with it, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0026] In addition, the functions of the source and drain are interchangeable depending on operating conditions, such as when transistors of different polarities are used or when the direction of current changes during circuit operation, making it difficult to define which is the source and which is the drain. For this reason, the terms source and drain can be used interchangeably in this specification.

[0027] Furthermore, in this specification, "electrically connected" includes both direct connection and connection via "something that has some kind of electrical effect." Here, "something that has some kind of electrical effect" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. Therefore, even when the expression "electrically connected" is used, in an actual circuit, there may be no physical connection and only wiring may be extended.

[0028] In this specification and elsewhere, when referring to counting values ​​and measurement values, terms such as "same," "equal," or "uniform" are used, they are considered to include an error of plus or minus 20%, unless otherwise specified.

[0029] Furthermore, voltage often refers to the potential difference between a certain potential and a reference potential (for example, ground potential or source potential). Therefore, voltage and potential can often be used interchangeably. In this specification and elsewhere, unless otherwise specified, voltage and potential can be used interchangeably.

[0030] It should be noted that even when written as "semiconductor," if the conductivity is sufficiently low, it will have the properties of an "insulator." Therefore, it is also possible to use "semiconductor" instead of "insulator." In this case, the boundary between "semiconductor" and "insulator" is vague, and it is difficult to strictly distinguish between the two. Therefore, "semiconductor" and "insulator" described in this specification may be read interchangeably.

[0031] Furthermore, even when written as "semiconductor," if the conductivity is sufficiently high, it will have the properties of a "conductor." Therefore, it is also possible to use "semiconductor" instead of "conductor." In this case, the boundary between "semiconductor" and "conductor" is vague, and it is difficult to strictly distinguish between the two. Therefore, "semiconductor" and "conductor" described in this specification may be read interchangeably.

[0032] Note that ordinal numbers such as "first" and "second" used in this specification are used to avoid confusion between components, and do not indicate any order or ranking, such as the order of processes or stacking. Furthermore, even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion between components. Furthermore, even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Furthermore, even if a term has an ordinal number in this specification, the ordinal number may be omitted in the claims.

[0033] In this specification and the like, the "on state" of a transistor refers to a state in which the source and drain of the transistor are considered to be electrically short-circuited (also referred to as a "conductive state"). The "off state" of a transistor refers to a state in which the source and drain of the transistor are considered to be electrically disconnected (also referred to as a "non-conductive state").

[0034] In this specification, the term "on-state current" may refer to a current that flows between the source and drain of a transistor when the transistor is on, and the term "off-state current" may refer to a current that flows between the source and drain of a transistor when the transistor is off.

[0035] In this specification, the high power supply potential VDD (hereinafter simply referred to as "VDD," "H potential," or "H") refers to a power supply potential that is higher than the low power supply potential VSS (hereinafter simply referred to as "VSS," "L potential," or "L"). VSS refers to a power supply potential that is lower than VDD. Ground potential (hereinafter simply referred to as "GND" or "GND potential") can also be used as VDD or VSS. For example, when VDD is the ground potential, VSS is a potential lower than the ground potential, and when VSS is the ground potential, VDD is a potential higher than the ground potential.

[0036] Unless otherwise specified, the transistors described in this specification and the like are enhancement-type (normally-off) n-channel field-effect transistors. Therefore, their threshold voltages (also referred to as "Vth") are assumed to be greater than 0 V. Unless otherwise specified, "supplying an H potential to the gate of a transistor" may be synonymous with "turning the transistor on." Unless otherwise specified, "supplying an L potential to the gate of a transistor" may be synonymous with "turning the transistor off."

[0037] In this specification and the like, a gate refers to a gate electrode and a part or all of a gate wiring, and a gate wiring refers to a wiring for electrically connecting the gate electrode of at least one transistor to another electrode or another wiring.

[0038] In this specification, the term "source" refers to a source region, a source electrode, and part or all of a source wiring. The term "source region" refers to a region of a semiconductor layer whose resistivity is equal to or less than a certain value. The term "source electrode" refers to a conductive layer connected to the source region. The term "source wiring" refers to wiring that electrically connects the source electrode of at least one transistor to another electrode or wiring.

[0039] In this specification, the term "drain" refers to a part or all of the drain region, drain electrode, and drain wiring. The term "drain region" refers to a region of the semiconductor layer whose resistivity is equal to or less than a certain value. The term "drain electrode" refers to a conductive layer connected to the drain region. The term "drain wiring" refers to wiring that electrically connects the drain electrode of at least one transistor to another electrode or wiring.

[0040] In addition, in drawings, etc., to make the potential of wiring, electrodes, etc. easier to understand, an "H" indicating an H potential or an "L" indicating an L potential may be written next to the wiring, electrode, etc. Furthermore, wiring, electrodes, etc. where a potential change has occurred may be written with "H" or "L" enclosed in letters. Furthermore, when a transistor is in an off state, an "x" symbol may be written next to the transistor.

[0041] Generally, a "capacitance" has a configuration in which two electrodes face each other via an insulator (dielectric). In this specification, etc., the term "capacitance element" includes the above-mentioned "capacitance." That is, in this specification, etc., the term "capacitance element" includes a configuration in which two electrodes face each other via an insulator, a configuration in which two wires face each other via an insulator, or a configuration in which two wires are arranged via an insulator.

[0042] Furthermore, in this specification and the like, when the same reference numeral is used for multiple elements, and when it is particularly necessary to distinguish between them, the reference numeral may be accompanied by an identifying symbol such as "_1," "_2," "[n]," "[m,n]," etc. For example, the second wiring CL may be described as wiring CL[2].

[0043] Note that the channel length refers to, for example, a region where the semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap in a top view of a transistor, or the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the channel formation region. Note that the channel length of one transistor does not necessarily have the same value in all regions. That is, the channel length of one transistor may not be fixed to a single value. Therefore, in this specification, the channel length is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0044] The channel width refers to, for example, the length of a channel formation region in a region where a semiconductor (or a portion of the semiconductor through which current flows when the transistor is on) and a gate electrode overlap in a top view of a transistor, or the length of the channel formation region in a direction perpendicular to the channel length direction in the channel formation region. Note that the channel width of a single transistor does not necessarily have the same value in all regions. That is, the channel width of a single transistor may not be determined to a single value. Therefore, in this specification, the channel width refers to any one value, maximum value, minimum value, or average value in the channel formation region.

[0045] In this specification and the like, depending on the structure of a transistor, the channel width in a region where a channel is actually formed (hereinafter also referred to as an "effective channel width") may differ from the channel width shown in a top view of the transistor (hereinafter also referred to as an "apparent channel width"). For example, when a gate electrode covers the side surface of a semiconductor, the effective channel width may be larger than the apparent channel width, and the influence thereof may not be negligible. For example, in a fine transistor in which a gate electrode covers the side surface of a semiconductor, the proportion of the channel formation region formed on the side surface of the semiconductor may be large. In such a case, the effective channel width is larger than the apparent channel width.

[0046] In such cases, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width.

[0047] In this specification, when simply referred to as a channel width, it may refer to an apparent channel width. Alternatively, when simply referred to as a channel width, it may refer to an effective channel width. Note that values ​​of the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image, etc.

[0048] Note that impurities in semiconductors refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities can, for example, increase the defect state density of the semiconductor or reduce the crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. For example, the inclusion of impurities can cause oxygen deficiency (V) in the oxide semiconductor. O :oxygen vacancy) may be formed.

[0049] In this specification and the like, an oxynitride is a material whose composition contains more oxygen than nitrogen, and a nitride oxide is a material whose composition contains more nitrogen than oxygen.

[0050] In this specification and the like, the term "insulator" can be replaced with an insulating film or an insulating layer, the term "conductor" can be replaced with a conductive film or a conductive layer, and the term "semiconductor" can be replaced with a semiconductor film or a semiconductor layer.

[0051] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0052] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as "oxide semiconductors" or simply as "OSs"). For example, when a metal oxide is used in a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0053] Furthermore, in this specification and the like, normally off means that when no potential is applied to the gate or when a ground potential is applied to the gate, the drain current flowing through the transistor per 1 μm of channel width is 1×10 -20 A or less, 1 x 10 at 85°C -18 A or less, or 1 x 10 at 125°C -16 This means that it is A or below.

[0054] (Embodiment 1) 1 to 8 , the structure of a memory cell 10 will be described as an example of a semiconductor device according to one embodiment of the present invention. The memory cell 10 functions as part of a memory device, includes a transistor 11, a transistor 12, and a capacitor 13, and is electrically connected to wirings CL, WL, RBL, SL, WBL, BGL1, and BGL2.

[0055] FIG. 1A is a circuit diagram of a memory cell 10, and FIG. 1B is a top view of the memory cell 10. FIG. 2A is a top view of FIG. 1B excluding the wiring CL. FIG. 2B is a top view of FIG. 1B excluding the wiring CL, wiring WL, conductor 207, dashed-dotted lines A1-A2-A3, and dashed-dotted lines A4-A5-A6. Note that some elements are omitted from the top views of FIGS. 1B, 2A, and 2B for clarity.

[0056] 3A is a cross-sectional view of the portion indicated by the dashed dotted line A1-A2-A3 in FIGS. 1B and 2A. Here, the cross-sectional view indicated by A1-A2 is a cross-sectional view in the channel length direction of transistor 12, and the cross-sectional view indicated by A2-A3 is a cross-sectional view in the channel width direction of transistor 11. Also, FIG. 3B is a cross-sectional view of the portion indicated by the dashed dotted line A4-A5-A6 in FIGS. 1B and 2A. Here, the cross-sectional view indicated by A4-A5 is a cross-sectional view in the channel width direction of transistor 12, and the cross-sectional view indicated by A5-A6 is a cross-sectional view in the channel length direction of transistor 11.

[0057] In the drawings, arrows may be used to indicate the x-direction, y-direction, and z-direction. The x-direction, y-direction, and z-direction are mutually orthogonal. In this specification, one of the x-direction, y-direction, and z-direction may be referred to as the "first direction." One of the other two may be referred to as the "second direction." The remaining one may be referred to as the "third direction."

[0058] <Configuration example of semiconductor device> First, an example of a circuit configuration of a memory cell 10 will be described. As shown in FIG. 1A, the memory cell 10 includes a transistor 11, a transistor 12, and a capacitor 13. One of the source and drain of the transistor 11 is electrically connected to a wiring RBL, and the other is electrically connected to a wiring SL. The backgate of the transistor 11 is electrically connected to a wiring BGL1. One of the source and drain of the transistor 12 is electrically connected to a wiring WBL, and the other is electrically connected to the gate of the transistor 11. Note that in this specification and elsewhere, a node or a wiring electrically connecting the gate of the transistor 11 and the other of the source and drain of the transistor 12 may be referred to as a node FN. The gate of the transistor 12 is electrically connected to a wiring WL, and the backgate is electrically connected to a wiring BGL2.

[0059] As shown in FIG. 1A, it is preferable that the transistors 11 and 12 are provided on the same plane, and the capacitor 13 is provided on the transistors 11 and 12. In other words, it is preferable that the capacitor 13 is arranged so as to overlap the transistors 11 and 12 in the z-axis direction. With this configuration, the capacitor 13 can be provided without increasing the area of ​​the transistors 11 and 12. This reduces the area occupied by the memory cell 10. This allows for a high degree of integration of the semiconductor device, and provides a semiconductor device with a large memory capacity. It also allows for a semiconductor device with a low manufacturing cost per memory capacity.

[0060] A wiring CL is disposed on the capacitor 13. Here, the wiring CL functions as an upper electrode of the capacitor 13. In contrast, the node FN functions as a lower electrode of the capacitor 13. That is, the capacitor 13 forms an MIM (Metal-Insulator-Metal) capacitance. It can also be said that the memory cell 10 includes the capacitor 13 between the node FN and the wiring CL.

[0061] The memory cell 10 has a function of retaining a potential (charge) written to the node FN and storing data. Specifically, a potential that turns on the transistor 12 is supplied to the wiring WL, thereby bringing the wiring WBL and the node FN into electrical continuity. Then, a charge for setting the node FN to a predetermined potential is supplied to the node FN through the wiring WBL. Then, a potential that turns off the transistor 12 is supplied to the gate of the transistor 12. By turning off the transistor 12, the charge written to the node FN is retained.

[0062] Furthermore, when reading data stored in the memory cell 10, a certain potential (hereinafter sometimes referred to as a read potential) may be applied to the wiring CL. When the read potential is supplied to the wiring CL, the transistor 11 is turned on or off depending on the potential written to the node FN. In other words, data stored in the node FN of the memory cell 10 can be read as the transistor 11 being turned on or off.

[0063] The semiconductor layers of the transistors 12 and 11 can be formed using a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like, either singly or in combination. Examples of semiconductor materials that can be used include silicon and germanium. Compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors can also be used.

[0064] Note that the semiconductor layers used in the transistor may be stacked. When the semiconductor layers are stacked, semiconductors having different crystal states or different semiconductor materials may be used for the respective layers.

[0065] In particular, the transistor 12 is preferably an OS transistor. An oxide semiconductor has a band gap of 2 eV or more, and therefore has a significantly small off-state current. When an OS transistor is used for the transistor 12, charge written to the node FN can be held for a long period of time. Therefore, the capacitance required for the capacitor 13 can be reduced. Therefore, when an OS transistor is used for the transistor 12, the area occupied by the capacitor 13 can be reduced. This makes it easier to arrange the capacitor 13 over the transistors 11 and 12, thereby reducing the area occupied by the memory cell 10. When an OS transistor is used for the transistor 12, the memory cell 10 can be called an "OS memory."

[0066] OS memory can retain written information for more than one year, or even more than ten years, even if the power supply is cut off, so OS memory can also be considered non-volatile memory.

[0067] Furthermore, since the amount of charge written into the OS memory is unlikely to change over a long period of time, the OS memory can hold not only binary (1-bit) information but also multi-value (multi-bit) information.

[0068] Furthermore, because OS memory writes charge to nodes via OS transistors, it does not require the high voltages required by conventional flash memory, enabling high-speed write operations. Furthermore, OS memory does not require the erase operation required before rewriting data, as is done with flash memory. Furthermore, because no charge is injected or extracted from the floating gate or charge trapping layer, OS memory allows for a virtually unlimited number of data write and read operations. OS memory is less susceptible to degradation than conventional flash memory, ensuring high reliability.

[0069] Furthermore, OS memory does not involve structural changes at the atomic level, as occurs in phase change memory (PCM), magnetoresistive random access memory (MRAM), or resistance random access memory (ReRAM). Therefore, OS memory has better rewrite endurance than phase change memory, magnetoresistive memory, and resistance random access memory.

[0070] Furthermore, the off-state current of an OS transistor hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an ambient temperature range of room temperature to 200°C. Furthermore, the on-state current is unlikely to decrease even in a high-temperature environment. A storage device including an OS memory has stable operation and high reliability even in a high-temperature environment. For this reason, when configuring an OS memory, it is preferable to use OS transistors for the transistors 11 and 12. Furthermore, OS transistors have a high withstand voltage between the source and drain. By using OS transistors as transistors constituting a semiconductor device, a semiconductor device with stable operation and high reliability even in a high-temperature environment can be realized.

[0071] 3A, 3B, etc., the memory cell 10 includes an insulator 212 on a substrate (not shown), an insulator 214 on the insulator 212, an insulator 216 on the insulator 214, an insulator 222 on the insulator 216, an insulator 224 on the insulator 222, an insulator 275 on the insulator 224, an insulator 280 on the insulator 275, an insulator 282 on the insulator 280, and an insulator 283 on the insulator 282. The insulators 212, 214, 216, 222, 224, 275, 280, 282, and 283 function as interlayer insulating films. The transistors 11 and 12 are provided in a layer between the insulator 214 and the insulator 282, and the capacitor 13 is provided on the insulator 280. An opening that reaches the other of the source and drain of the transistor 12 is formed in the insulator 280 and the insulator 275, and the conductor 240 is provided so as to be embedded in the opening. In addition, it is preferable that an insulator 241 be provided in contact with the side surface of the conductor 240.

[0072] The transistor 11 includes a conductor 205 (conductor 205a, conductor 205b, and conductor 205c) disposed so as to be embedded in the insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, an oxide 230c, an oxide 243a, and an oxide 243b on the oxide 230b, a conductor 242a on the oxide 243a, a conductor 242b on the oxide 243b, an insulator 250 on the oxide 230c, and a conductor 260 (conductor 260a and conductor 260b) located on the insulator 250 and overlapping with a part of the oxide 230b. Note that hereinafter, the oxide 230a, the oxide 230b, and the oxide 230c may be collectively referred to as the oxide 230. The oxide 243a and the oxide 243b may be collectively referred to as the oxide 243. The conductor 242a and the conductor 242b may be collectively referred to as the conductor 242.

[0073] Here, the conductor 260 functions as a top gate, and the conductor 205 functions as a back gate (wiring BGL1). The insulator 250 functions as a gate insulator for the top gate, and the insulators 222 and 224 function as gate insulators for the back gate. The conductor 242a functions as one of a source and a drain, and the conductor 242b functions as the other of the source and the drain. At least a part of the region of the oxide 230 that overlaps with the conductor 260 functions as a channel formation region.

[0074] Furthermore, the insulator 275 covers the insulator 224, the oxide 230a, the oxide 230b, the oxide 243, and the conductor 242, and the insulator 280 is provided in contact with the upper surface of the insulator 275. Openings that reach the oxide 230b and the insulator 224 are provided in the insulator 280 and the insulator 275, and the openings are provided so as to overlap the region between the conductor 242a and the conductor 242b.

[0075] 2B, 3A, and 3B, oxide 230c, insulator 250, and conductor 260 are disposed in the opening. Thus, oxide 230c is provided in contact with the upper surface of insulator 224, the side surface of oxide 230a, the upper surface and side surface of oxide 230b, the side surfaces of oxide 243a and oxide 243b, the side surfaces of conductor 242a and conductor 242b, the side surface of insulator 275, and the side surface of insulator 280. Furthermore, insulator 250 is provided in contact with the upper surface and side surface of oxide 230c, and conductor 260 is provided in contact with the upper surface and side surface of insulator 250. Furthermore, the upper surface of conductor 260, the top surface of insulator 250, and the top surface of oxide 230c are disposed so as to roughly coincide with the upper surface of insulator 280.

[0076] With this structure, the conductor 260, the insulator 250, and the oxide 230c can be formed in a self-aligned manner so as to be embedded in the openings formed in the insulator 280, etc. By forming the conductor 260, etc. in this manner, the conductor 260 can be placed in the region between the conductor 242a and the conductor 242b without alignment.

[0077] The transistor 12 also has a conductor 206 (conductor 206a, conductor 206b, and conductor 206c) arranged so as to be embedded in the insulator 216, an insulator 222 on the insulator 216 and on the conductor 206, an insulator 224 on the insulator 222, an oxide 231a on the insulator 224, an oxide 231b on the oxide 231a, an oxide 231c, an oxide 245a, and an oxide 245b on the oxide 231b, a conductor 244a on the oxide 245a, a conductor 244b on the oxide 245b, an insulator 251 on the oxide 231c, and a conductor 261 (conductor 261a and conductor 261b) located on the insulator 251 and overlapping with part of the oxide 231b. In the following, the oxide 231a, the oxide 231b, and the oxide 231c may be collectively referred to as the oxide 231. The oxide 245a and the oxide 245b may be collectively referred to as the oxide 245. The conductor 244a and the conductor 244b may be collectively referred to as the conductor 244.

[0078] Note that the transistor 12 has a similar structure to the transistor 11. Thus, the conductor 206 is formed in the same layer as the conductor 205, the oxide 231 is formed in the same layer as the oxide 230, the insulator 251 is formed in the same layer as the insulator 250, and the conductor 261 is formed in the same layer as the conductor 260, and thus has a similar structure. Therefore, in the following description, the conductor 206 can be referred to as the conductor 205, the oxide 231 as the oxide 230, the insulator 251 as the insulator 250, and the conductor 261 as the conductor 260 can be referred to.

[0079] Here, the conductor 261 functions as a top gate, and the conductor 206 functions as a back gate (wiring BGL2). The insulator 251 functions as a gate insulator for the top gate, and the insulators 222 and 224 function as gate insulators for the back gate. The conductor 244a functions as one of a source and a drain, and the conductor 244b functions as the other of the source and the drain. At least a part of a region of the oxide 231 that overlaps with the conductor 261 functions as a channel formation region.

[0080] Furthermore, the insulator 275 covers the insulator 224, the oxide 231a, the oxide 231b, the oxide 245, and the conductor 244, and the insulator 280 is provided in contact with the upper surface of the insulator 275. Openings that reach the oxide 231b and the insulator 224 are provided in the insulator 280 and the insulator 275, and the openings are provided overlapping the region between the conductor 244a and the conductor 244b.

[0081] 2B, 3A, and 3B, oxide 231c, insulator 251, and conductor 261 are disposed in the opening. Thus, oxide 231c is provided in contact with the upper surface of insulator 224, the side surface of oxide 231a, the upper surface and side surface of oxide 231b, the side surfaces of oxide 245a and oxide 245b, the side surfaces of conductor 244a and conductor 244b, the side surface of insulator 275, and the side surface of insulator 280. Furthermore, insulator 251 is provided in contact with the upper surface and side surface of oxide 231c, and conductor 261 is provided in contact with the upper surface and side surface of insulator 251. Furthermore, the upper surface of conductor 261, the top surface of insulator 251, and the top surface of oxide 231c are disposed so as to roughly coincide with the upper surface of insulator 280.

[0082] With this structure, the conductor 261, the insulator 251, and the oxide 231c can be formed in a self-aligned manner so as to be embedded in openings formed in the insulator 280, etc. By forming the conductor 261, etc. in this manner, the conductor 261 can be placed in the region between the conductor 244a and the conductor 244b without alignment.

[0083] The capacitance element 13 has a conductor 207 arranged in contact with the upper surface of the conductor 240 and the upper surface of the conductor 260, an insulator 282 arranged on the insulator 280 and the conductor 207, and a conductor 208 arranged on the insulator 282 and at least partially overlapping with the conductor 207.

[0084] Here, the conductor 207 functions as a node FN, and the conductor 208 functions as a wiring CL. In other words, the conductor 207 functions as a lower electrode of the capacitor 13, and the conductor 208 functions as an upper electrode of the capacitor 13. The insulator 282 functions as a dielectric of the capacitor 13.

[0085] 2A, the conductor 207 preferably includes the conductor 260 in a top view. In other words, the conductor 207 is preferably disposed so as to cover the conductor 260. Furthermore, the conductor 207 may also include the conductor 240 in a top view. With this configuration, the capacitor 13 can be disposed so as to cover the top gate of the transistor 11 and overlap with the other of the source and drain of the transistor 12. Therefore, the area of ​​the capacitor 13 can be increased without increasing the areas of the transistors 11 and 12.

[0086] 1B, 3A, and 3B, it is preferable that the insulator 282 is disposed so as to cover the conductor 207, and the conductor 208 is disposed so as to cover the conductor 207 via the insulator 282. As a result, the conductor 208 is also disposed on the side surface of the conductor 207 via the insulator 282. Therefore, the entire overlapping region between the conductor 208 and the conductor 207 and the side surface of the conductor 207 can function as the capacitance element 13.

[0087] By adopting the above-described configuration, the area occupied by the memory cell 10 can be reduced and the capacitor element 13 can be provided. This allows for a high level of integration of the semiconductor device, making it possible to provide a semiconductor device with a large memory capacity. In addition, it is possible to provide a semiconductor device with a low manufacturing cost per memory capacity.

[0088] Furthermore, a conductor 209 is disposed in contact with the upper surface of the conductor 261. The conductor 209 can be formed in the same layer as the conductor 207, and is covered with an insulator 282. The conductor 209 functions as the wiring WL.

[0089] A memory cell array can be formed by arranging a plurality of memory cells 10 in a matrix. In this case, it is preferable that the wiring connecting each memory cell 10 is provided so as to extend in one direction. For example, as shown in FIGS. 1A and 1B, the wiring CL (conductor 208), wiring WL (conductor 209), wiring BGL1 (conductor 205), and wiring BGL2 (conductor 206) may be provided so as to extend in the y direction. In this case, each memory cell 10 arranged in the y direction is connected to the common wiring CL (conductor 208), wiring WL (conductor 209), wiring BGL1 (conductor 205), and wiring BGL2 (conductor 206).

[0090] Furthermore, for example, if the conductor 261 is extended to serve as the wiring WL, a parasitic transistor will be formed where the wiring WL and the oxide 230b overlap. However, in this embodiment, the conductor 209 disposed on the conductor 261 functions as the wiring WL. As a result, as shown in A5 of FIG. 3B , the conductor 209 and the oxide 230b overlap with the insulator 280 or the like interposed therebetween. This makes it possible to prevent the formation of a parasitic transistor where the conductor 209 and the oxide 230b overlap.

[0091] Furthermore, when multiple memory cells 10 are arranged in the x direction, one of the source or drain of the transistor 11 of one memory cell 10 is connected to the other of the source or drain of the transistor 11 of an adjacent memory cell 10. Also, one of the source or drain of the transistor 12 of one memory cell 10 is connected to the other of the source or drain of the transistor 12 of the adjacent memory cell 10. That is, the sources and drains of multiple transistors 11 are connected in series, and the sources and drains of multiple transistors 12 are also connected in series. In other words, in the memory cell 10, one of the source or drain of the transistor 12 is electrically connected to the wiring WBL via another transistor 12, one of the source or drain of the transistor 11 is electrically connected to the wiring RBL via another transistor 11, and the other of the source or drain of the transistor 11 is electrically connected to the wiring SL via another transistor 11.

[0092] In this case, the node FN of the memory cell 10 is connected to the other of the source or drain of the transistor 12 of the memory cell 10 and to one of the source or drain of the transistor 12 of the adjacent memory cell 10. Therefore, the potential (charge) written to the node FN can be maintained by turning off the transistor 12 of each memory cell 10 and also turning off the transistor 12 of the adjacent memory cell 10.

[0093] 1B, the oxide 230b and the oxide 230a, and the oxide 231b and the oxide 231a may be provided so as to extend in the x-direction. As a result, the transistor 11 can be formed in the portion where the oxide 230b and the conductor 208 overlap, and the transistor 12 can be formed in the portion where the oxide 231b and the conductor 209 overlap. Here, the channel length direction of the transistor 11 and the channel length direction of the transistor 12 are approximately parallel. Furthermore, the channel length direction of the transistor 11 and the extension direction of the conductor 208 are approximately perpendicular. Furthermore, the channel length direction of the transistor 12 and the extension direction of the conductor 209 are approximately perpendicular.

[0094] In addition, the oxide 243 and the conductor 242 may be arranged extending in the x direction, similar to the oxide 230b, except for the region that overlaps with the conductor 260 and is removed. In addition, the oxide 245 and the conductor 244 may be arranged extending in the x direction, similar to the oxide 231b, except for the region that overlaps with the conductor 261 and is removed.

[0095] The configuration of the memory cell 10 is not limited to the above. For example, in each memory cell 10, the wiring RBL and the wiring SL may be connected to the transistor 11, and the transistor 12 may be connected to the wiring WBL. In this case, the oxides 230b, 231b, etc. are not provided in an elongated manner, but are patterned into an island shape in each memory cell 10. Therefore, the potential (charge) written to the node FN can be maintained by simply turning off the transistor 12 of each memory cell 10.

[0096] The details of the memory cell array in which a plurality of memory cells 10 are arranged in a matrix will be described later in the embodiments.

[0097] Next, an enlarged view of the vicinity of the channel formation region of the transistor 11 in Figure 3B is shown in Figure 4. Note that although the oxide 230 of the transistor 11 will be described below, the same description can also be referred to for the oxide 231 of the transistor 12. As shown in Figure 4, the oxide 230 has a region 232c that functions as a channel formation region of the transistor 11, and regions 232a and 232b that are provided on either side of the region 232c and function as source and drain regions of the transistor 11.

[0098] At least a portion of the region 232c overlaps with the conductor 260. In other words, the region 232c is provided in the region between the conductor 242a and the conductor 242b. The region 232a is provided overlapping with the conductor 242a, and the region 232b is provided overlapping with the conductor 242b.

[0099] The region 232c, which functions as a channel formation region, is a high-resistance region with a low carrier concentration because it has fewer oxygen vacancies or a lower impurity concentration than the regions 232a and 232b. Therefore, the region 232c can be said to be i-type (intrinsic) or substantially i-type.

[0100] Furthermore, the regions 232a and 232b that function as source and drain regions have many oxygen vacancies or high concentrations of impurities such as hydrogen, nitrogen, and metal elements, which increases the carrier concentration and reduces resistance. That is, the regions 232a and 232b are n-type regions with higher carrier concentrations and lower resistance than the region 232c.

[0101] Here, the carrier concentration of the region 232c functioning as a channel forming region is 1×10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the region 232c that functions as a channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0102] Furthermore, a region may be formed between region 232c and region 232a or region 232b, in which the carrier concentration is equal to or lower than the carrier concentration of region 232a and region 232b and equal to or higher than the carrier concentration of region 232c. That is, this region functions as a junction region between region 232c and region 232a or region 232b. The junction region may have a hydrogen concentration equal to or lower than the hydrogen concentration of region 232a and region 232b and equal to or higher than the hydrogen concentration of region 232c. The junction region may also have oxygen vacancies equal to or lower than the oxygen vacancies of region 232a and region 232b and equal to or higher than the oxygen vacancies of region 232c.

[0103] Furthermore, it may be difficult to clearly detect the boundaries between regions in the oxide 230. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may not necessarily vary stepwise from region to region, but may also vary continuously within each region. In other words, it is sufficient that the concentrations of metal elements and impurity elements such as hydrogen and nitrogen decrease in regions closer to the channel formation region.

[0104] The oxide 230 of the transistor 11, which includes a channel formation region, preferably includes a metal oxide functioning as a semiconductor (hereinafter also referred to as an oxide semiconductor). The oxide 230 preferably includes an oxide 230a disposed over the insulator 224, an oxide 230b disposed over the oxide 230a, and an oxide 230c disposed over the oxide 230b. Note that although the oxide 230 of the transistor 11 will be described below, the same description can also be referred to for the oxide 231 of the transistor 12.

[0105] Furthermore, it is preferable to use a metal oxide functioning as a semiconductor having a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of the transistor can be reduced. By using a metal oxide with a wide band gap, the off-state current of the transistor 11 and the transistor 12 can be reduced. In particular, by reducing the off-state current of the transistor 12, when the transistor 11 and the transistor 12 are used as memory cells of a storage device, stored data can be retained for a long period of time. That is, the storage device does not require a refresh operation, or the frequency of the refresh operation can be extremely low. This also allows the power consumption of the storage device to be sufficiently reduced.

[0106] As the oxide 230, for example, a metal oxide such as In-M-Zn oxide containing indium, element M, and zinc (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used. For example, as the oxide 230, an In-Ga-Zn oxide may be used, or an oxide obtained by adding tin to In-Ga-Zn oxide may also be used. Alternatively, as the oxide 230, an In-Ga oxide, an In-Zn oxide, or an indium oxide may also be used.

[0107] The metal oxide can be deposited on a substrate using a sputtering method or the like. Therefore, the transistors 11 and 12 can be provided overlapping peripheral circuits, such as driver circuits, formed on a silicon substrate. Therefore, when the transistors 11 and 12 are used as memory cells in a storage device, the area occupied by the memory cell array that can be provided on one chip can be increased, thereby increasing the storage capacity of the storage device. Furthermore, by depositing multiple layers of the metal oxide film, the memory cell array can be provided in a stacked configuration. This allows cells to be integrated and arranged without increasing the area occupied by the memory cell array. In other words, a stacked structure of the memory cell array (hereinafter, sometimes referred to as a 3D cell array) can be configured. As a result, a semiconductor device with high memory capacity and high integration of memory cells can be provided.

[0108] The method for forming the metal oxide film is not limited to sputtering, and other methods such as chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), and atomic layer deposition (ALD) may also be used as appropriate.

[0109] Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 230b is greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a. For oxide 230c, a metal oxide that can be used for oxide 230b or a metal oxide that can be used for oxide 230a may be used.

[0110] Specifically, the oxide 230a may be a metal oxide having an atomic ratio of In:M:Zn=1:3:4 or a similar composition, or an atomic ratio of In:M:Zn=1:1:0.5 or a similar composition. The oxide 230b may be a metal oxide having an atomic ratio of In:M:Zn=1:1:1 or a similar composition, an atomic ratio of In:M:Zn=4:2:3 or a similar composition, or an atomic ratio of In:M:Zn=5:1:3 or a similar composition. Note that a similar composition includes a range of ±30% of the desired atomic ratio. Gallium is preferably used as the element M.

[0111] When a metal oxide film is formed by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0112] By disposing the oxide 230a below the oxide 230b, it is possible to suppress the diffusion of impurities and oxygen from structures formed below the oxide 230a to the oxide 230b. In addition, by disposing the oxide 230c on the oxide 230b, it is possible to suppress the diffusion of impurities and oxygen from structures formed above the oxide 230c to the oxide 230b.

[0113] However, the oxide 230 is not limited to a three-layer structure of the oxide 230a, the oxide 230b, and the oxide 230c. For example, the oxide 230 may have a single layer of the oxide 230b, a two-layer structure of the oxide 230a and the oxide 230b, or a stacked structure of four or more layers. Alternatively, the oxide 230a, the oxide 230b, or the oxide 230c may each have a stacked structure. For example, the oxide 230c may have a two-layer stacked structure. In this case, a metal oxide that can be used for the oxide 230b may be provided as the oxide 230c, and a metal oxide that can be used for the oxide 230a may be provided on top of the metal oxide that can be used for the oxide 230a.

[0114] Furthermore, since the oxide 230a, the oxide 230b, and the oxide 230c have a common element other than oxygen (as a main component), the defect state density at the interface between the oxide 230a and the oxide 230b and at the interface between the oxide 230b and the oxide 230c can be reduced. Since the defect state density at the interface between the oxide 230a and the oxide 230b and at the interface between the oxide 230b and the oxide 230c can be reduced, the effect of interface scattering on carrier conduction is reduced, and a high on-current can be obtained.

[0115] Here, the conduction band minimum changes smoothly at the junction between the oxide 230a and the oxide 230b and at the junction between the oxide 230b and the oxide 230c. In other words, the conduction band minimum at the junction between the oxide 230a and the oxide 230b and at the junction between the oxide 230b and the oxide 230c can be said to change continuously or form a continuous junction. To achieve this, it is advisable to reduce the defect level density of the mixed layer formed at the interface between the oxide 230a and the oxide 230b and at the interface between the oxide 230b and the oxide 230c.

[0116] The oxide 230b preferably has crystallinity. In particular, it is preferable to use a c-axis aligned crystalline oxide semiconductor (CAAC-OS) as the oxide 230b. Alternatively, the oxide 230a or the oxide 230c may be made of CAAC-OS.

[0117] CAAC-OS has a highly crystalline and dense structure, and is free of impurities and defects (e.g., oxygen vacancies (V O The CAAC-OS is a metal oxide with low oxygen vacancy. In particular, by subjecting the formed metal oxide to heat treatment at a temperature at which the metal oxide does not polycrystallize (for example, 400°C or higher and 600°C or lower), the CAAC-OS can be made to have a dense structure with higher crystallinity. In this way, the density of the CAAC-OS can be increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.

[0118] On the other hand, since it is difficult to identify clear grain boundaries in CAAC-OS, it is said that the decrease in electron mobility due to grain boundaries is unlikely to occur. Therefore, metal oxides with CAAC-OS have stable physical properties. As a result, metal oxides with CAAC-OS are heat-resistant and highly reliable.

[0119] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in a region where a channel is formed in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may be reduced. In addition, hydrogen in the vicinity of the oxygen vacancy is converted into a defect where hydrogen enters the oxygen vacancy (hereinafter referred to as V O H.) and may generate electrons that serve as carriers even when no voltage is applied to the gate electrode of the transistor. Therefore, if oxygen vacancies are present in the region where a channel is formed in the oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the region where a channel is formed in the oxide semiconductor, impurities, oxygen vacancies, and V O It is preferable that H is reduced as much as possible. In other words, the region in the oxide semiconductor where the channel is formed has a reduced carrier concentration when no voltage is applied to the gate electrode of the transistor, and is preferably i-type (intrinsic) or substantially i-type.

[0120] In response to this problem, an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor, and heat treatment is performed to supply oxygen from the insulator to the oxide semiconductor, thereby eliminating oxygen vacancies and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or drain region, this may cause a decrease in the on-state current or a decrease in the field-effect mobility of the transistors 11 and 12. Furthermore, variations in the amount of oxygen supplied to the source region or drain region within the substrate surface will cause variations in the characteristics of the semiconductor device having the transistor.

[0121] Therefore, in the oxide semiconductor, the region 232c that functions as a channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, whereas the regions 232a and 232b that function as source and drain regions preferably have a high carrier concentration and are n-type. O It is preferable to reduce H so that an excessive amount of oxygen is not supplied to the regions 232a and 232b.

[0122] Therefore, with the conductor 242a and the conductor 242b provided on the oxide 230b, microwave treatment is performed in an oxygen-containing atmosphere to remove the oxygen vacancies in the region 232c and the V O It is preferable to reduce H. Here, the microwave treatment refers to treatment using, for example, an apparatus having a power source that generates high-density plasma using microwaves. Note that the transistor 12 is also subjected to microwave treatment in an oxygen-containing atmosphere with the conductors 244a and 244b provided therein.

[0123] By performing microwave processing in an atmosphere containing oxygen, oxygen gas can be converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be activated. At this time, microwaves or high frequency waves such as RF can also be irradiated onto region 232c. The action of plasma, microwaves, etc. can be used to irradiate the V of region 232c. O H is split off, hydrogen H is removed from the region 232c, and oxygen vacancies V O can be compensated with oxygen. O H → H + V O This reaction occurs, and the hydrogen concentration in the region 232c can be reduced. O H can be reduced to lower the carrier concentration.

[0124] Furthermore, when microwave processing is performed in an atmosphere containing oxygen, the effects of microwaves, high frequency waves such as RF, oxygen plasma, etc. are shielded by the conductors 242a and 242b and do not reach the regions 232a and 232b. Furthermore, the effects of oxygen plasma can be reduced by the insulators 275 and 280 that are provided to cover the oxide 230b and the conductor 242. As a result, during microwave processing, V O Since there is no reduction in H and no excessive supply of oxygen, it is possible to prevent a decrease in the carrier concentration.

[0125] In this way, oxygen vacancies and V O By removing H, the region 232c can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the region 232a, which functions as a source region or a drain region, and the region 232b can be prevented from being supplied with excessive oxygen, thereby maintaining n-type conductivity. This can suppress fluctuations in the electrical characteristics of the transistor 11 and prevent the electrical characteristics of the transistor 11 from varying across the substrate. Note that the same effect can be achieved with the transistor 12.

[0126] By adopting the above-described structure, it is possible to provide a semiconductor device with little variation in transistor characteristics, a semiconductor device with good electrical characteristics, and a semiconductor device with good reliability.

[0127] 3A and 3B, the side of the opening into which the conductor 260 and the like are embedded, including the groove in the oxide 230b, is generally perpendicular to the surface on which the oxide 230b is to be formed. However, this embodiment is not limited to this. For example, the bottom of the opening may be U-shaped, with a gently curved surface. Furthermore, for example, the side of the opening may be inclined relative to the surface on which the oxide 230b is to be formed.

[0128] 3A, in a cross-sectional view of the transistor 11 in the channel width direction, a curved surface may be formed between the side surface of the oxide 230b and the top surface of the oxide 230b. That is, the end of the side surface and the end of the top surface may be curved (hereinafter also referred to as rounded).

[0129] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 230b in the region overlapping with the conductor 242, or smaller than half the length of the region not having the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and smaller than 20 nm, preferably greater than 1 nm and smaller than 15 nm, and more preferably greater than 2 nm and smaller than 10 nm. This shape can improve the coverage of the oxide 230b with the insulator 250 and the conductor 260.

[0130] At least one of the insulators 212, 214, 275, 282, and 283 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistors 11 and 12 into the transistors 11 and 12. Therefore, at least one of the insulators 212, 214, 275, 282, and 283 is preferably an insulating material that suppresses the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), and copper atoms (i.e., through which the above impurities are less likely to permeate). Alternatively, it is preferably an insulating material that suppresses the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., through which the above oxygen is less likely to permeate).

[0131] In this specification, a barrier insulating film refers to an insulating film having barrier properties. In this specification, the barrier properties refer to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability) or a function of capturing and fixing a corresponding substance (also referred to as gettering).

[0132] For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used for the insulators 212, 214, 275, 282, and 283. For example, it is preferable to use silicon nitride, which has a higher hydrogen barrier property, for the insulators 212 and 283. Furthermore, it is preferable to use aluminum oxide or magnesium oxide, which has a high hydrogen capture and fixation function, for the insulators 214, 275, and 282. This can prevent impurities such as water and hydrogen from diffusing from the substrate side to the transistors 11 and 12 through the insulators 212 and 214. Alternatively, it can prevent impurities such as water and hydrogen from diffusing from an interlayer insulating film disposed above the insulator 283 to the transistors 11 and 12. Alternatively, oxygen contained in the insulator 224 or the like can be prevented from diffusing toward the substrate through the insulator 212 and the insulator 214. Alternatively, oxygen contained in the insulator 280 or the like can be prevented from diffusing upward from the transistors 11 and 12 through the insulator 282 or the like. In this way, it is preferable to have a structure in which the transistors 11 and 12 are surrounded by the insulators 212, 214, 275, 282, and 283, which have the function of preventing the diffusion of impurities such as water and hydrogen, and oxygen.

[0133] When aluminum oxide or the like is used as the insulators 212, 214, 275, 282, and 283, it is preferable to use an oxide having an amorphous structure. For example, AlO x (x is any number greater than 0), or MgO yIt is preferable to use a metal oxide such as y (where y is any number greater than 0). In such metal oxides having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. By using such a metal oxide having an amorphous structure as a component of the transistors 11 and 12 or by providing it around the transistors 11 and 12, hydrogen contained in the transistors 11 and 12 or hydrogen present around the transistors 11 and 12 can be captured or fixed. In particular, it is preferable to capture or fix hydrogen contained in the channel formation regions of the transistors 11 and 12. By using a metal oxide having an amorphous structure as a component of the transistors 11 and 12 or by providing it around the transistors 11 and 12, it is possible to manufacture the transistors 11 and 12 and the semiconductor device having excellent characteristics and high reliability.

[0134] Furthermore, when aluminum oxide or the like is used, the insulators 212, 214, 275, 282, and 283 preferably have an amorphous structure, but may have a polycrystalline structure in part. Furthermore, the insulators 212, 214, 275, 282, and 283 may have a multilayer structure in which an amorphous layer and a polycrystalline layer are stacked. For example, they may have a stacked structure in which a polycrystalline layer is formed on an amorphous layer.

[0135] The insulators 212, 214, 275, 282, and 283 can be formed by, for example, a sputtering method. Because the sputtering method does not require the use of hydrogen as a film formation gas, the hydrogen concentration of the insulators 212, 214, 275, 282, and 283 can be reduced. Note that the film formation method is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may also be used as appropriate.

[0136] It may also be preferable to reduce the resistivity of the insulators 212 and 283. For example, it is preferable to reduce the resistivity of the insulators 212 and 283 to approximately 1×10 13 By setting the resistivity to Ωcm, the insulator 212 and the insulator 283 may be able to reduce charge-up of the conductor 205, the conductor 242, or the conductor 260 in a process using plasma or the like in a semiconductor device manufacturing process. The resistivity of the insulator 212 and the insulator 283 is preferably 1×10 10 Ωcm or more 1×10 15 Ωcm or less.

[0137] Furthermore, the insulators 216 and 280 preferably have a lower dielectric constant than the insulator 214. Using a material with a low dielectric constant as an interlayer film can reduce parasitic capacitance between wirings. For example, the insulators 216 and 280 may be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like, as appropriate.

[0138] In the transistor 11, the conductor 205 is arranged to overlap with the oxide 230 and the conductor 260. The conductor 205 may be provided so as to extend in the y direction, as shown in FIG. 1B and other figures. Here, the conductor 205 is preferably provided by being embedded in an opening formed in the insulator 216. Note that although the conductor 205 of the transistor 11 will be described below, the same description can also be referred to for the conductor 206 of the transistor 12.

[0139] The conductor 205 includes conductor 205a, conductor 205b, and conductor 205c. The conductor 205a is provided in contact with the bottom surface and sidewall of the opening. The conductor 205b is provided so as to be embedded in a recess formed in the conductor 205a. Here, the upper surface of the conductor 205b is lower than the upper surface of the conductor 205a and the upper surface of the insulator 216. The conductor 205c is provided in contact with the upper surface of the conductor 205b and the side surface of the conductor 205a. Here, the height of the upper surface of the conductor 205c is approximately the same as the height of the upper surface of the conductor 205a and the height of the upper surface of the insulator 216. In other words, the conductor 205b is configured to be enclosed by the conductors 205a and 205c.

[0140] Here, the conductors 205a and 205c are preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0141] By using a conductive material that reduces hydrogen diffusion for the conductor 205a and the conductor 205c, it is possible to prevent impurities such as hydrogen contained in the conductor 205b from diffusing into the oxide 230 via the insulator 224 or the like. Furthermore, by using a conductive material that suppresses oxygen diffusion for the conductor 205a and the conductor 205c, it is possible to prevent the conductor 205b from being oxidized and its conductivity from decreasing. Examples of conductive materials that suppress oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductor 205a may be a single layer or a multilayer of the above conductive materials. For example, the conductor 205a may be made of titanium nitride.

[0142] The conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0143] The conductor 205 may function as a back gate electrode. In this case, the threshold voltage (Vth) of the transistor 11 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205 can increase the Vth of the transistor 11 and reduce its off-state current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V, compared to when a negative potential is not applied.

[0144] The electrical resistivity of the conductor 205 is designed taking into consideration the potential applied to the conductor 205, and the film thickness of the conductor 205 is set to match this electrical resistivity. The film thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to make the film thicknesses of the conductor 205 and the insulator 216 thin within the range permitted by the design of the conductor 205. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, thereby reducing the diffusion of the impurities into the oxide 230.

[0145] As shown in FIGS. 3A and 3B, the conductor 205 is preferably larger than the area of ​​the oxide 230 that does not overlap with the conductors 242a and 242b. In particular, the conductor 205 preferably extends to areas outside the ends of the oxides 230a and 230b that intersect with the channel width direction. That is, outside the side surfaces of the oxide 230 in the channel width direction, the conductor 205 and the conductor 260 preferably overlap with each other via an insulator. This structure allows the channel formation region of the oxide 230 to be electrically surrounded by the electric field of the conductor 260, which functions as a top gate electrode, and the electric field of the conductor 205, which functions as a back gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the top gate and the back gate is referred to as a surrounded channel (S-channel) structure.

[0146] In this specification and the like, a transistor with an S-channel structure refers to a transistor structure in which a channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. The S-channel structure disclosed in this specification and the like differs from a fin structure and a planar structure. By adopting the S-channel structure, the transistor can be made more resistant to the short-channel effect, in other words, less susceptible to the short-channel effect.

[0147] 1B and other figures, the conductor 205 is extended to function as wiring. However, the present invention is not limited to this, and a conductor functioning as wiring may be provided below the conductor 205. Furthermore, it is not necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by multiple transistors.

[0148] Although the conductor 205 has been shown as having a stacked structure of conductor 205a, conductor 205b, and conductor 205c, the present invention is not limited to this. The conductor 205 may have a single-layer, two-layer, or four or more-layer stacked structure. For example, when the conductor 205 has a two-layer stacked structure, the conductor 205c may not be provided, and the top surface of the conductor 205a may be flush with the top surface of the conductor 205b.

[0149] The insulators 222 and 224 function as gate insulators corresponding to the back gates of the transistors 11 and 12 .

[0150] The insulator 222 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). The insulator 222 also preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.

[0151] The insulator 222 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses oxygen release from the oxide 230 and the oxide 231 to the substrate and the diffusion of impurities such as hydrogen from the periphery of the transistor 11 and the transistor 12 to the oxide 230 and the oxide 231. Therefore, the provision of the insulator 222 can suppress the diffusion of impurities such as hydrogen into the inside of the transistor 11 and the transistor 12 and the generation of oxygen vacancies in the oxide 230 and the oxide 231. Furthermore, the conductors 205 and 206 can be prevented from reacting with the insulator 224 and the oxygen contained in the oxide 230 and the oxide 231.

[0152] Alternatively, the insulator may contain, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide. Alternatively, these insulators may be nitrided. Furthermore, the insulator 222 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0153] The insulator 222 may be a single layer or a multilayer of an insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, thinning the gate insulator can cause problems such as leakage current. Using a high-k material for the insulator that functions as the gate insulator allows for a reduction in the gate potential during transistor operation while maintaining the physical film thickness.

[0154] The insulator 224 in contact with the oxide 230 and the oxide 231 preferably contains excess oxygen (oxygen is released by heating). For example, the insulator 224 may be made of silicon oxide, silicon oxynitride, or the like as appropriate. By providing an insulator containing oxygen in contact with the oxide 230 and the oxide 231, oxygen vacancies in the oxide 230 and the oxide 231 can be reduced, and the reliability of the transistors 11 and 12 can be improved.

[0155] Specifically, it is preferable to use an oxide material from which a portion of oxygen is released by heating, in other words, an insulator material having an excess oxygen region, as the insulator 224. The oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen molecules is 1.0×10 18 molecules / cm 3 or more, preferably 1.0 × 10 19 molecules / cm 3 More preferably, 2.0 × 1019 molecules / cm 3 or more, or 3.0 x 10 20 molecules / cm 3 The oxide film is one having the above-mentioned properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0156] In addition, in the manufacturing process of the transistor 11 and the transistor 12, it is preferable to perform heat treatment while the surfaces of the oxide 230 and the oxide 231 are exposed. The heat treatment may be performed, for example, at a temperature of 100°C to 600°C, more preferably 350°C to 550°C. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 230 and the oxide 231, thereby eliminating oxygen deficiencies (V O ) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after the heat treatment in a nitrogen gas or inert gas atmosphere to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0157] By subjecting the oxide 230 and the oxide 231 to oxygen addition treatment, oxygen vacancies in the oxide 230 and the oxide 231 are repaired by the supplied oxygen. In other words, "V O +O→null reaction can be promoted. Furthermore, the supplied oxygen reacts with the hydrogen remaining in the oxide 230 and the oxide 231, and the hydrogen can be removed as HO (dehydration). As a result, the hydrogen remaining in the oxide 230 and the oxide 231 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0158] The insulators 222 and 224 may have a stacked structure of two or more layers. In this case, the stacked structures are not limited to those made of the same material, and may be stacked structures made of different materials. The insulator 224 may be formed in an island shape by overlapping with the oxide 230a and the oxide 231a. In this case, the insulator 275 is configured to contact the side surface of the insulator 224 and the top surface of the insulator 222.

[0159] The oxide 243a and the oxide 243b are provided over the oxide 230b. The oxide 243a and the oxide 243b are provided separately from each other with the conductor 260 interposed therebetween. Note that although the oxide 243 of the transistor 11 will be described below, the same description can also be referred to for the oxide 245 of the transistor 12.

[0160] The oxide 243 (oxide 243a and oxide 243b) preferably has a function of suppressing oxygen permeation. By disposing the oxide 243, which has a function of suppressing oxygen permeation, between the conductor 242, which functions as a source electrode or a drain electrode, and the oxide 230b, the electrical resistance between the conductor 242 and the oxide 230b is reduced, which is preferable. This structure can improve the electrical characteristics and reliability of the transistor 11. Note that if the electrical resistance between the conductor 242 and the oxide 230b can be sufficiently reduced, the oxide 243 may not be provided.

[0161] A metal oxide containing element M may be used as oxide 243. In particular, element M may be aluminum, gallium, yttrium, or tin. Preferably, oxide 243 has a higher concentration of element M than oxide 230b. Alternatively, oxide 243 may be gallium oxide. Alternatively, oxide 243 may be a metal oxide such as In-M-Zn oxide. Specifically, the atomic ratio of element M to In in the metal oxide used for oxide 243 is preferably greater than the atomic ratio of element M to In in the metal oxide used for oxide 230b. Furthermore, the film thickness of oxide 243 is preferably 0.5 nm to 5 nm, more preferably 1 nm to 3 nm, and even more preferably 1 nm to 2 nm. Furthermore, oxide 243 preferably has crystallinity. When oxide 243 has crystallinity, oxygen release from oxide 230 can be effectively suppressed. For example, oxide 243 with a hexagonal or other crystal structure may be able to suppress oxygen release from oxide 230.

[0162] It is preferable that the conductor 242a be provided in contact with the upper surface of the oxide 243a, and the conductor 242b be provided in contact with the upper surface of the oxide 243b. The conductors 242a and 242b are arranged in the A5-A6 direction and are spaced apart from each other with the conductor 260 sandwiched between them. Note that while the conductor 242 of the transistor 11 will be described below, the same description can also be taken into consideration for the conductor 244 of the transistor 12.

[0163] As the conductor 242 (conductor 242a and conductor 242b), it is preferable to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Also, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are resistant to oxidation or that maintain conductivity even when they absorb oxygen.

[0164] Note that hydrogen contained in the oxide 230b and the like may diffuse into the conductor 242a and the conductor 242b. In particular, by using a nitride containing tantalum for the conductor 242a and the conductor 242b, hydrogen contained in the oxide 230b and the like may diffuse into the conductor 242a and the conductor 242b, and the diffused hydrogen may bond with nitrogen contained in the conductor 242a and the conductor 242b. In other words, hydrogen contained in the oxide 230b and the like may be absorbed by the conductor 242a and the conductor 242b.

[0165] Alternatively, the conductor 242 may have a structure in which no curved surface is formed between the side surface and the top surface of the conductor 242. By forming the conductor 242 without such a curved surface, the cross-sectional area of ​​the conductor 242 in the cross section in the channel width direction can be increased. This increases the conductivity of the conductor 242 and the on-state current of the transistor 11.

[0166] The insulator 275 is provided to cover the insulator 224, the oxide 230, the oxide 231, the oxide 243, the oxide 245, the conductor 242, and the conductor 244, and openings are formed in the regions where the conductor 260, the conductor 261, the conductor 240, etc. are provided. The insulator 275 is preferably provided in contact with the top surface of the insulator 224, the side surface of the oxide 230, the side surface of the oxide 243, the side surface of the conductor 242, the top surface of the conductor 242, the side surface of the oxide 231, the side surface of the oxide 245, the side surface of the conductor 244, and the top surface of the conductor 244. The insulator 275 preferably functions as a barrier insulating film that suppresses oxygen permeation. The insulator 275 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above into the insulator 224, the oxide 230, or the oxide 231, and preferably has a function of capturing impurities such as hydrogen. The insulator 275 may be, for example, an insulator such as aluminum oxide or silicon nitride.

[0167] By providing insulator 275, which is in contact with insulator 280 and insulator 224 and has the function of capturing impurities such as hydrogen, in the region sandwiched between insulator 212 and insulator 283, impurities such as hydrogen contained in insulator 280 and insulator 224 can be captured, and the amount of hydrogen in the region can be kept constant. In this case, it is preferable to use aluminum oxide or the like as insulator 275.

[0168] Note that a barrier insulating film having a shape similar to that of the conductors 242 and 244 in a top view may be provided between the insulator 275 and the conductors 242 and 244. The insulator that can be used for the insulator 275 may be used for the barrier insulating film.

[0169] The insulator 250 functions as a gate insulator of the top gate of the transistor 11. In the transistor 11, the insulator 250 is preferably arranged to overlap with the oxide 230b. Note that although the insulator 250 of the transistor 11 will be described below, the same description can also be referred to for the insulator 251 of the transistor 12.

[0170] The insulator 250 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, etc. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat.

[0171] The insulator 250 preferably has a reduced concentration of impurities such as water and hydrogen, similar to the insulator 224. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0172] Although the insulator 250 is illustrated as a single layer in FIGS. 3A and 3B, it may have a laminated structure of two or more layers. When the insulator 250 has a laminated structure of two layers, it is preferable that the lower layer of the insulator 250 is formed using an insulator that releases oxygen when heated, and the upper layer of the insulator 250 is formed using an insulator that has the function of suppressing oxygen diffusion. This configuration can suppress the diffusion of oxygen contained in the lower layer of the insulator 250 into the conductor 260. In other words, it can suppress a decrease in the amount of oxygen supplied to the oxide 230. It can also suppress oxidation of the conductor 260 due to oxygen contained in the lower layer of the insulator 250. For example, the lower layer of the insulator 250 can be formed using a material that can be used for the insulator 250 described above, and the upper layer of the insulator 250 can be formed using a material similar to that of the insulator 222.

[0173] When silicon oxide or silicon oxynitride is used for the lower layer of the insulator 250, the upper layer of the insulator 250 may be made of an insulating material, which is a high-k material with a high dielectric constant. By forming the gate insulator into a laminated structure consisting of the lower layer of the insulator 250 and the upper layer of the insulator 250, a laminated structure that is stable against heat and has a high dielectric constant can be achieved. This makes it possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. It also makes it possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

[0174] Specifically, the upper layer of the insulator 250 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc., or a metal oxide that can be used as the oxide 230. In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium. For example, the insulator 250 can be a stacked structure containing silicon oxide and hafnium oxide on the silicon oxide.

[0175] Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. In other words, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Furthermore, oxidation of the conductor 260 by oxygen from the insulator 250 can be suppressed.

[0176] The metal oxide may be configured to function as part of the top gate electrode. For example, the metal oxide that can be used as the oxide 230 can be used as the metal oxide. In this case, by forming the conductor 260a by a sputtering method, the electrical resistance value of the metal oxide can be reduced to make it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0177] The presence of the metal oxide can improve the on-state current of the transistor 11 without weakening the influence of the electric field from the conductor 260. Furthermore, the physical thickness of the insulator 250 and the metal oxide can maintain a distance between the conductor 260 and the oxide 230, thereby suppressing leakage current between the conductor 260 and the oxide 230. Furthermore, the provision of a stacked structure of the insulator 250 and the metal oxide can easily and appropriately adjust the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230.

[0178] The conductor 260 functions as a top gate electrode of the transistor 11. In the transistor 11, the conductor 260 preferably includes a conductor 260a and a conductor 260b disposed over the conductor 260a. Note that although the conductor 260 of the transistor 11 will be described below, the same description can also be referred to for the conductor 261 of the transistor 12.

[0179] For example, conductor 260a is preferably disposed so as to wrap around the bottom and side surfaces of conductor 260b. Furthermore, as shown in Figures 3A and 3B, the top surface of conductor 260 is generally flush with the top surface of insulator 250 and the top surface of oxide 230c. While conductor 260 is shown in Figures 3A and 3B as having a two-layer structure of conductor 260a and conductor 260b, it may have a single-layer structure or a stacked structure of three or more layers.

[0180] The conductor 260a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0181] Furthermore, since the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 250. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0182] Furthermore, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 260b can be made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 260b may also have a layered structure, such as a layered structure of titanium or titanium nitride and the above conductive material.

[0183] 3A, in the channel width direction of the transistor 11, the height of the bottom surface of the conductor 260 in a region where the conductor 260 and the oxide 230b do not overlap is preferably lower than the height of the bottom surface of the oxide 230b, relative to the bottom surface of the insulator 222. The conductor 260, which functions as a gate electrode, covers the side and top surfaces of the channel formation region of the oxide 230b via the insulator 250 or the like, making it easier for the electric field of the conductor 260 to act on the entire channel formation region of the oxide 230b. This increases the on-state current of the transistor 11 and improves its frequency characteristics. The difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b in a region where the oxides 230a and 230b do not overlap with the conductor 260, relative to the bottom surface of the insulator 222, is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0184] The insulator 280 is provided on the insulator 275, and has openings formed in the areas where the conductors 260, 261, 240, etc. are to be provided. The upper surface of the insulator 280 may be flattened.

[0185] The insulator 280, which functions as an interlayer film, preferably has a low dielectric constant. Using a material with a low dielectric constant as the interlayer film can reduce the parasitic capacitance that occurs between wirings. The insulator 280 is preferably formed using, for example, the same material as the insulator 216. For example, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferred because they can easily form regions containing oxygen that is released by heating.

[0186] Like the insulator 224, the insulator 280 preferably has an excess oxygen region or excess oxygen. Furthermore, the concentration of impurities such as water and hydrogen in the insulator 280 is preferably reduced. For example, the insulator 280 may be an oxide containing silicon, such as silicon oxide or silicon oxynitride, as appropriate. By providing an insulator having excess oxygen in contact with the oxide 230 and the oxide 231, oxygen vacancies in the oxide 230 and the oxide 231 can be reduced, thereby improving the reliability of the transistors 11 and 12.

[0187] The conductor 240 provided between the transistor 12 and the capacitor 13 has a bottom surface in contact with the conductor 244b and a top surface in contact with the conductor 207. Furthermore, an insulator 241 is preferably provided in contact with the side surface of the conductor 240 functioning as a plug.

[0188] Insulator 241 is provided in contact with the inner walls of the openings of insulator 275 and insulator 280, a first conductor of conductor 240 is provided in contact with the side surface of insulator 241, and a second conductor of conductor 240 is provided further inward. Note that while Fig. 3A shows a configuration in which the first conductor of conductor 240 and the second conductor of conductor 240 are stacked, the present invention is not limited to this. For example, conductor 240 may be provided as a single layer or a stacked structure of three or more layers.

[0189] The conductor 240 is preferably made of a conductive material primarily composed of tungsten, copper, or aluminum. The conductor 240 may also have a layered structure. When the conductor 240 has a layered structure, the insulator 275 and the conductor in contact with the insulator 280 are preferably made of a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is preferably used. Furthermore, the conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a layered structure. This prevents impurities such as water and hydrogen contained in the insulator 280 from being mixed into the oxide 231 through the conductor 240.

[0190] The insulator 241 may be, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. The insulator 241 is provided in contact with the insulator 275 and the insulator 280, and therefore can prevent impurities such as water and hydrogen contained in the insulator 280 from mixing into the oxide 230 through the conductor 240. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. In addition, the oxygen contained in the insulator 280 can be prevented from being absorbed by the conductor 240.

[0191] Furthermore, the conductor 207 is provided in contact with the top surface of the conductor 240 and the top surface of the conductor 260. Here, the conductor 207 functions as a node FN. That is, the conductor 244b functioning as the other of the source and the drain of the transistor 12 is electrically connected to the conductor 260 functioning as the gate of the transistor 11 through the conductor 240 and the conductor 207.

[0192] Furthermore, in the same layer as the conductor 207, a conductor 209 is provided in contact with the top surface of the conductor 261. Here, the conductor 209 functions as a wiring WL.

[0193] The conductor 207 and the conductor 209 may be formed by patterning the same conductive film. The conductor 207 and the conductor 209 are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 207 and the conductor 209 may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above conductive material. The conductor 207 and the conductor 209 may be formed so as to be embedded in an opening provided in an insulator.

[0194] The insulator 282 covers the conductors 207 and 209 and is disposed in contact with the upper surface of the insulator 280. Because the insulator 282 functions as a dielectric of the capacitor 13, it is preferable to use an insulator with a small equivalent oxide thickness (EOT). Examples of the insulator 282 that can be used include aluminum oxide, gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, or a nitride containing silicon and hafnium. In this specification, the equivalent oxide thickness refers to a value obtained by converting a physical film thickness into an electrical film thickness equivalent to that of silicon oxide or silicon oxynitride.

[0195] For example, if aluminum oxide with a relative dielectric constant of 8.5 is used as the insulator 282 and the area of ​​the capacitance element 13 is 61800 nm 2 Then, by making the film thickness of the insulator 282 5 nm or less, the capacitance value of the capacitive element 13 can be made 0.9 fF or more. Here, if the film thickness of the insulator 282 is expressed using the EOT with a relative dielectric constant of 3.9, the film thickness of the insulator 282 becomes 2.3 nm.

[0196] If the capacitance value of the capacitor 13 is 0.9 fF or more, it is sufficiently larger than the gate capacitance of the transistor 12, and therefore data can be written to and read from the memory cell 10. In other words, by setting the film thickness of the insulator 282 to approximately 5 nm or less, the memory cell 10 can function sufficiently as a memory device.

[0197] The insulator 282 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above into the insulator 280 and preferably has a function of capturing impurities such as hydrogen. The insulator 282 preferably functions as a barrier insulating film that suppresses the permeation of oxygen. For example, an insulator such as aluminum oxide may be used as the insulator 282. By providing the insulator 282 in contact with the insulator 280 in the region sandwiched between the insulator 212 and the insulator 283 and having a function of capturing impurities such as hydrogen, impurities such as hydrogen contained in the insulator 280 can be captured and the amount of hydrogen in the region can be kept constant.

[0198] The insulator 282 is preferably formed by sputtering. For example, the insulator 282 may be formed by sputtering in an oxygen-containing atmosphere. By forming the insulator 282 by sputtering, oxygen can be added to the insulator 280. This allows the oxygen contained in the insulator 280 to be efficiently supplied to the oxide 230 or the oxide 231 through the oxide 230c or the oxide 231c, thereby reducing oxygen vacancies in the oxide 230 and the oxide 231 and improving the electrical characteristics and reliability of the transistors 11 and 12. However, the method for forming the insulator 282 is not limited to sputtering, and CVD, MBE, PLD, ALD, or the like may also be used as appropriate.

[0199] Moreover, the conductor 208 is provided over the insulator 282 so as to overlap at least a portion with the conductor 207. Here, the conductor 208 functions as the wiring CL. The conductor 208 may be a conductor that can be used for the conductor 209, etc. Note that the conductor 208 may be formed so as to be embedded in an opening provided in the insulator.

[0200] The insulator 283 is provided to cover the insulator 282 and the conductor 208. The insulator 283 functions as a barrier insulating film that prevents impurities such as water and hydrogen from diffusing from above into the insulator 280. The insulator 283 is preferably a nitride containing silicon, such as silicon nitride or silicon nitride oxide. For example, the insulator 283 may be a silicon nitride film formed by a sputtering method. By forming the insulator 283 by a sputtering method, a silicon nitride film that is high in density and less likely to form voids can be formed. Alternatively, the insulator 283 may be formed by stacking a silicon nitride film formed by a CVD method on a silicon nitride film formed by a sputtering method.

[0201] <Materials for semiconductor devices> The following describes constituent materials that can be used in semiconductor devices.

[0202] The insulators, conductors, and oxides described below can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0203] CVD methods can be classified into plasma-enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, and photo-CVD (Photo-CVD), which uses light. They can also be further divided into metal CVD (MCVD) and metal-organic CVD (MOCVD), depending on the source gas used.

[0204] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a plasma enhanced ALD method in which a plasma excited reactant is used, or the like can be used.

[0205] <<Substrate>> The substrate on which the transistors 11 and 12 are formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having a metal nitride and a metal oxide. Examples of other substrates include a substrate in which a conductor or semiconductor is provided on an insulating substrate, a substrate in which a conductor or insulator is provided on a semiconductor substrate, and a substrate in which a semiconductor or insulator is provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0206] <<Insulators>> Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0207] For example, as transistors become more miniaturized and highly integrated, thinner gate insulators can cause problems such as leakage current. Using a high-k material for the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the interlayer insulator can reduce the parasitic capacitance between wiring. Therefore, it is best to select materials based on the insulator's function.

[0208] Furthermore, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0209] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, and resin.

[0210] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0211] The insulator functioning as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated for.

[0212] <<Conductors>> The conductor is preferably a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal elements as a component, or an alloy combining the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0213] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0214] When an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing the metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0215] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, a conductive material containing the aforementioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0216] <<Metal oxides>> It is preferable to use a metal oxide (oxide semiconductor) that functions as a semiconductor as the oxide 230. Metal oxides that can be used as the oxide 230 according to the present invention will be described below.

[0217] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0218] Here, we consider the case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. The element M is one or more selected from aluminum, gallium, yttrium, and tin. Other elements that can be used for element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, there are cases where the element M can be a combination of multiple of the aforementioned elements.

[0219] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0220] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 5A. Fig. 5A is a diagram illustrating classification of crystal structures of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0221] As shown in FIG. 5A, oxide semiconductors are broadly classified into "amorphous," "crystalline," and "crystal." "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC) (excluding single crystal and polycrystal). "Crystalline" excludes single crystal, polycrystal, and completely amorphous. "Crystalline" includes single crystal and polycrystal.

[0222] The structure within the bold frame in Figure 5A is an intermediate state between "amorphous" and "crystal," and is a structure that belongs to a new boundary region (new crystalline phase). In other words, this structure can be described as a structure that is completely different from the energetically unstable "amorphous" or "crystal."

[0223] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 5B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in Figure 5B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 5B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 5B is 500 nm.

[0224] In Figure 5B, the horizontal axis is 2θ [deg.] and the vertical axis is intensity [au]. As shown in Figure 5B, a peak indicating clear crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ = 31° in the XRD spectrum of the CAAC-IGZO film. Note that, as shown in Figure 5B, the peak near 2θ = 31° is asymmetrical with respect to the angle at which the peak intensity is detected.

[0225] The crystalline structure of a film or substrate can be evaluated by the diffraction pattern (also called the nanobeam electron diffraction pattern) observed using nanobeam electron diffraction (NBED). Figure 5C shows the diffraction pattern of a CAAC-IGZO film. Figure 5C shows a diffraction pattern observed using NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 5C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed using a probe diameter of 1 nm.

[0226] As shown in Figure 5C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0227] <<Oxide semiconductor structure>> Note that oxide semiconductors may be classified differently from those shown in FIG. 5A when focusing on their crystal structures. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0228] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0229] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. Note that distortion refers to a location where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0230] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0231] In an In-M-Zn oxide (wherein M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and the element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. The In layer may contain M. The In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0232] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metallic elements constituting the CAAC-OS.

[0233] Furthermore, for example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0234] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the distortion may have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundaries are observed even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by metal atom substitution.

[0235] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in the on-state current and field-effect mobility of a transistor. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in the semiconductor layer of a transistor. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0236] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by impurities or defects, the CAAC-OS can be said to be an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even under high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0237] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystalline structures. The size of the microcrystalline structures is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore these microcrystalline structures are also called nanocrystalline structures. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystalline structures. Therefore, the entire film lacks orientation. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD system, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when an nc-OS film is subjected to electron diffraction (also known as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystalline structures (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0238] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0239] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, which relates to the material composition.

[0240] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range. Hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range, is also referred to as a mosaic or patch state.

[0241] Furthermore, CAC-OS has a mosaic structure in which the material is separated into first and second regions, and the first regions are distributed throughout the film (hereinafter also referred to as a cloud structure). That is, CAC-OS is a composite metal oxide having a structure in which the first and second regions are mixed.

[0242] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0243] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0244] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0245] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) confirms that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0246] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, thereby providing the CAC-OS with a switching function (the ability to turn on and off). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0247] Oxide semiconductors have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0248] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0249] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0250] An oxide semiconductor with a low carrier concentration is preferably used for a channel formation region of a transistor. For example, the carrier concentration of the channel formation region of an oxide semiconductor is preferably 1×10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm-3 It is more preferable that the carrier concentration of the oxide semiconductor film is less than 1000 . In order to reduce the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, an oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. An oxide semiconductor having a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0251] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0252] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0253] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0254] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0255] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentrations of silicon and carbon in the channel formation region of the oxide semiconductor and the silicon and carbon near the interface with the channel formation region of the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are calculated to be 2×10 18 atoms / cm 3Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0256] Furthermore, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect states may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0257] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of an oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 Do the following:

[0258] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration measured by SIMS in the channel formation region of the oxide semiconductor is 1×10 20 atoms / cm 3 Less than 5 x 10 19 atoms / cm 3 less than 1×10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0259] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0260] <<Other semiconductor materials>> The semiconductor material that can be used for the oxide 230 is not limited to the metal oxides described above. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may also be used for the oxide 230. For example, it is preferable to use a semiconductor of a simple element such as silicon, a compound semiconductor such as gallium arsenide, or a layered material that functions as a semiconductor (also called an atomic layer material or a two-dimensional material). In particular, it is preferable to use a layered material that functions as a semiconductor.

[0261] In this specification and the like, a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0262] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen. Chalcogen is a general term for elements in Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides also include transition metal chalcogenides and Group 13 chalcogenides.

[0263] It is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor as the oxide 230. Specific examples of transition metal chalcogenides that can be used as the oxide 230 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0264] <Modification of Semiconductor Device> An example of a semiconductor device according to one embodiment of the present invention will be described below with reference to FIGS. 6, 7A, 7B, 8A, and 8B.

[0265] FIG. 6 is a top view of the memory cell 10. FIG. 7A is a cross-sectional view of the portion indicated by the dashed line A1-A2-A3 in FIG. 6. Here, the cross-sectional view indicated by A1-A2 is a cross-sectional view in the channel length direction of the transistor 12, and the cross-sectional view indicated by A2-A3 is a cross-sectional view in the channel width direction of the transistor 11. FIG. 7B is a cross-sectional view of the portion indicated by the dashed line A4-A5-A6 in FIG. 6. Here, the cross-sectional view indicated by A4-A5 is a cross-sectional view in the channel width direction of the transistor 12, and the cross-sectional view indicated by A5-A6 is a cross-sectional view in the channel length direction of the transistor 11. Note that in the top view of FIG. 6, some elements (e.g., wiring CL) are omitted for clarity.

[0266] 6, 7A, and 7B, the same reference numerals are used to designate structures having the same functions as those constituting the semiconductor device shown in <Configuration Example of Semiconductor Device>. Note that, in this section as well, the explanation in <Configuration Example of Semiconductor Device> can be referred to for the components of the semiconductor device.

[0267] The semiconductor device shown in Figures 6, 7A, and 7B is a modified example of the semiconductor device shown in Figures 1B, 2A, 2B, 3A, and 3B. Memory cell 10 shown in Figures 6, 7A, and 7B differs from memory cell 10 shown in Figures 1B, 2A, 2B, 3A, and 3B in that a portion of conductor 260 is exposed from conductor 207.

[0268] Here, a portion of the conductor 260 is in contact with the insulator 282. Therefore, in the memory cell 10 shown in FIGS. 6, 7A, and 7B, the conductor 207 and the conductor 260 function as the lower electrode of the capacitor 13.

[0269] 6, 7A, and 7B, the insulator 282 is in contact with the insulator 280, the oxide 230c, the insulator 250, and the conductor 260 near the top of the channel formation region of the transistor 11.

[0270] With this structure, a barrier insulating film against impurities such as water and hydrogen can be provided near the top of the channel formation region of the transistor 11, thereby more effectively reducing the diffusion of the impurities into the oxide 230 through the oxide 230c, the insulator 250, or the like. Furthermore, by forming the insulator 282 by a sputtering method, oxygen can be added to a region of the insulator 280 closer to the channel formation region of the transistor 11. This allows oxygen contained in the insulator 280 to be more efficiently supplied to the oxide 230 through the oxide 230c or the insulator 250, thereby reducing oxygen vacancies in the oxide 230 and improving the electrical characteristics and reliability of the transistor 11.

[0271] 1A and the like show an example in which the wirings BGL1 and BGL2 extend in the y direction, but the semiconductor device according to the present invention is not limited to this. For example, as shown in FIG. 8A, a configuration may be adopted in which the transistors 11 and 12 do not have back gates. Furthermore, for example, as shown in FIG. 8B, a configuration may be adopted in which the wirings BGL1 and BGL2 extend in the x direction.

[0272] 1A and other figures show an example in which the wiring CL that applies a read potential when reading data from the memory cell 10 is connected to the upper electrode of the capacitor 13, but the semiconductor device according to the present invention is not limited to this. For example, the wiring CL may be connected to the back gate electrode of the transistor 11. In this case, a low power supply potential VSS may be applied to the wiring connected to the upper electrode of the capacitor 13. That is, the conductor 205 may be the wiring CL that applies a read potential when reading data from the memory cell 10, and the conductor 208 may be the wiring to which the low power supply potential VSS is applied.

[0273] According to one embodiment of the present invention, a semiconductor device with a small occupation area can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device which enables high integration can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with a large storage capacity can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device which can be manufactured at low cost can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high reliability can be provided. Alternatively, according to one embodiment of the present invention, a novel semiconductor device can be provided.

[0274] The structures, methods, and the like described in this embodiment can be used in appropriate combination with other structures, methods, and the like described in this embodiment or other embodiments.

[0275] (Embodiment 2) In this embodiment, a configuration example of a semiconductor device 500 including the memory cell 10 shown in the previous embodiment will be described.

[0276] FIG. 9A is a block diagram illustrating a configuration example of a semiconductor device 500 according to one embodiment of the present invention. The semiconductor device 500 illustrated in FIG. 9A includes a driver circuit 510 and a memory cell array 520. The memory cell array 520 is a NAND memory cell array including a plurality of memory cell strings 20. Each memory cell string 20 includes a plurality of memory cells 10. FIG. 9A illustrates an example in which the memory cell array 520 includes n memory cell strings 20[1] to 20[n] (n is an integer greater than or equal to 2). However, the present invention is not limited thereto. For example, the memory cell array 520 may include a plurality of blocks, each of which includes n memory cell strings 20.

[0277] The drive circuit 510 includes a PSW 541 (power switch), a PSW 542, and a peripheral circuit 515. The peripheral circuit 515 includes a peripheral circuit 511, a control circuit 512, and a voltage generation circuit 528.

[0278] In the semiconductor device 500, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0279] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 512.

[0280] The control circuit 512 is a logic circuit having a function of controlling the overall operation of the semiconductor device 500. For example, the control circuit 512 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 500. Alternatively, the control circuit 512 generates a control signal for the peripheral circuit 511 so that this operation mode is executed.

[0281] The voltage generating circuit 528 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 528. For example, when an H-level signal is applied to the signal WAKE, the signal CLK is input to the voltage generating circuit 528, and the voltage generating circuit 528 generates a negative voltage.

[0282] The peripheral circuit 511 is a circuit for writing and reading data to and from the memory cells 10. The peripheral circuit 511 includes a row decoder 521, a column decoder 522, a row driver 523, a column driver 524, an input circuit 525, an output circuit 526, and a sense amplifier 527.

[0283] The row decoder 521 and the column decoder 522 have the function of decoding the signal ADDR. The row decoder 521 is a circuit for specifying a row to be accessed, and the column decoder 522 is a circuit for specifying a column to be accessed. The row driver 523 has the function of selecting the wiring WL specified by the row decoder 521. The column driver 524 has the function of writing data to the memory cell 10, reading data from the memory cell 10, and retaining the read data.

[0284] The input circuit 525 has a function of holding a signal WDA. The data held by the input circuit 525 is output to the column driver 524. The output data of the input circuit 525 is data (Din) to be written to the memory cell 10. The data (Dout) read from the memory cell 10 by the column driver 524 is output to the output circuit 526. The output circuit 526 has a function of holding Dout. In addition, the output circuit 526 has a function of outputting Dout to the outside of the semiconductor device 500. The data output from the output circuit 526 is a signal RDA.

[0285] PSW541 is the V to the peripheral circuit 515 DD The PSW 542 has the function of controlling the supply of V to the row driver 523. HM Here, the high power supply voltage of the semiconductor device 500 is V DD and the low power supply voltage is GND (ground potential). HM is the high supply voltage used to drive the word line high, and V DD 9A, in the peripheral circuit 515, V DD Although the number of power domains to which power is supplied is set to one, it is also possible to set multiple power domains. In this case, a power switch should be provided for each power domain.

[0286] The drive circuit 510 and the memory cell array 520 may be provided on the same plane. Alternatively, as shown in FIG. 9B, the drive circuit 510 and the memory cell array 520 may be provided overlapping each other. By providing the drive circuit 510 and the memory cell array 520 overlapping each other, the signal propagation distance can be shortened. Furthermore, the semiconductor device 500 can be made smaller.

[0287] FIG. 10 shows a circuit diagram illustrating an example of the arrangement of memory cells 10 in a memory cell array 520. The memory cell array 520 has n memory cell strings 20[1] to 20[n] extending in the x direction. Each memory cell string 20 has m (m is an integer equal to or greater than 2) memory cells 10 arranged in the x direction, a transistor 14, and a transistor 15. Thus, in the memory cell array 520, m×n memory cells 10 are arranged in a matrix of n rows and m columns. Furthermore, n transistors 14[1] to 14[n] and n transistors 15[1] to 15[n] are arranged in the y direction. Note that the circuit configuration of each memory cell 10 is similar to the configuration shown in FIG. 1A, and the wiring connections and the like are also similar, so the description of the previous embodiment can be referred to.

[0288] In each memory cell string 20, the sources and drains of multiple transistors 11 are connected in series, and the sources and drains of multiple transistors 12 are also connected in series. At one end of each memory cell string 20, one of the source or drain of transistor 11 is electrically connected to one of the source or drain of transistor 14. At the other end of each memory cell string 20, the other of the source or drain of transistor 11 is electrically connected to one of the source or drain of transistor 15.

[0289] 10, the memory cell 10 in the first row and first column is indicated as memory cell 10[1,1], the memory cell 10 in the nth row and mth column is indicated as memory cell 10[n,m], and the memory cell 10 in the jth row and ith column (j is an integer between 1 and n, and i is an integer between 1 and m) is indicated as memory cell 10[j,i].

[0290] The rows and columns extend in directions perpendicular to each other. In this embodiment, the x direction is referred to as the "rows" and the y direction is referred to as the "columns," but the x direction may also be referred to as the "columns" and the y direction as the "rows."

[0291] The memory cell array 520 also includes m wirings CL[1] to CL[m] extending in the y direction, m wirings WL[1] to WL[m] extending in the y direction, m wirings BGL1[1] to BGL1[m] extending in the y direction, m wirings BGL2[1] to BGL2[m] extending in the y direction, and two wirings SEL[1] and SEL[2] extending in the y direction. Here, the wiring SEL[1] is electrically connected to the gates of transistors 14[1] to 14[n], and the wiring SEL[2] is electrically connected to the gates of transistors 15[1] to 15[n].

[0292] The memory cell array 520 also includes n wirings RBL[1] to RBL[n], n wirings SL[1] to SL[n], and n wirings WBL[1] to WBL[n]. In each memory cell string 20, the wiring WBL is electrically connected to the transistor 12 at one end, the wiring RBL is electrically connected to the transistor 14 at one end, and the wiring SL is electrically connected to the transistor 15 at the other end.

[0293] For example, in the memory cell string 20[1], the wiring RBL[1] is electrically connected to one of the source and drain of the transistor 11 in the memory cell 10[1,1] via the transistor 14[1]. The wiring SL[1] is electrically connected to the other of the source and drain of the transistor 11 in the memory cell 10[1,m] via the transistor 15[1]. The wiring WBL[1] is electrically connected to one of the source and drain of the transistor 12 in the memory cell 10[1,1].

[0294] FIG. 11 shows a top view of the memory cell array 520 corresponding to the circuit diagram of FIG. 10. Note that in the top view of FIG. 11, some elements are omitted for clarity. Also, for clarity, some elements such as the conductor 207 are shown with solid lines instead of hidden lines. Here, the structure of each memory cell 10 is similar to the structures shown in FIGS. 1B, 2A, 2B, 3A, 3B, etc., and the description of the previous embodiments can be referred to.

[0295] 11 , the memory cell array 520 extends in the y direction and includes m conductors 208[1] to 208[m] functioning as wirings CL, m conductors 209[1] to 209[m] functioning as wirings WL, m conductors 205[1] to 205[m] functioning as wirings BGL1, m conductors 206[1] to 206[m] functioning as wirings BGL2, a conductor 210[1] functioning as wiring SEL[1], and a conductor 210[2] functioning as wiring SEL[2]. The conductors 210 functioning as wirings SEL[1] and SEL[2] may be formed using the same conductive material as the conductor 209.

[0296] 11, the memory cell array 520 includes n oxides 230b[1] to 230b[n] and n oxides 231b[1] to 231b[n] extending in the x-direction. Each memory cell string 20 includes one oxide 230b and one oxide 231b. A plug electrically connected to the wiring RBL is provided at one end of the oxide 230b, and a plug electrically connected to the wiring SL is provided at the other end of the oxide 230b. A plug electrically connected to the wiring WBL is provided at one end of the oxide 231b. Although not shown, the oxides 230a, 231a, 243, 245, conductor 242, and conductor 244 are also appropriately extended and arranged, similar to the oxides 230b and 231b.

[0297] In the oxide 230b, the transistor 11 is formed in a portion overlapping with the conductor 208. In addition, in the oxide 231b, the transistor 12 is formed in a portion overlapping with the conductor 209, the transistor 14 is formed in a portion overlapping with the conductor 210[1], and the transistor 15 is formed in a portion overlapping with the conductor 210[2]. Here, the transistors 14 and 15 may have the same structure as the transistor 11. However, the top surface of the top gate of the transistor 14 is in contact with the conductor 210[1], and the top surface of the top gate of the transistor 15 is in contact with the conductor 210[2].

[0298] 3A, 3B, etc., memory cell array 520 has insulator 212 on a substrate (not shown), insulator 214 on insulator 212, insulator 216 on insulator 214, insulator 222 on insulator 216, insulator 224 on insulator 222, insulator 275 on insulator 224, insulator 280 on insulator 275, insulator 282 on insulator 280, and insulator 283 on insulator 282. Also, m conductors 205 and m conductors 206 are arranged in the same layer as insulator 216, n oxides 230b and n oxides 231b, etc. are arranged on insulator 224, m conductors 209 are arranged on insulator 280, and m conductors 208 are arranged on insulator 282. In addition, in each memory cell 10, transistors 11 and 12 are provided in a layer between insulator 214 and insulator 282, capacitor 13 is provided on insulator 280, and conductor 240 is provided connecting transistor 11 and transistor 12.

[0299] For example, the memory cell 10[1,1] and the memory cell 10[1,2] constituting the memory cell array 520 also have the structures shown in Figures 3A and 3B, respectively. However, the transistor 11 of the memory cell 10[1,2] and the transistor 11 of the memory cell 10[1,2] are both formed on the oxide 230b[1]. Also, the transistor 12 of the memory cell 10[1,2] and the transistor 12 of the memory cell 10[1,2] are both formed on the oxide 231b[1].

[0300] 11, in a NAND-type memory cell array 520, it is not necessary to form contact plugs connected to the wiring WBL, wiring RBL, etc. in each memory cell 10. Therefore, it is not necessary to provide space for forming extra contact holes in the memory cell 10. Therefore, by designing the shape of the memory cell 10 based on a rectangle surrounded by the oxide 230b, the oxide 231b, the conductor 208 (wiring CL), and the conductor 209 (wiring WL), it is possible to minimize the area occupied by the memory cell 10.

[0301] Here, it is preferable to design the layout of oxide 230b, oxide 231b, conductor 208, and conductor 209 so that the area of ​​memory cell 10 is as small as possible, based on the parasitic capacitance between wirings, the minimum processing dimensions, etc. This also limits the area of ​​memory cell 10 occupied by conductor 208, which functions as the upper electrode of capacitance element 13, i.e., the maximum area that capacitance element 13 can occupy. For this reason, it is preferable to make the area that conductor 207 overlaps with designed conductor 208 as large as possible.

[0302] In the memory cell 10 described in this embodiment and the like, the conductor 207 functioning as the node FN is arranged to overlap with the oxide 230b and the oxide 231b. This allows the overlapping area of ​​the conductor 208 and the conductor 207 in the memory cell 10 to be expanded in the y direction.

[0303] By adopting such a configuration, the capacitance of the capacitive element 13 can be increased without increasing the area of ​​the limited memory cell 10. Therefore, the area occupied by the memory cell 10 can be reduced. This allows for a high integration of the semiconductor device, and a semiconductor device with a large memory capacity can be provided. Furthermore, a semiconductor device with a low manufacturing cost per memory capacity can be provided.

[0304] 12A and 12B, an example of a data write operation and a data read operation of the memory cell array 520 will be described. Below, the operation will be described using the memory cell string 20[1] as a model when m=4.

[0305] First, an example of writing data to the memory cell string 20[1] in the periods T1 to T4 will be described with reference to the timing chart shown in FIG. WBL[1] [V], potential V of wiring WL[4] WL[4] [V], potential V of wiring WL[3] WL[3] [V], potential V of wiring WL[2] WL[2][V], potential V of wiring WL[1] WL[1] Note that in the periods T1 to T4, the potentials of the wirings RBL[1], SL[1], CL[1] to CL[4], BGL1[1] to BGL1[4], and BGL2[1] to BGL2[4] are 0 V.

[0306] During the period T1, data 0 is written to the memory cell 10[1,4]. WBL[1] is the potential of data 0 (for example, 0V), and the potential V WL[4] to potential V WL[1] is set to a potential (for example, 4 V) at which the transistors 11 in the memory cells 10[1,4] to 10[1,1] are turned on. This causes electrical continuity between the wiring WBL[1] and the node FN of the memory cell 10[1,4], and a potential of data 0 is applied to the node FN. When the period T1 is switched to the period T2, the potential V WL[4] is set to a potential (for example, −4 V) that turns off the transistor 11. This puts the node FN of the memory cell 10[1,4] into a floating state, and the potential corresponding to the data 0 applied to the node FN can be held.

[0307] During the period T2, data 1 is written to the memory cell 10[1,3]. WBL[1] is the potential of data 1 (for example, 2V), and the potential V WL[3] to potential V WL[1] is set to a potential (for example, 4 V) that turns on the transistors 11 in the memory cells 10[1,3] to 10[1,1]. This brings the wiring WBL[1] and the node FN of the memory cell 10[1,3] into conduction, and the potential of data 1 is applied to the node FN. At this time, the transistor 11 of the memory cell 10[1,4] is in an off state, so that the data 0 written to the memory cell 10[1,4] in the period T1 is retained. When switching from the period T2 to the period T3, the potential V WL[3] is set to a potential (for example, −4 V) that turns off the transistor 11. This causes the node FN of the memory cell 10[1,3] to be in a floating state, and the potential corresponding to the data 1 applied to the node FN can be held.

[0308] Thereafter, during period T3, data 0 is written to memory cell 10[1,2] in the same manner as during period T1, and during period T4, data 1 is written to memory cell 10[1,1] in the same manner as during period T2.

[0309] Next, an example of reading data from the memory cell string 20[1], to which data is written during the periods T1 to T4, during the periods T5 to T8 will be described with reference to the timing chart shown in FIG. CL[4] [V], potential V of wiring CL[3] CL[3] [V], potential V of wiring CL[2] CL[2] [V], potential V of wiring CL[1] CL[1] [V], current value I of wiring RBL[1] RBL[1] In the periods T5 to T8, the potentials of the wirings WL[1] to WL[4] are −4 V, the potential of the wiring RBL[1] is 1.2 V, and the potentials of the wiring SL[1], the wiring WBL[1], the wirings BGL1[1] to BGL1[4], and the wirings BGL2[1] to BGL2[4] are 0 V. The transistors 14[1] and 15[1] are on.

[0310] During the period T5, data 0 is read from the memory cell 10[1,4]. CL[4] is the readout potential (for example, 0 V), and the potential V CL[3] to potential V CL[1] is set to a potential (for example, 4 V) that turns on the transistors 11 of the memory cells 10[1,3] to 10[1,1] regardless of the data stored therein. As a result, the conduction state of the wiring RBL[1] and the wiring SL[1] is determined by the conduction state of the transistor 11 of the memory cell 10[1,4]. Here, when a read potential is applied to the wiring CL, the transistor 11 of the memory cell 10 is turned off if data 0 is stored therein, and turned on if data 1 is stored therein. As shown in FIG. 12B, I RBL[1]is 0 μA, and the wiring RBL[1] and the wiring SL[1] are in a non-conductive state, so it can be read that data 0 is held in the memory cell 10[1,4].

[0311] In the period T6, the data 1 is read from the memory cell 10[1,3]. CL[3] is the readout potential (for example, 0 V), and the potential V CL[4] , potential V CL[2] , and potential V CL[1] is set to a potential (for example, 4 V) that turns on the transistors 11 of the memory cell 10[1,4], memory cell 10[1,2], and memory cell 10[1,1] regardless of the data stored therein. As a result, the conduction state of the wiring RBL[1] and the wiring SL[1] is determined by the conduction state of the transistor 11 of the memory cell 10[1,3]. As shown in FIG. 12B, I RBL[1] has a positive value, and the wiring RBL[1] and the wiring SL[1] are in a conductive state, so it can be read that data 1 is held in the memory cell 10[1,3].

[0312] Thereafter, during period T7, data 0 is read from memory cell 10[1,2] in the same manner as during period T5, and during period T8, data 1 is read from memory cell 10[1,1] in the same manner as during period T6.

[0313] In this manner, data can be written to and read from the memory cell string 20[1]. Note that, although writing and reading are performed for one memory cell string 20 in the above, data can be written to and read from multiple memory cell strings 20 simultaneously in a similar manner. For example, in the memory cell array 520 shown in FIG. 10, data can be written to and read from the memory cell strings 20[1] to 20[n] simultaneously.

[0314] Note that the above-described data write operation and data read operation of the memory cell array 520 are merely examples, and the present invention is not limited thereto. For example, as described in the previous embodiment, during a data read operation, the conductor 205 may function as a wiring CL that applies a read potential, and the conductor 208 may function as a wiring to which a low power supply potential VSS is applied.

[0315] Furthermore, the layout of the memory cell array 520 described above is merely an example, and the present invention is not limited to this. For example, the wiring WBL may be provided not only at one end of the memory cell string 20 but also at the other end, that is, two wirings WBL may be connected to one memory cell string 20. With this configuration, data can be written simultaneously from two directions of the memory cell string 20 in the above data write operation, thereby improving the data write speed.

[0316] For example, the wirings BGL1 and BGL2 may not be provided, or the wirings BGL1 and BGL2 may extend in the x-direction. Also, the transistors 14 and 15 may be provided with back gates and wirings BGL1.

[0317] Although the memory cell array 520 is a NAND type memory cell array, the present invention is not limited to this. For example, the oxide 230b and the oxide 231b may be patterned in an island shape in each memory cell 10 to form a NOR type memory cell array.

[0318] The structures, methods, and the like described in this embodiment can be used in appropriate combination with other structures, methods, and the like described in this embodiment or other embodiments.

[0319] (Embodiment 3) In this embodiment, an application example of a memory device according to one embodiment of the present invention will be described.

[0320] Generally, various memory devices are used in semiconductor devices such as computers depending on the application. Figure 13 shows various memory devices by layer. The higher the layer, the faster the access speed required, while the lower the layer, the larger the memory capacity and recording density required. Figure 13 shows, from the top layer, memory integrated as a register in a processing unit such as a CPU, SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and 3D NAND memory.

[0321] The memory embedded as a register in a CPU or other processing unit is frequently accessed by the processing unit because it is used to temporarily store the results of calculations. Therefore, a faster operating speed is required than a larger memory capacity. Registers also have the function of storing setting information for the processing unit.

[0322] SRAM is used, for example, in caches. Caches have the function of storing a copy of the information stored in main memory. By storing copies of frequently used data in the cache, access speed to the data can be increased.

[0323] DRAM is used, for example, as main memory. Main memory has the function of storing programs and data read from storage. The recording density of DRAM is approximately 0.1 to 0.3 Gbit / mm 2 is.

[0324] 3D NAND memory is used, for example, in storage. Storage has the function of storing data that requires long-term storage and various programs used by processing units. Therefore, storage requires a large memory capacity and high recording density rather than an operating speed. The recording density of memory devices used in storage is approximately 0.6 to 6.0 Gbit / mm 2 is.

[0325] A storage device according to one embodiment of the present invention has a large storage capacity, a high operating speed, and is capable of long-term data retention. The storage device according to one embodiment of the present invention can be suitably used as a storage device located in a boundary area 901 that includes both a tier where a cache is located and a tier where a main memory is located. The storage device according to one embodiment of the present invention can also be suitably used as a storage device located in a boundary area 902 that includes both a tier where a main memory is located and a tier where a storage is located.

[0326] A storage device according to one embodiment of the present invention can be applied to, for example, storage devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital still cameras, video cameras, recording / playback devices, navigation systems, game consoles, etc.). It can also be used in image sensors, IoT (Internet of Things), healthcare, and the like. Note that the term "computer" as used herein refers to a tablet computer, a notebook computer, a desktop computer, and a large-scale computer such as a server system.

[0327] Furthermore, a storage device according to an embodiment of the present invention is applicable to various removable storage devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid state drives). Figures 14A to 14E show schematic diagrams of several configuration examples of removable storage devices. For example, a storage device according to an embodiment of the present invention is processed into a packaged memory chip and used in various storage devices and removable memories.

[0328] 14A is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the board 1104. The semiconductor device described in the above embodiment can be incorporated into the memory chip 1105 of the board 1104.

[0329] FIG. 14B is a schematic diagram of the appearance of an SD card, and FIG. 14C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. The capacity of the SD card 1110 can be increased by providing a memory chip 1114 on the back side of the substrate 1113. A wireless chip with a wireless communication function may also be provided on the substrate 1113. This enables data to be read from and written to the memory chip 1114 through wireless communication between a host device and the SD card 1110. The semiconductor device described in the above embodiment can be incorporated into the memory chip 1114 of the substrate 1113 or the like.

[0330] FIG. 14D is a schematic diagram of the appearance of an SSD, and FIG. 14E is a schematic diagram of the internal structure of the SSD. SSD 1150 has a housing 1151, a connector 1152, and a board 1153. Board 1153 is housed in housing 1151. For example, memory chip 1154, memory chip 1155, and controller chip 1156 are attached to board 1153. Memory chip 1155 is a work memory for controller chip 1156, and may be, for example, a DOSRAM chip. By providing memory chip 1154 on the back side of board 1153, the capacity of SSD 1150 can be increased. The semiconductor device described in the previous embodiment can be incorporated into memory chip 1154 of board 1153, etc.

[0331] The structures, methods, and the like described in this embodiment can be used in appropriate combination with other structures, methods, and the like described in this embodiment or other embodiments.

[0332] (Fourth embodiment) Specific examples of electronic devices including a semiconductor device according to one embodiment of the present invention are illustrated in FIGS.

[0333] <Electronic devices and systems> A semiconductor device according to one embodiment of the present invention can be incorporated into various electronic devices. Examples of such electronic devices include electronic devices with relatively large screens, such as televisions, monitors for desktop or notebook information terminals, digital signage, and large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, electronic book readers, mobile phones, portable game machines, personal digital assistants, and sound players. Furthermore, a semiconductor device according to one embodiment of the present invention can be used as a component of artificial intelligence. Artificial intelligence can be implemented in electronic devices using a semiconductor device according to one embodiment of the present invention.

[0334] An electronic device according to one embodiment of the present invention may include an antenna. By receiving a signal through the antenna, images, information, and the like can be displayed on a display portion. When the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0335] An electronic device according to one embodiment of the present invention may have a sensor (including a function for measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0336] An electronic device according to one embodiment of the present invention can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, or time, a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, etc.

[0337] [Information terminal] 15A shows a mobile phone (smartphone), which is one type of information terminal. The information terminal 5100 has a housing 5101 and a display unit 5102. As input interfaces, a touch panel is provided on the display unit 5102 and buttons are provided on the housing 5101.

[0338] The information terminal 5100 can execute applications using artificial intelligence using the semiconductor device of one embodiment of the present invention. Examples of applications using artificial intelligence include an application that recognizes a conversation and displays the conversation content on the display portion 5102, an application that recognizes characters, figures, or the like input by a user to a touch panel included in the display portion 5102 and displays the characters, figures, or the like on the display portion 5102, and an application that performs biometric authentication such as fingerprint or voiceprint authentication.

[0339] 15B illustrates a notebook information terminal 5200. The notebook information terminal 5200 includes a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203.

[0340] Like the information terminal 5100 described above, the notebook information terminal 5200 can execute applications using artificial intelligence using a semiconductor device according to one embodiment of the present invention. Examples of applications using artificial intelligence include design support software, text correction software, and automatic menu generation software. Furthermore, new artificial intelligence can be developed by using the notebook information terminal 5200.

[0341] 15A and 15B, a smartphone and a notebook type information terminal are used as examples of electronic devices, but information terminals other than smartphones and notebook type information terminals can also be used. Examples of information terminals other than smartphones and notebook type information terminals include PDAs (Personal Digital Assistants), desktop type information terminals, and workstations.

[0342] [Game consoles] FIG. 15C illustrates a portable game console 5300, which is an example of a game console. The portable game console 5300 includes a housing 5301, a housing 5302, a housing 5303, a display portion 5304, a connection portion 5305, operation keys 5306, and the like. The housings 5302 and 5303 can be detached from the housing 5301. By attaching the connection portion 5305 of the housing 5301 to another housing (not shown), the video displayed on the display portion 5304 can be output to another video device (not shown). In this case, the housings 5302 and 5303 can each function as an operation portion. This allows multiple players to play a game simultaneously. A semiconductor device according to one embodiment of the present invention can be incorporated into chips or the like provided on substrates of the housings 5301, 5302, and 5303.

[0343] 15D shows an example of a game machine, a stationary game machine 5400. A controller 5402 is connected to the stationary game machine 5400 wirelessly or via a wire.

[0344] A game machine with low power consumption can be realized by applying a GPU or a chip of one embodiment of the present invention to a game machine such as a portable game machine 5300 or a stationary game machine 5400. Furthermore, low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0345] Furthermore, the portable game console 5300 can have artificial intelligence by using a semiconductor device according to one embodiment of the present invention.

[0346] Originally, the expression of the progress of a game, the behavior of creatures appearing in the game, and phenomena occurring in the game are determined by the program of the game, but by applying artificial intelligence to the portable game console 5300, it becomes possible to express things that are not limited to the game program. For example, it becomes possible to express things such as changes in the questions asked by the player, the progress of the game, the time, and the behavior of people appearing in the game.

[0347] Furthermore, when playing a game requiring multiple players on the portable game console 5300, the game players can be personified using artificial intelligence, so that the game can be played by one person by making the opponent a game player based on artificial intelligence.

[0348] 15C and 15D illustrate a portable game machine and a stationary game machine as examples of game machines, but game machines to which the semiconductor device according to an embodiment of the present invention can be applied are not limited to these. Examples of game machines to which the semiconductor device according to an embodiment of the present invention can be applied include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0349] [Mainframe Computer] A semiconductor device according to one embodiment of the present invention can be applied to a mainframe computer.

[0350] 15E is a diagram showing a supercomputer 5500, which is an example of a mainframe computer. FIG. 15F is a diagram showing a rack-mounted computer 5502 included in the supercomputer 5500.

[0351] The supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. The plurality of computers 5502 are stored in the rack 5501. The computer 5502 is provided with a plurality of boards 5504, and a semiconductor device according to one embodiment of the present invention can be mounted on the board.

[0352] The supercomputer 5500 is a large-scale computer mainly used for scientific and technological calculations. Scientific and technological calculations require high-speed processing of enormous amounts of calculations, resulting in high power consumption and large amounts of heat generated by the chip. By applying a semiconductor device according to one embodiment of the present invention to the supercomputer 5500, a supercomputer with low power consumption can be realized. Furthermore, low power consumption can reduce heat generation from circuits, thereby reducing the influence of heat on the circuits themselves, peripheral circuits, and modules.

[0353] 15E and 15F illustrate a supercomputer as an example of a mainframe computer, but the mainframe computer to which the semiconductor device according to an embodiment of the present invention is applied is not limited to this. Examples of the mainframe computer to which the semiconductor device according to an embodiment of the present invention is applied include a computer (server) that provides services, a mainframe computer (mainframe), etc.

[0354] [Moving object] A semiconductor device according to one embodiment of the present invention can be applied to automobiles, which are moving objects, and to the vicinity of a driver's seat of an automobile.

[0355] Fig. 15G is a diagram showing the area around the windshield in the interior of an automobile 5600, which is an example of a moving body. Fig. 15G shows display panel 5601, display panel 5602, and display panel 5603 attached to the dashboard, as well as display panel 5604 attached to a pillar.

[0356] The display panels 5601 to 5603 can provide various information by displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear state, air conditioning settings, etc. The display items and layouts displayed on the display panels can be changed as appropriate to suit the user's preferences, thereby improving the design. The display panels 5601 to 5603 can also be used as lighting devices.

[0357] The display panel 5604 can complement the view (blind spot) blocked by the pillar by displaying an image from an imaging device (not shown) installed in the vehicle. That is, by displaying an image from an imaging device installed outside the vehicle, blind spots can be complemented and safety can be improved. Furthermore, by displaying an image that complements the invisible part, safety can be confirmed more naturally and without discomfort. The display panel 5604 can also be used as a lighting device.

[0358] Since the semiconductor device according to one embodiment of the present invention can be used as a component of artificial intelligence, the chip can be used, for example, in an automatic driving system for automobiles. The chip can also be used in a system that provides road guidance, hazard prediction, etc. The display panels 5601 to 5604 may be configured to display information such as road guidance and hazard prediction.

[0359] Although an automobile is described above as an example of a moving object, the moving object is not limited to an automobile. For example, moving objects include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets). A semiconductor device according to one embodiment of the present invention can be applied to these moving objects to provide them with a system using artificial intelligence.

[0360] [electric appliances] 15H shows an example of an electric appliance, an electric refrigerator-freezer 5700. The electric refrigerator-freezer 5700 includes a housing 5701, a refrigerator door 5702, a freezer door 5703, and the like.

[0361] The electric refrigerator-freezer 5700 can have artificial intelligence by using the semiconductor device according to one embodiment of the present invention in the electric refrigerator-freezer 5700. By using artificial intelligence, the electric refrigerator-freezer 5700 can have a function of automatically generating a menu based on ingredients stored in the electric refrigerator-freezer 5700 and their expiration dates, a function of automatically adjusting the temperature to match the ingredients stored in the electric refrigerator-freezer 5700, and the like.

[0362] Although electric refrigerator-freezers have been described as an example of electrical appliances, other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0363] The electronic devices, functions of the electronic devices, application examples of artificial intelligence, and effects thereof described in this embodiment can be appropriately combined with descriptions of other electronic devices.

[0364] The structures, methods, and the like described in this embodiment can be used in appropriate combination with other structures, methods, and the like described in this embodiment or other embodiments. [Explanation of symbols]

[0365] BGL1: wiring, BGL2: wiring, CL: wiring, RBL: wiring, SL: wiring, SEL: wiring, T1: period, T2: period, T3: period, T4: period, T5: period, T6: period, T7: period, T8: period, WBL: wiring, WL: wiring, 10: memory cell, 11: transistor, 12: transistor, 13: capacitance element, 14: transistor, 15: transistor, 20: memory cell string, 205: conductor, 205a: conductor, 205b: conductor, 205c: conductor, 206: conductor, 206a: conductor, 206b: conductor, 206c: conductor, 207: conductor conductor, 208: conductor, 209: conductor, 210: conductor, 212: insulator, 214: insulator, 216: insulator, 222: insulator, 224: insulator, 230: oxide, 230a: oxide, 230b: oxide, 230c: oxide, 231: oxide, 231a: oxide, 231b: oxide, 231c: oxide, 232a: region, 232b: region, 232c: region, 240: conductor, 241: insulator, 242: conductor, 242a: conductor, 242b: conductor, 243: oxide, 243a: oxide, 243b: oxide, 244: conductor, 244a: conductor, 244 b: conductor, 245: oxide, 245a: oxide, 245b: oxide, 250: insulator, 251: insulator, 260: conductor, 260a: conductor, 260b: conductor, 261: conductor, 261a: conductor, 261b: conductor, 275: insulator, 280: insulator, 282: insulator, 283: insulator, 500: semiconductor device, 510: driver circuit, 511: peripheral circuit, 512: control circuit, 515: peripheral circuit, 520: memory cell array, 521: row decoder, 522: column decoder, 523: row driver, 524: column driver, 525: input circuit, 526: output power circuit, 527: sense amplifier, 528: voltage generation circuit, 541: PSW, 542: PSW, 901: boundary area, 902: boundary area, 1100: USB memory, 1101: housing, 1102: cap, 1103: USB connector, 1104: board, 1105: memory chip, 1106: controller chip, 1110: SD card, 1111: housing, 1112: connector, 1113: board, 1114: memory chip, 1115: controller chip, 1150: SSD, 1151: housing, 1152: connector, 1153: board, 1154: memory chip,1155: memory chip, 1156: controller chip, 5100: information terminal, 5101: housing, 5102: display unit, 5200: notebook information terminal, 5201: main body, 5202: display unit, 5203: keyboard, 5300: portable game console, 5301: housing, 5302: housing, 5303: housing, 5304: display unit, 5305: connection unit, 5306: operation keys, 5400: type game machine, 5402: controller, 5500: supercomputer, 5501: rack, 5502: calculator, 5504: circuit board, 5600: automobile, 5601: display panel, 5602: display panel, 5603: display panel, 5604: display panel, 5700: electric refrigerator-freezer, 5701: housing, 5702: refrigerator compartment door, 5703: freezer compartment door,

Claims

1. a first to fourth transistors, a first oxide semiconductor, a second oxide semiconductor, a first capacitor, a second capacitor, a first insulator, a second insulator, a first conductor, and a second conductor; the first transistor and the third transistor are formed in the first oxide semiconductor; the second transistor and the fourth transistor are formed in the second oxide semiconductor; the first transistor has a first gate and a first gate insulator; the second transistor has a second gate and a second gate insulator; the third transistor has a third gate and a third gate insulator; the fourth transistor has a fourth gate and a fourth gate insulator; the first capacitive element has a third conductor and a fourth conductor; the second capacitive element has a fifth conductor and a sixth conductor; the first insulator is disposed on the first oxide semiconductor and on the second oxide semiconductor; the first insulator has a first opening and a second opening reaching the first oxide semiconductor, a third opening and a fourth opening reaching the second oxide semiconductor, a fifth opening reaching one of a source or a drain of the second transistor, and a sixth opening reaching one of a source or a drain of the fourth transistor; the first gate insulator and the first gate are disposed in the first opening; the third gate insulator and the third gate are disposed in the second opening; the second gate insulator and the second gate are disposed in the third opening; the fourth gate insulator and the fourth gate are disposed in the fourth opening; the first conductor is disposed in the fifth opening; the second conductor is disposed in the sixth opening; the third conductor is disposed in contact with an upper surface of the first conductor and an upper surface of the first gate; the fifth conductor is disposed in contact with an upper surface of the second conductor and an upper surface of the third gate; the second insulator is disposed on the third conductor, on the fifth conductor and on the first insulator; the fourth conductor is disposed to cover the third conductor with the second insulator interposed therebetween; The sixth conductor is disposed to cover the fifth conductor with the second insulator interposed therebetween.

2. In claim 1, each of the first oxide semiconductor and the second oxide semiconductor contains indium, an element M (M is one or more selected from the group consisting of gallium, aluminum, yttrium, and tin), and zinc.

3. In claim 1, each of the first oxide semiconductor and the second oxide semiconductor contains indium oxide.

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