METHOD FOR MANUFACTURING A SEMICONDUCTOR BODY AND SEMICONDUCTOR DEVICE - Patent application

Abstract

The present invention relates to a method for manufacturing a semiconductor body, in which an auxiliary support is provided. A stack is formed on the auxiliary support, the stack having a first layer including a doped semiconductor material and a second layer including an undoped semiconductor material formed thereon. The first layer of the stack is electrochemically porosified, with a porosity of at least 20% by volume. Mesa structures are then formed in the porosified first layer and in the second layer, resulting in a functional stack having at least one planar third layer formed on the second layer provided with the mesa structures. The at least one planar third layer has a lattice constant different from that of the second layer.

Description

[Technical field]

[0001] This application claims priority to German Patent Application No. 102020128680.5, filed October 30, 2020, the contents of which are incorporated herein by reference.

[0002] The invention relates to a method for manufacturing a semiconductor body, in particular an optoelectronic module.The invention also relates to a semiconductor device, in particular an optoelectronic module.

[0003] In the manufacture of semiconductor modules, different or at least modified material systems are often used to form the required functional parts. In this case, these material systems may each have different lattice constants, i.e. the atoms in the lattice structure have different distances in the respective material systems. Besides the lattice spacing, the electrical properties also change. A known representation showing the relationship between the band gap and the lattice constants can be found at the address https: / / de.wikipedia.org / wiki / III-V-Verbindungshalbleiter# / media / Datei:III-V-Halbleiter.png. There, the band gaps are shown in terms of the lattice constants of the wurtzite and zinc-blende structures. The lines between the elements represent ternary connections. Wurtzite crystals have two lattice constants a and c, zinc-blende has only one lattice constant.

[0004] In optoelectronic modules, for example, the growth of InGaN quantum wells emitting at wavelengths above 600 nm is difficult due to the increase in indium content (more than 30%). The reason is that the lattice spacing increases with increasing In proportion. Such InGaN-rich alloys have a large lattice.

[0005] Due to the different lattice constants, deposition of such materials on a GaN buffer layer typically results in a degree of mismatch with the underlying GaN layer, which leads to high defect densities and / or phase separation due to the different In concentrations.

[0006] Similar problems arise in the case of InGaAlP modules, which have better temperature stability and / or better efficiency. In the case of this material system, the growth of carrier-limiting barriers on both sides of the multiple quantum wells for light formation, i.e. direct bandgap materials with a larger bandgap, is promoted. However, such materials have a significant lattice mismatch with the GaAs substrate and cannot be grown with good crystalline quality.

[0007] Thus, in general, growth of certain compound semiconductors with large lattice constant mismatches to underlying layers is difficult when high crystal quality is required.

[0008] To avoid or at least reduce these problems, for example, very thick and gradually adapted buffers, defect-induced lattice relaxation, small-scale patterning and masking with dielectric masks are used. However, for example, thick layers or gradually adapted buffer layers are also disadvantageous in some applications in terms of their electrical properties. Furthermore, the manufacturing costs and the effort of controlling the manufacturing conditions increase.

[0009] Therefore, there is a need to provide a method for manufacturing a semiconductor module that can reduce the above-mentioned problems.

[0010] Summary of the Invention In the following, a process is presented in which the holding forces between the sapphire substrate and the layers that are part of the module are reduced, so that the different lattice constants resulting from the different material systems act less strongly. In this way, in particular the stresses can be reduced, which allows epitaxial growth even with less complete adaptation of the lattice constants. This is achieved by modifying the individual layers using an electrochemical dissolution process.

[0011] For this purpose, the inventors propose a method for producing a semiconductor body, in which in a first step an auxiliary support is provided. Subsequently, a first layer comprising a doped semiconductor material, in particular a III-V semiconductor material, and a second layer comprising an undoped semiconductor material on the first layer are deposited. In a next step, the first layer is electrochemically porosified, where the porosity is at least 20% by volume.

[0012] The inventors also propose, as an option, to form a mesa structure in the porous first layer and in the second layer. A functional stack is then formed on the second layer. To this end, the functional stack has at least one flat third layer formed on the second layer provided with the mesa structure, where the at least one flat third layer has a specific lattice constant different from that of the second layer. Similarly, the porosity may be between 50% and 90% by volume.

[0013] The porosification introduces intermediate or hollow spaces into the structure of the first layer. These hollow spaces allow stress compensation without an increased number of defects in the layers formed on the porosified layer. In other words, the porosification allows stress compensation based on different lattice constants so that lattice effects do not occur. Optionally, the use of additional mesa structures further amplifies this effect. In some material systems, the mesa structuring with porosification of the first layer is particularly suitable for compensating even larger differences in lattice constants.

[0014] In this context, the lattice constant is to be understood as the length of a unit cell in a defined material system. In this case, the material system is homogeneous and does not contain defects or lattice defects. Therefore, no stress occurs in the material system. The lattice constant is a characteristic quantity for each material system and is also called the specific lattice constant for a material system that does not produce stress. Different material systems can therefore have different specific lattice constants, as shown in the link above. Thus, when material systems with different lattice constants are integrated, stresses occur in the boundary region of these systems, i.e. the lattice constant changes. The change becomes smaller with increasing distance to the boundary region. Moreover, if the difference in the lattice constants is too large, defect locations or defects may occur. The proposed method and the embodiments according to the invention allow deliberate use of such effects.

[0015] In the following, a functional semiconductor stack or a functional semiconductor body that is structured so that it can assume an electrical function as a completed module is referred to as a stack. Here, the functional semiconductor stack can be individualized, with each individual element having the desired functionality. An example of a functional semiconductor stack is, for example, a stack having a region suitable for light emission. Another example is an npn junction region with a transistor function. A stack can also combine several functions with each other.

[0016] The auxiliary support is a support made of an inert material that is used as a basis for further processes, in particular for the epitaxial deposition of semiconductor materials. The material of the auxiliary support is for example sapphire (Al2O3), but can also be silicon nitride or other materials. It can be advantageous if the material is inert to the various etching processes used during the formation of the semiconductor module. In some cases, the auxiliary support remains in the module and becomes part of this module, in which case the auxiliary support is also referred to as the carrier substrate for short. In other cases, a release of the module manufactured on the auxiliary support is performed (as explained below).

[0017] Semiconductor materials are generally understood to be undoped compound semiconductor materials, unless otherwise specified. In this case, the expression "undoped" means that there is no dedicated, deliberate and purposeful doping with another element or material. Defects or impurities, which are always present in practice, are not included in doping within the meaning of this application. Compound semiconductor materials are combinations of two, three or more elements formed in a crystalline structure, which form a band structure and the resulting component has electrical semiconducting properties. Typical compound semiconductors are the so-called III-V compound semiconductors, which consist of one or more elements of group V and one or more elements of group III. Examples of compound semiconductor materials are GaAs, AlGaAs, GaN, AlGaN, InGaN, GaP, InGaP, AlGaP, AlInGaN, AlInGaP and others listed herein.

[0018] A doped semiconductor is a semiconductor material into which a dopant has been introduced. Depending on the desired doping in the III-V compound semiconductor, the dopant can be Si, Te, Se, Ge or Ge for n-type doping, e.g. Mg, Be or C for p-type doping. Other dopants are also described in this application. The dopants are introduced during the epitaxial deposition of the III-V compound semiconductor material, although the doping here can also be carried out later by various processes. The doping concentration is several orders of magnitude lower than the concentration of atoms in the starting or base material. For example, the concentration can be 1 * 10 17 Doping atoms / cm 3 ~5 * 10 21 Doping atoms / cm 3 is in the range.

[0019] Electrochemical decomposition or electrochemical etching is a process in which a semiconductor material is dissolved by voltage and current. In this way, a layer of semiconductor material can be peeled off or etched. However, such a process is not uniform, but rather non-uniform, for example due to dislocations or material defects. This can be exploited in appropriate parameter selection, for example in the selection of the applied voltage and the dopant concentration and concentration of the semiconductor material to be etched. Thus, for example, different speeds and also different porosities of the material to be etched can be achieved. The term electrochemical porosification is therefore to be understood as an electrochemical process in which material is selectively dissociated from the body leaving a porous or sponge-like structure. That is to say, the porosified semiconductor body or semiconductor layer forms a mesh-like structure similar to a sponge or bone, which has a small mass or a small material volume and at the same time has sufficient stability.

[0020] The layer can be subjected to a selective porosification process, in which a patterning mask is applied before the process. The patterning mask reduces or blocks the flow of current in the region of the layer due to so-called shading, so that no or only very little porosification occurs in the region where the mask is arranged. Correspondingly, a non-porosified semiconductor body does not exhibit a mesh-like or sponge-like structure, but it can still have various defects or lattice defects. Furthermore, in some embodiments, in the boundary region, a part of the region that is not per se porosified can exhibit a slight porosity, especially at the edge of such a region, which can have the effect that the so-called porosity (see below) decreases with increasing distance from the edge.

[0021] In the non-porous regions, during the electrochemical etching process, the electrolyte is difficult to penetrate or similarly prevented from penetrating below the shaded regions, so that no further etching channels are formed there or existing channels are not expanded by the electrolyte. As a result, the etching rate is significantly reduced below the shaded regions, so that the material in these regions is only slightly or not at all porosified.

[0022] The term porosity refers to the ratio of the material volume to the total volume of the layer. Here, a porosity in the range of 30% means that 30% of the original volume of material has been removed. A porosity of 90% means that 90% of the material has been dissolved by the electrochemical deposition process, leaving only 10% of the material remaining.

[0023] After the functional semiconductor stack is produced, in some aspects, the functional stack is peeled off from the first layer, optionally leaving the second layer on the functional stack. Alternatively, the functional stack may be peeled off from the auxiliary support, so that the porosified first layer remains on the functional semiconductor stack and can optionally be used as an output structure for electromagnetic radiation. In such an embodiment, the porosified first layer may be further processed. For example, a contact area may be deposited on the first layer.

[0024] In some aspects, a mesa structure is formed in a first step by depositing a patterning mask onto the second layer, followed by etching the second layer and the porosified first layer to form a recess, which in some embodiments is configured as a trench in the porosified first layer.

[0025] In some aspects, the mesa structures are formed after porosifying the first layer, although depending on the material system used, the mesa structures can also be formed prior to the electrochemical porosification step.

[0026] Another aspect relates to the configuration of the first layer. In some embodiments, the first layer is formed in partial steps, where after the first partial step, the layer formation is interrupted and a thin separation layer, in particular an undoped separation layer, is deposited. The epitaxial deposition of the first layer then proceeds. This divides the first layer into a region facing the support and a region facing away from the support. In some aspects, the doping concentration of the first layer in each region can be different in this case or a different material system can be used for the separation layer. By forming the first layer with different doping strengths and / or with a thin separation layer in each region, respectively different porosities can be obtained. In this way, the porosity can be adapted to the requirements for the growth of further layers, both for the entire wafer and locally.

[0027] Another embodiment relates to the manufacture of further structures in the first layer. In one embodiment, the step of forming the stack includes the step of forming non-porous regions. This is done by depositing a patterning mask on the second layer of the stack for the formation of the regions below that should not be structured, and then removing this patterning mask after the electrochemical porosity of the first layer. This leaves the regions of the first layer below the "shaded" regions, i.e. they are not porosified at all or are porosified to a very small extent. These regions now exhibit different mechanical and electrical properties. Thus, during the formation of the third layer, the non-porous or slightly porosified regions can cause stresses in the third layer. In some embodiments, this is used to form active regions, which for example emit light of different wavelengths.

[0028] Thus, a functional stack can be constructed having an active region configured to emit light at a first wavelength through a porosified region and an active region configured to emit light at a second wavelength through a non-porosified region, the different wavelengths being caused, inter alia, by stresses due to different lattice constants for the porosified or non-porosified regions.

[0029] In some embodiments, it may be preferable to select a dimension in the patterning mask that is somewhat larger than one or more non-porous regions of the first layer below the patterning mask. The mask shading prevents or reduces the flow of current along and below that region of the first layer during the electrochemical process. This leaves the material of the first layer substantially intact. The slightly larger mask dimension also compensates for any minor undercutting that may occur.

[0030] In some embodiments, a mesa structure can be formed before or after the above-mentioned selective porosity, which allows the porosity to be at least partially controlled. Thus, a combination of mask structuring and mesa structuring can be performed, which results in a structure after the individual method steps in which porosity and non-porosity areas of the first layer alternate, separated by trenches.

[0031] The recesses, in particular in the form of trenches, in some embodiments have a width in the range of 5 nm to 500 nm, in particular in the range of 20 nm to 300 nm, more particularly less than 200 nm, in which case the trenches can extend to the auxiliary support but can also terminate before it or at the separating layer, if present in the first layer.

[0032] In order to absorb the stress caused by the difference in lattice constant, it is desirable that the mesa structure formed as a trench or a recess is not excessively large. The above-mentioned values ​​have been found to be advantageous in experiments. It is also desirable that the interval between the mesa structures is not excessively large in order to compensate for the stress caused by the trench or the recess. As the interval between two adjacent mesa structures, a range of 400 nm to 4 μm, particularly a range of 800 nm to 2.5 μm, and particularly a range of less than 2 μm is proposed. In some embodiments, the ratio of the width of the mesa structure to the interval between the two mesa structures can be defined. This may be in the range of 4 to 15, particularly a range of 8 to 12, and particularly a range of 9.5 to 10.5.

[0033] Further aspects relate to deviations in the lattice constants, in particular between the second and third layers forming part of the functional stack. In this case, the lattice constant of the planar third layer may deviate from the lattice constant of the second layer by up to 20%, in particular within the range of about 0.4% to 3%, in particular within the range of 0.5% to 2.7%. As materials for the different layers, materials based on GaN or GaAs, which may be doped with Si, C, Ge or Mg, can be used. The third layer of the functional stack may in particular comprise an indium-containing layer. The layer may be formed as a superlattice or may itself comprise a stack. Here, the indium proportion may be in the range of 0.0001% to 25%, for example in the range of 2% to 20%. The layer may be formed as a superlattice or may itself comprise a stack. The rear layers of the second semiconductor stack, in particular those contributing to the optical function, may have an indium content of at least 20%, in particular at least 40%, in particular in the range of 30% to 60%. In some embodiments, the indium content may be up to 100%. Alternative base materials are further listed above. Doping can be performed during epitaxial deposition. This also allows the doping concentration to be continuously adapted.

[0034] In one embodiment, the second layer comprises undoped GaN and the planar third layer comprises an indium-containing material, such as InGaN. Indium Percentage. The first layer is formed from doped GaN, with a doping concentration of 1. * 10 17 atoms / cm 3 ~5 * 10 21 atoms / cm 3 is in the range.

[0035] The inventors have recognized that the orientation of the crystal structure, especially during mesa structuring, is an important factor for further reducing the defect density and preserving a smooth surface during deposition and growth processes. Thus, in some embodiments, it is proposed to orient the coalescence planes in a wurtzite structure material so that they lie perpendicular to the a-axis in a

[1120] orientation.

[0036] Another aspect relates to various configurations of the functional stack. In some embodiments, the epitaxial formation of the functional stack includes the formation of a multiple quantum well structure. The multiple quantum well is configured to emit light of a predetermined wavelength. In this case, the multiple quantum well structure can extend over at least one mesa structure. In some aspects, the multiple quantum well structure extends over both the porous and non-porous regions of the first layer. This creates different band characteristics in the multiple quantum well structure over different regions of the first layer based on the existing stress. This is achieved because the stress changes the stoichiometry of the grown material during the growth process by changing the lattice constant locally, which in turn changes the band gap. This effect can be exploited, for example, in indium-containing material systems, because as the lattice constant increases, the Ga / In ratio is shifted toward indium and thus to longer wavelengths. This allows the creation of multiple different wavelengths of light.

[0037] The inventors have realized that, contrary to the obvious assumption when depositing a third layer on a mesa-structured second layer, the material of the third layer does not penetrate into the trenches at all or only very slightly. In particular, it does not fill these trenches but forms bridges over them, thus leaving hollow spaces. At the same time, the mesa structure in combination with the porosified first layer compensates for the stresses due to the change in the lattice constant.

[0038] Another embodiment relates to a semiconductor device or semiconductor body. In some embodiments, the semiconductor device or semiconductor body includes an auxiliary support and a stack having a first layer including a doped semiconductor material and a second layer formed thereon. The second layer includes an undoped semiconductor material, where the first layer includes at least one porosity region, and the porosity is at least 20% by volume. Furthermore, a mesa structure consisting of a plurality of recesses is introduced in the first layer and the second layer. A functional stack having at least one planar third layer is formed on the second layer provided with the mesa structure, where the at least one planar third layer has a lattice constant different from that of the second layer.

[0039] The combination of the introduced mesa structure and the porosified first layer reduces or prevents stress in the planar third layer, which allows the use of material systems with different lattice constants, where the porosification allows relaxation of the third layer and thus of the functional stack.

[0040] In some embodiments, the width of the recess or the width of the trench is also less than 200 nm, and the distance between two recesses is less than 2000 nm. Other dimensions for the trench and the distance between them are further indicated above. In some examples, the width of the recess is about 1 / 5 to 1 / 20 of the distance between two adjacent recesses.

[0041] In some alternative embodiments, the first layer is not entirely porosified. Rather, it may have at least one non-porous region at least partially surrounded by a porosified region. This allows for a variety of applications. For example, the at least one non-porous region may provide a support structure for a functional semiconductor body that is subsequently placed. Similarly, the non-porous region may be used to selectively introduce stress at different locations in another layer to achieve a change in band gap or electrical properties.

[0042] At least one non-porous region can be configured to be separated from a porosity region by a trench that forms a mesa structure.

[0043] Another aspect relates to the construction of a functional stack, where in some embodiments the functional stack is formed with a multiple quantum well structure formed on a third layer, where in some aspects a first region of the multiple quantum well structure above a porous region of the first layer is configured to emit light at a first wavelength, and a second region of the multiple quantum well structure above a non-porous region of the first layer is configured to emit light at a second shorter wavelength.

[0044] In some other embodiments, the first layer may have a first subregion with a first porosity and may include a second subregion with a second porosity separated by a separation layer, for example, to realize various applications requiring different lattice constants separated by positions, and the additional separation layer may further reduce the defect density in the third layer.

[0045] In one embodiment, the first layer has n-type doping, whereas the second layer is undoped, where the first and second layers comprise the same base material. For example, the second layer can comprise an undoped GaN layer, and the third layer can be formed of InGaN with an indium percentage in the range of 0.0001% to 25%, in particular less than 15%. The third layer can be formed as a superlattice or the third layer itself can comprise a stack. The rear layers of the second semiconductor stack, in particular the layers contributing to the optical function, can have an indium content of at least 20%, in particular at least 40%, in particular in the range of 30% to 60%. In some embodiments, an indium percentage of 100% can also be used, especially when the indium layer is formed very thin. During the epitaxial growth process, the stoichiometric composition of the grown material changes during the growth process, since stress causes local changes in the lattice constant. This causes, for example, a local change in the indium percentage in the grown material system, which in turn changes the band gap. This allows the creation of multiple regions that each produce different wavelengths of light during operation.

[0046] Further aspects and embodiments of the proposed basic scheme will become apparent from reference to the various embodiments and examples described in detail in conjunction with the accompanying drawings. [Brief description of the drawings]

[0047] [Figure 1] 1A-1D illustrate various steps of a method for producing a functional semiconductor body, realizing some aspects of the proposed basic scheme. [Diagram 2] 1A-1D illustrate various steps of a method for producing a functional semiconductor body, realizing some aspects of the proposed basic scheme. [Figure 3A] FIG. 1 illustrates some aspects of another embodiment according to the proposed basic scheme. [Figure 3B] FIG. 1 illustrates some aspects of another embodiment according to the proposed basic scheme. [Figure 4]5 shows another embodiment with several steps of a method for producing a functional semiconductor body, realizing some aspects of the proposed basic scheme. [Diagram 5] 5 shows another embodiment with several steps of a method for producing a functional semiconductor body, realizing some aspects of the proposed basic scheme. [Figure 6] FIG. 1 shows one possible configuration of mesa structures for a material system having a wurtzite structure. [Figure 7] FIG. 13 shows another possible configuration of mesa structures for a material system having a wurtzite structure. [Figure 8] 5 shows another embodiment with several steps of a method for producing a functional semiconductor body, realizing some aspects of the proposed basic scheme. [Figure 9] 9A-9C are two plan views showing the light-emitting surface of an optoelectronic module that can be manufactured by the method of FIG. 8.

[0048] Detailed Description The following embodiments and examples show various aspects and combinations of the proposed basic scheme. The embodiments and examples are not necessarily drawn to scale. Similarly, various elements are shown enlarged or reduced in size to emphasize individual aspects. It is obvious that individual aspects and features of the embodiments and examples shown in the drawings can be easily combined with each other without compromising the basic scheme according to the present invention. Some aspects have regular structures or shapes. It should be noted that in practice, slight deviations from the ideal shapes may occur, but do not contradict the idea of ​​the present invention.

[0049] Furthermore, the individual drawings, features and aspects are not necessarily drawn to scale, and the proportions between the individual elements are not necessarily essentially accurate. Some aspects and features are emphasized by enlargement. Furthermore, terms such as "upper", "upper", "lower", "lower", "greater", "smaller", etc. are expressed precisely with reference to the elements in the drawings. Thus, it is possible to derive such relationships between the elements based on the drawings.

[0050] The inventors have realized that partial electrochemical decomposition (herein also referred to as porosification) of a precisely defined GaN-containing layer significantly reduces the retention of the GaN epitaxy stack with respect to the epitaxy substrate (sapphire or Si, GaN) or with respect to other layers to be further grown. In this case, very uniform porosity (within the range of 20 nm to 100 nm) is evenly distributed and etched in a particular GaN layer. The selectivity of the "porosification" can be achieved by a high n-doping (Si) of the GaN layer, i.e. only layers that are doped with a sufficiently high concentration are porosified. Not only are the adhesion forces reduced, but an improved relaxation is also achieved. This means that the forces between the porosified layer and another layer to be further grown are also reduced by the porosification. Thus, when the lattice constants are different respectively, the porosification significantly reduces the stress in the growing layer, which allows this layer to be grown substantially without lattice defects. This effect can be used on the one hand to produce alternating porous and non-porous regions, which can lead to localized stresses. On the other hand, by providing an additional mesa structure with a trench, the effect of stress compensation can be amplified, which can alleviate cases of overgrowth and thus contribute to reducing the stress due to the different lattice constants.

[0051] Due to the different lattice constants in the layers thus grown, the indium content is incorporated in different stoichiometric compositions depending on the stress present during epitaxial deposition of the indium-containing material, and thus depending on the different lattice constants. Here, the band gap is changed due to the local change in the indium content in the material system. In addition to indium, this effect can also be achieved by Al or other materials that are incorporated with a lattice constant-dependent stoichiometric change, which causes a change in the band gap.

[0052] Because the chemical etching attack by vertical mass transport in the GaN epitaxy stack occurs over the entire surface, it is possible to perform "porosification" over the entire wafer, where the layer to be porosified may be buried under another GaN layer or a layer of other material.

[0053] Alternatively, partial passivation of the surface during "porosification" can result in selective etching attack in the lateral direction. Due to the mask applied, the buried regions in the first layer to be porosified below the masked surface regions are not or only slightly porosified or etched laterally in the plane, so that they have different chemical and mechanical properties in the subsequent process steps. Optionally, an additional second layer can be inserted between the first layer to be porosified and another layer forming the semiconductor module, so that the additional layer can be used as a mechanical break point in further process steps. In this way, different regions can have different porosities in the lateral or vertical direction, depending on the application and design.

[0054] 1 and 2 show a first exemplary configuration of a method for producing a semiconductor body according to the proposed basic scheme, which has reduced lattice stress and can be particularly easily removed from the carrier by means of a porous separating layer.

[0055] For this purpose, in a first step S1, a carrier substrate 1 is provided as an auxiliary carrier. In the present embodiment, the substrate is a sapphire carrier substrate, but carrier substrates with other material systems may also be used. For example, silicon-based, silicon nitride-based or as shown, sapphire-based carrier substrates come into consideration. In this case, the auxiliary carrier is selected in particular further according to the material system to be used later.

[0056] In the next step S2, a first layer 2 of the stack 4 is formed on the auxiliary support 1. This first layer 2 is further provided with dopants during epitaxial deposition on the substrate of the auxiliary support 1. The layer thickness is in the range of 500 nm to 3 μm, for example 1.5 μm. As materials, GaN or also AlInGaP or as a further material system AlGaAs can be used, the last of which can be used for the production of red LEDs. In the present example, GaN is used as the material of the first layer, which is epitaxially deposited on the auxiliary support 1 with silicon Si as dopant. In this case, the doping concentration of silicon atoms is 10×10 19 atoms / cm 3 . Additionally, before epitaxial growth of the GaN layer 2, one or more thin buffer layers in the range of less than 10 nm to 100 nm can be formed on the material of the auxiliary support 1. These are not shown in detail in step S2, but can be used to further planarize the auxiliary support 1. Note that the additional buffer layer can also be used as an etch stop structure or a matching lattice structure or as a current spreading layer for a later electrochemical dissolution process, depending on the material system used.

[0057] In a subsequent step S3, an undoped GaN layer 3 is formed on the epitaxially deposited doped GaN layer 2. Alternatively, AlInGaP can be used if layer 2 consists of doped AlGaAs or doped AlInGaP. The thickness of layer 3 is, for example, 100 nm (in the range 20 nm to 150 nm), and is configured to be significantly thinner in terms of its dimensions than the doped GaN layer 2. This causes layer 3 to exhibit different mechanical, chemical and electrical properties with respect to this layer 3. The undoped GaN layer 3 and the doped GaN layer 2 together form a stack 4.

[0058] In step S4, the wafer thus produced is subjected to an electrochemical stripping process. This process is called a porosification process. For this purpose, a voltage is applied to the formed wafer structure and stack 4, which causes a current flow through the undoped GaN layer 3 and the doped GaN layer 2. This current flow causes a partial chemical decomposition of the doped GaN layer. This process is called porosification. In the doped GaN layer 2, the electrochemical process then uniformly etches pores having a size ranging from a few tens to a few hundreds of nanometers. It has been found that the distribution of the pores is substantially uniform and approximately perpendicular to the sapphire surface. The etching rate as well as the pore diameter and the associated material removal amount depend on the applied voltage, the current flow during the electrochemical process, the electrolyte used and the dopant atomic concentration in the GaN layer 2. It should be noted here that the electrochemical process also attacks the essentially undoped GaN layer 3. Material removal takes place in both layers, since they are not electrically insulating. However, the conductivity of the undoped GaN layer is significantly lower, so silicon doping in layer 2 provides selectivity during the porosification process.

[0059] In other words, the doped GaN layer 2 is significantly more aggressively attacked and etched during the electrochemical process, which dissolves the material to a greater extent than the undoped GaN layer 3. In this example, the current is introduced over the entire surface of the wafer during porosification, so that the electrochemical process continues over the entire surface in the stack 4. The layer 2a thus porosified in step S4 is therefore embedded beneath the undoped GaN layer 3.

[0060] In this case, the amount of material removed by porosification is adjustable by the duration and the above mentioned parameters. To ensure a good subsequent release by laser lift-off or other mechanical methods, the inventors propose a porosity of at least 20% by volume. In this case, it has been found that up to a porosity of about 90% to 95% by volume, the mechanical stability of the remaining material is still sufficient to allow further manufacturing steps. However, due to the large amount of material removal, the adhesion forces between the support 1 and the porosified GaN layer 2a or between the support 1 and the undoped GaN layer 3 are significantly reduced. A porosity of 40% to 90% by volume is therefore considered advantageous in this respect.

[0061] After porosification of the first layer 2 of the stack 4, the wafer thus produced can be further processed to prepare further layers with further lattice constants. For this purpose, in step S5, a patterning mask is applied onto the undoped GaN layer 3, which in this example is configured as strips when viewed from above. Here, the ratio of the width of the strips to the spacing between two adjacent strips is about 10. The spacing between two strips is in this configuration in the range of 1 μm to 2 μm. Such spacings and widths of about 100 nm to 200 nm can also be produced lithographically with current technology.

[0062] Subsequently, in step S6, a selective etching process is performed in which the porosified layer is etched through the undoped GaN layer right up to the auxiliary support. In this way, a mesa structure with a narrow but deep trench is formed. The ratio of the depth to the width of the trench is in the range of 5 to 14, in particular in the range of 10. The structure thus produced offers the special property that, in combination with the mesa-structured porosified layer, stresses due to non-adapted lattice constants can be absorbed. In other words, the layer is suitable for overgrowth with material systems having different lattice constants respectively, without causing stresses in this layer and thus defects in the crystal structure. Rather, the mesa-structured porosified layer 2a causes stresses, which allows another layer to be grown as such without significant stresses. This allows the layer grown on the mesa-structured porosified layer to be produced almost flat without significant defects, and therefore this layer can be used as a base layer for a functional semiconductor body or a functional semiconductor stack.

[0063] The illustration of step S7 in Fig. 2 shows a first step here of growing an n-type doped indium-containing layer 10, e.g. an InGaN layer, having a lattice constant larger than that of the layer stack 4. The growth process of the n-type doped InGaN layer 10 generates stresses in the layer stack 4, which are compensated by the porosified regions 2a and the mesa structures in the layer stack 4. This allows the InGaN layer 10 to grow substantially error- and defect-free. Additionally, during the growth process, material bridges are formed that span over the trenches 20. Thus, in other words, the material InGaN of the layer 10 penetrates only slightly into the trenches 20 and grows substantially only in the surface regions of the undoped GaN layer 3, leaving these trenches unfilled.

[0064] This results in cavities, as shown in step S7, which can absorb the crystal stresses in the stack 4. By changing the porosity over the layer 2c or by other lithographic or epitaxial means, a large relaxation rate in the stack 4 can be achieved, so that the defect density in the layer 10 remains low. The grown layer 10 therefore has a substantially flat and defect-free surface after the growth process, on which further layers of the functional semiconductor or functional stack 6 can be deposited with high quality. Step S8 shows the production of the stack 6, in which the layers are n-type doped during the growth process.

[0065] On said n-doped layer 10 further layers 11 and 12 are deposited. Layer 11 forms a multiple quantum well for emitting light of a given wavelength. Layer 12 is formed by a p-doped GaN layer or a p-doped AlInGaP layer. In this case, the use of a GaN layer can be particularly easily performed. Alternatively, however, a layer combination, for example consisting of p-doped InGaN / AlGaN / GaN layers, can also be formed. The stack 6 thus forms a module through which a current flows during operation to form light of a given wavelength. The wavelength is determined by the band structure of the multiple quantum well, which again depends on the stresses that may occur in the underlying layer 10. Due to the low defect density and the almost flat surface, in this embodiment the defect density of the multiple quantum well is also low, so that a high radiative recombination rate can be achieved.

[0066] In step S9, the module or modules thus produced are transferred from the auxiliary support 1 to the final support substrate 5. For this, the final support substrate 5 is covered with a metallization layer 70 forming a p-type contact for the contact connection of the functional stack 6. The p-type doped layer 12 is fixed on the metallization layer 70 by means of solder. The auxiliary support 1 is then removed by means of laser lift-off or other processes. Here, due to the porosification of the regions 2a, the adhesion forces between the auxiliary support 1 and the porosified regions 2a are significantly reduced. This also results in a lower energy input being required for the laser lift-off process, which results in less damage to the surface.

[0067] In a further method step S10, the remaining structure of the stack 4 after the laser lift-off can be removed, thereby exposing the planar layer 10, on which further metallized contact areas 7 are formed, so that the resulting module is formed as a vertical light-emitting diode, which structure is shown as a result in step S10 for the individual diodes.

[0068] Alternatively, the mesa-structured and porosified layer 2a can remain on the module and be used for electrical contact connection and as output structure. Such an embodiment is shown in FIG. 2 in step S10′. In this case, metal contacts 7a are deposited on the porosified regions 2a. Since the porosified regions and the layer 3 lying below them are electrically conductive, a current flow also occurs in this embodiment through the different layers 2a, 3a, 10 and 12, respectively, which leads to a recombination of the charge carriers in the multiple quantum well 11. Furthermore, the porosified regions 2a are also used as output structures, since they form a refractive index transition between the layer 3 and the air medium. Therefore, in this embodiment, an additional roughening of the layer 10 or further output structures and means can be omitted.

[0069] Here, depending on the application, various modifications of the proposed basic concept are possible, ie the first layer of the stack is made porous.

[0070] FIG. 3A shows an embodiment in which different doping regions are proposed to produce different porosities. Here, FIG. 3A shows the result of a first step of the manufacturing process of a semiconductor module. Here, on an auxiliary support 1, a first layer 2 is deposited adjacent to the auxiliary support 1, which comprises a region 2' and a region 2''. The regions 2' and 2'' are separated from each other by a thin separating layer 3b. The separating layer 3b is used on the one hand as a target breaking point and comprises AlGaInN or, for example, silicon nitride SiN as a monolayer. Furthermore, the layer 3b separates the different doping concentrations from each other. The doping rate of the region 2' is therefore different from that of the region 2'' and thus a different porosity is obtained in the subsequent electrochemical process. In this embodiment, the doping amount in the region 2' is selected to be significantly higher than that in the region 2''. As a result, during the electrochemical process, significantly more material is removed and decomposed in the region 2' than in the region 2'' which is closer to the undoped GaN layer 3.

[0071] The structure produced in this way is, for example, particularly suitable as an output structure. After the functional semiconductor body designed for light emission has been produced, the auxiliary carrier is separated from the material 2' and the separating layer 3b. For this purpose, the target break point 3b can also be removed in a separate step, so that only the porosified area 2'' of the first layer remains on the module. The porosity of the porosified layer is selected so that the layer 2'' is used as an output structure, since the porous structure of the layer 2'' forms a suitable refractive index jump. Subsequent roughening with KOH or other means is therefore not necessary.

[0072] In Fig. 3B the structure of Fig. 3A is shown after mesa structuring, as for example carried out in steps S5 and S6 in the previous embodiment of Fig. 1. The etching process penetrates the two partial regions 2' and 2'' and the thin separating layer 3b, right up to the auxiliary support 1. The structure thus produced can be overgrown with other material systems, each having a different lattice constant, without causing stresses and defects in this layer, as in the previous embodiment.

[0073] 4 and 5 show various steps of another embodiment of the proposed basic scheme, in which additional measures and structuring of the stack 4 are performed before the formation of the mesa structures, thereby realizing further applications.

[0074] Steps S1 and S2 are similar to the embodiment of FIG. 1 or 2. Thus, again after the auxiliary support 1 is prepared, a doped GaN layer 2 is epitaxially grown. A thin target breaking layer or target separation layer 3a is then deposited on the doped GaN layer 2. The thin target breaking layer can be made, for example, of AlGaInN or can also be made of intrinsic silicon nitride, for example a single layer of SiN, and also extends over the entire wafer in this embodiment. On the thin target breaking layer 3a, again an undoped GaN layer 3 is epitaxially grown. The resulting stack 4 on the support substrate 1 is shown in FIG. 4 in step S3.

[0075] Here, in step S3, a patterning mask 8 is applied, for example in two places, on the undoped GaN layer 3. The mask 8 is chemically inert with respect to the subsequent electrochemical porosity step and is configured, for example, as a hard mask. As shown in step S4, after the application of the patterning mask 8, the electrochemical porosity is carried out. However, in this case, the structure of the mask 8 acts as a shading portion, so that the areas below the mask 8 in the first layer 2a are not porosified or etched, but remain as non-porous areas 2b. In the example of steps S3 and S4 of FIG. 4, the two non-porous areas 2b are two areas having a width of a few micrometers and substantially forming a square in a top view. However, other dimensions and / or other numbers of such areas can also be provided. Similarly, the shape can be configured differently, for example as a polygon or as a circle or rectangle.

[0076] The reason behind such selective porosification is the fact that the current flow through the layers 3, 3a and the first layer 2 is largely prevented due to the insulating properties of the mask 8. In other words, the current always seeks the path of least resistance (i.e. the shortest path when the resistivity is constant in most cases) and therefore does not flow under the areas covered by the mask 8 or shaded during the electrochemical process. This results in the current flow porosifying, inter alia, the non-shaded areas of the first layer, so that the porosified areas 2c are formed there. Similarly, the penetration of the electrolyte under the shaded areas during the electrochemical etching process is difficult or is prevented in the same way as described above, so that no further etching channels are formed here or no expansion of existing channels occurs by the electrolyte.

[0077] The dimensions of the mask 8 are adapted to the dimensions of the later non-porous regions 2b. Due to the higher surface resistance below the mask, the current flow there is significantly smaller, but in the edge regions a slight undercut occurs to a small extent. Due to the undercut occurring during electrochemical porosification, it is reasonable to configure the resist mask 8 somewhat larger in terms of its dimensions than the later non-porous regions. This compensates for the slight undercut below the mask and thus in the shaded regions. The undercut can be in the range of 200 nm to about 800 nm for nitrides and can be more than 1000 nm for materials based on GaAs or GaP. The dimensions and lateral extension must be selected accordingly.

[0078] In the following process step S5, the mask 8 is removed again and instead a mask 8a for forming mesa structures is applied to the surface of the layer 3. The mask is configured such that the non-porous regions 2b are partially covered by the mask structure. Only the edges in the mask between the porosified and non-porous regions of the layer 2 are provided with cutouts. Furthermore, a mask structure with periodic recesses may be arranged over the remaining modified regions 2c. This results in a mask structure 8a, which can be used to etch the mesa structures described in the previous examples.

[0079] Process step S6 in Fig. 5 shows the result after a selective etching process, in which trenches 20 are etched at regular intervals into the stack 4. In particular, here every two trenches 20 are provided next to a non-porous region, so that each trench 20 separates a porous region 2c from a non-porous region 2b.

[0080] On the structure thus produced, an AlInGaN layer 10 is subsequently formed, which, as in the previous embodiment, may be p-doped, n-doped or undoped, depending on the application and the desired design of the module. The additional mesa structure reduces the stress in the layer 10, so that it grows as defect-free and flat as possible. On the grown layer 10, a multiple quantum well 11 is deposited, which is followed by a further doped layer 12. The layers 10, 11, 12 form the stack 6 of the functional semiconductor stack. A patterning mask 8b is then arranged on the deposited layer 12, where each part of the mask covers the non-porous region 2b and the adjacent trench 20 as well as a part of the subsequent porosity region 2c. Furthermore, between the individual masks 8b, a surface part of the layer 12 is exposed.

[0081] In a subsequent selective etching process, as shown in step S7 of FIG. 5, the exposed areas of layer 12 and the underlying areas of the multiple quantum wells 11 of layer 10 and stack 4 are etched. This divides the semiconductor stack into individual functional modules. Etching trenches 20' reach from the surface of semiconductor stack 6 almost down to carrier 1. After this etching step, further contact regions 7a and 7 are provided for each module. In this case, contact region 7a is electrically insulated from layer 12 and multiple quantum wells 11 and is in contact with doped buried layer 10. Contact region 7 is electrically connected directly to layer 12.

[0082] The trenches 20' formed by the selective etching process allow the porosified regions 2c to be reached and removed by selective wet chemical etching processes. The columnar structures 20b, shown in process step S8, are thus made of non-porous material and form the support structures for the modules located above them. The selective process further slightly roughens the layers 3a and 3b, which allows them to be used as output structures for the light formed in the multi-quantum well. These columnar structures can take various shapes depending on the design. In some embodiments, the support structures can form truncated cones, pyramids or square truncations, where the smaller base of the base of these truncations is connected to the module. In other words, their diameter decreases towards the module. This reduction in diameter, or more generally, the change in diameter, is achieved by different doping during the epitaxial deposition of the first layers. The doping also controls, among other things, the porosity and thus also influences the undercut below the shaded region.

[0083] In one or more further method steps, as shown in step S9 in Fig. 5, the stamp pad 30 is selectively applied onto the functional semiconductor body 60, which is then separated from the pillar-shaped holding structure 20b by a mechanical or laser lift-off process. The semiconductor body 60 is now attached to the stamp pad 30 and can be moved for further process guidance or processing. Recesses in the layer 3a or in the layer 3 which are still present due to the structuring can be used as further output structures or filled with a suitable material.

[0084] Depending on the material system, different prerequisites may be required or should be taken into account to form the mesa structures to reduce possible stress in the overlying layers.

[0085] On the other hand, in order to still ensure sufficient stress compensation, the height of the layer to be subsequently porosified, and thus also of the trench, should not exceed a few micrometers. Moreover, the trench cannot be etched uniformly if the ratio of depth to trench width is too large, so that instead of a substantially rectangular extension as shown in the cross-sectional view, a triangular recess is formed. Corresponding to the previous example, the height of the porosified layer 2 should therefore be about 1 μm to 2 μm, possibly only 500 nm.

[0086] If the height and width of layer 2 are of the same order of magnitude, as shown in step S6 of Fig. 1, the width of the trench can be chosen to be approximately 1 / 10 smaller than the width of each section of layer 2 to be porosified, thus obtaining the square cross section shown in step S6 of Fig. 1. In this case, the trench should generally be as narrow as possible, but preferably large enough to ensure relaxation or stress compensation of the stress layer formed on stack 4.

[0087] The various etching and masking steps are accomplished by various lithographic processes, in which a wet chemical etching process can be realized for layer 2a to form the mesa structure, but also a dry chemical etching process can be realized.

[0088] 6 and 7 show various geometries for this type of mesa structure in plan view. Depending on the material system, the mesa structure has to be formed along a predefined axis or a predefined orientation. In Fig. 6 and Fig. 7, this is shown in accordance with a wurtzite structure for a nitride-based material system. In the case of a wurtzite structure, it is advantageous to orient the merger plane 21 so that it lies substantially perpendicular to the a-axis

[1120] . This allows the trenches of the mesa structure to be etched parallel to the merger plane as well, resulting in the structure shown in Fig. 6, for example.

[0089] 7 shows another embodiment in which the mesa structures are configured as periodic hexagons, where the trenches and the joining surface 21 are configured to form polygonal, in particular hexagonal, structures, the edge length of which is less than 2 μm as shown, and the width of the trenches is substantially less than 1 / 10 of that, i.e. in the range of 200 nm or less.

[0090] 8 shows another embodiment and application, in which porosified and non-porous regions are used to form a light-emitting semiconductor body, which emits light of different wavelengths. In a first process step shown, an auxiliary support 1 is provided, on which a doped GaN layer 2 is formed, as already explained in the previous embodiment. Furthermore, an undoped layer of the same material system is deposited on the doped GaN layer, resulting in the proposed layer stack 4 in process step S1.

[0091] In a subsequent process step, a patterning mask 8 is first deposited on the surface of the undoped GaN layer 3. The structure thus obtained is then subjected to an electrochemical stripping and decomposition process, which in particular porosifies the non-shaded areas of the doped layer 2. Where the mask 8 covers the layer 2, a continuous material of essentially doped GaN is preserved in said areas, since no dedicated porosification takes place due to the reduced or absent current flow as described above. Therefore, in the area 2b, no subsequent stress reduction by porosification can be expected.

[0092] In a further process step, shown in S3 in FIG. 8, the mask 8 is removed and a mask 8b is applied anew to the layer 3. However, in this case the mask structuring is performed in such a way that parts of the mask 8b are located above the non-porous regions 2b. Similarly, mask sections are also deposited on the porous regions 2c. It is assumed here that small parts remain open between the individual mask sections, so that the layer 3 underneath is exposed. The positions of the exposed parts here are selected in such a way that the exposure is essentially along the interface between the porous regions 2c or between the non-porous regions 2b. A selective etching process can then be performed which likewise forms trenches at the interface between the regions 2b and 2c down to the auxiliary support 1 below. Thus, a structuring is performed which separates the porous regions 2c from the non-porous regions 2b by means of the trenches.

[0093] Subsequently, in the present embodiment using a GaN layer 10, the mesa structure thus including the indium-containing layer is overgrown (see step S4 in FIG. 8). As in the previous embodiment, the InGaN layer forms bridges between the individual trenches 20, so that these trenches remain substantially hollow and do not grow. Note that the InGaN material can at least partially reach into the upper regions of the trenches between the undoped layers 3.

[0094] Due to the non-porous region 2b, the deposited material of the layer 10 is stressed above said region, which is visible in a change in the lattice structure and in the stress, where whether said stress leads to additional lattice defects depends on the dimensioning of the doped InGaN layer 10 and the undoped layer 3 and the difference between these two lattice constants.

[0095] Here, in a further deposition process, layer 12 is deposited on layer 10 with the other multiple quantum wells included. In this case, layer 12 contains doped AlInGaN or doped gradient AlInGaN depending on the configuration. Due to the stress introduced by the non-porous region 2b, the band structure and thus the band gap of the multiple quantum well 11 change. This is caused by the stress continuing through layer 10 and reaching into layer 12 and into the multiple quantum well 11. For this reason, it is necessary to configure InGaN layer 10 as thin but flat as possible in order to direct the stress through layer 10 into layer 11. As a result, the stress leads to the emission of light with different wavelengths. In this case, a wide range of possible wavelengths can be obtained by appropriate selection of the stress and the material system.

[0096] The electronic module thus produced is shown in plan view in various alternative configurations in FIG. 9. A light emitting surface is visible, below which are multiple quantum wells with different porosity rates and possibly porosified regions. By suitable porosification and the introduction of mesa structures, different stresses can be produced in the material arranged above. The different bandgaps caused by the stress, based on the changed indium percentage, now result in the emission of light with different wavelengths. In this way, in a suitable material system, for example the above-mentioned AlInGaN, light emission in the blue, green and red ranges can be achieved by stress.

[0097] In the left part of FIG. 9, the maximum stress is shown in the upper left region b, where, for example, a non-porous layer 2b is arranged. In this case too, the region r is significantly less stressed, so that the multiple quantum well emits substantially red light here. The two lower regions g are arranged with a porosity between the blue region b and the red region r, so that the multiple quantum well emits light in the green region when it is slightly stressed here. Alternatively, pixels with blue, red and green light-emitting surfaces can be arranged next to each other. Such an embodiment is shown in the right part of FIG. 9, where the regions are porosified with different intensities to generate light in the blue, red and green spectrum.

[0098] To produce different porosities, it is envisioned, for example, that the individual masks 8 are selectively removed as described above with reference to step S2 of Fig. 8, and then the electrochemical deposition process continues. For example, to produce different porosities for forming blue, red and green emitting surfaces, shadow masks 8 can be deposited on the subsequent blue and green emitting surfaces, while leaving the red surface exposed.

[0099] A first electrochemical stripping process is then performed, resulting in a first porosification for the red light-emitting surface. The electrochemical stripping process is then stopped, the mask above the green area is removed, and then the electrochemical stripping process is continued. Correspondingly, the red and green surfaces (or layer 2, which is later located below the multiple quantum wells) are further porosified. This allows different porosity rates to be achieved on each surface. Alternatively, additional layers can be provided that can be used to create differences in porosity and to configure different colored areas, as shown, for example, in Figures 3A and 3B. [Explanation of symbols]

[0100] 1 Auxiliary support 2. Doped first layer 2',2'' doped first layer region 2a Porous first layer 2b Non-porous region 2c Porous region 3 Undoped second layer 3a,3b separation layer 4. Laminate 5 Support 6. Functional semiconductor body 7,7a Contact area 8,8a,8b Resist mask 10 layers 11 Multiple quantum wells 12 layers 20' Trench 20 Mesa structure 20b Holding structure 21 Combined surface 30 Stamps 60 Functional semiconductor body 70 Contact Area

Claims

1. 1. A method for manufacturing a semiconductor body, the method comprising the steps of: Providing an auxiliary support; forming a stack having a first layer comprising a doped semiconductor material and a second layer comprising an undoped semiconductor material formed thereon; electrochemically porosifying the first layer of the laminate, wherein the porosity is at least 20% by volume; forming a mesa structure in the second layer and at least partially in the porosified first layer; epitaxially forming a functional stack having at least one planar third layer formed on the second layer provided with a mesa structure, the material of the third layer forming a bridge spanning an end region of the mesa structure opposite the auxiliary support, the at least one planar third layer having a lattice constant different from that of the second layer; A method comprising:

2. The method further comprises: peeling the functional laminate from the first layer, optionally leaving the second layer behind on the functional laminate; or peeling off the functional stack from the auxiliary support, whereby the porosified first layer remains in the functional semiconductor stack and is configured as an output structure for optional electromagnetic radiation; The method of claim 1 , further comprising one of:

3. The method of claim 1 , wherein the functional stack includes at least one active area configured for light emission.

4. forming the mesa structure, forming a patterning mask on the second layer; Etching the second layer and the porosified first layer to form a recess in the form of a trench in the porosified first layer. The method of claim 1 , comprising:

5. 2. The method according to claim 1, wherein in the step of forming the stack, during the epitaxial deposition of the first layer, a thin separation layer, in particular an undoped separation layer, is deposited, thereby dividing the first layer into a region facing the auxiliary support and a region opposite the auxiliary support.

6. The method of claim 1 , wherein the step of forming a stack includes introducing dopants into the first layer during epitaxial deposition of the first layer at at least two different dopant concentrations.

7. The step of forming the laminate includes: applying a patterning mask onto the second layer of the stack to form a non-porous region beneath the patterning mask; The patterning mask is removed after electrochemical porosification of the first layer. forming a non-porous region by The method of claim 1.

8. 8. The method of claim 7, wherein the dimensions of the patterning mask are selected to be somewhat larger than the non-porous area or areas of the first layer beneath the patterning mask.

9. 9. The method of claim 7 or 8, wherein the functional laminate is configured to have an active region configured to emit light of a first wavelength through a porosified region and an active region configured to emit light of a second wavelength through a non-porous region.

10. 5. The method according to claim 4, wherein the recess in the form of a trench has a width in the range of 5 nm to 500 nm, in particular in the range of 20 nm to 300 nm, more particularly less than 200 nm, and wherein the recess in the form of a trench optionally extends to the auxiliary support.

11. 5. The method according to claim 4, wherein the recesses in the form of two trenches adjacent to one another have a spacing in the range of 400 nm to 4 μm, in particular a spacing in the range of 800 nm to 2.5 μm, in particular a spacing of less than 2 μm.

12. 5. Method according to claim 4, in which the ratio between the width of the mesa structure and the width of the recess in the form of a trench is in the range from 4 to 15, in particular in the range from 8 to 12, in particular in the range from 9.5 to 10.

5.

13. 2. The method according to claim 1, wherein the lattice constant of the planar third layer deviates from the lattice constant of the second layer within a range of 0.2% to 3%, in particular within a range of 0.5% to 2.7%.

14. The first layer and the second layer are GaN, GAP, AlGaN, InGaN, AlInGaN, AlInGaP, and AlGaAs and a dopant is applied to the first layer during epitaxial deposition. The method of claim 1.

15. The method of claim 1 , wherein the second layer comprises undoped GaN and the planar third layer comprises an indium-containing material having an indium percentage in the range of 0.0001% to 25%.

16. The step of epitaxially forming the functional stack includes: forming a multiple quantum well structure configured to emit light of a predetermined wavelength, wherein the multiple quantum well structure extends across a plurality of mesa structures; 16. The method of any one of claims 1 to 15, comprising:

17. The step of epitaxially forming the functional stack includes: depositing the planar third layer on the mesa structured second layer, where the trenches between the mesa structures are left substantially unfilled. The method of claim 1 , comprising:

18. 1. A semiconductor device comprising: An auxiliary support; 1. A stack having a first layer including a doped semiconductor material and a second layer including an undoped semiconductor material formed thereon, the first layer comprises at least one porosified region having a porosity of at least 20% by volume; The first layer and the second layer include a mesa structure between the recesses. A laminate; a functional stack having at least one flat third layer formed on the second layer on which the mesa structure is provided, the material of the at least one flat third layer forming a bridge spanning an end region of the mesa structure opposite the auxiliary support, the at least one flat third layer having a lattice constant different from that of the second layer; A semiconductor device comprising:

19. 20. The semiconductor device according to claim 18, wherein a width of the recess is about 1 / 5 to 1 / 20 of a distance between two adjacent recesses.

20. The semiconductor device of claim 18 , wherein the first layer includes at least one non-porous region at least partially surrounded by a porosified region.

21. 21. The semiconductor device of claim 20, wherein the at least one non-porous region is separated from the porosity region by a trench that forms the mesa structure.

22. The semiconductor device of claim 20 , wherein the functional stack includes a multiple quantum well structure formed on the third layer.

23. 23. The semiconductor device of claim 22, wherein a first region of the multiple quantum well structure above the porous region of the first layer is configured to emit light at a first wavelength, and a second region of the multiple quantum well structure above the non-porous region of the first layer is configured to emit light at a second, shorter wavelength.

24. 20. The semiconductor device of claim 18, wherein the first layer has a first subregion having a first porosity and a second subregion having a second porosity, the first subregion being separated from the second subregion by a separation layer.

25. 20. The semiconductor device of claim 18, wherein the first layer has an n-type doping and the second layer is undoped, and the first layer and the second layer comprise the same base material.

26. The semiconductor device of claim 18, wherein the second layer comprises an undoped GaN layer and the third layer comprises InGaN with an indium percentage in the range of 0.0001% to 25%, in particular in the range of 5% to 20%.

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