Semiconductor Device

Abstract

To provide a semiconductor device capable of suppressing adverse influences upon a resistance value of ON resistance of a built-in diode.SOLUTION: First trenches 7 and 31 extend in a first direction X. A depth of the second trench 31, in which an SBD is embedded, is deeper than a depth of the first trench 7 in which a MOS gate is embedded. A first p+ type region 6a is selectively provided at a depth position of a bottom face of the second trench 31 and in contact oppositely to the bottom face of the second trench 31. Between the second trenches 31 which are adjacent to each other in a second direction Y, in a depth range from a depth position of a bottom face of the first trench 7 to a depth position of a top face of the first p+ type region 6a, n type current diffusion regions 3 are provided in contact with the bottom face of the first trench 7 and sidewalls of the second trenches 31 at both sides in the second direction Y. Between the n type current diffusion regions 3 distributed in the first direction X, a second p+ type region 6b is interposed in contact with a p type silicon carbide layer 42, the first p+ type region 6a and the sidewalls of the second trenches 31 at both sides in the second direction Y.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Conventionally, in power semiconductor devices using semiconductors with a band gap wider than that of silicon (Si) (hereinafter referred to as wide band gap semiconductors), low on-resistance, suppression of forward characteristic degradation, and reduction of reverse recovery loss are required. For example, in order to realize low on-resistance, a trench gate structure is adopted in vertical MOSFETs (metal oxide semiconductor field effect transistors), which is structurally easier to obtain low on-resistance characteristics than a planar gate structure in which a MOS gate is provided in a flat plate shape on the front surface of a semiconductor chip.

[0003] The trench gate structure is a MOS gate structure in which a MOS gate is embedded in a trench formed on the front surface of a semiconductor chip, and it is possible to reduce the on-resistance by shortening the cell pitch (the repeat width of a unit cell (a constituent unit of an element)). Suppression of forward characteristic degradation and reduction of reverse recovery loss can be achieved by incorporating a Schottky barrier diode (SBD) in the same semiconductor substrate (semiconductor chip) as the MOSFET. In a MOSFET with an SBD incorporated in the same semiconductor substrate, if the SBD is configured using a conductive layer arranged in a flat plate shape on the semiconductor substrate, the cell pitch of the MOSFET will be large.

[0004] When the cell pitch of a MOSFET becomes larger, the on-resistance increases compared to a MOSFET without an SBD. For this reason, it has been proposed to incorporate a trench-type SBD that extends in a direction perpendicular to the front surface of the semiconductor substrate (vertical direction) in the same semiconductor substrate as the MOSFET. In a MOSFET with a trench-type SBD, the lateral width of the SBD can be reduced compared to when a flat SBD that extends in a direction parallel to the front surface of the semiconductor substrate (horizontal direction) is incorporated. For this reason, an SBD can be incorporated without increasing the on-resistance, even if the cell pitch of the MOSFET is reduced to around 3.2 μm.

[0005] A conventional trench-gate MOSFET incorporating a trench-type SBD in the same semiconductor substrate will be described below by taking as an example a case where silicon carbide (SiC) is used as the wide band gap semiconductor. Fig. 11 is a cross-sectional view showing the structure of a conventional semiconductor device. Fig. 12 is a plan view showing the layout of the trench in Fig. 11 as viewed from the front surface side of the semiconductor substrate. The trench-gate MOSFET shown in Fig. 11 includes, on the front surface side of a silicon carbide substrate 110, a trench (hereinafter referred to as a gate trench) 107 in which a MOS gate of a trench-gate MOSFET 121 is embedded, and a trench 131 in which a trench-type SBD 122 is embedded.

[0006] The silicon carbide substrate 110 is a n-type semiconductor substrate made of silicon carbide. + On the starting substrate 101, - The silicon carbide epitaxial substrate is formed by epitaxially growing in order the silicon carbide layers that become the p-type drift region 102 and the p-type base region 104. The gate trenches 107 and the trenches 131 in which the trench SBDs 122 are embedded are alternately and repeatedly arranged in a direction parallel to the front surface of the silicon carbide substrate 110 (see FIG. 12 ). That is, one unit cell of the trench SBD 122 is embedded between adjacent unit cells of the trench-gate MOSFET 121, i.e., between adjacent gate trenches 107.

[0007] A unit cell of the trench-gate MOSFET 121 is composed of a MOS gate in one gate trench 107 and adjacent mesa regions sandwiching the MOS gate. The mesa region is a portion (silicon portion) of the silicon carbide substrate 110 sandwiched between adjacent gate trenches 107. The trench SBD 122 includes a trench 131 between the gate trenches 107 and a conductive layer 132 embedded inside the trench 131, and is composed of a Schottky junction 133 between the conductive layer 132 formed along the sidewall of the trench 131 and the n-type current diffusion region 103.

[0008] Reference numeral 106 denotes a p + 12, the gate electrode 109 embedded in the gate trench 107 and the conductive layer 132 embedded in the trench 131 are shown with different hatching. In FIG. 12, the gate insulating film 108 and the various parts in the mesa region are omitted in order to clarify the layout of the trenches 107 and 131. Reference numerals 105, 111, and 113 respectively denote n-type regions and n-type regions. + a source region, an interlayer insulating film, and a drain electrode.

[0009] A trench-gate MOSFET with a trench SBD built in the same semiconductor substrate has been proposed, in which a trench is formed between gate trenches (mesa region) arranged in a striped layout with a uniform pitch, facing the gate trench with a p-type base region interposed therebetween, and a Schottky junction is formed between a metal layer and an n-type epitaxial layer on the bottom surface of the trench (see, for example, Patent Document 1 below (paragraphs 0029 and 0039, FIG. 2)). In Patent Document 1 below, a trench SBD is built in between the gate trenches without widening the cell pitch of the MOSFET, thereby preventing an increase in the area of ​​the MOSFET and an increase in the on-resistance of the MOSFET.

[0010] In addition, a trench-gate MOSFET with a trench-type SBD built in the same semiconductor substrate was developed, with n+ Through the n-type source region - The conductive layer and the n-type epitaxial layer are located near the bottom of the trench with a V-shaped cross section. - A device has been proposed in which a Schottky junction is formed between a conductive layer and an n-type epitaxial layer (see Patent Document 2 below (paragraphs 0016, 0026, and 0064, FIG. 1)). In Patent Document 2 below, a conductive layer and an n-type epitaxial layer are connected at the inclined sidewall of a trench. + The contact area with the n-type source region is increased to reduce the source contact resistance (on-resistance), and the conductive layer and n-type source region are formed near the bottom of the trench. - A Schottky junction is formed between the epitaxial layer and the silicon-type epitaxial layer. [Prior art documents] [Patent documents]

[0011] [Patent Document 1] JP 2005-354037 A [Patent Document 2] Special Publication No. 2008-536316 Summary of the Invention [Problem to be solved by the invention]

[0012] However, as a result of extensive research by the inventors, it was found that in a conventional semiconductor device (see FIG. 11), when the cell pitch of the trench-gate MOSFET 121 is reduced to less than 3.2 μm, the on-resistance increases compared to a trench-gate MOSFET that does not incorporate an SBD.

[0013] SUMMARY OF THE PRESENT DISCLOSURE In order to solve the above-mentioned problems associated with the conventional techniques, an object of the present invention is to provide a semiconductor device capable of suppressing the adverse effect of the on-resistance of a built-in diode on the resistance value. [Means for solving the problem]

[0014] In order to solve the above-mentioned problems and achieve the object of the present invention, the semiconductor device according to the present invention has the following features. A first semiconductor layer having a drift region of a first conductivity type is provided in a semiconductor substrate. A second semiconductor layer having a base region of a second conductivity type is provided between a front surface of the semiconductor substrate and the first semiconductor layer. A first semiconductor region of a first conductivity type having a higher impurity concentration than the drift region is selectively provided between the front surface and the base region inside the second semiconductor layer. A first trench penetrates from the front surface through the first semiconductor region and the base region in the depth direction to reach a depth deeper than the base region, and extends in a first direction parallel to the front surface. A second trench penetrates from the front surface through the first semiconductor region and the base region in the depth direction to reach a depth deeper than the first trench, and extends in the first direction.

[0015] A first high concentration region of a second conductivity type having a higher impurity concentration than the base region is selectively provided facing the bottom surface of the second trench. The first high concentration region is in contact with the bottom surface of the second trench. In a first cross section parallel to the second direction of a first region sandwiched between the second trenches adjacent to each other in a second direction perpendicular to the first direction, the first semiconductor layer of the first conductivity type in contact with the bottom surface of the first trench and the sidewall of the second trench is arranged in a first depth range from a depth position of the bottom surface of the first trench to a depth position of the surface on the front surface side of the first high concentration region. In a second cross section of the first region parallel to the second direction and different from the first cross section, an intermediate region of a second conductivity type in contact with the second semiconductor layer and the first high concentration region and the sidewall of the second trench is provided in the first depth range.

[0016] In addition, in the semiconductor device according to the present invention, in the above-mentioned invention, the intermediate region is a second high concentration region of a second conductivity type having a higher impurity concentration than the base region.

[0017] In addition, the semiconductor device of the present invention is characterized in that, in the above-mentioned invention, it comprises a MOS gate structure including the first trench in which a gate electrode is embedded, a first electrode electrically connected to the first semiconductor region and the base region, embedded in the second trench and in contact with the first semiconductor layer of a first conductivity type on a sidewall of the second trench, and a second electrode provided on a back surface of the semiconductor substrate.

[0018] According to the above-mentioned invention, a forward current of the built-in diode formed by the junction between the first electrode and the first semiconductor layer of the first conductivity type flows through a first depth range in the first region, and does not flow into a second depth range on the back surface side of the semiconductor substrate further than the first high concentration region. Effect of the Invention

[0019] The semiconductor device according to the present invention has an advantage in that it is possible to suppress the adverse effect of the on-resistance of the built-in diode on the resistance value. [Brief description of the drawings]

[0020] [Figure 1] FIG. 1 is a plan view showing a planar layout of a semiconductor device according to a first embodiment. [Diagram 2] 2 is a cross-sectional view showing a cross-sectional structure taken along line AA' in FIG. [Diagram 3] 2 is a cross-sectional view showing a cross-sectional structure taken along line BB' in FIG. [Figure 4] 4 is a cross-sectional view showing the structure of another example of the semiconductor device according to the first embodiment. FIG. [Diagram 5] FIG. 11 is a plan view showing a planar layout of a semiconductor device according to a second embodiment. [Figure 6] 6 is a cross-sectional view showing a cross-sectional structure taken along line DD' in FIG. 5. [Figure 7] FIG. 11 is a cross-sectional view showing a structure of a semiconductor device according to a third embodiment. [Figure 8] FIG. 11 is a cross-sectional view showing a structure of a semiconductor device according to a fourth embodiment. [Figure 9]FIG. 11 is a characteristic diagram showing the relationship between the distance between a pin diode and a unipolar element arranged on the same semiconductor substrate and the bipolar current. [Figure 10] FIG. 10 is a cross-sectional view showing a cross-sectional structure of a sample used in the verification of FIG. [Figure 11] FIG. 1 is a cross-sectional view showing a structure of a conventional semiconductor device. [Figure 12] 12 is a plan view showing the layout of the trench in FIG. 11 as viewed from the front surface side of the semiconductor substrate. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Preferred embodiments of the semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, in layers and regions prefixed with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - appended to n or p respectively mean that the impurity concentration is higher and lower than that of layers and regions not prefixed with them. In the following description of the embodiments and the accompanying drawings, the same reference numerals are assigned to similar configurations, and duplicated explanations will be omitted.

[0022] (Embodiment 1) The semiconductor device according to the first embodiment is constructed using a semiconductor (referred to as a wide bandgap semiconductor) having a wider bandgap than silicon (Si). The structure of the semiconductor device according to the first embodiment will be described taking, as an example, a case where silicon carbide (SiC) is used as the wide bandgap semiconductor. FIG. 1 is a plan view showing a planar layout of the semiconductor device according to the first embodiment. The planar layout refers to the planar shape and arrangement of each part as viewed from the front surface side of a semiconductor substrate 10. FIG. 1 shows a layout of first and second trenches 7, 31 as viewed from the front surface side of a semiconductor substrate (semiconductor chip) 10.

[0023] In FIG. 1, in order to clarify the layout of the first and second trenches 7 and 31, the gate insulating film 8 and each part in the mesa region are omitted. In FIG. 1, the gate electrode 9 embedded in the first trench 7 and the conductive layer 32 embedded in the second trench 31 are shown with different hatching (similar to FIG. 5). FIG. 2 is a cross-sectional view showing a cross-sectional (first cross-sectional) structure taken along the line A-A' in FIG. 1. FIG. 3 is a cross-sectional view showing a cross-sectional (second cross-sectional) structure taken along the line B-B' in FIG. 1. In FIGS. 1 to 3, only some unit cells (components of the element) arranged in the active region are shown, and the edge termination region surrounding the periphery of the active region is omitted (similar to FIGS. 4 to 9). In FIGS. 2 and 3, only the conductive layer 32 is shown with hatching (similar to FIGS. 4, 6 to 8).

[0024] The active region is the region through which current flows when the semiconductor device is in an on-state. The edge termination region is the region between the active region and the side of the semiconductor substrate 10, and - The mesa region is a region that maintains a breakdown voltage (withstand voltage) by relaxing the electric field on the substrate front surface (front surface of the semiconductor substrate 10) side of the type drift region 2. In the edge termination region, a general breakdown voltage structure such as a guard ring, field plate, or resurf is arranged. The breakdown voltage is the limit voltage at which the semiconductor device does not malfunction or break down. The mesa region is the portion (silicon portion) of the semiconductor substrate 10 that is sandwiched between the adjacent first and second trenches 7, 31.

[0025] The semiconductor device according to the first embodiment shown in FIG. 1 is a trench-gate MOSFET 21 having a trench SBD 22 built in the same semiconductor substrate 10 made of silicon carbide. The trench-gate MOSFET 21 has a p-type base region 4, an n-type base region 5, and a n-type base region 6 on the front surface side of the semiconductor substrate 10. + type source region (first semiconductor region) 5, p ++The trench-gate MOSFET 21 has a MOS gate structure consisting of a first contact region (not shown), a first trench (gate trench) 7, a gate insulating film 8, and a gate electrode 9. The trench-type SBD 22 is composed of a second trench 31, a conductive layer 32, and an n-type current diffusion region 3 provided on the front surface side of the semiconductor substrate 10. The trench-type SBD 22 has a function of preventing degradation of a parasitic diode (body diode) formed inside the trench-gate MOSFET 21.

[0026] Specifically, the semiconductor substrate 10 is a n-type semiconductor substrate made of silicon carbide. + Starting substrate 1 - The silicon carbide epitaxial substrate is formed by epitaxially growing silicon carbide layers (first and second semiconductor layers) 41, 42, which become the n-type drift region 2 and the p-type base region 4, in that order. - An n-type region (hereinafter referred to as n-type current diffusion region) 3 is provided in a surface layer on the source side (source electrode (first electrode) 12 side) of the type silicon carbide layer 41 so as to contact the p-type silicon carbide layer 42 (p-type base region 4). The n-type current diffusion region 3 is a so-called current spreading layer (Current Spreading Layer: CSL) that reduces the spreading resistance of carriers.

[0027] The n-type current diffusion region 3 is uniformly provided in a direction parallel to the front surface of the substrate. The n-type current diffusion region 3 extends from the interface with the p-type base region 4 to a position deeper on the drain side (the drain electrode (second electrode) 13 side) than the bottom surfaces of the first and second trenches 7 and 31 described later. - The portion of the n-type silicon carbide layer 41 other than the n-type current diffusion region 3 is n - The n-type drift region 2 is an n-type current diffusion region 3. - The n-type current diffusion region 3 is exposed on the inner walls of the first and second trenches 7 and 31 between the n-type drift region 2 and the p-type base region 4. The n-type current diffusion region 3 does not necessarily have to be provided.

[0028] n-type current diffusion region 3 (n if n-type current diffusion region 3 is not present) - In the drift region 2), the first and second + The mold regions 6a and 6b are selectively provided.+ The mold regions 6a are provided in a plurality of locations spaced apart from each other. + The mold region 6a faces the first and second trenches 7 and 31, respectively, in the depth direction Z, and covers the bottom surfaces of the first and second trenches 7 and 31, respectively, which face each other (see FIGS. 2 and 3). + The type region 6 a is disposed at a position deeper on the drain side than the interface between the p-type base region 4 and the n-type current diffusion region 3 and separated from the p-type base region 4 .

[0029] 1st p. + The type region 6a is electrically connected to a source electrode (first electrode) 12 at a portion not shown. + The width w1 of the mold region 6a (width in the second direction Y described later) is preferably equal to or larger than the width w11 of the first and second trenches 7 and 31 (width in the second direction Y), for example. + The drain side end of the n-type region 6a may be terminated inside the n-type current diffusion region 3, or may be connected to the n-type current diffusion region 3 and the n-type current diffusion region 3. - When the interface with the n-type drift region 2 is reached, - It may terminate inside the mold drift region 2.

[0030] Also, page 1 + The mold region 6a may cover the bottom surfaces and bottom corner portions of the first and second trenches 7, 31 from the bottom surfaces to the bottom corner portions of the first and second trenches 7, 31. The bottom surfaces of the first and second trenches 7, 31 are surfaces of the inner walls of the first and second trenches 7, 31 that are located at the deepest portion from the front surface of the semiconductor substrate 10 and are approximately parallel to the front surface of the substrate (front surface of the semiconductor substrate 10). The bottom corner portions of the first and second trenches 7, 31 are boundaries between the bottom surfaces and side walls of the first and second trenches 7, 31.

[0031] Also, page 1 + The mold regions 6a are arranged in a stripe-like layout extending in a direction parallel to the front surface of the semiconductor substrate 10 (see FIG. 1). +The direction in which the mold regions 6a extend in a stripe shape (the depth direction in FIG. 2) is defined as a first direction X. + The mold regions 6a are partially in contact with each other and connected to each other. + The connecting portion (p + type region) to p + The type linking region is 6c. + The thickness of the mold connection region 6c and the depth from the front surface of the substrate are, for example, + It is similar to the mold region 6a.

[0032] p + The type connection regions 6c are arranged in a stripe-like layout extending in a direction parallel to the front surface of the semiconductor substrate 10 and in a direction Y (the horizontal direction in FIGS. 2 and 3: hereinafter referred to as the second direction) perpendicular to the first direction X (see FIG. 1). + Type region 6a and its p + p of a grid-like layout consisting of type-connected regions 6c + In Fig. 1, the p + Only one straight line portion constituting a stripe in the second direction Y of the mold connection region 6c is shown.

[0033] 2nd p. + The mold region (intervening region, second high concentration region) 6b is p + The second p-type connecting region 6c is provided between the p-type silicon carbide layer 42 (p-type base region 4) and is in contact with both regions. + The mold regions 6b are arranged in a striped layout extending in the second direction Y (see FIG. 1). + The width (width in the first direction X) w2 of the mold region 6b in the short side direction is p + It may be approximately the same as the width in the short side direction (width in the first direction X) w3 of the mold connection region 6c.

[0034] These 1st and 2nd pages + The first and second p-type regions 6a and 6b are depleted when the trench-gate MOSFET 21 is turned off, and have the function of reducing the electric field applied to the bottom surfaces of the first and second trenches 7 and 31.+ By providing the die regions 6a and 6b, it is possible to reduce the cell pitch (repeated width of a unit cell) of the trench-gate MOSFET 21 and reduce the on-resistance while maintaining the breakdown voltage.

[0035] The p-type silicon carbide layer 42 is provided with first and second trenches 7 and 31 that penetrate the p-type silicon carbide layer 42 from the front surface of the semiconductor substrate 10 (the surface of the p-type silicon carbide layer 42) in the depth direction Z to reach the n-type current diffusion region 3. The first and second trenches 7 and 31 are respectively located in different first p + The first and second trenches 7 and 31 are terminated inside the second p region 6a. + In the portion where the p-type region 6b is arranged, the p-type silicon carbide layer 42 and the second p + The first p + Type 6a p + The depth direction Z is the direction from the front surface of the semiconductor substrate 10 toward the back surface.

[0036] The bottom corners of the first and second trenches 7, 31 may be curved in a circular arc shape with a predetermined curvature. The smaller the curvature of the bottom corners of the first and second trenches 7, 31, the greater the proportion of the bottom corners on the drain side of the first and second trenches 7, 31, and the closer the bottoms of the first and second trenches 7, 31 are to a point (vertex). The sidewalls of the first and second trenches 7, 31 are the surfaces of the inner walls of the first and second trenches 7, 31 that are continuous with the front surface of the substrate (front surface of the semiconductor substrate 10) and are approximately perpendicular to the front surface of the substrate.

[0037] The first and second trenches 7 and 31 are formed in a stripe-shaped first p + The electrodes are arranged in a striped layout extending in the first direction X so as to overlap with the mold region 6a (see FIG. 1).

[0038] A gate insulating film 8 is provided inside the first trench (gate trench) 7 along the inner wall of the first trench 7. A gate electrode 9 such as a polysilicon (poly-Si) layer is provided on the gate insulating film 8 so as to be embedded inside the first trench 7, thereby forming a MOS gate of the trench-gate MOSFET 21. The drain side end of the gate electrode 9 reaches a position deeper on the drain side than the interface between the p-type base region 4 and the n-type current diffusion region 3.

[0039] The MOS gate in one first trench 7 and the adjacent mesa regions sandwiching the MOS gate form one unit cell of the trench-gate MOSFET 21. The cell pitch of the trench-gate MOSFET 21 and the cell pitch between the trench-gate MOSFET 21 and the adjacent trench SBD 22 are, for example, less than 4.0 μm. The cell pitch is the distance w4 between the centers of the adjacent mesa regions sandwiching one trench (the first trench 7 or the second trench 31).

[0040] A conductive layer 32, such as a metal layer made of a metal material such as titanium (Ti), nickel (Ni), tungsten (W), or molybdenum (Mo) or a polysilicon (poly-Si) layer, is buried inside the second trench 31. The conductive layer 32 contacts the n-type current diffusion region 3 on the sidewall of the second trench 31. A Schottky junction 33 is formed between the conductive layer 32 and the n-type current diffusion region 3 along the sidewall of the second trench 31. A source side end of the conductive layer 32 may protrude outward from the second trench 31.

[0041] As described above, the bottom surface of the second trench 31 is the first p + Because the second trench 31 is covered with the type region 6a, the Schottky junction 33 is formed only on the sidewall of the second trench 31. Therefore, the Schottky characteristics of the trench SBD 22 are determined only by the Schottky barrier height based on one plane orientation (the plane orientation of the sidewall of the second trench 31). In other words, the portion along the bottom surface (or including the bottom corner portions) of the second trench 31 is an ineffective region in which the trench SBD 22 is not formed.

[0042] One unit cell of the trench SBD 22 is composed of a Schottky junction 33 formed on the sidewall of one second trench 31. Each unit cell of the trench SBD 22 extends in a first direction X in which the second trenches 31 extend in a stripe shape. The area of ​​the unit cell of the trench SBD 22 (the surface area of ​​the Schottky junction 33) can be adjusted by the depth of the second trench 31 and the length over which the second trench 31 extends in a stripe shape (the length of the second trench 31 in the longitudinal direction (first direction X)).

[0043] The unit cells of the trench-gate MOSFET 21 and the unit cells of the trench SBD 22 (that is, the first and second trenches 7 and 31) are arranged so as to satisfy the following two conditions (hereinafter referred to as the first and second conditions).

[0044] The first condition is that at least one unit cell of the trench-gate MOSFET 21 is disposed in a predetermined region (hereinafter referred to as a MOS cell region (second region)) C' between adjacent unit cells of the trench SBD 22 (i.e., between adjacent second trenches 31). The MOS cell region C' is a region between adjacent second trenches 31, in which the first p + The first p region 6a extends from the end of the mold region 6a on the side of the one second trench 31 to cover the bottom surface of the first trench 7 located closest to the other second trench 31. + This region has a width w22 (=w21 / 2) that is half the width w21 of the region (first region) C up to the end of the mold region 6a on the other second trench 31 side.

[0045] That is, two MOS cell regions C' are present between adjacent unit cells of the trench SBD 22. At least one unit cell of the trench-gate MOSFET 21 is disposed in each of the two MOS cell regions C'. Therefore, the unit cells of the trench SBD 22 are thinned out and disposed on the same semiconductor substrate 10 as the trench-gate MOSFET 21, and the number of unit cells of the trench SBD 22 is less than that of the conventional structure (see FIGS. 11 and 12).

[0046] In the conventional structure, the width w102 of the MOS cell region C' is narrow, and the first p + The width w102 is half the width w01 of the mold region 106, for example, about 0.3 μm to 1.0 μm (w102=w101 / 2). In the MOS cell region C' between adjacent unit cells of the trench SBD 122, only half the unit cells of the trench-gate MOSFET 121 are arranged. On the other hand, in the present invention, two or more unit cells of the trench-gate MOSFET 21 can be arranged between adjacent unit cells of the trench SBD 22. This makes it possible to increase the density of the trench-gate MOSFETs 21 in the semiconductor substrate 10 (the density of the first trenches 7 (gate trenches)).

[0047] 1 to 3 show a case where one unit cell of a trench-gate MOSFET 21 is disposed in each MOS cell region C' between adjacent unit cells of the trench SBD 22. That is, Fig. 1 shows a state where the first and second trenches 7, 31 are disposed in a stripe shape in which one unit cell of the trench SBD 22 (one second trench 31) is disposed between every two unit cells of the trench-gate MOSFET 21 (every two first trenches 7) as viewed from the front surface of the semiconductor substrate 10.

[0048] It is preferable to arrange the same number of unit cells of trench-gate MOSFET 21 in each MOS cell region C' between adjacent unit cells of trench SBD 22. The reason is that if the number of unit cells of trench-gate MOSFET 21 is reduced in one MOS cell region C' between adjacent unit cells of trench SBD 22, the on-resistance increases, and if the number of unit cells of trench-gate MOSFET 21 is increased, the process becomes more difficult. Also, all the first p + The width w1 of the first p type regions 6a is preferably the same. + When the width w1 of the mold region 6a is increased, the parasitic resistance increases. +This is because narrowing the width w1 of the mold region 6a reduces the breakdown voltage and the avalanche resistance.

[0049] The second condition is that all the first p + The total width w1 of the n-type regions 6a, 6b, 6c, 6d, 6e, 6f, 6g, 6h, 6h, 6i, 6j ... + Through the portion between the mold regions 6a, n - The first p-type drift region 2 (or n-type current diffusion region 3) + 4) directly below (on the drain side) of the type region 6a. Therefore, the length of this portion 2a (= the length of all the first p + The width w1) of the MOSFET region 6a acts as a resistance, and the resistance of the MOSFET portion 2a adversely affects the on-resistance of the trench SBD 22. The upper limit of the second condition is an allowable range for suppressing the adverse effect of the resistance of the MOSFET portion 2a on the on-resistance of the trench SBD 22 and for turning on the trench SBD 22 earlier than the parasitic pn diode of the trench-gate MOSFET 21, as described below. The lower limit of the second condition is a permissible range for suppressing the adverse effect of the resistance of the MOSFET portion 2a on the on-resistance of the trench SBD 22. + This is the same as the upper limit of the range of the width w1 of the mold region 6a.

[0050] For example, as another example of the semiconductor device according to the first embodiment, FIG. 4 shows a case where four unit cells of a trench-gate MOSFET 21 are arranged in each MOS cell region C' between adjacent unit cells of a trench SBD 22. FIG. 4 is a cross-sectional view showing the structure of another example of the semiconductor device according to the first embodiment. In the example shown in FIG. 4, four first p + The sum Σw1 of the widths w1 of the mold regions 6a may be within the above range (i.e., 2 μm≦4×w1≦8 μm). + The width w1 of the mold region 6a may be, for example, about 0.6 μm or more and 2.0 μm or less.

[0051] In the p-type silicon carbide layer 42, n-type silicon carbide layers are formed in all mesa regions so as to be in contact with each other.+ Type source region 5 and p ++ A contact region (not shown) is selectively provided on each of the n + The n-type source region 5 is disposed so as to be in contact with the first trench 7, and faces the gate electrode 9 via the gate insulating film 8 on the sidewall of the first trench 7. + The n-type source region 5 is disposed in contact with the second trench 31 and in contact with the conductive layer 32 at the side wall of the second trench 31. + Type source region 5 and p ++ The portion other than the p-type contact region is a p-type base region 4 .

[0052] The gate electrode 9 is extended to the front surface of the semiconductor substrate 10 at a portion not shown, and is electrically connected to a gate electrode pad (not shown). The interlayer insulating film 11 covers the gate electrode 9. The interlayer insulating film 11 may be provided on the gate electrode 9 inside the first trench 7. By disposing the interlayer insulating film 11 inside the first trench 7, the cell pitch of the trench-gate MOSFET 21 can be further shortened.

[0053] The source electrode 12 is + Type source region 5, p ++ The source electrode 12 is in contact with and electrically connected to the type contact region and the conductive layer 32. The source electrode 12 is electrically insulated from the gate electrode 9 by an interlayer insulating film 11. The source electrode 12 also serves as, for example, a source electrode pad. + n-type drain region + A drain electrode (second electrode) 13 is provided on the rear surface of the starting mold substrate 1.

[0054] Next, the operation of the semiconductor device according to the first embodiment will be described. When a parasitic pn diode formed by the pn junction between the p-type base region 4 and n-type current diffusion region 3 of the trench-gate MOSFET 21 is forward biased, the trench SBD 22 turns on at a lower voltage than the parasitic pn diode of the trench-gate MOSFET 21 and earlier than the parasitic pn diode. Therefore, the n-type current diffusion region 3, the p-type base region 4 and the n-type current diffusion region 3 of the trench-gate MOSFET 21 are connected to each other. + No base current flows through a vertical parasitic npn bipolar transistor (body diode) formed of the type-source region 5, and the parasitic npn bipolar transistor does not operate. Therefore, forward degradation due to the parasitic npn bipolar transistor does not occur. In addition, the turn-on loss (reverse recovery loss) due to the parasitic npn bipolar transistor can be reduced.

[0055] The semiconductor device according to the first embodiment described above can be fabricated by forming the second trench 31 constituting the trench SBD 22 and filling the second trench 31 with a conductive layer 32 in a typical trench-gate MOSFET manufacturing method. The second trench 31 may be formed simultaneously with the first trench 7, which is a gate trench, or may be formed at a different time from the formation of the first trench 7. + Type regions 6a, 6b and p + The type linking region 6c is + n epitaxially grown on a starting substrate 1 - The n-type silicon carbide layer 41 may be formed by ion implantation of p-type impurities. - The n-type silicon carbide layer 41 may be epitaxially grown in two stages to increase the thickness in stages. - After the epitaxial growth of the first layer of the silicon carbide layer 41, the first p + Type regions 6a and p + Forming a type-linked region 6c, - After the epitaxial growth of the second layer of the silicon carbide layer 41, a second p + A mold region 6b can be formed.

[0056] As described above, according to the first embodiment, by arranging the trench SBD on the same semiconductor substrate (semiconductor chip) as the trench-gate MOSFET, it is possible to suppress the degradation of forward characteristics and reduce the reverse recovery loss. Also, according to the first embodiment, by arranging the unit cells of the trench SBD every two or more unit cells of the trench-gate MOSFET, it is possible to increase the density of the trench-gate MOSFET in the semiconductor chip. This makes it possible to suppress an increase in on-resistance compared to a conventional structure in which the unit cells of the trench-gate MOSFET and the unit cells of the trench SBD are arranged alternately. Therefore, it is possible to simultaneously achieve a low on-resistance, suppression of deterioration of forward characteristics, and reduction in reverse recovery loss.

[0057] (Embodiment 2) Next, the structure of the semiconductor device according to the second embodiment will be described. FIG. 5 is a plan view showing a planar layout of the semiconductor device according to the second embodiment. FIG. 6 is a cross-sectional view showing a cross-sectional structure taken along line D-D' in FIG. 5. The cross-sectional structure taken along line A-A' in FIG. 5 is the same as that in FIG. 2. The semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment in that the second p + The point is that no mold region is provided. + Type 6a p + An n-type current diffusion region 3 is located between the type coupling region 6c and the p-type silicon carbide layer 42 (p-type base region 4).

[0058] As described above, according to the second embodiment, it is possible to obtain the same effects as those of the first embodiment. According to the second embodiment, the surface area of ​​the channel region is increased, and therefore the current capability of the trench-gate MOSFET can be improved.

[0059] (Embodiment 3) Next, the structure of the semiconductor device according to the third embodiment will be described. Fig. 7 (first cross section) is a cross-sectional view showing the structure of the semiconductor device according to the third embodiment. The semiconductor device according to the third embodiment differs from the semiconductor device according to the first embodiment in that the first trench 7 is formed in the depth direction Z through the n-type current diffusion region 3, and the first p + It is the point facing the mold region 6a. + The mold region 6a is disposed away from the first trench 7. The second trench 31 is deeper than the first trench 7 and is located at a depth of the first p from the front surface of the substrate. + It may be provided to a depth reaching the mold region (first high concentration region) 6a.

[0060] In the third embodiment, when the trench SBD 22 is on, a forward current of the trench SBD 22 flows from the conductive layer 32 to the first p + The forward current of the trench SBD 22 flows to a portion 51 between the first trench region 6a and the bottom surface of the first trench 7. That is, the forward current of the trench SBD 22 is n - The first p + Therefore, the on-resistance of the trench SBD 22 is n - The first p + Therefore, there is no adverse effect on the resistance value of the portion directly below (on the drain side of) the mold region 6a. Therefore, when designing the layout of the unit cells of the trench-gate MOSFET 21 and the unit cells of the trench SBD 22, the constraint of the second condition above is eliminated.

[0061] The third embodiment may be applied to the second embodiment.

[0062] As described above, according to the third embodiment, it is possible to obtain the same effects as those of the first and second embodiments. + By arranging the mold region away from the gate trench (first trench), the degree of freedom in arranging the unit cells of the trench-gate MOSFET 21 and the unit cells of the trench SBD 22 is increased.

[0063] (Embodiment 4) Next, the structure of the semiconductor device according to the fourth embodiment will be described. Fig. 8 is a cross-sectional view showing the structure of the semiconductor device according to the fourth embodiment. The semiconductor device according to the fourth embodiment differs from the semiconductor device according to the third embodiment in that the bottom surface of the first trench 7 and the first p + Between the mold region 6a and the first p + Apart from the type region 6a, + The point is that a mold area 52 is provided.

[0064] p + The p-type region 52 is in contact with the bottom surface of the first trench 7 and faces the gate electrode 9 via the gate insulating film 8 on the bottom surface of the first trench 7. + The p-type region 52 is covered with the n-type current diffusion region 3 except for the portion in contact with the gate insulating film 8. + The width w5 of the mold region 52 is narrower than the width w11 of the first trench 7.

[0065] The fourth embodiment may be applied to the second embodiment.

[0066] As described above, according to the fourth embodiment, it is possible to obtain the same effects as those of the first and second embodiments. + Between the mold region, the first p + Apart from the type region, + By providing the type region, the feedback capacitance (gate-drain capacitance) can be reduced.

[0067] (Example) Next, the upper limit of the second condition was examined. Fig. 9 is a characteristic diagram showing the relationship between the distance between a pin (p-intrinsic-n) diode and a unipolar element arranged on the same semiconductor substrate, and the bipolar current. The horizontal axis of Fig. 9 is the distance between the pin diode 60a and the unipolar element 60b in Fig. 10. The vertical axis of Fig. 9 is the ratio of the current amount of a bipolar element (not shown) arranged on the semiconductor substrate 65 to the current amount of the unipolar element 60b (=current amount of bipolar element / current amount of unipolar element). When the ratio of the current amounts is 1 x 10 -1The above range F means that a bipolar current flows.

[0068] Fig. 10 is a cross-sectional view showing the cross-sectional structure of the sample used in the verification of Fig. 9. The sample shown in Fig. 10 has a unipolar element 60b built in the same semiconductor substrate 65 as a bipolar element (not shown). The semiconductor substrate 65 is a n-type + Starting substrate 61 - The silicon carbide epitaxial substrate is formed by epitaxially growing a mold layer 62. - Mold layer 62, n + Two p-type regions 63 were selectively formed apart from each other on the surface layer (the surface layer of the front surface of the semiconductor substrate 65) opposite to the starting substrate 61. The width w JFET was set to 1.0 μm.

[0069] The bipolar element (not shown) disposed on the same semiconductor substrate 65 is the n-type current diffusion region 3, the p-type base region 4 and the n-type current diffusion region 5 of the trench gate type MOSFET 21 of the present invention. + It is assumed that the vertical parasitic npn bipolar transistor (body diode) is composed of a p-type source region 5. - Type layers 62 and n + A pin diode 60a formed at a pn junction with a starting substrate 61 is assumed to be a parasitic pn diode formed at a pn junction between a p-type base region 4 and an n-type current diffusion region 3 of a trench-gate MOSFET 21 of the present invention. A unipolar element 60b consisting of a JFET region 64 and a conductive layer (not shown) is assumed to be a trench SBD 22 of the present invention.

[0070] 9 shows the relationship between the ratio of the amount of current through the bipolar element arranged on the semiconductor substrate 65 to the amount of current through the unipolar element 60b when the bipolar element is turned on in the sample shown in FIG. 10, and the distance E between the pin diode 60a and the unipolar element 60b. The distance E between the pin diode 60a and the unipolar element 60b is set to the ratio of the amount of current through the bipolar element arranged on the semiconductor substrate 65 to the amount of current through the unipolar element 60b when the bipolar element is turned on in the sample shown in FIG. 10. +9 shows the results of measuring the ratio of the current flowing through the bipolar element disposed on the semiconductor substrate 65 to the current flowing through the unipolar element 60b while varying the critical current density Jc of the bipolar element.

[0071] 9, it was confirmed that the greater the distance E between the pin diode 60a and the unipolar element 60b, the easier it is for a bipolar current to flow. - This is because the type layer 62 acts as a resistor, increasing the on-resistance of the unipolar element 60b. This effect becomes more pronounced as the critical current density Jc of the bipolar element is increased. 2 It was confirmed that even if the temperature is increased to 1000° C., if the distance E between the pin diode 60a and the unipolar element 60b is 8 μm or less, no bipolar current flows. + It can be seen that if the sum Σw1 of the widths w1 of the mold regions 6a is 8 μm or less, no bipolar current flows.

[0072] The present invention can be modified in various ways without departing from the spirit of the present invention, and in each of the above-mentioned embodiments, for example, the dimensions and impurity concentrations of each part are set in various ways according to the required specifications. In addition, in the above-mentioned embodiments, a silicon carbide epitaxial substrate formed by epitaxially growing a silicon carbide layer on a starting substrate made of silicon carbide is used as an example, but each region constituting the semiconductor device according to the present invention may be formed on the silicon carbide substrate by, for example, ion implantation. The present invention also has the same effect when applied to a wide band gap semiconductor other than silicon carbide (e.g., gallium (Ga)). The present invention also holds true when the conductivity type (n-type, p-type) is reversed. [Industrial Applicability]

[0073] As described above, the semiconductor device according to the present invention is useful as a MOS type semiconductor device having a trench gate structure. [Explanation of symbols]

[0074] 1n + Starting substrate 2n - Mold Drift Region 2a n - The first p + The part directly below the type area 3 n-type current diffusion region 4 p-type base region 5n + Type Source Area 6a Covering the bottom of the first and second trenches + Type area (1st p + type area) 6b 1st p. + p in the type domain + Between the p-type junction region and the p-type base region + Type area (2nd p + type area) 6c 1st p. + p in the type domain + type connection area 7 First trench (gate trench) 8 Gate insulating film 9 Gate electrode 10. Semiconductor Substrate 11 Interlayer insulating film 12 Source electrode 13 Drain electrode 21 Trench-gate MOSFET 22 Trench type SBD 31 Second trench (trench with trench-type SBD buried inside) 32 Conductive layer 33 Schottky Junction 41 n - mold silicon carbide layer 42 p-type silicon carbide layer 51 The first p of the n-type current diffusion region + A portion between the mold region and the bottom surface of the first trench 52 1st p. +Between the p-type region and the bottom surface of the first trench + type area C' MOS cell area w1 1st p + Mold area width w2 2nd p + Mold area width w3 1st p + p in the type domain + Width of the mold connection area w4: Distance between the centers of adjacent mesa regions across one trench (first trench or second trench) (cell pitch of trench-gate MOSFET) w5 1st p + Between the p-type region and the bottom surface of the first trench + Mold area width w11 Width of first and second trenches w21 is the first p that covers the bottom surface of the first trench arranged closest to the second trench. + The width between the ends of the mold region on the side of the adjacent second trenches w22 Width of MOS cell area X is a first p in a direction parallel to the front surface of the semiconductor substrate. + A direction in which the mold region and the first and second trenches extend in a stripe shape (first direction) Y: A direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction (second direction) Z depth direction

Claims

1. A first semiconductor layer provided on a semiconductor substrate and having a drift region of a first conductivity type; a second semiconductor layer having a base region of a second conductivity type provided between the front surface of the semiconductor substrate and the first semiconductor layer; a first semiconductor region of a first conductivity type selectively provided between the front surface and the base region in the second semiconductor layer, the first semiconductor region having a higher impurity concentration than the drift region; a first trench extending in a first direction parallel to the front surface, the first trench penetrating the first semiconductor region and the base region in a depth direction to a depth deeper than the base region; a second trench extending in the first direction, the second trench penetrating the first semiconductor region and the base region from the front surface in a depth direction to a depth deeper than the first trench; a first high concentration region of a second conductivity type having a higher impurity concentration than the base region, the first high concentration region being selectively provided opposite to a bottom surface of the second trench and in contact with the bottom surface of the second trench; Equipped with the first semiconductor layer of the first conductivity type is in contact with a bottom surface of the first trench and a sidewall of the second trench, and is disposed in a first depth range from a depth position of a bottom surface of the first trench to a depth position of a surface of the first high concentration region on the front surface side in a first cross section parallel to the second direction of a first region sandwiched between the second trenches adjacent to each other in a second direction parallel to the front surface and perpendicular to the first direction; A semiconductor device characterized in that, in a second cross section parallel to the second direction of the first region and different from the first cross section, an intermediate region of a second conductivity type is provided in the first depth range, the intermediate region being in contact with the second semiconductor layer, the first high concentration region, and a sidewall of the second trench.

2. 2. The semiconductor device according to claim 1, wherein the intermediate region is a second high concentration region of a second conductivity type having a higher impurity concentration than the base region.

3. a MOS gate structure including the first trench having a gate electrode embedded therein; a first electrode electrically connected to the first semiconductor region and the base region, embedded in the second trench, and in contact with the first semiconductor layer of the first conductivity type on a sidewall of the second trench; A second electrode provided on a rear surface of the semiconductor substrate; 3. The semiconductor device according to claim 1, further comprising:

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