Semiconductor Device

Abstract

Provided is a semiconductor device in which each of a transistor portion and a diode portion includes one or more trench contact portions provided in a depth direction of a semiconductor substrate from an upper surface of the semiconductor substrate. The transistor portion includes a first bottom portion region of a second conductivity type provided in contact with a bottom portion of one of the trench contact portions. The diode portion includes a second bottom portion region of the second conductivity type provided in contact with a bottom portion of one of the trench contact portions. The length of the first bottom portion region in an extending direction thereof is greater than the length of the second bottom portion region in an extending direction thereof.

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Conventionally, in semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors), a structure is known in which a contact trench is provided to connect an electrode above a semiconductor substrate to the semiconductor substrate (see, for example, Patent Documents 1 and 2). [Prior art document] [Patent documents] [Patent Document 1] WO2018 / 52099 [Patent Document 2] JP 2018-195798 A Problem to be Solved

[0003] In semiconductor devices, it is desirable to prevent latch-up while improving other characteristics.

[0004] In order to solve the above problems, a first aspect of the present invention provides a semiconductor device. The semiconductor device may include a semiconductor substrate having an upper surface and a lower surface, and a drift region of a first conductivity type provided therein. The semiconductor device may include a transistor portion provided in the semiconductor substrate. The semiconductor device may include a diode portion provided in the semiconductor substrate. Each of the transistor portion and the diode portion may have one or more trench contact portions provided from the upper surface of the semiconductor substrate in a depth direction of the semiconductor substrate. The transistor portion may have a first bottom region of a second conductivity type provided in contact with a bottom portion of any of the trench contact portions. The diode portion may have a second bottom region of a second conductivity type provided in contact with a bottom portion of any of the trench contact portions. The length of the first bottom region in the extension direction may be greater than the length of the second bottom region in the extension direction.

[0005] In the diode portion, a plurality of second bottom regions may be discretely arranged along the extending direction.

[0006] The semiconductor device may include a boundary portion provided between the transistor portion and the diode portion and including one or more trench contact portions. The boundary portion may have a third bottom region of a second conductivity type provided in contact with a bottom portion of any of the trench contact portions. The length of the first bottom region in the extension direction may be greater than the length of the third bottom region in the extension direction.

[0007] The length of the second bottom region in the stretching direction may be the same as the length of the third bottom region in the stretching direction.

[0008] The transistor section may have an emitter region of a first conductivity type provided in contact with an upper surface of the semiconductor substrate and having a doping concentration higher than that of the drift region. The transistor section may have a base region of a second conductivity type provided between the emitter region and the drift region. The transistor section may have a contact region of the second conductivity type provided in contact with the upper surface of the semiconductor substrate, connected to the base region, and having a doping concentration higher than that of the base region. The transistor section may have a gate trench section provided from the upper surface to the lower surface in contact with the emitter region and the base region. The extension direction may be the longitudinal direction in which the gate trench section extends.

[0009] The contact regions may be arranged alternately with the emitter regions in the extending direction, and the first bottom region may connect two contact regions arranged apart in the extending direction.

[0010] A portion of the first bottom region may be provided on the upper surface side of the semiconductor substrate relative to a lower end of the contact region.

[0011] The first bottom region may have a doping concentration higher than the doping concentration of the contact region.

[0012] The first bottom region may have a first concentration peak in a depth direction of a doping concentration. The contact region may have a second concentration peak in a depth direction of a doping concentration. A half width at half maximum of the first concentration peak may be smaller than a half width at half maximum of the second concentration peak.

[0013] The lower end of the trench contact portion may be located closer to the upper surface of the semiconductor substrate than the lower end of the emitter region.

[0014] The trench contact portion of the diode portion may be provided below the trench contact portion of the transistor portion.

[0015] The trench contact portion of the diode portion may have a smaller width on the upper surface of the semiconductor substrate than the trench contact portion of the transistor portion.

[0016] The trench contact portion in the boundary portion may be provided below both the trench contact portion in the diode portion and the trench contact portion in the transistor portion.

[0017] The trench contact portion in the boundary portion may have a smaller width on the upper surface of the semiconductor substrate than both the trench contact portion in the diode portion and the trench contact portion in the transistor portion.

[0018] The diode portion may have an anode region of the second conductivity type provided between the drift region and the upper surface of the semiconductor substrate, The anode region may have a doping concentration lower than that of the base region.

[0019] The transistor portion may have a plurality of accumulation regions provided in a depth direction between the base region and the drift region, the accumulation regions having a doping concentration higher than that of the drift region.

[0020] In a second aspect of the present invention, a semiconductor device is provided. The semiconductor device may include a semiconductor substrate having an upper surface and a lower surface, and a drift region of a first conductivity type is provided therein. The semiconductor device may include a transistor portion provided in the semiconductor substrate. The transistor portion may have one or more trench contact portions provided from the upper surface of the semiconductor substrate in a depth direction of the semiconductor substrate. The transistor portion may have a first bottom region of a second conductivity type provided in contact with a bottom portion of any of the trench contact portions. The transistor portion may have an emitter region of the first conductivity type provided in contact with the upper surface of the semiconductor substrate and having a doping concentration higher than that of the drift region. The transistor portion may have a base region of the second conductivity type provided between the emitter region and the drift region. The transistor portion may have a contact region of the second conductivity type provided in contact with the upper surface of the semiconductor substrate, connected to the base region, and having a doping concentration higher than that of the base region. The doping concentration of the first bottom region may be higher than the doping concentration of the contact region.

[0021] The first bottom region may have a first concentration peak in a depth direction of a doping concentration. The contact region may have a second concentration peak in a depth direction of a doping concentration. A half width at half maximum of the first concentration peak may be smaller than a half width at half maximum of the second concentration peak.

[0022] The above summary of the invention does not list all of the necessary features of the present invention. Also, subcombinations of these features may also be inventions. [Brief description of the drawings]

[0023] [Figure 1] FIG. 1 is a top view illustrating an example of a semiconductor device 100 according to an embodiment of the present invention. [Diagram 2] FIG. 2 is an enlarged view of an area D in FIG. [Figure 3A] FIG. 3 is a diagram showing an example of an ee cross section in FIG. 2. [Figure 3B] FIG. 13 is a diagram showing another example of the ee cross section. [Figure 4A]2 is a perspective cross-sectional view showing an example of a mesa portion 60 of a transistor portion 70. FIG. [Figure 4B] 13 is a perspective cross-sectional view showing another example of the mesa portion 60-1 of the transistor portion 70. FIG. [Diagram 5] 2 is a perspective cross-sectional view showing an example of a mesa portion 61 of a diode portion 80. FIG. [Figure 6] 1 is a perspective cross-sectional view showing an example of a mesa portion 62 at a boundary portion 72. FIG. [Figure 7A] 3B shows an example of a YZ cross section taken along line aa shown in FIG. 3A. [Figure 7B] 3B shows another example of the YZ cross section taken along line aa shown in FIG. 3A. [Figure 8] 3B shows an example of a YZ cross section taken along line bb shown in FIG. 3A. [Figure 9] 3B shows an example of a YZ cross section taken along line cc shown in FIG. 3A. [Figure 10A] 1 shows an XZ cross section in the vicinity of the trench contact portion 55 of the mesa portion 60. [Figure 10B] 13 shows another example of the XZ cross section in the vicinity of the trench contact portion 55 of the mesa portion 60. [Figure 11] 13 is a diagram showing another example of the mesa portion 60 of the transistor section 70. FIG. [Figure 12] 1 is a diagram showing a YZ cross section of a mesa portion 60-2. [Figure 13] FIG. 8 is a diagram showing an example of a doping concentration distribution along the ff line in FIG. [Figure 14] 11A and 11B are diagrams showing examples of the structure of trench contact portions 55 in each mesa portion. [Figure 15] 11A and 11B are diagrams showing examples of the structure of trench contact portions 55 in each mesa portion. [Figure 16A] 13 is a diagram showing another example of the mesa portion 60 of the transistor section 70. FIG. [Figure 16B] FIG. 13 is a diagram showing another example of the mesa portion 60-3. [Figure 17] 13 is a diagram showing another example of the mesa portion 61 of the diode portion 80. FIG. [Figure 18] 13 is a diagram showing another example of the mesa portion 61 of the diode portion 80. FIG. [Figure 19] 2 is a diagram showing an example of a combination of mesa portions in the semiconductor device 100. FIG. [Figure 20] 13 is a diagram showing another example of a combination of mesa portions in the semiconductor device 100. FIG. [Figure 21] 13 is a diagram showing another example of a combination of mesa portions in the semiconductor device 100. FIG. [Figure 22] 13 is a diagram showing another example of a combination of mesa portions in the semiconductor device 100. FIG. [Diagram 23] 13 is a diagram showing another example of a combination of mesa portions in the semiconductor device 100. FIG. [Figure 24] 13 is a diagram showing another example of a combination of mesa portions in the semiconductor device 100. FIG. [Diagram 25] 13 is a diagram showing another example of a combination of mesa portions in the semiconductor device 100. FIG. [Figure 26] 11 is an ee cross section showing another configuration example of the semiconductor device 100. [Figure 27] 11 is an ee cross section showing another configuration example of the semiconductor device 100. [Figure 28] 1 is a top view showing another configuration example of the semiconductor device 100. FIG. [Figure 29] 1 is a top view showing another configuration example of the semiconductor device 100. FIG. [Diagram 30] 1 is a top view showing another configuration example of the semiconductor device 100. FIG. [Diagram 31] 1 is a top view showing another configuration example of the semiconductor device 100. FIG. [Diagram 32] 1 is a top view showing another configuration example of the semiconductor device 100. FIG. [Diagram 33] FIG. 2 is a diagram showing another configuration example of the semiconductor device 100. [Diagram 34] FIG. 34 is a diagram showing an example of an ee cross section in FIG. 33. [Figure 35A] FIG. 2 is a diagram showing another configuration example of the semiconductor device 100. [Figure 35B] 35B is a diagram showing an example of doping concentration distribution in the aa cross section and the a'-a' cross section in FIG. 35A. FIG. [Diagram 36] An example is shown in which a trench bottom region 260 is added to the structure of the mesa portion 60 shown in FIG. 7A. [Figure 37] This shows an example in which a trench bottom region 260 is added to the structure of the mesa portion 61 shown in FIG. [Figure 38] This shows an example in which a trench bottom region 260 is added to the structure of the mesa portion 62 shown in FIG. [Figure 39] FIG. 2 is a diagram showing another configuration example of the semiconductor device 100. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0025] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0026] In this specification, technical matters may be explained using orthogonal coordinate axes of X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components, and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without indicating positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.

[0027] In this specification, the orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are the X-axis and the Y-axis. The axis perpendicular to the upper and lower surfaces of the semiconductor substrate is the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. In this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and the Y-axis, may be referred to as the horizontal direction.

[0028] The region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate may be referred to as the top surface side. Similarly, the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate may be referred to as the bottom surface side.

[0029] In this specification, when the term "same" or "equal" is used, it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0030] In this specification, the conductivity type of a doped region doped with impurities is described as P type or N type. In this specification, the impurity may particularly mean either an N type donor or a P type acceptor, and may be described as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to make it a semiconductor exhibiting an N type conductivity type or a semiconductor exhibiting a P type conductivity type.

[0031] In this specification, the doping concentration means the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration means the net concentration obtained by adding up the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, including the polarity of the charge. As an example, the donor concentration is N D , acceptor concentration N A Then, the net doping concentration at any position is N D -N A In this specification, the net doping concentration may be simply referred to as the doping concentration.

[0032] A donor has the function of supplying electrons to a semiconductor. An acceptor has the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, a VOH defect, which is a combination of a vacancy (V), oxygen (O), and hydrogen (H) present in a semiconductor, functions as a donor that supplies electrons. In this specification, a VOH defect may be referred to as a hydrogen donor.

[0033] In this specification, the semiconductor substrate has N-type bulk donors distributed throughout. The bulk donor is a donor due to a dopant that is contained almost uniformly in the ingot when the ingot that is the base of the semiconductor substrate is manufactured. The bulk donor in this example is an element other than hydrogen. The dopant of the bulk donor is, for example, phosphorus, antimony, arsenic, selenium, or sulfur, but is not limited thereto. The bulk donor in this example is phosphorus. The bulk donor is also contained in the P-type region. The semiconductor substrate may be a wafer cut from a semiconductor ingot, or may be a chip obtained by dividing the wafer. The semiconductor ingot may be manufactured by any of the Czochralski method (CZ method), the magnetic field-applied Czochralski method (MCZ method), and the float zone method (FZ method). The ingot in this example is manufactured by the MCZ method. The oxygen concentration in the substrate manufactured by the MCZ method is 1×10 17 ~7×10 17 / cm 3 The oxygen concentration in the substrate manufactured by the FZ method is 1×10 15 ~5×10 16 / cm 3 A higher oxygen concentration tends to generate hydrogen donors more easily. The bulk donor concentration may be the chemical concentration of the bulk donors distributed throughout the semiconductor substrate, and may be between 90% and 100% of the chemical concentration. A non-doped substrate that does not contain dopants such as phosphorus may be used as the semiconductor substrate. In this case, the bulk donor concentration (D0) of the non-doped substrate is, for example, 1×10 10 / cm 3 That's it, 5 x 10 12 / cm 3The bulk donor concentration (D0) of the non-doped substrate is preferably 1×10 11 / cm 3 The bulk donor concentration (D0) of the non-doped substrate is preferably 5×10 12 / cm 3 The concentrations in the present invention may be values ​​at room temperature. For example, the values ​​at room temperature may be values ​​at 300 K (Kelvin) (approximately 26.9° C.).

[0034] In this specification, when P+ type or N+ type is described, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is described, it means that the doping concentration is lower than that of P type or N type. Also, when P++ type or N++ type is described in this specification, it means that the doping concentration is higher than that of P+ type or N+ type. The unit system in this specification is the SI unit system unless otherwise specified. The unit of length may be expressed in cm, but various calculations may be performed after converting to meters (m).

[0035] In this specification, the chemical concentration refers to the atomic density of an impurity measured regardless of the state of electrical activation. The chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The above-mentioned net doping concentration can be measured by voltage-capacitance measurement (CV). The carrier concentration measured by spreading resistance measurement (SR) may be the net doping concentration. The carrier concentration measured by CV or SR may be a value in a thermal equilibrium state. In addition, in an N-type region, since the donor concentration is sufficiently larger than the acceptor concentration, the carrier concentration in that region may be the donor concentration. Similarly, in a P-type region, the carrier concentration in that region may be the acceptor concentration. In this specification, the doping concentration in an N-type region may be referred to as the donor concentration, and the doping concentration in a P-type region may be referred to as the acceptor concentration.

[0036] In addition, when the concentration distribution of the donor, acceptor or net doping has a peak, the peak value may be taken as the concentration of the donor, acceptor or net doping in the region. In cases where the concentration of the donor, acceptor or net doping is almost uniform, the average value of the concentration of the donor, acceptor or net doping in the region may be taken as the concentration of the donor, acceptor or net doping. In this specification, the concentration per unit volume is expressed in atoms / cm. 3 , or / cm 3 This unit is used for donor or acceptor concentration or chemical concentration in a semiconductor substrate. The atom count notation may be omitted.

[0037] The carrier concentration measured by the SR method may be lower than the concentration of the donor or acceptor. In the range where the current flows when measuring the spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The reduction in carrier mobility occurs when the carriers are scattered due to a disorder in the crystal structure caused by lattice defects, etc.

[0038] The donor or acceptor concentration calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element indicating the donor or acceptor. As an example, the donor concentration of phosphorus or arsenic, which acts as a donor in a silicon semiconductor, or the acceptor concentration of boron, which acts as an acceptor, is about 99% of the chemical concentration. On the other hand, the donor concentration of hydrogen, which acts as a donor in a silicon semiconductor, is about 0.1% to 10% of the chemical concentration of hydrogen.

[0039] Fig. 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. Fig. 1 shows the positions of each component projected onto the top surface of a semiconductor substrate 10. Fig. 1 shows only some of the components of the semiconductor device 100, and some components are omitted.

[0040] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate made of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has end sides 162 in a top view. When simply referred to as a top view in this specification, it means a view from the top surface side of the semiconductor substrate 10. The semiconductor substrate 10 of this example has two pairs of end sides 162 facing each other in a top view. In FIG. 1, the X-axis and the Y-axis are parallel to either of the end sides 162. The Z-axis is perpendicular to the top surface of the semiconductor substrate 10.

[0041] An active portion 160 is provided on the semiconductor substrate 10. The active portion 160 is a region through which a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode is provided above the active portion 160, but is omitted in FIG. 1 . The active portion 160 may refer to a region overlapped by the emitter electrode in a top view. In addition, a region sandwiched between the active portions 160 in a top view may also be included in the active portion 160.

[0042] The active section 160 is provided with a transistor section 70 including a transistor element such as an IGBT. The active section 160 may further be provided with a diode section 80 including a diode element such as a free wheel diode (FWD). In the example of Fig. 1, the transistor sections 70 and the diode sections 80 are alternately arranged along a predetermined arrangement direction (X-axis direction in this example) on the upper surface of the semiconductor substrate 10. The semiconductor device 100 of this example is a reverse conducting IGBT (RC-IGBT).

[0043] In FIG. 1, the region in which the transistor section 70 is arranged is marked with the symbol "I", and the region in which the diode section 80 is arranged is marked with the symbol "F". In this specification, the direction perpendicular to the arrangement direction in a top view may be referred to as the extension direction (Y-axis direction in FIG. 1). The transistor section 70 and the diode section 80 may each have a longitudinal direction in the extension direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section.

[0044] The diode section 80 has an N+ type cathode region in a region in contact with the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode section 80. In other words, the diode section 80 is a region that overlaps with the cathode region in a top view. A P+ type collector region may be provided in a region other than the cathode region on the lower surface of the semiconductor substrate 10. In this specification, an extension region 81 in which the diode section 80 is extended in the Y-axis direction to a gate wiring to be described later may also be included in the diode section 80. A collector region is provided on the lower surface of the extension region 81.

[0045] The transistor section 70 has a P+ type collector region in a region in contact with the lower surface of the semiconductor substrate 10. In addition, the transistor section 70 has a gate structure, which has an N type emitter region, a P type base region, a gate conductive portion, and a gate insulating film, periodically arranged on the upper surface side of the semiconductor substrate 10.

[0046] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 164. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is disposed near an end edge 162. The vicinity of the end edge 162 refers to the region between the end edge 162 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire.

[0047] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to a conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes a gate wiring that connects the gate pad 164 and the gate trench portion. In FIG. 1, the gate wiring is hatched with oblique lines.

[0048] The gate wiring in this example has a peripheral gate wiring 130 and an active side gate wiring 131. The peripheral gate wiring 130 is disposed between the active portion 160 and an edge 162 of the semiconductor substrate 10 in a top view. The peripheral gate wiring 130 in this example surrounds the active portion 160 in a top view. The region surrounded by the peripheral gate wiring 130 in a top view may be the active portion 160. In addition, a well region is formed below the gate wiring. The well region is a P-type region with a higher concentration than a base region described later, and is formed from the top surface of the semiconductor substrate 10 to a position deeper than the base region. The region surrounded by the well region in a top view may be the active portion 160.

[0049] The peripheral gate wiring 130 is connected to the gate pad 164. The peripheral gate wiring 130 is disposed above the semiconductor substrate 10. The peripheral gate wiring 130 may be a metal wiring containing aluminum or the like.

[0050] The active side gate wiring 131 is provided in the active section 160. By providing the active side gate wiring 131 in the active section 160, the variation in wiring length from the gate pad 164 for each region of the semiconductor substrate 10 can be reduced.

[0051] The peripheral gate wiring 130 and the active side gate wiring 131 are connected to a gate trench portion of the active section 160. The peripheral gate wiring 130 and the active side gate wiring 131 are disposed above the semiconductor substrate 10. The peripheral gate wiring 130 and the active side gate wiring 131 may be wiring formed of a semiconductor such as polysilicon doped with impurities.

[0052] The active side gate wiring 131 may be connected to the peripheral gate wiring 130. In this example, the active side gate wiring 131 is provided extending in the X-axis direction from one peripheral gate wiring 130 to the other peripheral gate wiring 130 sandwiching the active portion 160, so as to cross the active portion 160 at approximately the center in the Y-axis direction. When the active portion 160 is divided by the active side gate wiring 131, the transistor portion 70 and the diode portion 80 may be arranged alternately in the X-axis direction in each divided region.

[0053] Furthermore, the semiconductor device 100 may include a temperature sensor (not shown) that is a PN junction diode formed of polysilicon or the like, and a current detector (not shown) that simulates the operation of a transistor section provided in the active section 160.

[0054] In the present example, semiconductor device 100 includes an edge termination structure 90 between active portion 160 and edge 162 when viewed from above. Edge termination structure 90 in the present example is disposed between peripheral gate wiring 130 and edge 162. Edge termination structure 90 relieves electric field concentration on the top surface side of semiconductor substrate 10. Edge termination structure 90 may include at least one of a guard ring, a field plate, and a resurf that are provided in an annular shape surrounding active portion 160.

[0055] FIG. 2 is an enlarged view of a region D in FIG. 1. The region D is a region including a transistor section 70, a diode section 80, and an active side gate wiring 131. As shown in FIG. 2, a boundary section 72 may be provided between the transistor section 70 and the diode section 80. The semiconductor device 100 of this example includes a gate trench section 40, a dummy trench section 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 provided inside the upper surface side of the semiconductor substrate 10. The gate trench section 40 and the dummy trench section 30 are each an example of a trench section. The semiconductor device 100 of this example also includes an emitter electrode 52 and an active side gate wiring 131 provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the active side gate wiring 131 are provided separately from each other.

[0056] An interlayer insulating film is provided between the emitter electrode 52 and the active side gate wiring 131 and the upper surface of the semiconductor substrate 10, but is omitted in Fig. 2. In the interlayer insulating film of this example, a contact hole is provided so as to penetrate the interlayer insulating film. A conductive member such as the emitter electrode 52 may be provided inside the contact hole.

[0057] In this embodiment, a trench contact portion 55 is provided on the upper surface of the semiconductor substrate 10. The trench contact portion 55 is a member in which a conductive material is filled in a groove-shaped structure provided from the upper surface of the semiconductor substrate 10 to a predetermined depth. The inside of the groove of the trench contact portion 55 is filled with a conductive material such as tungsten. A barrier metal including at least one of a titanium film and a titanium nitride film may be provided between the conductive material and the semiconductor substrate 10 inside the groove of the trench contact portion 55. The trench contact portion 55 is provided extending in the extension direction (Y-axis direction). The trench contact portion 55 is disposed below the contact hole of the interlayer insulating film described above. The emitter electrode 52 may be connected to the semiconductor substrate 10 via the contact hole of the interlayer insulating film and the trench contact portion 55. In FIG. 2, each trench contact portion 55 is hatched with oblique lines.

[0058] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 contacts at least a part of the well region 11, the emitter region 12, the contact region 15, the anode region 17, and the base region 14 on the upper surface of the semiconductor substrate 10 through a contact hole and a trench contact portion 55. The emitter electrode 52 is also connected to a dummy conductive portion in the dummy trench portion 30 through a contact hole provided in the interlayer insulating film. The emitter electrode 52 may be connected to the dummy conductive portion of the dummy trench portion 30 at the tip of the dummy trench portion 30 in the Y-axis direction.

[0059] The active side gate wiring 131 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The active side gate wiring 131 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction. The active side gate wiring 131 is not connected to the dummy conductive portion in the dummy trench portion 30.

[0060] The emitter electrode 52 is made of a material containing metal. FIG. 2 shows the range in which the emitter electrode 52 is provided. For example, at least a portion of the emitter electrode 52 is made of aluminum or an aluminum-silicon alloy, such as a metal alloy such as AlSi or AlSiCu. The emitter electrode 52 may have a barrier metal made of titanium, a titanium compound, or the like, below the region made of aluminum or the like. Furthermore, the emitter electrode 52 may have a plug formed by embedding tungsten or the like in the contact hole so as to contact the barrier metal and aluminum or the like.

[0061] The well region 11 is provided so as to overlap with the active side gate wiring 131. The well region 11 is also provided so as to extend by a predetermined width to an area where it does not overlap with the active side gate wiring 131. The well region 11 in this example is provided away from the end of the contact hole in the Y-axis direction toward the active side gate wiring 131. The well region 11 is a region of a second conductivity type having a higher doping concentration than the base region 14. In this example, the base region 14 is P type, and the well region 11 is P+ type.

[0062] Each of the transistor section 70, the boundary section 72, and the diode section 80 has one or more trench sections arranged in the arrangement direction. In the transistor section 70 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately provided along the arrangement direction. In the diode section 80 of this example, a plurality of dummy trench sections 30 are provided along the arrangement direction. In the diode section 80 of this example, no gate trench section 40 is provided. In the boundary section 72 of this example, one or more dummy trench sections 30 are provided along the arrangement direction. In the boundary section 72, a gate trench section 40 may be further provided.

[0063] The gate trench portion 40 in this example may have two straight line portions 39 (portions of the trench that are straight along the extension direction) extending along an extension direction perpendicular to the arrangement direction, and a tip portion 41 connecting the two straight line portions 39. The extension direction in FIG. 2 is the Y-axis direction.

[0064] At least a part of the tip portion 41 is preferably curved in a top view. By connecting the ends of the two straight portions 39 in the Y-axis direction with each other by the tip portion 41, electric field concentration at the ends of the straight portions 39 can be alleviated.

[0065] In the transistor section 70, the dummy trench section 30 is provided between the respective straight line portions 39 of the gate trench section 40. One dummy trench section 30 may be provided between the respective straight line portions 39, or a plurality of dummy trench sections 30 may be provided. The dummy trench section 30 may have a straight line shape extending in the extension direction, and may have a straight line portion 29 and a tip section 31, similar to the gate trench section 40. The semiconductor device 100 shown in FIG. 2 includes both a straight line dummy trench section 30 without a tip section 31 and a dummy trench section 30 with a tip section 31.

[0066] The diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. The ends in the Y-axis direction of the gate trench portion 40 and the dummy trench portion 30 are provided in the well region 11 when viewed from above. That is, at the ends in the Y-axis direction of each trench portion, the bottoms in the depth direction of each trench portion are covered by the well region 11. This makes it possible to alleviate electric field concentration at the bottoms of each trench portion.

[0067] A mesa portion is provided between each trench portion in the arrangement direction. The mesa portion refers to a region sandwiched between the trench portions inside the semiconductor substrate 10. As an example, the upper end of the mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the trench portion. The mesa portion in this example is provided on the upper surface of the semiconductor substrate 10, extending in the extension direction (Y-axis direction) along the trench. In this example, the mesa portion 60 is provided in the transistor portion 70, the mesa portion 61 is provided in the diode portion 80, and the mesa portion 62 and the mesa portion 63 are provided in the boundary portion 72. The mesa portion 62 is the mesa portion closest to the transistor portion 70 at the boundary portion 72, and the mesa portion 63 is the mesa portion closest to the diode portion 80 at the boundary portion 72. One or more mesa portions 62 may be further provided between the mesa portion 62 and the mesa portion 63. One or more mesa portions 63 may be further provided between the mesa portion 62 and the mesa portion 63. In this specification, when the term "mesa portion" is simply referred to, it refers to each of the mesa portion 60, the mesa portion 61, the mesa portion 62, and the mesa portion 63.

[0068] A base region 14 is provided in each mesa portion. Of the base regions 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion, the region closest to the active side gate wiring 131 is defined as the base region 14-e. In FIG. 2, the base region 14-e is shown at one end in the extension direction of each mesa portion, but the base region 14-e is also provided at the other end of each mesa portion. In each mesa portion, at least one of the emitter region 12 of the first conductivity type, the contact region 15 of the second conductivity type, and the anode region 17 of the second conductivity type may be provided in a region sandwiched between the base regions 14-e in a top view. In this example, the emitter region 12 is N+ type, the contact region 15 is P+ type, and the anode region 17 is P type. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction. The anode region 17 may be provided in the same depth range as the base region 14. The anode region 17 may have the same doping concentration as the base region 14, or may have a lower doping concentration than the base region 14.

[0069] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 may be provided with a contact region 15 exposed on the upper surface of the semiconductor substrate 10.

[0070] Each of the contact region 15 and the emitter region 12 in the mesa portion 60 is provided from one trench portion to the other trench portion in the X-axis direction. As an example, the contact region 15 and the emitter region 12 in the mesa portion 60 are alternately arranged along the extension direction of the trench portion (the Y-axis direction).

[0071] In another example, the contact region 15 and the emitter region 12 of the mesa portion 60 may be provided in a stripe shape along the extension direction (Y-axis direction) of the trench portion. For example, the emitter region 12 is provided in a region in contact with the trench portion, and the contact region 15 is provided in a region sandwiched between the emitter regions 12.

[0072] The mesa portion 61 of the diode portion 80 does not have an emitter region 12. A base region 14, an anode region 17, and a contact region 15 may be provided on the upper surface of the mesa portion 61. In a region sandwiched between the base regions 14-e on the upper surface of the mesa portion 61, a contact region 15 may be provided in contact with each of the base regions 14-e. In a region sandwiched between the contact regions 15 on the upper surface of the mesa portion 61, an anode region 17 may be provided. The anode region 17 may be disposed in the entire region sandwiched between the contact regions 15.

[0073] A contact region 15 may be provided on the upper surface of the mesa portion 62 at the boundary portion 72. In this example, the contact region 15 is the entire region on the upper surface of the mesa portion 61 that is sandwiched between the base regions 14-e.

[0074] The mesa portion 63 at the boundary portion 72 is not provided with the emitter region 12. The base region 14, the anode region 17, and the contact region 15 may be provided on the upper surface of the mesa portion 63. In the region sandwiched between the base regions 14-e on the upper surface of the mesa portion 63, the contact regions 15 may be provided in contact with each of the base regions 14-e. The anode region 17 may be provided in the region sandwiched between the contact regions 15 on the upper surface of the mesa portion 63. The anode region 17 may be disposed in the entire region sandwiched between the contact regions 15. In the example of FIG. 2, the mesa portion 61 and the mesa portion 63 have the same structure. In another example, the mesa portion 63 may have a structure different from that of the mesa portion 61.

[0075] A trench contact portion 55 is provided in each mesa portion. A contact hole is provided in the interlayer insulating film above the trench contact portion 55. The trench contact portion 55 is disposed in a region sandwiched between the base regions 14-e. The trench contact portion 55 in this example is provided above each of the contact region 15, the base region 14, the anode region 17, and the emitter region 12. The trench contact portion 55 is not provided in a region corresponding to the base region 14-e and the well region 11. The trench contact portion 55 may be disposed in the center of each mesa portion in the arrangement direction (X-axis direction).

[0076] In the diode section 80, an N+ type cathode region 82 is provided in a region in contact with the lower surface of the semiconductor substrate 10. In the region in the lower surface of the semiconductor substrate 10 where the cathode region 82 is not provided, a P+ type collector region 22 may be provided. In the transistor section 70 and the boundary section 72, a collector region 22 is provided in a region in contact with the lower surface of the semiconductor substrate 10. In FIG. 2, the boundary between the cathode region 82 and the collector region 22 is indicated by a dotted line.

[0077] The cathode region 82 is disposed away from the well region 11 in the Y-axis direction. This ensures a distance between the cathode region 82 and a P-type region (well region 11) that has a relatively high doping concentration and is formed deep, thereby improving the breakdown voltage. In this example, the end of the cathode region 82 in the Y-axis direction is disposed farther from the well region 11 than the end of the trench contact portion 55 in the Y-axis direction. In another example, the end of the cathode region 82 in the Y-axis direction may be disposed between the well region 11 and the trench contact portion 55.

[0078] Fig. 3A is a diagram showing an example of an ee cross section in Fig. 2. The ee cross section is an XZ plane passing through the emitter region 12 and the cathode region 82. In this cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24.

[0079] The interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and other insulating films. The interlayer insulating film 38 is provided with the contact hole 54 described in FIG. 2.

[0080] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 is connected to the semiconductor substrate 10 through a contact hole 54 in the interlayer insulating film 38. The inside of the contact hole 54 may be filled with the same conductive material as that of the emitter electrode 52 above the interlayer insulating film 38, or may be filled with a different conductive material. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum. The inside of the contact hole 54 may be filled with tungsten or the like. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (Z-axis direction) is referred to as the depth direction.

[0081] The semiconductor substrate 10 has an N-type or N-type drift region 18. The drift region 18 is provided in each of the transistor portion 70, the boundary portion 72, and the diode portion 80.

[0082] In the mesa portion 60 of the transistor section 70, an N+ type emitter region 12 and a P type base region 14 are provided in this order from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An N+ type accumulation region 16 may be provided in the mesa portion 60. The accumulation region 16 is disposed between the base region 14 and the drift region 18.

[0083] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10, and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The emitter region 12 has a higher doping concentration than the drift region 18.

[0084] The base region 14 is provided below the emitter region 12. In this example, the base region 14 is provided in contact with the emitter region 12. The base region 14 may be in contact with the trench portions on both sides of the mesa portion 60.

[0085] The accumulation region 16 is provided below the base region 14. The accumulation region 16 is an N+ type region having a higher doping concentration than the drift region 18. In other words, the accumulation region 16 has a higher donor concentration than the drift region 18. By providing the high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection enhancement effect (IE effect) can be enhanced and the on-voltage can be reduced. The accumulation region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60.

[0086] The mesa portion 60 may have two or more accumulation regions 16 in the depth direction. Each accumulation region 16 has a peak of doping concentration in the depth direction. Between the two accumulation regions 16, there is a valley of doping concentration in the depth direction. That is, the mesa portion 60 may have two or more doping concentration peaks from the base region 14 toward the drift region 18. The drift region 18 may be provided between the accumulation region 16 and the base region 14, and the accumulation region 16 and the base region 14 may be in contact with each other. The boundary portion 72 and the diode portion 80 may or may not have the accumulation region 16. In this example, the boundary portion 72 and the diode portion 80 do not have the accumulation region 16.

[0087] A P-type anode region 17 is provided in the mesa portion 61 of the diode portion 80 in contact with the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the anode region 17. In any of the structures of the mesa portion 61 described in this specification, the anode region 17 may have the same doping concentration as the base region 14, or may have a doping concentration lower than that of the base region 14. By reducing the concentration of the anode region 17, hole injection in the mesa portion 61 can be suppressed, and reverse recovery loss can be reduced.

[0088] A P+ type contact region 15 is provided in the mesa portion 62 of the boundary portion 72 in contact with the upper surface 21 of the semiconductor substrate 10. The base region 14 or the anode region 17 may be provided between the contact region 15 and the drift region 18, and the contact region 15 and the drift region 18 may be in contact with each other.

[0089] A P-type anode region 17 is provided in the mesa portion 63 of the boundary portion 72 in contact with the upper surface 21 of the semiconductor substrate 10. Below the anode region 17, a drift region 18 is provided.

[0090] In each of the transistor section 70, the boundary section 72, and the diode section 80, an N+ type buffer region 20 may be provided below the drift region 18. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may have a concentration peak having a higher doping concentration than the drift region 18. The doping concentration of the concentration peak refers to the doping concentration at the apex of the concentration peak. The doping concentration of the drift region 18 may be the average value of the doping concentration in a region where the doping concentration distribution is approximately flat.

[0091] The buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peak of the buffer region 20 may be provided at the same depth position as the chemical concentration peak of hydrogen (protons) or phosphorus, for example. The buffer region 20 may function as a field stop layer that prevents the depletion layer spreading from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0092] A P+ type collector region 22 is provided below the buffer region 20 in the transistor portion 70 and the boundary portion 72. The doping concentration of the collector region 22 is higher than the doping concentration of the base region 14. The collector region 22 may contain the same acceptor as the base region 14, or may contain a different acceptor. The acceptor of the collector region 22 is, for example, boron.

[0093] In the diode section 80, an N+ type cathode region 82 is provided under the buffer region 20. The doping concentration of the cathode region 82 is higher than the doping concentration of the drift region 18. The donor of the cathode region 82 is, for example, hydrogen or phosphorus. The elements serving as the donor and acceptor of each region are not limited to the above-mentioned examples. The collector region 22 and the cathode region 82 are exposed to the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum. In the diode section 80, a part of the cathode region 82 may be replaced with a P-type region. The P-type region is disposed between the cathode regions 82. The P-type region may be between the cathode regions 82 in the Y-axis direction.

[0094] At least one gate trench portion 40 and at least one dummy trench portion 30 are provided on the upper surface 21 side of the semiconductor substrate 10. Each trench portion is provided from the upper surface 21 of the semiconductor substrate 10, penetrating the base region 14, to below the base region 14. In a region where at least one of the emitter region 12, the contact region 15, and the accumulation region 16 is provided, each trench portion also penetrates these doped regions. The trench portion penetrating the doped region is not limited to a case where the trench portion is formed in the order of forming the doped region and then the trench portion. A case where the trench portion is formed and then the doped region is formed between the trench portions is also included in the case where the trench portion penetrates the doped region.

[0095] As described above, the transistor section 70 is provided with the gate trench section 40 and the dummy trench section 30. The boundary section 72 is provided with the dummy trench section 30. The boundary section 72 may further be provided with the gate trench section 40. The diode section 80 is provided with the dummy trench section 30, but is not provided with the gate trench section 40.

[0096] The boundary between the collector region 22 and the cathode region 82 may be the boundary in the X-axis direction between the boundary portion 72 and the diode portion 80. When the boundary portion 72 is not provided, the boundary between the collector region 22 and the cathode region 82 may be the boundary in the X-axis direction between the transistor portion 70 and the diode portion 80. Furthermore, of the trench portions in contact with the emitter region 12, the trench portion closest to the diode portion 80 may be the boundary between the transistor portion 70 and the boundary portion 72.

[0097] The gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate insulating film 42 within the gate trench. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0098] The gate conductive portion 44 may be provided longer in the depth direction than the base region 14. The gate trench portion 40 in this cross section is covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench portion 40.

[0099] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided on the inner side of the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.

[0100] The gate trench portion 40 and the dummy trench portion 30 in this example are covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottoms of the dummy trench portion 30 and the gate trench portion 40 may be curved and convex downward (curved in cross section).

[0101] At least one mesa portion 60 of the transistor portion 70 is provided with a trench contact portion 55 and a first bottom region 201 of the second conductivity type. All mesa portions 60 may be provided with the trench contact portion 55 and the first bottom region 201. In the cross section shown in FIG. 3A, the trench contact portion 55 is provided in the depth direction from the upper surface 21 toward the lower surface 23 of the semiconductor substrate 10. The trench contact portion 55 of this example is formed shallower than the lower end of the emitter region 12. The trench contact portion 55 of other examples may be provided to the same depth as the lower end of the emitter region 12, or may be formed deeper than the lower end of the emitter region 12.

[0102] A plug 56 made of a metal such as tungsten may be embedded in the trench contact portion 55. When the plug 56 is embedded in the trench contact portion 55, the upper surface 58 of the plug 56 may be the upper surface 58 of the trench contact portion 55. The upper surface 58 of the plug 56 may be located closer to the emitter electrode 52 (i.e., on the upper side) than the upper surface 21 of the semiconductor substrate 10. When the upper surface 58 of the plug 56 is located closer to the emitter electrode 52 than the upper surface 21, the trench contact portion 55 may be provided from the upper surface 58 of the plug 56 to the lower surface 23 side of the upper surface 21 of the semiconductor substrate 10. That is, the upper surface 58 of the trench contact portion 55 may be located closer to the upper surface 21 than the upper surface of the interlayer insulating film 38, or may be located closer to the emitter electrode 52 than the upper surface 21. Alternatively, the upper surface 58 of the trench contact portion 55 may be provided to the same depth position as the upper surface of the interlayer insulating film 38.

[0103] The first bottom region 201 in this example is a P+ type region having a higher doping concentration than the base region 14. The first bottom region 201 is provided in contact with the bottom of the trench contact portion 55. The first bottom region 201 is connected to the base region 14. At least a part of the first bottom region 201 is provided below the emitter region 12. The first bottom region 201 is provided extending in the Y-axis direction along the trench contact portion 55. The first bottom region 201 is connected to the contact region 15 shown in FIG. 2. According to this example, when the transistor portion 70 is turned off, holes moving from the lower surface 23 toward the emitter region 12 can be made to flow to the contact region 15 or the trench contact portion 55 via the first bottom region 201. This can reduce the resistance of the path through which the holes pass, thereby suppressing latch-up.

[0104] At least one mesa portion 61 of the diode portion 80 is provided with a trench contact portion 55 and a second bottom region 202 of the second conductivity type. All of the mesa portions 61 may be provided with the trench contact portion 55 and the second bottom region 202. The trench contact portion 55 of the diode portion 80 may have the same structure as the trench contact portion 55 of the transistor portion 70. The lower end of the trench contact portion 55 of the diode portion 80 may be disposed inside the anode region 17.

[0105] The second bottom region 202 in this example is a P+ type region having a higher doping concentration than the anode region 17 and the base region 14. The second bottom region 202 is provided in contact with the bottom of the trench contact portion 55. The second bottom region 202 may be provided inside the anode region 17. In other words, the second bottom region 202 does not need to be in contact with the drift region 18. The second bottom region 202 is provided extending in the Y-axis direction along the trench contact portion 55. By providing the second bottom region 202, the contact resistance between the emitter electrode 52 and the semiconductor substrate 10 can be reduced.

[0106] The length in the Y-axis direction of the first bottom region 201 is greater than the length in the Y-axis direction of the second bottom region 202. By making the second bottom region 202 smaller, the amount of holes injected from the upper surface 21 side in the mesa portion 61 can be reduced. This shortens the reverse recovery time of the diode portion 80, and reduces the reverse recovery loss.

[0107] The mesa portion 62 of the boundary portion 72 is provided with a trench contact portion 55. The mesa portion 62 of the boundary portion 72 may be provided closest to the transistor portion 70 in the boundary portion 72. The trench contact portion 55 of the mesa portion 62 may have the same structure as the trench contact portion 55 of the transistor portion 70. The lower end of the trench contact portion 55 of the mesa portion 62 is disposed inside the contact region 15. The lower end of the trench contact portion 55 of the mesa portion 62 is not provided with a P-type bottom region having a doping concentration higher than that of the contact region 15. In another example, a P-type bottom region 204 having a doping concentration higher than that of the contact region 15 may be provided at the lower end of the trench contact portion 55 of the mesa portion 62. In FIG. 3A, the position in the case where the bottom region 204 is provided is indicated by a dotted line. The doping concentration of the contact region 15 may be the doping concentration at the upper surface 21 of the mesa portion 62.

[0108] The mesa portion 63 of the boundary portion 72 is provided with a trench contact portion 55 and a third bottom region 203 of the second conductivity type. The mesa portion 63 of the boundary portion 72 may be provided on the diode portion 80 side of the mesa portion 62 of the boundary portion 72. The trench contact portion 55 and the third bottom region 203 may be provided in all the mesa portions 63. The trench contact portion 55 of the mesa portion 63 may have the same structure as the trench contact portion 55 of the transistor portion 70. The lower end of the trench contact portion 55 of the mesa portion 63 may be disposed inside the anode region 17.

[0109] The third bottom region 203 in this example is a P+ type region having a higher doping concentration than the anode region 17 and the base region 14. The third bottom region 203 is provided in contact with the bottom of the trench contact portion 55. The third bottom region 203 may be provided inside the anode region 17. In other words, the third bottom region 203 does not need to be in contact with the drift region 18. The third bottom region 203 is provided extending in the Y-axis direction along the trench contact portion 55. By providing the third bottom region 203, the contact resistance between the emitter electrode 52 and the semiconductor substrate 10 can be reduced.

[0110] The length of the first bottom region 201 in the Y-axis direction is greater than the length of the third bottom region 203 in the Y-axis direction. By making the third bottom region 203 smaller, the amount of holes injected from the upper surface 21 side in the mesa portion 63 arranged in the vicinity of the diode portion 80 can be reduced. This shortens the reverse recovery time of the diode portion 80, and reduces the reverse recovery loss. The doping concentration, region size, shape, and position on the Y-axis of the third bottom region 203 may be the same as those of the second bottom region 202.

[0111] 3A and the like, the boundary portion 72 has one mesa portion 62 and one mesa portion 63. In another example, the boundary portion 72 may have a plurality of mesa portions 63 between the mesa portion 62 and the diode portion 80. The boundary portion 72 may have a plurality of mesa portions 62 between the mesa portion 63 and the transistor portion 70. By providing the boundary portion 72, a distance between the transistor portion 70 and the diode portion 80 can be secured, and a current can be prevented from flowing between the mesa portion 60 and the cathode region 82, for example.

[0112] Fig. 3B is a diagram showing another example of the ee cross section. In this example, the trench contact portion 55 is formed deeper than in the example of Fig. 3A. The other structures may be similar to those of the semiconductor device 100 shown in Fig. 3A.

[0113] In the mesa portion 60, the trench contact portion 55 is formed deeper than the emitter region 12. In other words, the trench contact portion 55 penetrates the emitter region 12, and the lower end of the trench contact portion 55 is disposed lower than the lower end of the emitter region 12. The lower end of the trench contact portion 55 of the mesa portion 60 may be disposed at the same depth as the base region 14.

[0114] The trench contact portions 55 of the other mesa portions may have the same structure as the mesa portion 60. In this case, the lower end of the trench contact portion 55 of the mesa portion 61 may be disposed at the same depth as the anode region 17. The lower end of the trench contact portion 55 of the mesa portion 62 may be disposed at the same depth as the contact region 15, or may be disposed at the same depth as the base region 14 below the contact region 15. The lower end of the trench contact portion 55 of the mesa portion 63 may be disposed at the same depth as the anode region 17.

[0115] 3A. That is, the trench contact portion 55 of the other mesa portion may be formed shallower than the trench contact portion 55 of the mesa portion 60.

[0116] Similar to the example of FIG. 3A, a bottom region (201, 202, 203, or 204) may be formed at the bottom of each trench contact portion 55. The bottom region 201 may be separated from the emitter region 12 or may be in contact with the emitter region 12. The lower end of the bottom region 201 may be disposed at the same depth as the base region 14. The lower ends of the bottom region 202 and the bottom region 203 may be disposed at the same depth as the anode region 17. The lower end of the bottom region 204 may be disposed at the same depth as the contact region 15 or may be disposed at the same depth as the base region 14.

[0117] 4A is a perspective cross-sectional view showing an example of the mesa portion 60 of the transistor portion 70. The mesa portion 60 shown in FIG. 4A may be referred to as a mesa portion 60-1. FIG. 4A shows an XZ cross section and a top surface (XY surface) of the mesa portion 60-1, and a side surface ( YZ The figure shows the surface.

[0118] The structure of the mesa portion 60-1 in the XZ cross section is similar to that of the mesa portion 60 shown in FIG. 3A. The structure of the mesa portion 60-1 on the upper surface is similar to that of the mesa portion 60 shown in FIG. 2. On the upper surface of the mesa portion 60-1, the emitter regions 12 and the contact regions 15 are alternately arranged along the Y-axis direction. In addition, a trench contact portion 55 is provided at the center of the mesa portion 60-1 in the X-axis direction. Note that in FIG. 4A, the metal inside the trench contact portion 55 is omitted to show the groove structure of the trench contact portion 55.

[0119] As described above, the first bottom region 201 is provided extending in the Y-axis direction along the bottom surface of the trench contact portion 55. In FIG. 4A, the first bottom region 201 is hatched with diagonal lines. The length L1 of the first bottom region 201 in the Y-axis direction may be the same as the length of the trench contact portion 55 in the Y-axis direction. The length L1 of the first bottom region 201 is the length of the first bottom region 201 provided continuously along the Y-axis direction.

[0120] The first bottom region 201 may be formed by forming the groove structure of the trench contact portion 55, injecting acceptor ions from the groove structure, and heat-treating the semiconductor substrate 10. Since the acceptor ions are diffused by the heat treatment, the length L1 of the first bottom region 201 may be slightly longer than the length of the trench contact portion 55 in the Y-axis direction. The difference between the length L1 and the length of the trench contact portion 55 may be 10 μm or less, or may be 5 μm or less. The length L1 may be shorter than the length of the trench contact portion 55. The first bottom region 201 that is shorter than the trench contact portion 55 can be formed by injecting acceptor ions while masking a part of the groove structure of the contact hole 54 or a part of the groove structure of the trench contact portion 55.

[0121] The length L1 of the first bottom region 201 may be smaller than the length in the Y-axis direction of the trench portion (the gate trench portion 40 or the dummy trench portion 30) disposed closest to the first bottom region 201. The first bottom region 201 may be separated from the well region 11 shown in FIG.

[0122] The width in the X-axis direction of the first bottom region 201 may be the same as the width of the bottom surface of the trench contact portion 55, or may be larger than the width of the bottom surface of the trench contact portion 55. The bottom surface of the trench contact portion 55 may be the surface of the trench contact portion 55 that is formed closest to the lower surface 23. The width in the X-axis direction of the first bottom region 201 in this example is larger than the width of the bottom surface of the trench contact portion 55. The width in the X-axis direction of the first bottom region 201 is smaller than the width of the mesa portion 60. The first bottom region 201 is provided away from the trench portion.

[0123] The first bottom region 201 may be exposed to the entire bottom surface of the trench contact portion 55. The first bottom region 201 may also be exposed to a portion of the side surface of the groove structure of the trench contact portion 55.

[0124] FIG. 4B is a perspective cross-sectional view showing another example of the mesa portion 60-1 of the transistor portion 70. The structure of the mesa portion 60-1 in the XZ cross section of this example is similar to that of the mesa portion 60 shown in FIG. 3B. The structure of the mesa portion 60-1 on the upper surface is similar to that of the mesa portion 60 shown in FIG. 2. That is, the mesa portion 60-1 of this example differs from the mesa portion 60-1 shown in FIG. 4A in that the trench contact portion 55 penetrates the emitter region 12. As the trench contact portion 55 is formed deeper, the bottom region 201 is also provided at a deeper position than in the example of FIG. 4A. The other structures are similar to the example of FIG. 4A.

[0125] 5 is a perspective cross-sectional view showing an example of the mesa portion 61 of the diode section 80. The mesa portion 61 shown in FIG. 5 may be referred to as a mesa portion 61-1. FIG. 5 shows an XZ cross section and a top surface (XY surface) of the mesa portion 61-1, and a side surface ( YZ The figure shows the surface.

[0126] The structure of the mesa portion 61-1 in the XZ cross section is similar to that of the mesa portion 61 shown in Fig. 3A. The structure of the mesa portion 61-1 on the upper surface is similar to that of the mesa portion 61 shown in Fig. 2. The anode region 17 and the trench contact portion 55 are disposed on the upper surface of the mesa portion 61-1. The structure of the trench contact portion 55 is similar to that of the trench contact portion 55 in Fig. 4A.

[0127] As described above, the second bottom region 202 is exposed on the bottom surface of the trench contact portion 55. The second bottom region 202 may also be exposed on a part of the side surface of the groove structure of the trench contact portion 55. In FIG. 5, the second bottom region 202 is hatched with diagonal lines. The length L2 of the second bottom region 202 in the Y-axis direction is smaller than the length of the trench contact portion 55 in the Y-axis direction. In the mesa portion 61-1 of this example, the multiple second bottom regions 202 are discretely arranged along the Y-axis direction. The multiple second bottom regions 202 may be arranged at regular intervals in the Y-axis direction. The length L2 of the second bottom region 202 is the length of one second bottom region 202 provided continuously along the Y-axis direction. The trench contact portion 55 of the mesa portion 61-1 may be formed deeper, similar to the trench contact portion 55 shown in FIG. 4B.

[0128] 4A or 4B is greater than the length L2 of the second bottom region 202. This makes it possible to suppress the injection of holes in the diode section 80 while suppressing latch-up in the transistor section 70. Furthermore, by providing the second bottom region 202 in the diode section 80, the contact between the emitter electrode 52 and the anode region 17 in the diode section 80 can be improved.

[0129] The length L1 may be twice or more, five times or more, or ten times or more, of the length L2. The sum of the lengths L1 of one or more first bottom regions 201 in one mesa portion 60 (referred to as the first sum) is greater than the sum of the lengths L2 of the plurality of second bottom regions 202 in one mesa portion 61 (referred to as the second sum). The first sum may be 1.5 times or more, two times or more, or three times or more, of the second sum. The total area of ​​one or more first bottom regions 201 in one mesa portion 60 in a top view (first total area) is greater than the total area of ​​the plurality of second bottom regions 202 in one mesa portion 61 in a top view (referred to as the second total area). The first total area may be 1.5 times or more, two times or more, or three times or more, of the second total area.

[0130] The second bottom region 202 may be formed in a manner similar to that of the first bottom region 201. However, when the second bottom region 202 is formed, acceptor ions are selectively implanted into the trench contact portion 55. The second bottom region 202 may be separate from the well region 11 shown in FIG.

[0131] The width in the X-axis direction of the second bottom region 202 may be the same as or larger than the width of the trench contact portion 55. The width in the X-axis direction of the second bottom region 202 is smaller than the width in the X-axis direction of the mesa portion 61. The second bottom region 202 is provided away from the trench portion.

[0132] The width in the X-axis direction of the second bottom region 202 may be the same as or different from the width in the X-axis direction of the first bottom region 201. The width in the X-axis direction of the second bottom region 202 may be smaller than the width in the X-axis direction of the first bottom region 201. In this case, hole injection in the diode section 80 can be further suppressed.

[0133] The doping concentration of the second bottom region 202 may be the same as or different from the doping concentration of the first bottom region 201. The doping concentration of the second bottom region 202 may be lower than the doping concentration of the first bottom region 201. In this case, hole injection in the diode portion 80 can be further suppressed.

[0134] The mesa portion 63 of the boundary portion 72 may have the same structure as the mesa portion 61 of the diode portion 80. For example, the mesa portion 63 has a third bottom region 203 instead of the second bottom region 202 in the mesa portion 61. The other structures are similar to those of the mesa portion 61.

[0135] The shape, size and arrangement of the third bottom region 203 may be the same as those of the second bottom region 202. That is, the length L1 of the first bottom region 201 in the Y-axis direction is greater than the length of the third bottom region 203 in the Y-axis extension direction. Also, the length L2 of the second bottom region 202 in the Y-axis direction may be the same as the length of the third bottom region 203 in the Y-axis direction. In another example, the second bottom region 202 may be longer or shorter than the third bottom region 203. The doping concentration of the third bottom region 203 may be the same as or different from the doping concentration of the second bottom region 202.

[0136] Also, at least one mesa portion 63 For example, the third bottom region 203 may not be provided in the mesa portion closest to the diode portion 80. 63 The third bottom region 203 may not be provided in the mesa portion. 63 Since the cathode region 82 is not provided below the mesa portion 80, the mesa portion 80 does not function as a diode portion 80. 63 The contact between the third bottom region 203 and the emitter electrode 52 may be low. Furthermore, by omitting the third bottom region 203, the amount of holes injected in the vicinity of the diode portion 80 can be suppressed.

[0137] 6 is a perspective cross-sectional view showing an example of the mesa portion 62 of the boundary portion 72. FIG. 6 shows the XZ cross section and the top surface (XY plane) of the mesa portion 62 and the side surface ( YZ4A shows a cross-sectional view of the mesa portion 62 (XZ cross section). The structure of the mesa portion 62 in the XZ cross section is the same as that of the mesa portion 62 shown in FIG. 3A. The structure of the mesa portion 62 in the upper surface is the same as that of the mesa portion 62 shown in FIG. 2. The contact region 15 and the trench contact portion 55 are arranged on the upper surface of the mesa portion 62. The structure of the trench contact portion 55 is the same as that of the trench contact portion 55 in FIG. 4A. The contact region 15 is exposed on the bottom surface and side surface of the trench contact portion 55 of the mesa portion 62. When the bottom region 204 is provided on the bottom surface of the trench contact portion 55 of the mesa portion 62, the bottom region 204 is exposed on the bottom surface and side surface of the trench contact portion 55 of the mesa portion 62. The trench contact portion 55 of the mesa portion 62 may be formed deeper, similar to the trench contact portion 55 shown in FIG. 4B.

[0138] Fig. 7A shows an example of a YZ cross section taken along line aa shown in Fig. 3A. Fig. 7A shows a cross section of the mesa portion 60 of the transistor portion 70. The cross section passes through the trench contact portion 55. In Fig. 7A, the emitter region 12 and the contact region 15 projected onto the cross section are shown by dashed lines.

[0139] The contact regions 15 and the emitter regions 12 are alternately arranged in the Y-axis direction. The contact regions 15 and the emitter regions 12 are formed to a predetermined depth from the upper surface 21 of the semiconductor substrate 10. The contact regions 15 may be formed to a depth lower than the emitter regions 12.

[0140] The first bottom region 201 is spaced apart in the Y-axis direction. hand The first bottom region 201 connects the two arranged contact regions 15. The first bottom region 201 may connect all of the contact regions 15 provided in the mesa portion 60.

[0141] As an example of a method for manufacturing the semiconductor device 100, the emitter region 12 and the contact region 15 may be formed on the upper surface 21 of the semiconductor substrate 10, and then the groove structure of the trench contact portion 55 may be formed. When forming the groove structure, a part of the emitter region 12 and the contact region 15 is removed. The groove structure is preferably formed shallower than the lower end of the contact region 15. That is, the contact region 15 remains below the groove structure. The groove structure may be formed shallower than the lower end of the emitter region 12, or may be formed deeper than the lower end of the emitter region 12. In the example of FIG. 7A, the groove structure of the trench contact portion 55 is shallower than the lower end of the emitter region 12. That is, the emitter region 12 remains below the bottom surface 210 of the groove structure.

[0142] Next, acceptor ions are implanted from the bottom surface 210 of the groove structure to form a first bottom region 201. At this time, the acceptor ions are implanted at a dose amount that can invert the emitter region 12 below the bottom surface 210 to a P-type region. The bottom of the emitter region 12 indicated by the dashed line in FIG. 7A corresponds to the bottom of the emitter region 12 before the acceptor ions are implanted. The acceptor ions may also be implanted into the region in which the contact region 15 is formed. That is, the first bottom region 201 may be formed so as to overlap with the contact region 15. The doping concentration of the first bottom region 201 and the contact region 15 is superimposed in the overlapping portion, so that the doping concentration is higher than that of the original contact region 15. In this specification, the overlapping portion of the contact region 15 and the first bottom region 201 is also referred to as the first bottom region 201. In the first bottom region 201, portions with a relatively high doping concentration and portions with a relatively low doping concentration may be alternately arranged along the Y-axis direction. In the first bottom region 201 of this example, the doping concentration of the portion overlapping with the contact region 15 is higher than the doping concentration of the portion overlapping with the emitter region 12.

[0143] The first bottom region 201 may have a portion formed at a position deeper than the emitter region 12. At least a portion of the first bottom region 201 is provided on the upper surface 21 side of the lower end 19 of the contact region 15. In the example of FIG. 7A, the entire first bottom region 201 is disposed above the lower end 19 of the contact region 15. By making the contact region 15 protrude downward, holes attracted to the emitter region 12 can be easily extracted via the contact region 15.

[0144] According to this example, hole carriers moving from the drift region 18 toward the emitter region 12 can be caused to flow to the contact region 15 or the trench contact portion 55 via the first bottom region 201. This makes it possible to suppress latch-up of the transistor portion 70.

[0145] FIG. 7B shows another example of the YZ cross section at the line aa shown in FIG. 3A. The mesa portion 60-1 of this example differs from the mesa portion 60-1 shown in FIG. 7A in that the trench contact portion 55 penetrates the emitter region 12. That is, the bottom surface 210 of the trench contact portion 55 is formed deeper than the lower end of the emitter region 12. As the trench contact portion 55 is formed deeper, the bottom region 201 is also provided at a deeper position than in the example of FIG. 7A. The other structures are the same as in the example of FIG. 7A. The bottom region 201 of this example also connects two contact regions 15 adjacent to each other in the Y-axis direction. The bottom region 201 may be separated from the emitter region 12 in the Z-axis direction or may be in contact with the emitter region 12.

[0146] Fig. 8 shows an example of a YZ cross section taken along line bb shown in Fig. 3A. Fig. 8 shows a cross section of the mesa portion 61 of the diode portion 80. The cross section passes through the trench contact portion 55. In Fig. 8, the anode region 17 projected onto the cross section is shown by a dashed line.

[0147] The second bottom regions 202 are arranged discretely along the Y-axis direction. The second bottom regions 202 are formed to a predetermined depth from the bottom surface 210 of the trench contact portion 55. The second bottom regions 202 may be formed shallower than the lower end of the anode region 17.

[0148] As an example of a method for manufacturing the semiconductor device 100, the anode region 17 may be formed on the upper surface 21 of the semiconductor substrate 10, and then the groove structure of the trench contact portion 55 may be formed. Next, acceptor ions are implanted from the bottom surface 210 of the groove structure to form the second bottom region 202. The first bottom region 201 and the second bottom region 202 may be formed in the same process. The dose amount per unit area of ​​the first bottom region 201 and the second bottom region 202 may be the same.

[0149] According to this example, it is possible to suppress hole injection from the second bottom region 202 while ensuring contact between the emitter electrode 52 and the anode region 17. This makes it possible to reduce the reverse recovery loss of the diode portion 80. The trench contact portion 55 of the mesa portion 61 may be formed deeper, similar to the trench contact portion 55 shown in FIG. 7B.

[0150] FIG. 9 shows an example of a YZ cross section on the line cc shown in FIG. 3A. FIG. 9 shows a cross section of the mesa portion 62 at the boundary portion 72. The cross section passes through the trench contact portion 55. In FIG. 9, the contact region 15 projected onto the cross section is shown by a dashed line. As described above, in the mesa portion 62, a bottom region having a higher concentration than the contact region 15 is not formed at the bottom of the trench contact portion 55. Note that, in the case where the bottom region 204 is provided on the bottom surface of the trench contact portion 55 of the mesa portion 62, the bottom region 204 is shown by a dotted line. The trench contact portion 55 of the mesa portion 62 may be formed deeper, similar to the trench contact portion 55 shown in FIG. 7B.

[0151] Fig. 10A shows an XZ cross section in the vicinity of trench contact portion 55 of mesa portion 60. In Fig. 10A, the conductive material inside trench contact portion 55 is omitted and only the groove structure is shown.

[0152] The lower end (bottom surface 210) of the trench contact portion 55 may be located closer to the upper surface 21 of the semiconductor substrate 10 than the lower end 25 of the emitter region 12. In another example, the bottom surface 210 of the trench contact portion 55 may be at the same depth as the lower end 25 of the emitter region 12, and may be located closer to the lower surface 23 than the lower end 25.

[0153] A lower end 27 of the first bottom region 201 is disposed closer to the lower surface 23 than a lower end 25 of the emitter region 12. The lower end 27 of the first bottom region 201 may be disposed inside the base region 14. The first bottom region 201 may have a portion 220 disposed closer to the upper surface 21 than a bottom surface 210 of the trench contact portion 55.

[0154] FIG. 10B shows another example of an XZ cross section in the vicinity of the trench contact portion 55 of the mesa portion 60. The mesa portion 60 of this example differs from the mesa portion 60 shown in FIG. 10A in that the trench contact portion 55 penetrates the emitter region 12. That is, the bottom surface 210 of the trench contact portion 55 is formed deeper than the lower end 25 of the emitter region 12. As the trench contact portion 55 is formed deeper, the bottom region 201 is also provided at a deeper position than in the example of FIG. 10A. The other structures are the same as those in the example of FIG. 10A. The bottom region 201 may be separated from the emitter region 12 in the Z-axis direction or may be in contact with it.

[0155] Fig. 11 is a diagram showing another example of the mesa portion 60 of the transistor portion 70. The mesa portion 60 shown in Fig. 11 is referred to as mesa portion 60-2. The mesa portion 60-2 of this example differs from the mesa portion 60-1 in the structure of the first bottom region 201. Other points are similar to the mesa portion 60-1.

[0156] The mesa portion 60-2 has a plurality of first bottom regions 201 that are discretely arranged along the Y-axis direction. In this example, the first bottom regions 201 may be arranged between two adjacent contact regions 15 in the Y-axis direction. The contact region 15 may be exposed between the two adjacent first bottom regions 201 on the bottom surface of the trench contact portion 55. The trench contact portion 55 of the mesa portion 60-2 may penetrate the emitter region 12, similar to the trench contact portion 55 shown in FIG. 4B.

[0157] 12 is a diagram showing a YZ cross section of the mesa portion 60-2. The first bottom region 201 of this example connects two contact regions 15 adjacent to each other in the Y-axis direction. The first bottom region 201 may or may not have a portion overlapping with the contact region 15. The trench contact portion 55 of the mesa portion 60-2 may penetrate the emitter region 12, similar to the trench contact portion 55 shown in FIG. 7B.

[0158] 13 is a diagram showing an example of the doping concentration distribution on the ff line in FIG. 7A. The ff line is a line passing through the contact region 15 and the first bottom region 201 of the mesa portion 60-1. The position in the depth direction of the upper surface 21 of the semiconductor substrate 10 is Z21, and the position in the depth direction of the bottom surface 210 of the trench contact portion 55 is Z210. In FIG. 13, the doping concentration distribution of the contact region 15 projected onto the cross section of FIG. 7A is shown from position Z21 to position Z210 of the upper surface 21. In FIG. 13, the doping concentration distribution at a position deeper than position Z210 is the distribution below the trench contact portion 55.

[0159] The doping concentration D1 ( / cm 3 ) is the doping concentration D2 ( / cm 3 ) The doping concentration D1 of the first bottom region 201 may be the maximum value of the doping concentration in the P-type region between the position Z210 and the N-type region (e.g., the accumulation region 16 or the drift region 18). The doping concentration at the position Z210 may be the doping concentration D1 of the first bottom region 201.

[0160] The maximum value of the doping concentration in the P-type region from position Z21 to position Z210 may be set as the doping concentration D2 of the contact region 15. The doping concentration at position Z21 may be set as the doping concentration D2 of the contact region 15. The doping concentration D1 may be two or more times, five or more times, or ten or more times the doping concentration D2. Increasing the doping concentration D1 makes it easier to suppress latch-up.

[0161] The first bottom region 201 may have a first concentration peak 251 in the depth direction of the doping concentration. When the apex of the first concentration peak 251 is located at the position Z210, the first concentration peak 251 has a slope from the apex toward the lower surface 23 side, and does not have a slope from the apex toward the upper surface 21 side.

[0162] The contact region 15 may have a second concentration peak 252 in the depth direction of the doping concentration. When the apex of the second concentration peak 252 is located at position Z21, the second concentration peak 252 has a slope from the apex toward the lower surface 23 side, but does not have a slope from the apex toward the upper surface 21 side.

[0163] The half width at half maximum HWHM1 of the first concentration peak 251 may be smaller than the half width at half maximum HWHM2 of the second concentration peak 252. The half width at half maximum HWHM1 may be half or less, ¼ or less, or 1 / 10 or less of the half width at half maximum HWHM2. This allows the doping concentration D1 of the first concentration peak 251 to be increased without increasing the dose of the acceptor ions for forming the first bottom region 201. The half width at half maximum HWHM1 of the first concentration peak 251 can be controlled by the temperature or time of the heat treatment after the acceptor ions are implanted to form the first bottom region 201. Although the doping concentration distribution of the first bottom region 201 has been described in FIG. 13, the second bottom region 202 and the third bottom region 203 may also have the same doping concentration distribution as the first bottom region 201.

[0164] 14 is a diagram showing a structural example of the trench contact portion 55 in each mesa portion. In this example, the trench contact portion 55-1, the trench contact portion 55-2, and the trench contact portion 55-3 in the mesa portion 60, the mesa portion 61, and the mesa portion 63 have different depths. The trench contact portion 55 in the mesa portion 62 may have the same structure as the trench contact portion 55-2 in the mesa portion 61.

[0165] The trench contact portion 55-1 of the mesa portion 60 has a width in the X-axis direction W1 and a depth in the Z-axis direction Z1. The trench contact portion 55-2 of the mesa portion 61 has a width in the X-axis direction W2 and a depth in the Z-axis direction Z2. The trench contact portion 55-3 of the mesa portion 63 has a width in the X-axis direction W3 and a depth in the Z-axis direction Z3. In this example, the width W1, the width W2, and the width W3 are the same. On the other hand, the depth Z2 is greater than the depth Z1. That is, the trench contact portion 55-2 is provided below the contact portion 55-1. By making the depth Z2 greater than the depth Z1, the width of the bottom surface 210-2 of the trench contact portion 55-2 can be made smaller than the width of the bottom surface 210-1 of the trench contact portion 55-1. Therefore, the width in the X-axis direction of the second bottom region 202 provided at the bottom of the trench contact portion 55-2 can be made smaller than the width in the X-axis direction of the first bottom region 201 provided at the bottom of the trench contact portion 55-1, thereby suppressing the injection of holes into the mesa portion 61.

[0166] Moreover, the depth Z3 may be greater than the depth Z2. That is, the trench contact portion 55-3 is provided below the contact portion 55-2. By making the depth Z3 greater than the depth Z2, the width in the X-axis direction of the bottom surface 210-3 of the trench contact portion 55-3 can be made smaller than the width in the X-axis direction of the bottom surface 210-2 of the trench contact portion 55-2. Therefore, the third bottom region 203 provided at the bottom of the trench contact portion 55-3 can be made smaller than the second bottom region 202 provided at the bottom of the trench contact portion 55-2, and the injection of holes in the mesa portion 63 can be suppressed. The depth Z3 may be 1.1 times or more, 1.2 times or more, or 1.5 times or more of the depth Z2. The depth Z2 may be 1.1 times or more, 1.2 times or more, or 1.5 times or more of the depth Z1. The trench contact portion 55 of the mesa portion 60 may extend through the emitter region 12, similar to the trench contact portion 55 shown in FIG. 4B.

[0167] 15 is a diagram showing a structural example of the trench contact portion 55 in each mesa portion. In this example, the trench contact portion 55-1, the trench contact portion 55-2, and the trench contact portion 55-3 in the mesa portion 60, the mesa portion 61, and the mesa portion 63 have different widths in the X-axis direction. The trench contact portion 55 in the mesa portion 62 may have the same structure as the trench contact portion 55-2 in the mesa portion 61.

[0168] The width in the X-axis direction of trench contact portion 55-1 of mesa portion 60 is W1, the width in the X-axis direction of trench contact portion 55-2 of mesa portion 61 is W2, and the width in the X-axis direction of trench contact portion 55-3 of mesa portion 63 is W3. The width of each trench contact portion 55-1 is the width at upper surface 21 of semiconductor substrate 10. Note that each trench contact portion 55 may have the same depth. Each trench contact portion 55 may have a different depth. Each trench contact portion 55 may have the depth shown in FIG. 14.

[0169] The width W2 is smaller than the width W1. By making the width W2 smaller than the width W1, the width of the bottom surface 210-2 of the trench contact portion 55-2 can be made smaller than the width of the bottom surface 210-1 of the trench contact portion 55-1. Therefore, the width in the X-axis direction of the second bottom region 202 provided at the bottom of the trench contact portion 55-2 can be made smaller than the width in the X-axis direction of the first bottom region 201 provided at the bottom of the trench contact portion 55-1, thereby suppressing the injection of holes into the mesa portion 61.

[0170] Moreover, the width W3 may be smaller than the width W2. By making the width W3 smaller than the width W2, the width of the bottom surface 210-3 of the trench contact portion 55-3 can be made smaller than the width of the bottom surface 210-2 of the trench contact portion 55-2. Therefore, the width in the X-axis direction of the third bottom region 203 provided at the bottom of the trench contact portion 55-3 can be made smaller than the width in the X-axis direction of the second bottom region 202 provided at the bottom of the trench contact portion 55-2, and the injection of holes in the mesa portion 63 can be suppressed. The width W1 may be 1.1 times or more, 1.2 times or more, or 1.5 times or more, of the width W2. The width W2 may be 1.1 times or more, 1.2 times or more, or 1.5 times or more, of the width W3. The trench contact portion 55 of the mesa portion 60 may penetrate the emitter region 12, similar to the trench contact portion 55 shown in FIG. 4B.

[0171] 16A is a diagram showing another example of the mesa portion 60 of the transistor portion 70. The mesa portion 60 shown in FIG. 16A is referred to as mesa portion 60-3. The mesa portion 60-3 of this example differs from the mesa portion 60-1 shown in FIG. 4A in that it has a base region 14 instead of the contact region 15. Other points are similar to the mesa portion 60-1 shown in FIG. 4A. This example also allows holes to be extracted via the first bottom region 201 and the trench contact portion 55, so that latch-up of the transistor portion 70 can be suppressed.

[0172] 16B is a diagram showing another example of the mesa portion 60-3. The mesa portion 60-3 of this example differs from the mesa portion 60-1 shown in FIG. 4B in that it has a base region 14 instead of the contact region 15. Other points are similar to the mesa portion 60-1 shown in FIG. 4B. This example also allows holes to be extracted via the first bottom region 201 and the trench contact portion 55, so that latch-up of the transistor portion 70 can be suppressed.

[0173] FIG. 17 is a diagram showing another example of the mesa portion 61 of the diode portion 80. The mesa portion 61 shown in FIG. 17 is referred to as mesa portion 61-2. The mesa portion 61-2 of this example differs from the mesa portion 61-1 in that it has one continuously formed second bottom region 202. Other points are similar to the mesa portion 61-1. The length L2 of the second bottom region 202 may be shorter than the length L1 of the first bottom region 201. In another example, the length L2 of the second bottom region 202 may be the same as the length L1 of the first bottom region 201.

[0174] Also, the doping concentration of the second bottom region 202 may be lower than the doping concentration of the first bottom region 201. In this case, even if the length L2 is the same as the length L1, the amount of holes injected into the mesa portion 61-2 can be suppressed. In another example, the doping concentration of the second bottom region 202 may be the same as the doping concentration of the first bottom region 201. The trench contact portion 55 of the mesa portion 61-2 may be formed deeper, similar to the trench contact portion 55 shown in FIG. 4B.

[0175] Fig. 18 is a diagram showing another example of the mesa portion 61 of the diode portion 80. The mesa portion 61 shown in Fig. 18 is referred to as mesa portion 61-3. The mesa portion 61-3 of this example differs from the mesa portion 61-1 or mesa portion 61-2 in that the emitter region 12 and the anode region 17 are alternately exposed along the Y-axis direction on the upper surface 21. In other respects, it is similar to the mesa portion 61-1 or mesa portion 61-2.

[0176] The transistor section 70 may have the mesa section 60 having any of the configurations described in Figures 1 to 18. The diode section 80 may have the mesa section 61 having any of the configurations described in Figures 1 to 18. The transistor section 70 and the diode section 80 may have any combination of the mesa sections 60 and 61 described above. The trench contact section 55 of the mesa section 61-3 may be formed deeper, similar to the trench contact section 55 shown in Figure 4B.

[0177] 19 is a diagram showing an example of a combination of mesa portions in the semiconductor device 100. In this example, the transistor portion 70 has a mesa portion 60-1. The diode portion 80 has a mesa portion 61-1. The structure of the mesa portion 63 is similar to that of the mesa portion 61-1.

[0178] 20 is a diagram showing another example of a combination of mesa portions in the semiconductor device 100. In this example, the transistor portion 70 has a mesa portion 60-2. The diode portion 80 has a mesa portion 61-1. The structure of the mesa portion 63 is similar to that of the mesa portion 61-1.

[0179] 21 is a diagram showing another example of a combination of mesa portions in the semiconductor device 100. In this example, the transistor portion 70 has a mesa portion 60-1. The diode portion 80 has a mesa portion 61-2. The structure of the mesa portion 63 is similar to that of the mesa portion 61-2.

[0180] 22 is a diagram showing another example of a combination of mesa portions in the semiconductor device 100. In this example, the transistor portion 70 has a mesa portion 60-3. The diode portion 80 has a mesa portion 61-2. The structure of the mesa portion 63 is similar to that of the mesa portion 61-2.

[0181] 23 is a diagram showing another example of a combination of mesa portions in the semiconductor device 100. In this example, the transistor portion 70 has a mesa portion 60-3. The diode portion 80 has a mesa portion 61-3. The structure of the mesa portion 63 is similar to that of the mesa portion 61-3.

[0182] 24 is a diagram showing another example of a combination of mesa portions in the semiconductor device 100. In this example, the transistor portion 70 has a mesa portion 60-3. The diode portion 80 has a mesa portion 61-3. The structure of the mesa portion 63 is similar to that of the mesa portion 61-2.

[0183] 25 is a diagram showing another example of a combination of mesa portions in the semiconductor device 100. The transistor portion 70 in this example has a mesa portion 60-3. The diode portion 80 has a mesa portion 61-2. The structure of the mesa portion 63 is similar to that of the mesa portion 61-3. Note that the combination of mesa portions in the semiconductor device 100 is not limited to the examples in FIGS. 19 to 25.

[0184] Fig. 26 is an ee cross section showing another configuration example of the semiconductor device 100. The semiconductor device 100 of this example differs from the semiconductor device 100 described with reference to Figs. 1 to 25 in the structures of the boundary portion 72 and the diode portion 80. The other structures are similar to any of the semiconductor devices 100 described with reference to Figs. 1 to 25.

[0185] The diode section 80 of this example does not have a trench contact section 55 and a second bottom region 202. The other structures are similar to any of the diode sections 80 described in FIG. 1 to FIG. 25. The boundary section 72 of this example does not have a trench contact section 55 and a third bottom region 203. The other structures are similar to any of the boundary sections 72 described in FIG. 1 to FIG. 25. The trench contact section 55 of this example may be formed deeper, similar to the trench contact section 55 shown in FIG. 3B.

[0186] Fig. 27 is an ee cross section showing another configuration example of the semiconductor device 100. The semiconductor device 100 of this example does not include the boundary portion 72 and the diode portion 80. In other respects, it is similar to any of the semiconductor devices 100 described in Fig. 1 to Fig. 25. The trench contact portion 55 of this example may be formed deeper, similar to the trench contact portion 55 shown in Fig. 3B.

[0187] 26 and 27 has the doping concentration distribution described in FIG. 13. Providing first bottom region 201 having a higher concentration than contact region 15 makes it easier to suppress latch-up. A half width at half maximum HWHM1 of first concentration peak 251 may be smaller than a half width at half maximum HWHM2 of second concentration peak 252.

[0188] 28 is a top view showing another example of the configuration of the semiconductor device 100. In this example, each mesa portion does not have a trench contact portion 55 and a bottom region. The other structures are the same as any of the examples described in FIG. 1 to FIG. 27.

[0189] In the example of FIG. 28, the mesa portion 60 has the emitter regions 12 and the contact regions 15 arranged alternately along the Y-axis direction on the upper surface 21. The mesa portion 61 and the mesa portion 63 have the anode region 17 on the upper surface 21. The anode region 17 may have a lower doping concentration than the base region 14, or may have the same doping concentration as the base region 14. The mesa portion 62 A contact region 15 is provided on the upper surface 21 .

[0190] Fig. 29 is a top view showing another configuration example of the semiconductor device 100. In this example, the structures of the mesa portion 61 and the mesa portion 63 are different from the example in Fig. 28. Other points are similar to the example in Fig. 28. In the mesa portion 61 and the mesa portion 63, the emitter regions 12 and the contact regions 15 are alternately arranged along the Y-axis direction.

[0191] Fig. 30 is a top view showing another configuration example of the semiconductor device 100. In this example, the structure of the mesa portion 61 is different from the example in Fig. 28. Other points are similar to the example in Fig. 28. In the mesa portion 61, the emitter regions 12 and the contact regions 15 are alternately arranged along the Y-axis direction.

[0192] Fig. 31 is a top view showing another configuration example of the semiconductor device 100. In this example, the structures of the mesa portion 61 and the mesa portion 63 are different from the example in Fig. 28. Other points are similar to the example in Fig. 28. In the mesa portion 61 and the mesa portion 63, the anode regions 17 and the contact regions 15 are alternately arranged along the Y-axis direction.

[0193] Fig. 32 is a top view showing another configuration example of the semiconductor device 100. In this example, the structure of the mesa portion 61 is different from the example in Fig. 28. Other points are similar to the example in Fig. 28. In the mesa portion 61, the anode regions 17 and the contact regions 15 are alternately arranged along the Y-axis direction.

[0194] FIG. 33 is a diagram showing another example of the configuration of the semiconductor device 100. The semiconductor device 100 described in FIG. 1 to FIG. 32 has the mesa portion 62, but the semiconductor device 100 of this example does not have the mesa portion 62. The semiconductor device 100 of this example may have a mesa portion 63 instead of the mesa portion 62. The boundary portion 72 may have one or more mesa portions 63 continuously between the transistor portion 70 and the diode portion 80. Except for not having the mesa portion 62, the structure of the semiconductor device 100 of this example is similar to that of any of the semiconductor devices 100 of the aspects described in FIG. 1 to FIG. 32. FIG. 33 shows an example in which the mesa portion 62 is not included in the structure shown in FIG. 2 as an example.

[0195] 34 is a diagram showing an example of an ee cross section in FIG. 33. The semiconductor device 100 of this example differs from the semiconductor device 100 of FIG. 33 in that it has a mesa portion 63 instead of the mesa portion 62. 3 The other structure is different from the semiconductor device 100 shown in FIG. 3 This is similar to the semiconductor device 100 shown in FIG.

[0196] Fig. 35A is a diagram showing another example of the configuration of the semiconductor device 100. The semiconductor device 100 of this example further includes a trench bottom region 260 in addition to the configuration of any of the semiconductor devices 100 described in Fig. 1 to Fig. 34. The trench bottom region 260 may be applied to any of the semiconductor devices 100 described in Fig. 1 to Fig. 34. Fig. 35A shows an example in which the trench bottom region 260 is added to the configuration of the semiconductor device 100 shown in Fig. 3A.

[0197] The trench bottom region 260 is a P-type region provided in contact with the bottom end of the trench portion. The doping concentration of the trench bottom region 260 may be equal to or lower than the doping concentration of the base region 14. In this example, the doping concentration of the trench bottom region 260 is lower than the doping concentration of the base region 14.

[0198] The trench bottom region 260 is provided continuously so as to contact the lower ends of two or more trench portions in the X-axis direction. In other words, the trench bottom region 260 is provided so as to cover the mesa portion between the trench portions. The trench bottom region 260 may cover multiple mesa portions.

[0199] The trench bottom region 260 may be in contact with the lower ends of two or more trench portions in each transistor portion 70. Also, the trench bottom region 260 may be in contact with the lower ends of two or more gate trench portions 40 in each transistor portion 70. The trench bottom region 260 may be in contact with the lower ends of all trench portions in at least one transistor portion 70. Also, the trench bottom region 260 may be in contact with the lower ends of all gate trench portions 40 in at least one transistor portion 70.

[0200] The trench bottom region 260 may contact the bottom ends of two or more trench portions in each diode portion 80. The trench bottom region 260 may contact the bottom ends of all of the trench portions in at least one diode portion 80.

[0201] The trench bottom region 260 may contact the lower ends of two or more trench portions at the boundary 72. The trench bottom region 260 may contact the lower ends of all of the trench portions at the boundary 72. In the example of FIG. 35A, the trench bottom region 260 is provided in all of the mesa portions of the semiconductor device 100.

[0202] The trench bottom region 260 is disposed between an upper surface side P-type region (i.e., the base region 14, the anode region 17, or the contact region 15) disposed on the upper surface 21 side of the semiconductor substrate 10, and the drift region 18. The trench bottom region 260 may be disposed apart from the upper surface side P-type region. An N-type region (at least one of the accumulation region 16 and the drift region 18 in this example) is provided between the trench bottom region 260 and the upper surface side P-type region.

[0203] The trench bottom region 260 is provided extending in the Y-axis direction. The length of the trench bottom region 260 in the Y-axis direction is shorter than the length of the trench portion in the Y-axis direction. Furthermore, the length of the trench bottom region 260 in the Y-axis direction may be 50% or more, 70% or more, or 90% or more of the length of the trench portion in the Y-axis direction.

[0204] Providing trench bottom region 260 can suppress a rise in potential near the bottom end of the trench when semiconductor device 100 is turned on. This can reduce the gradient (dv / dt) of the emitter-collector voltage waveform when turned on, thereby reducing noise in the voltage or current waveform during switching.

[0205] The potential of the trench bottom region 260 is different from the potential of the emitter electrode 52. As described above, the trench bottom region 260 is disposed apart from the base region 14 connected to the emitter electrode 52 in the Z-axis direction. The trench bottom region 260 is also disposed apart from the well region 11 connected to the emitter electrode 52 in a top view. An N-type region such as the drift region 18 may be provided between the well region 11 and the trench bottom region 260. The trench bottom region 260 in this example is a P-type region having a lower doping concentration than the well region 11.

[0206] FIG. 35B is a diagram showing an example of the doping concentration distribution in the aa cross section and the a'-a' cross section in FIG. 35A. The horizontal axis in FIG. 35B indicates the position in the Z-axis direction with the upper surface 21 of the semiconductor substrate 10 as the reference position (0 μm). In FIG. 35B, the doping concentration distribution in the aa cross section is shown by a solid line, and the doping concentration distribution in the a'-a' cross section is shown by a dotted line. A first bottom region 201 and a base region 14 are provided near the bottom surface of the trench contact 55 in the aa cross section. An emitter region 12 and a base region 14 are provided near the upper surface 21 of the semiconductor substrate 10 in the a'-a' cross section. The accumulation region 16 in this example has two peaks 261 in the doping concentration distribution. The doping concentration distribution in the trench bottom region 260 may have a peak 262. The peak value P2 of the doping concentration in the trench bottom region 260 may be smaller than the minimum value P1 of the two peak values ​​of the doping concentration in the accumulation region 16. The peak value P2 of the doping concentration in the trench bottom region 260 may be smaller than the minimum value M1 between the two peaks of the doping concentration in the accumulation region 16. Alternatively, the accumulation region 16 in this example may be smaller than the minimum value M1 between the two peaks of the doping concentration distribution. Peak 261 , and may have a kink shape rather than the minimum value M1.

[0207] Fig. 36 shows an example in which a trench bottom region 260 is added to the structure of the mesa portion 60 shown in Fig. 7A. The trench bottom region 260 extends in the Y-axis direction. The trench bottom region 260 may be provided in a range wider than the first bottom region 201 in the Y-axis direction, may be provided in the same range as the first bottom region 201, or may be provided in a range narrower than the first bottom region 201.

[0208] FIG. 37 shows an example in which a trench bottom region 260 is added to the structure of the mesa portion 61 shown in FIG. 8. The trench bottom region 260 extends in the Y-axis direction. The trench bottom region 260 in the mesa portion 61 may have the same structure as the trench bottom region 260 in the mesa portion 60. In another example, the trench bottom region 260 may be arranged discretely in the Y-axis direction, similar to the first bottom region 201. At least a portion of the trench bottom region 260 may overlap with the first bottom region 201 in a top view. At least a portion of the trench bottom region 260 may not overlap with the first bottom region 201 in a top view.

[0209] Fig. 38 shows an example in which a trench bottom region 260 is added to the structure of the mesa portion 62 shown in Fig. 9. The trench bottom region 260 extends in the Y-axis direction. The trench bottom region 260 in the mesa portion 62 may have the same structure as the trench bottom region 260 in the mesa portion 60.

[0210] Fig. 39 is a diagram showing another configuration example of the semiconductor device 100. The semiconductor device 100 of this example differs from the semiconductor device 100 shown in Fig. 35A in the range in which the trench bottom region 260 is provided. The other structures are similar to the example of Fig. 35A. The trench bottom region 260 of this example may also be applied to any of the semiconductor devices 100 of the forms described in Figs. 1 to 34.

[0211] The trench bottom region 260 of this example is provided in at least a portion of the transistor section 70. In the example of Fig. 39, the trench bottom region 260 is provided across the entire transistor section 70 in the X-axis direction.

[0212] The trench bottom region 260 may be provided in at least a portion of the boundary portion 72. In this example, the trench bottom region 260 is provided in at least a portion of the mesa portion of the boundary portion 72 that is closest to the transistor portion 70. The trench bottom region 260 may extend from the transistor portion 70 to partway across the boundary portion 72.

[0213] The trench bottom region 260 may or may not be provided in at least a part of the diode section 80. In this example, the trench bottom region 260 is not provided in the diode section 80. The aa cross section in FIG. 39 is similar to the example shown in FIG. 36. The bb cross section and the cc cross section in FIG. 39 are similar to any of the examples described in FIG. 1 to FIG. 34.

[0214] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included in the technical scope of the present invention.

[0215] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically indicated as "before," "prior to," etc., and may be realized in any order unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is explained using "first," "next," etc. for convenience, it does not mean that it is essential to perform the process in this order. [Explanation of symbols]

[0216] 10 semiconductor substrate, 11 well region, 12 emitter region, 14 base region, 15 contact region, 16 accumulation region, 17 anode region, 18 drift region, 19 bottom end, 20 buffer region, 21 top surface, 22 collector region, 23 bottom surface, 24 collector electrode, 25 bottom end , 27 bottom end, 29 straight portion, 30 dummy trench portion, 31 tip portion, 32 dummy insulating film, 34 dummy conductive portion, 38 interlayer insulating film, 39 straight portion, 40 gate trench portion, 41 tip portion, 42 gate insulating film, 44 gate conductive portion, 52 emitter electrode, 54 contact hole , 55 trench contact portion, 56 plug, 58 upper surface, 60, 61, 62, 63 mesa portion, 70 transistor portion, 72 boundary portion, 80 diode portion, 81 extension region, 82 cathode region, 90 edge termination structure portion, 100 semiconductor device, 130 peripheral gate wiring, 131 active side gate 1. A trench wiring, 160... active portion, 162... edge, 164... gate pad, 201... first bottom region, 202... second bottom region, 203... third bottom region, 204... bottom region, 210... bottom surface, 220... portion, 251... first concentration peak, 252... second concentration peak, 260... trench bottom region, 261, 262... peak

Claims

1. a semiconductor substrate having an upper surface and a lower surface and having a first conductivity type drift region provided therein; A transistor portion provided on the semiconductor substrate; a diode portion provided on the semiconductor substrate; Equipped with each of the transistor portion and the diode portion is provided in a depth direction of the semiconductor substrate from the top surface of the semiconductor substrate and has one or more trench contact portions extending in an extension direction on the top surface of the semiconductor substrate; the transistor portion has a first bottom region of a second conductivity type provided in contact with a bottom of any one of the trench contact portions; the diode portion has a second bottom region of a second conductivity type provided in contact with a bottom of any one of the trench contact portions; The length of the first bottom region in the extension direction is greater than the length of the second bottom region in the extension direction. Semiconductor device.

2. In the diode portion, a plurality of the second bottom regions are discretely arranged along the extending direction. The semiconductor device according to claim 1 .

3. a boundary portion provided between the transistor portion and the diode portion and including one or more of the trench contact portions; the boundary portion has a third bottom region of a second conductivity type provided in contact with a bottom of any one of the trench contact portions; The length of the first bottom region in the extension direction is greater than the length of the third bottom region in the extension direction. The semiconductor device according to claim 1 .

4. The length of the second bottom region in the extension direction is the same as the length of the third bottom region in the extension direction. The semiconductor device according to claim 3 .

5. The transistor portion is an emitter region of a first conductivity type provided in contact with the upper surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; a second conductivity type base region provided between the emitter region and the drift region; a contact region of a second conductivity type provided in contact with the upper surface of the semiconductor substrate, connected to the base region, and having a doping concentration higher than that of the base region; a gate trench portion in contact with the emitter region and the base region and provided from the upper surface toward the lower surface, The extension direction is the longitudinal direction in which the gate trench portion extends. The semiconductor device according to claim 1 .

6. the contact regions are arranged alternately with the emitter regions in the extension direction; The first bottom region connects two of the contact regions that are spaced apart in the extending direction. The semiconductor device according to claim 5 .

7. A portion of the first bottom region is provided closer to the upper surface of the semiconductor substrate than a lower end of the contact region. The semiconductor device according to claim 6.

8. The doping concentration of the first bottom region is higher than the doping concentration of the contact region. The semiconductor device according to claim 7.

9. the first bottom region has a first concentration peak in a depth direction of a doping concentration; the contact region has a second concentration peak in a depth direction of the doping concentration; The half width at half maximum of the first concentration peak is smaller than the half width at half maximum of the second concentration peak. The semiconductor device according to claim 8.

10. A lower end of the trench contact portion is disposed closer to the upper surface of the semiconductor substrate than a lower end of the emitter region. The semiconductor device according to claim 5 .

11. The trench contact portion of the diode portion is provided below the trench contact portion of the transistor portion. The semiconductor device according to claim 1 .

12. The trench contact portion of the diode portion has a smaller width on the upper surface of the semiconductor substrate than the trench contact portion of the transistor portion. The semiconductor device according to claim 1 .

13. The trench contact portion of the boundary portion is provided below both the trench contact portion of the diode portion and the trench contact portion of the transistor portion.

5. The semiconductor device according to claim 3.

14. The trench contact portion of the boundary portion has a width on the upper surface of the semiconductor substrate smaller than both the trench contact portion of the diode portion and the trench contact portion of the transistor portion.

5. The semiconductor device according to claim 3.

15. the diode portion has an anode region of a second conductivity type provided between the drift region and the upper surface of the semiconductor substrate, The doping concentration of the anode region is lower than the doping concentration of the base region. The semiconductor device according to claim 5 .

16. The transistor portion further includes a plurality of accumulation regions provided in the depth direction between the base region and the drift region, the accumulation regions having a doping concentration higher than that of the drift region. The semiconductor device according to claim 5 .

17. a semiconductor substrate having an upper surface and a lower surface and having a first conductivity type drift region provided therein; A transistor portion provided on the semiconductor substrate; Equipped with The transistor portion is one or more trench contact portions provided in a depth direction of the semiconductor substrate from the top surface of the semiconductor substrate; a first bottom region of a second conductivity type provided in contact with a bottom of any one of the trench contact portions; an emitter region of a first conductivity type provided in contact with the upper surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; a second conductivity type base region provided between the emitter region and the drift region; a contact region of a second conductivity type provided in contact with the upper surface of the semiconductor substrate, connected to the base region, and having a doping concentration higher than that of the base region; having a doping concentration of the first bottom region is higher than a doping concentration of the contact region; the bottom of the trench contact portion is disposed closer to the top surface of the semiconductor substrate than a lower end of the contact region; The entire first bottom region is disposed above a lower end of the contact region. Semiconductor device.

18. the first bottom region has a first concentration peak in a depth direction of a doping concentration; the contact region has a second concentration peak in a depth direction of the doping concentration; The half width at half maximum of the first concentration peak is smaller than the half width at half maximum of the second concentration peak. The semiconductor device according to claim 17.

19. the trench contact portion extends in an extension direction on the top surface of the semiconductor substrate, The first bottom regions are arranged discretely along the extension direction.

19. The semiconductor device according to claim 17 or 18.

20. The bottom of the trench contact portion is disposed closer to the upper surface of the semiconductor substrate than a lower end of the emitter region.

19. The semiconductor device according to claim 17 or 18.

21. the bottom of the trench contact portion is located closer to the top surface of the semiconductor substrate than a lower end of the emitter region; A lower end of the first bottom region is disposed closer to the lower surface of the semiconductor substrate than the lower end of the emitter region.

19. The semiconductor device according to claim 17 or 18.

22. the trench contact portion extends in an extension direction on the top surface of the semiconductor substrate, The length of the first bottom region in the extension direction is smaller than the length of the trench contact portion in the extension direction.

19. The semiconductor device according to claim 17 or 18.

23. Further comprising a diode portion provided on the semiconductor substrate, each of the transistor portion and the diode portion is provided in a depth direction of the semiconductor substrate from the top surface of the semiconductor substrate and has one or more trench contact portions extending in an extension direction on the top surface of the semiconductor substrate; the diode portion has a second bottom region of a second conductivity type provided in contact with a bottom of any one of the trench contact portions; The length of the first bottom region in the extension direction is smaller than the length of the second bottom region in the extension direction.

19. The semiconductor device according to claim 17 or 18.

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