Semiconductor device and its manufacturing method

Abstract

To obtain a semiconductor device having a built-in gate resistance region where a resistance value for a gate electrode of a switching element is easily adjusted.SOLUTION: All of four of built-in gate resistance trenches 8 function as practical built-in gate resistance trenches. One end portion of each of four of the built-in gate resistance trenches 8 is electrically connected to a wiring side contact region 30 of a gate wiring 3 via a wiring contact 9L. The other end portion is electrically connected to a pad side contact region 40 of a gate pad 4 via a pad contact 9P. In each of four of the built-in gate resistance trenches 8, a distance between the wiring contact 9L and the pad contact 9P is defined as an inter-contact distance Lr.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device having a switching element with an insulated gate structure, and more particularly to a semiconductor device in which the built-in gate resistance value for the gate electrode of the switching element can be easily adjusted, and a method for manufacturing the same. [Background technology]

[0002] In recent years, switching elements with an insulated gate structure, such as IGBTs and MOSFETs, have been adopted as power semiconductor elements. In order to control the switching speed of the switching elements, a resistive element integrated on a chip may be used as an internal gate resistor for the gate electrode of the switching element.

[0003] For example, Patent Document 1 proposes a structure in which a trench-type internal gate resistor is formed as an internal gate resistor for a gate electrode, thereby reducing the area of ​​the internal gate resistor in plan view while suppressing the gate current density. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2013-062523 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the conventional structure disclosed in Patent Document 1 and the like, it was common to connect the trench-type internal gate resistor and the gate electrode of the switching element formed in the cell section with polysilicon wiring, and the gate electrode has a trench gate structure.

[0006] For this reason, in order to control the resistance value of the gate electrode, it is necessary to change multiple patterns such as the trench, polysilicon wiring, and contacts, and there is a problem that it is not easy to adjust the resistance value. This is because multiple masks must be prepared to correspond to multiple patterns. Note that the trench corresponds to the trench-type built-in gate resistor and the trench gate of the switching element.

[0007] Furthermore, the conventional structure has a problem in that the internal gate resistor region is easily subjected to stress because of the relatively thick thermal oxide film around it. The thermal oxide film is used as a field oxide film or LOCOS.

[0008] The present disclosure has been made to solve the problems described above, and aims to provide a semiconductor device having an internal gate resistance region that is electrically connected to a gate electrode of a switching element and whose resistance value is easily adjusted. [Means for solving the problem]

[0009] A semiconductor device according to the present disclosure is a semiconductor device including a switching element of an insulated gate structure, the switching element being provided on a semiconductor substrate of a first conductivity type, a gate wiring provided on the semiconductor substrate via an interlayer insulating film and electrically connected to a gate electrode of the switching element, a gate pad provided on the semiconductor substrate via the interlayer insulating film and having an electrical connection region with an exposed surface, and an internal gate resistance region electrically connecting the gate wiring and the gate pad, the internal gate resistance region including N (N≧2) partial internal gate resistance regions connected in parallel between the gate wiring and the gate pad, and the N partial internal gate resistance regions each having the gate pad has a pad-side contact region overlapping with the M built-in gate resistor trenches in a planar view, and the M built-in gate resistor trenches are each embedded in the semiconductor substrate. Among the M built-in gate resistor trenches, K (M≧K≧2) trenches function as practical built-in gate resistor trenches, and the K practical built-in gate resistor trenches are each connected to the gate wiring via a wiring contact provided through the interlayer insulating film. a pad contact formed through the interlayer insulating film, the pad contact region of the gate pad being electrically connected to the wiring contact region, and the pad contact being electrically connected to the pad contact region of the gate pad via the pad contact formed through the interlayer insulating film, a gate current path is provided between the wiring contact and the pad contact in each of the K practical built-in gate resistor trenches, a distance between the wiring contact and the pad contact in the gate current path is defined as a contact distance, and the K practical built-in gate resistor trenches are physically connected to the wiring contact and the pad contact, respectively. , M>K, each of the M built-in gate resistor trenches has a rectangular shape in a plan view with a longer side in a first direction and a shorter side in a second direction, the M built-in gate resistor trenches have 1st to Mth built-in gate resistor trenches arranged in the second direction in the order of 1st, 2nd, ..., Mth, at least one of the M built-in gate resistor trenches is an unused built-in gate resistor trench, the first built-in gate resistor trench and the Mth built-in gate resistor trench do not fall under the at least one unused built-in gate resistor trench, and the at least one unused built-in gate resistor trench does not have an electrical connection relationship between the gate wiring and the gate pad, . Effect of the Invention

[0010] In the semiconductor device disclosed herein, a gate current path is provided between a wiring contact and a pad contact in each of K practical built-in gate resistor trenches, and the distance between the wiring contact and the pad contact in the gate current path is defined as the contact-to-contact distance.

[0011] Therefore, the resistance value of the gate current path of each of the K practical internal gate resistor trenches can be adjusted by the contact distance. Furthermore, by adjusting the number K of practical internal gate resistor trenches, the resistance value of each of the N partial internal gate resistor regions can be adjusted.

[0012] As a result, the semiconductor device disclosed herein enables the resistance value of the internal gate resistor region including N partial internal gate resistor regions to be relatively easily adjusted during manufacture based on the contact distance and the number K of practical internal gate resistor trenches. [Brief description of the drawings]

[0013] [Figure 1] 1 is an explanatory diagram illustrating a planar structure of a first mode of the semiconductor device of the first embodiment; [Diagram 2] FIG. 2 is an explanatory diagram illustrating a planar structure of a second mode of the first embodiment. [Diagram 3] FIG. 11 is an explanatory diagram illustrating a planar structure of a third mode of the first embodiment. [Figure 4] 4 is a cross-sectional view showing a cross-sectional structure of an IGBT provided in the cell region shown in FIGS. 1 to 3. [Diagram 5] 2 is an explanatory diagram illustrating a schematic diagram of a detailed structure of the gate pad peripheral region illustrated in FIG. 1. [Figure 6] 6 is an enlarged plan view showing the internal gate resistor peripheral region of FIG. 5. [Figure 7] 7 is a cross-sectional view showing a cross-sectional structure taken along the line AA in FIG. 6. [Figure 8] 13 is a graph showing the resistance value dependency of an internal gate resistor trench in the semiconductor device of the second embodiment. [Figure 9] 13 is an enlarged plan view showing an internal gate resistor peripheral region in a semiconductor device of a third embodiment. FIG. [Figure 10] 13 is an enlarged plan view showing an internal gate resistor peripheral region in a semiconductor device according to a fourth embodiment. FIG. [Figure 11] 13 is an enlarged plan view showing an internal gate resistor peripheral region in a semiconductor device according to a fifth embodiment. FIG. [Figure 12] 13 is an enlarged plan view showing an internal gate resistor peripheral region in a semiconductor device according to a sixth embodiment. FIG. [Figure 13] 13 is an explanatory diagram illustrating a schematic detailed structure of a gate pad peripheral region in a semiconductor device according to a seventh embodiment. FIG. [Figure 14] 13 is an explanatory diagram illustrating a schematic detailed structure of a gate pad peripheral region in a semiconductor device according to an eighth embodiment. FIG. [Figure 15] 13 is a cross-sectional view showing a cross-sectional structure taken along line AA of FIG. 6 according to a ninth embodiment. [Figure 16] FIG. 16 is a cross-sectional view showing a cross-sectional structure taken along line AA of FIG. 6 according to a tenth embodiment. [Figure 17] FIG. 22 is a cross-sectional view showing a cross-sectional structure taken along line BB in FIG. 6 according to the eleventh embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] <Embodiment 1> 1 to 3 are explanatory diagrams each showing a schematic planar structure of a semiconductor device according to a first embodiment of the present disclosure. A semiconductor device 101A shown in Fig. 1 is a first aspect of the first embodiment, a semiconductor device 101B shown in Fig. 2 is a second aspect of the first embodiment, and a semiconductor device 101C shown in Fig. 3 is a third aspect of the first embodiment. Hereinafter, when semiconductor devices 101A to 101C are collectively referred to, they may be simply referred to as "semiconductor device 101."

[0015] As shown in these figures, a semiconductor device 101 includes a cell region 1, a gate wiring 3, a gate pad 4, an internal gate resistor region 5, and a termination region 6 as main components.

[0016] The cell region 1 has a rectangular shape with rounded corners in plan view, except for some cell missing regions. The semiconductor device 101 has an IGBT in the cell region 1 as a switching element with an insulated gate structure.

[0017] 1, in a cell missing region where the cell region 1 is not formed, a gate wiring 3 that runs vertically from the top to the center of the cell region 1 in the figure and a gate pad peripheral region A1 are provided. The gate pad peripheral region A1 is disposed in the center below the cell region 1.

[0018] In a semiconductor device 101B of the second embodiment shown in Fig. 2, a gate pad peripheral area A2 is provided in the cell missing area. The gate pad peripheral area A2 is located in the lower left of the figure. In a semiconductor device 101C of the third embodiment shown in Fig. 3, the cell missing area is provided with a gate wiring 3 that runs vertically from the upper center to the lower center, and a gate pad peripheral area A3. The gate pad peripheral area A3 is located in the center of the figure.

[0019] Each of the gate pad peripheral regions A1 to A3 has a gate pad 4 provided in the center in a planar view, an internal gate resistance region 5 provided surrounding the outer periphery of the gate pad 4 in a planar view, and a gate wiring 3 provided surrounding the outer periphery of the internal gate resistance region 5 in a planar view.

[0020] An IGBT 50 (not shown in FIGS. 1 to 3) is provided in a cell region 1 of the semiconductor device 101, and a trench gate 2 which is a gate electrode of the IGBT 50 is provided in the cell region 1, extending in the lateral direction in the drawings.

[0021] The gate wiring 3 is also provided in the outer periphery of the cell region 1 and is electrically connected to the trench gate 2 .

[0022] Gate pad 4 has an electrical connection region with an exposed surface. This electrical connection region allows electrical connection to the outside. As described above, internal gate resistance region 5 is provided surrounding the periphery of gate pad 4, and gate wiring 3 is provided surrounding internal gate resistance region 5.

[0023] Gate wiring 3 and gate pad 4 are electrically connected via an internal gate resistance region 5. Furthermore, a termination region 6 is provided surrounding the peripheral region of gate wiring 3.

[0024] The gate wiring 3 may be provided around the entire periphery of the cell region 1 as in the semiconductor device 101A and the semiconductor device 101C, or may be provided on a part of the outer periphery of the cell region 1 as in the semiconductor device 101B. In the semiconductor device 101B, the gate wiring 3 is not provided in the peripheral region at the upper side of the cell region 1 in the figure.

[0025] Also, like the semiconductor device 101A and the semiconductor device 101C, the gate wiring 3 may be provided so as to run vertically through the center of the cell region 1 in the figure.

[0026] The gate pad 4 may be positioned in the lower center of the cell region 1 in the figure, as in semiconductor device 101A, or in the center of the cell region 1 in the figure, as in semiconductor device 101C, or in the lower left corner of the cell region 1 in the figure, as in semiconductor device 101B.

[0027] FIG. 4 is a cross-sectional view showing the cross-sectional structure of an IGBT 50 provided in the cell region 1. As shown in FIG.

[0028] 4, the semiconductor substrate 11 includes, from top to bottom, a range from a drift layer 21 including a base layer 22 to a collector layer 26. The base layer 22 includes an emitter layer 23 and a contact layer 24 formed thereon.

[0029] 4, the upper end of drift layer 21 including base layer 22 on the paper surface is called the first main surface of semiconductor substrate 11, and the lower end of collector layer 26 on the paper surface is called the second main surface of semiconductor substrate 11. The first main surface of semiconductor substrate 11 is the main surface on the front surface side of semiconductor device 101, and the second main surface of semiconductor substrate 11 is the main surface on the back surface side of semiconductor device 101.

[0030] Thus, the semiconductor substrate 11 includes the drift layer 21, the buffer layer 25, and the collector layer .

[0031] A buffer layer 25 is provided adjacent to the second main surface side of the n-type drift layer 21, which is the first conductivity type. The buffer layer 25 has a higher n-type impurity concentration than the drift layer 21. + It shows a type.

[0032] A collector layer 26 is provided adjacent to the second main surface side of the buffer layer 25. The collector layer 26 is a p-type semiconductor having a relatively high impurity concentration of p-type, which is a second conductivity type. + A collector electrode 28 is provided on the second major surface of the collector layer 26.

[0033] A base layer 22 is provided on the first main surface side in the drift layer 21. The base layer 22 has a second conductivity type, that is, a p-type.

[0034] A plurality of trench gates 2 are formed, penetrating the emitter layer 23 and the base layer 22 from the first main surface of the semiconductor substrate 11 to reach the drift layer 21. The plurality of trench gates 2 are provided with buried gate electrodes 2b serving as buried gate electrodes via gate insulating films 2a serving as gate trench insulating films.

[0035] A plurality of n + A type emitter layer 23 is provided. Each of the multiple emitter layers 23 is provided adjacent to a corresponding one of the multiple trench gates 2.

[0036] Between the adjacent buried gate electrodes 2b, 2b, the p+ A contact layer 24 is provided on the trench gate 2. The contact layer 24 is provided so as to be in contact with each of a pair of emitter layers 23 present on both sides. The emitter layers 23 and the contact layers 24 may be formed alternately along the extension direction of the trench gate 2.

[0037] Furthermore, an interlayer insulating film 10 is provided on the first main surfaces of the multiple trench gates 2.

[0038] The emitter electrode 27 is provided over the entire region on the first main surface of the semiconductor substrate 11 via the interlayer insulating film 10. Therefore, the emitter electrode 27 is electrically connected to the emitter layer 23 and the contact layer 24.

[0039] The IGBT 50 is configured by mainly comprising the trench gate 2, drift layer 21, base layer 22, emitter layer 23, contact layer 24, buffer layer 25, collector layer 26, emitter electrode 27, and collector electrode 28. In the structure shown in Fig. 4, the IGBT 50 is an n-channel IGBT, and serves as a switching element with an insulated gate structure.

[0040] To be precise, the trench gate 2 shown in FIGS. 1 to 3 means the buried gate electrode 2b.

[0041] 5 is an explanatory diagram showing a schematic diagram of the detailed structure of the gate pad peripheral region A1. The detailed structures of the gate pad peripheral regions A2 and A3 are similar to that of the gate pad peripheral region A1. In the following, the gate pad peripheral region A1 will be described as a representative example.

[0042] As shown in the figure, the gate pad 4 has a pad main region 4M provided in the center, and four pad side contact regions 40 provided extending in a direction from the pad main region 4M toward the gate wiring 3.

[0043] The pad main region 4M has a rectangular shape in a plan view and serves as an electrical connection region with an exposed surface, allowing electrical connection to the outside through the pad main region 4M.

[0044] As shown in the figure, the gate wiring 3 has a peripheral wiring region 3P provided along the periphery of the gate pad 4, and four wiring side contact regions 30 provided extending in a direction from the peripheral wiring region 3P toward the gate pad 4. The four wiring side contact regions 30 and the four pad side contact regions 40 are in one-to-one correspondence.

[0045] Of the four wiring side contact regions 30 and four pad side contact regions 40, an internal gate resistor unit 7 is provided between corresponding wiring side contact regions 30 and pad side contact regions 40. Therefore, the four internal gate resistor units 7 are provided in one-to-one correspondence with the four wiring side contact regions 30 and four pad side contact regions 40. The internal gate resistor units 7 electrically connect the corresponding wiring side contact regions 30 and pad side contact regions 40.

[0046] The four internal gate resistor units 7 function as N (N≧2) partial internal gate resistor regions, are provided facing the four sides of pad main region 4M in plan view, and are classified into first to fourth partial internal gate resistor regions, where {N=4} in the first embodiment.

[0047] In the first embodiment, the four internal gate resistor units 7 have the same resistance value R0. Note that the resistance values ​​of some of the four internal gate resistor units 7 may be set to different values.

[0048] Fig. 6 is an enlarged plan view showing the internal gate resistor peripheral region B1 of Fig. 5. Fig. 7 is a cross-sectional view showing the cross-sectional structure taken along the line AA of Fig. 6. An XYZ orthogonal coordinate system is depicted in each of Figs. 6 and 7.

[0049] As shown in these figures, in the gate pad 4, a pad side contact region 40 is provided extending in the -Y direction from the pad main region 4M, and in the gate wiring 3, a wiring side contact region 30 is provided extending in the +Y direction from the peripheral wiring region 3P. The pad side contact region 40 and the wiring side contact region 30 are provided without overlapping each other in a plan view.

[0050] In the semiconductor device 101 of embodiment 1, the wiring side contact region 30 is provided outside the peripheral wiring region 3P, and the pad side contact region 40 is provided outside the pad main region 4M, so that the pad wiring distance Wm between the gate wiring 3 and the gate pad 4 is relatively short.

[0051] In plan view, four built-in gate resistor trenches 8 are provided from pad-side contact region 40 to wiring-side contact region 30. Each of the four built-in gate resistor trenches 8 has a rectangular shape in plan view, and has long sides extending in the X direction and short sides extending in the Y direction.

[0052] 6, the four internal gate resistor trenches 8 have the same shape, and each of the internal gate resistor trenches 8 has a constant resistor trench width Wr in the short side direction. Parts of the four internal gate resistor trenches 8 overlap with the pad-side contact region 40 in plan view, and other parts overlap with the wiring-side contact region 30 in plan view.

[0053] In this way, the gate wiring 3 has wiring-side contact regions 30 overlapping in plan view with M (M≧2) built-in gate resistor trenches 8, and the gate pad 4 has pad-side contact regions 40 overlapping in plan view with M built-in gate resistor trenches 8. In the example shown in FIG. 6, {M=4}.

[0054] As shown in Fig. 7, internal gate resistor trench 8 is embedded in semiconductor substrate 11 of n-type, which is a first conductivity type, and includes trench insulating film 8a and trench electrode 8b as main components. For convenience of explanation, only a region of semiconductor substrate 11 corresponding to drift layer 21 shown in Fig. 4 is shown in Fig. 7.

[0055] Parameters such as the resistor trench width Wr and the contact distance Lr of the internal gate resistor trench 8 are, more precisely, parameters related to the trench electrode 8b which is a resistance component. More precisely, the resistor trench width Wr is the formation width of the trench electrode 8b, and the contact distance Lr is the distance between the pad contact 9P and the wiring contact 9L in the trench electrode 8b.

[0056] The trench electrode 8b has a resistive trench depth Dr, and the trench insulating film 8a is provided so as to cover the entire periphery of the trench electrode 8b. Therefore, the trench electrode 8b is not electrically connected to the semiconductor substrate 11.

[0057] To be precise, the electrical connection of the internal gate resistor trench 8 is made by trench electrode 8b which becomes a resistance component in the internal gate resistor trench 8. For convenience of explanation, in this specification, this may be described as "electrical connection of the internal gate resistor trench 8."

[0058] As shown in FIG. 7, an interlayer insulating film 10 is provided on a first main surface of a semiconductor substrate 11 including a trench gate 2, and a gate wiring 3 and a gate pad 4 are provided on the interlayer insulating film 10.

[0059] It should be noted that interlayer insulating film 10 is omitted in Fig. 6. Furthermore, in order to clearly show the shapes of the four internal gate resistor trenches 8 and the positions of the internal gate resistor contacts 9, a part of the wiring-side contact region 30 and a part of the pad-side contact region 40 present on the four internal gate resistor trenches 8 are omitted in Fig. 6.

[0060] 6, all four internal gate resistor trenches 8 function as practical internal gate resistor trenches. That is, of M internal gate resistor trenches 8, K (M≧K≧2) serve as practical internal gate resistor trenches. In the first embodiment, {K=M=4}.

[0061] As shown in Figures 6 and 7, one end on the -X side of each of the four built-in gate resistor trenches 8 is electrically connected to the wiring side contact region 30 of the gate wiring 3 via a wiring contact 9L provided to penetrate the interlayer insulating film 10.

[0062] The other end on the +X side of each of the four internal gate resistor trenches 8 is electrically connected to pad-side contact region 40 of gate pad 4 via pad contact 9P provided to penetrate interlayer insulating film 10.

[0063] Hereinafter, when the wiring contacts 9L and the pad contacts 9P are collectively referred to, they may be referred to as the "internal gate resistor contacts 9." That is, the internal gate resistor contacts 9 include the wiring contacts 9L and the pad contacts 9P.

[0064] Therefore, in each of the four built-in gate resistor trenches 8, each of which functions as a practical built-in gate resistor trench, a gate current path is provided between the pad contact 9P and the wiring contact 9L, and the distance between the wiring contact 9L and the pad contact 9P in the gate current path is defined as the contact distance Lr.

[0065] Therefore, resistance value R0 of one unit of internal gate resistor unit 7 has a characteristic that satisfies the following formula (1) using the above-mentioned parameters {Lr, K, Wr, Dr}. Note that in the first embodiment, it is assumed that resistor trench width Wr is constant in the depth direction.

[0066] R0 ∝ Lr / (K × Sr)…(1) In addition, in formula (1), {Sr=Wr×Dr}, where Sr is the cross-sectional area in the YZ plane.

[0067] In the first embodiment, it is assumed that the trench electrode 8b has a rectangular parallelepiped structure, the cross section in the YZ plane is rectangular, and the cross-sectional area Sr is the area of ​​the rectangle.

[0068] Here, the number K of practical internal gate resistor trenches can be adjusted in the range of {1 to M} during manufacture depending on the presence or absence of internal gate resistor contact 9. For example, in one of four internal gate resistor trenches 8, the electrical connection between gate wiring 3 and gate pad 4 by internal gate resistor contact 9 can be omitted, thereby setting the number K of practical internal gate resistor trenches to "3".

[0069] Specifically, the patterning mask for forming internal gate resistor contact 9 can be changed so that internal gate resistor contact 9 is not formed in one internal gate resistor trench 8 .

[0070] In addition, the inter-contact distance Lr can be changed relatively easily by changing the arrangement of at least one of the wiring contacts 9L and the pad contacts 9P.

[0071] Specifically, the patterning mask for forming internal gate resistor contacts 9 can be changed, and the positions at which internal gate resistor contacts 9 electrically connected to four internal gate resistor trenches 8 are formed can be changed.

[0072] In this manner, by changing number K of practical internal gate resistor trenches and contact distance Lr during manufacture of semiconductor device 101, resistance value R0 of one unit of internal gate resistor unit 7 can be adjusted relatively easily.

[0073] The interlayer insulating film 10 is a CVD (Chemical Vapor Deposition) film such as a BPSG (Boron Phospho Silicate Glass) film or a TEOS (tetraethylorthosilicate) oxide film, and is different from a thermal oxide film such as a silicon oxide film formed by a thermal oxidation method. Note that a CVD film means a film formed by a CVD method, and a thermal oxide film means an oxide film formed by a thermal oxidation method. Note that other possible CVD films include a BPTEOS (Boro-Phospho Tetraethylorthosilicate) oxide film, a PSG (Phospho Silicate Glass) film, aluminum oxide (Al2O3), and hafnium oxide (HfO2).

[0074] When interlayer insulating film 10 is a thermal oxide film, a stress is generated due to the thermal oxide film being relatively thick, and resistance value R0 of internal gate resistor unit 7 may fluctuate.

[0075] In the first embodiment, interlayer insulating film 10 is a CVD film. When a CVD film and a thermal oxide film are formed to have the same film thickness, the CVD film has a stress suppression characteristic in which the stress exerted on semiconductor substrate 11 and the peripheral region including trench gate 2 is smaller than that of a thermal oxide film. Therefore, in the first embodiment, by forming a CVD film having a relatively thin film thickness of about 0.1 μm to 0.8 μm as interlayer insulating film 10, the stress caused by interlayer insulating film 10 is reduced, and therefore the fluctuation of resistance value R0 of internal gate resistor unit 7 can be suppressed.

[0076] The internal gate resistor contact 9 can be formed by embedding a W plug or the like, or by embedding a metal that forms the gate wiring 3 or the gate pad 4. Possible metals for forming the gate wiring 3 or the gate pad 4 include AlSi, AlSiC, and the like.

[0077] Furthermore, in order to improve the embeddability of the internal gate resistor contact 9, the internal gate resistor contact 9 may be provided with a taper that slopes inwardly as it descends. Note that since the contact resistance between the internal gate resistor contact 9 and the trench electrode 8b of the internal gate resistor trench 8 is sufficiently small, the presence or absence of a taper in the internal gate resistor contact 9 does not affect the resistance value of each internal gate resistor trench 8.

[0078] As described above, trench insulating film 8a is provided on the inner wall of internal gate resistor trench 8, and trench electrode 8b is provided so as to face first conductivity type semiconductor substrate 11 via trench insulating film 8a.

[0079] The trench insulating film 8a may be a thermal oxide film or a CVD film. The trench electrode 8b is polysilicon doped with impurities. The doped impurities are 1×10 18 cm -2 The doped impurity may be, for example, phosphorus, and the polysilicon may be, for example, doped polysilicon.

[0080] By forming the trench electrode 8b from doped polysilicon, the contact resistance between the gate wiring 3 or the gate pad 4 and the trench electrode 8b can be reduced.

[0081] Thus, internal gate resistor region 5 of semiconductor device 101 of embodiment 1 has four internal gate resistor units 7. The four internal gate resistor units 7 function as N (N≧2) partial internal gate resistor regions connected in parallel between gate line 3 and gate pad 4. In embodiment 1, {N=4}.

[0082] Each of the four internal gate resistor units 7 includes four internal gate resistor trenches 8. The four internal gate resistor trenches become M (M≧2) internal gate resistor trenches 8 connected in parallel between gate wiring 3 and gate pad 4. In the first embodiment, {M=4}.

[0083] Of the four internal gate resistor trenches 8, K (M≧K≧2) trenches function as practical internal gate resistor trenches. In the first embodiment, {K=M=4}.

[0084] In semiconductor device 101 of the first embodiment, four internal gate resistor units 7 included in internal gate resistor region 5 each have four internal gate resistor trenches 8. All four internal gate resistor trenches 8 function as practical internal gate resistor trenches.

[0085] Each of the four built-in gate resistor trenches 8 is electrically connected to the gate wiring 3 via a wiring contact 9L, and is also electrically connected to the gate pad 4 via a pad contact 9P.

[0086] In each of the four built-in gate resistor trenches 8, a gate current path is provided between the wiring contact 9L and the pad contact 9P, and the distance between the wiring contact 9L and the pad contact 9P in the gate current path is defined as the contact distance Lr.

[0087] Therefore, in the semiconductor device 101 of embodiment 1, the resistance value R0 of one unit of internal gate resistor unit 7 is determined by the above-mentioned equation (1), so that the resistance value R0 can be adjusted during manufacture by the parallel number K of practical internal gate resistor trenches and the contact distance Lr.

[0088] The resistance value of internal gate resistor region 5 is the combined resistance value of four internal gate resistor units 7 .

[0089] As a result, in the semiconductor device of the first embodiment, the resistance value of internal gate resistor region 5 can be adjusted relatively easily during manufacturing based on the number K of practical internal gate resistor trenches and contact distance Lr.

[0090] In addition, the interlayer insulating film 10 of the semiconductor device 101 is a CVD film containing at least one of a TEOS oxide film, a BPTEOS oxide film, a PSG film, a BPSG film, an aluminum oxide, and a hafnium oxide. The CVD film has the above-mentioned stress suppression characteristics and can be formed with a relatively thin film thickness of about 0.1 μm to 0.8 μm.

[0091] Therefore, the stress around the four internal gate resistor trenches 8 caused by the interlayer insulating film 10 can be alleviated, and fluctuations in the resistance characteristics of each of the four internal gate resistor trenches 8 can be suppressed.

[0092] Furthermore, internal gate resistor region 5 of semiconductor device 101 of the first embodiment includes four internal gate resistor units 7 provided opposite to the four sides of pad main region 4M which is rectangular in plan view.

[0093] Since the four internal gate resistor units 7 are provided facing the four sides of pad main region 4M in plan view, the formation length of the four internal gate resistor trenches 8 included in each internal gate resistor unit 7 can be made relatively long. Therefore, the inter-contact distance Lr of each of the four internal gate resistor trenches 8 can be set to a length sufficient to obtain a desired resistance value.

[0094] Therefore, semiconductor device 101 of the first embodiment can be provided with four internal gate resistor units 7, each having a significant resistance value, relatively easily.

[0095] <Embodiment 2> 8 is a graph showing the resistance dependency of the internal gate resistor trench 8 functioning as a practical internal gate resistor trench. In the figure, the horizontal axis represents the contact distance Lr (μm), and the vertical axis represents the resistance value (au; arbitrary unit) per internal gate resistor trench 8.

[0096] As shown in the figure, the resistance value R8 per one internal gate resistor trench 8 varies depending on the inter-contact distance Lr and the number K of parallel connections.

[0097] On the other hand, when the parallel number K of practical internal gate resistor trenches in each internal gate resistor unit 7 is set to three or more and the contact distance Lr is set to 100 μm or more, the resistance value R8 per internal gate resistor trench 8 is stabilized at a constant value, as shown in the region of interest Z1.

[0098] As can be seen from Figure 8, in each built-in gate resistor unit 7, if the condition "the number K is 3 or more and the contact distance Lr is 100 μm or more" is satisfied, the Lr dependence of the resistance value R8 of each built-in gate resistor trench 8 will be equivalent, and the resistance value R8 will stabilize at a constant value.

[0099] The semiconductor device 102 of the second embodiment has the same structure as that of the first embodiment shown in FIGS. 1 to 7, and is characterized in that it satisfies the following conditions (1) and (2).

[0100] Condition (1): In each internal gate resistor unit 7, the number K of parallel-connected internal gate resistor trenches 8 functioning as practical internal gate resistor trenches is 3 or more. Condition (2): Contact distance Lr of internal gate resistor trench 8 functioning as a practical internal gate resistor trench is 100 μm or more.

[0101] The semiconductor device 102 of the second embodiment has the same effects as the semiconductor device 101 of the first embodiment, and further has the following effects.

[0102] Semiconductor device 102 of the second embodiment, which satisfies the above-mentioned conditions (1) and (2), can stably adjust resistance value R8 of internal gate resistor trench 8 that functions as a practical internal gate resistor trench.

[0103] <Embodiment 3> The overall structure of semiconductor device 103 of the third embodiment is similar to that of the first embodiment shown in Figures 1 to 4, and the structure of gate pad peripheral region A1 is also similar to that of the first embodiment shown in Figure 5. However, the structure in internal gate resistor peripheral region B1 of Figure 5 is different from the structure of the first embodiment shown in Figure 6.

[0104] Fig. 9 is an enlarged plan view showing the internal gate resistor peripheral region B1 shown in Fig. 5 in semiconductor device 103 of the embodiment 3. Fig. 7 is a cross-sectional view showing the cross-sectional structure at cross section CC in Fig. 9. An XYZ orthogonal coordinate system is shown in Fig. 9.

[0105] Hereinafter, structures similar to those of the first embodiment shown in FIG. 6 are denoted by the same reference numerals, and explanations thereof will be omitted as appropriate, and the features of the third embodiment will be mainly explained.

[0106] In semiconductor device 103, similarly to the first embodiment, gate wiring 3 has wiring-side contact region 30 overlapping M built-in gate resistor trenches 8 in a planar view, and gate wiring 3 has pad-side contact region 40 overlapping M built-in gate resistor trenches 8 in a planar view. In the example shown in FIG. 9, {M=4}.

[0107] 9, the four built-in gate resistor trenches 8 have the same shape. That is, each of the four built-in gate resistor trenches 8 has a rectangular shape in plan view with its long sides in the X direction, which is a first direction, and its short sides in the Y direction, which is a second direction, and the Y direction intersects with the X direction at a right angle.

[0108] The four internal gate resistor trenches 8 are classified into first to fourth internal gate resistor trenches arranged in the order of first, second, third and fourth along the Y direction. That is, from the top to the bottom of FIG. 9, the four internal gate resistor trenches 8 are classified into the first to fourth internal gate resistor trenches.

[0109] Of the four built-in gate resistor trenches 8, one becomes an unused built-in gate resistor trench 8X. Specifically, the third built-in gate resistor trench becomes an unused built-in gate resistor trench 8X, and the first, second and fourth built-in gate resistor trenches become working built-in gate resistor trenches.

[0110] Therefore, the first internal gate resistor trench and the fourth internal gate resistor trench which are the internal gate resistor trenches at both ends in the Y direction do not correspond to unused internal gate resistor trench 8X.

[0111] Thus, in embodiment 3, of the M built-in gate resistor trenches, at least one is an unused built-in gate resistor trench, and the first built-in gate resistor trench and the Mth built-in gate resistor trench do not correspond to at least one unused built-in gate resistor trench.

[0112] In the third embodiment, the number of at least one unused internal gate resistor trench is "1", and therefore, M=4.

[0113] Since no internal gate resistor contact 9 is formed overlapping unused internal gate resistor trench 8X in a plan view, unused internal gate resistor trench 8X has no electrical connection relationship with either gate wiring 3 or the gate pad.

[0114] 9, three of the four built-in gate resistor trenches 8, excluding unused built-in gate resistor trench 8X, function as practical built-in gate resistor trenches. That is, of M built-in gate resistor trenches 8, K (M≧K≧2) function as practical built-in gate resistor trenches. In the third embodiment, {K=3}, and therefore the relationship is {M>K}.

[0115] As shown in Figures 9 and 7, one end of each of the three built-in gate resistor trenches 8, excluding the unused built-in gate resistor trench 8X, among the four built-in gate resistor trenches 8, is electrically connected to the pad side contact region 40 of the gate pad 4 via a pad contact 9P provided through the interlayer insulating film 10.

[0116] The other end of each of the three internal gate resistor trenches 8 described above is electrically connected to the wiring-side contact region 30 of the gate wiring 3 via a wiring contact 9L provided to penetrate the interlayer insulating film 10.

[0117] Therefore, in each of the three built-in gate resistor trenches 8 described above, a gate current path is provided between the pad contact 9P and the wiring contact 9L, and the distance between the wiring contact 9L and the pad contact 9P in the gate current path is defined as the contact distance Lr.

[0118] The semiconductor device 103 of the third embodiment has the same effects as the semiconductor device 101 of the first embodiment, and further has the following effects.

[0119] In the semiconductor device 103 of embodiment 3, by providing at least one unused internal gate resistor trench 8X, a difference of "1" or more can be provided between the number K of practical internal gate resistor trenches and the total number M of internal gate resistor trenches 8.

[0120] The unused internal gate resistor trench 8X can be realized relatively easily by omitting the formation of the wiring contact 9L and the pad contact 9P.

[0121] By reducing the number K of practical internal gate resistor trenches, that is, the number K of parallel practical internal gate resistor trenches, it is possible to increase resistance value R0 of internal gate resistor unit 7 which becomes the partial internal gate resistor region relatively easily.

[0122] As a result, semiconductor device 103 of the third embodiment can increase the resistance value of internal gate resistor region 5 including four internal gate resistor units 7 relatively easily.

[0123] <Fourth embodiment> The overall structure of semiconductor device 104 of the fourth embodiment is similar to that of the first embodiment shown in Figures 1 to 4, and the structure of gate pad peripheral region A1 is also similar to that of the first embodiment shown in Figure 5. However, the structure in internal gate resistor peripheral region B1 of Figure 5 is different from the structure of the first embodiment shown in Figure 6.

[0124] Fig. 10 is an enlarged plan view of the internal gate resistor peripheral region B1 of Fig. 5 in the semiconductor device 104 according to the fourth embodiment. An XYZ orthogonal coordinate system is depicted in Fig. 10.

[0125] Hereinafter, structures similar to those of the first embodiment shown in FIG. 6 are denoted by the same reference numerals, and explanations thereof will be omitted as appropriate, and the features of the fourth embodiment will be mainly explained.

[0126] In the fourth embodiment, a gate line 3B having a different shape from the gate line 3 in the first embodiment is provided, and a gate pad 4B having a different shape from the gate pad 4 in the first embodiment is provided.

[0127] As shown in Figure 10, in the gate pad 4B, two pad side contact regions 41 and 42 are provided extending from the pad main region 4M in the -Y direction, and in the gate wiring 3, two wiring side contact regions 31 and 32 are provided extending from the peripheral wiring region 3P in the +Y direction.

[0128] Thus, in the fourth embodiment, the wiring-side contact region 30 includes two wiring-side contact regions 31 and 32, and the pad-side contact region 40 includes two pad-side contact regions 41 and 42. The pad-side contact regions 41 and 42 form a plurality of pad-side contact regions, and the wiring-side contact regions 31 and 32 form a plurality of wiring-side contact regions.

[0129] Wiring-side contact regions 31 and 32, which are multiple wiring-side contact regions, each overlaps in plan view with a portion of M built-in gate resistor trenches 8. Pad-side contact regions 41 and 42, which are multiple pad contact regions, each overlaps in plan view with a portion of M built-in gate resistor trenches 8. In the example shown in FIG. 10, {M=4}.

[0130] 10, the four internal gate resistor trenches 8 have the same shape. That is, each of the four internal gate resistor trenches 8 has a rectangular shape in plan view with its long sides in the X direction (first direction) and its short sides in the Y direction (second direction), and the Y direction intersects with the X direction at a right angle.

[0131] The pad side contact regions 41 and 42 and the wiring side contact regions 31 and 32 are provided along the +X direction in the order of pad side contact region 41, wiring side contact region 31, pad side contact region 42, and wiring side contact region 32 without overlapping in plan view. In other words, the multiple pad contact regions and the multiple wiring side contact regions are provided alternately along the X direction, which is the formation direction of the internal gate resistor trench 8.

[0132] 10, all four internal gate resistor trenches 8 function as practical internal gate resistor trenches. That is, of M internal gate resistor trenches 8, K (M≧K≧2) function as practical internal gate resistor trenches. In the fourth embodiment, {K=M=4}.

[0133] 10, the four internal gate resistor trenches 8 are electrically connected to the wiring-side contact region 31 via the respective wiring contacts 9L1, and are electrically connected to the wiring-side contact region 32 via the respective wiring contacts 9L2. Therefore, there is a one-to-one correspondence between the wiring contacts 9L1 and 9L2 and the wiring-side contact regions 31 and 32. The wiring contacts 9L1 and 9L2 form a plurality of wiring contacts.

[0134] Similarly, each of the four internal gate resistor trenches 8 is electrically connected to pad-side contact region 41 via pad contact 9P1, and is electrically connected to pad-side contact region 42 via pad contact 9P2. Therefore, there is a one-to-one correspondence between the pad contacts 9P1 and 9P2 and the pad-side contact regions 41 and 42. The pad contacts 9P1 and 9P2 form multiple pad contacts.

[0135] The pad contacts 9P1 and 9P2 and the wiring contacts 9L1 and 9L2 are arranged discretely along the +X direction in the order of the pad contact 9P1, the wiring contact 9L1, the pad contact 9P2, and the wiring contact 9L2.

[0136] Therefore, a first partial gate current path is provided between the pad contact 9P1 and the wiring contact 9L1 in each of the four built-in gate resistor trenches 8. Similarly, a second partial gate current path is provided between the wiring contact 9L1 and the pad contact 9P2, and a third partial gate current path is provided between the pad contact 9P2 and the wiring contact 9L2.

[0137] Thus, in each internal gate resistor trench 8, the gate current path includes, as a plurality of partial gate current paths, first to third partial gate current paths connected in parallel between gate wiring 3B and gate pad 4B.

[0138] As described above, each of the partial gate current paths is provided between one of the pad contacts 9P1 and 9P2 for the built-in gate wiring and one of the wiring contacts 9L1 and 9L2 for the built-in gate pad.

[0139] The distance between the wiring contact 9L1 and the pad contact 9P1 in the first partial gate current path is defined as the contact distance Lr1. The distance between the wiring contact 9L1 and the pad contact 9P2 in the second partial gate current path is defined as the contact distance Lr2. The distance between the wiring contact 9L2 and the pad contact 9P2 in the third partial gate current path is defined as the contact distance Lr3. The contact distances Lr1 to Lr3 may all be set to the same distance, or may be set to different distances among the contact distances Lr1 to Lr3.

[0140] The semiconductor device 104 of the fourth embodiment has the same effects as the semiconductor device 101 of the first embodiment, and further has the following effects.

[0141] In the semiconductor device 104 of embodiment 4, the gate current path of each of the four built-in gate resistor trenches 8, each of which functions as a practical built-in gate resistor trench, includes first to third partial gate current paths connected in parallel between the gate wiring 3B and the gate pad 4B.

[0142] By providing first to third partial gate current paths connected in parallel to each of four internal gate resistor trenches 8, the substantial parallel number of practical internal gate resistor trenches in one unit of internal gate resistor unit 7 can be increased from "K" to "3×K". As a result, the resistance value R0 of internal gate resistor unit 7 including four internal gate resistor trenches 8 decreases compared to the resistance value when the parallel number is "K".

[0143] In addition, assuming that the formation length in the X direction of each of the four internal gate resistor trenches 8 is the same as that in the first embodiment, each of inter-contact distances Lr1 to Lr3 is shorter than inter-contact distance Lr.

[0144] Therefore, in semiconductor device 104 of the fourth embodiment, the resistance value of internal gate resistance region 5 can be reduced relatively easily during manufacturing.

[0145] <Fifth Preferred Embodiment> The overall structure of semiconductor device 105 of the fifth embodiment is similar to that of the first embodiment shown in Figures 1 to 4. The structure of gate pad peripheral region A1 is also substantially similar to that of the first embodiment shown in Figure 5. However, the structure in internal gate resistor peripheral region B1 of Figure 5 is different from that of the first embodiment shown in Figure 6.

[0146] Fig. 11 is an enlarged plan view of the internal gate resistor peripheral region B1 of Fig. 5 in the semiconductor device 105 of the fifth embodiment. An XYZ orthogonal coordinate system is depicted in Fig. 11.

[0147] Hereinafter, structures similar to those of the first embodiment shown in FIG. 6 are denoted by the same reference numerals, and explanations thereof will be omitted as appropriate, and the features of the fifth embodiment will be mainly explained.

[0148] In the fifth embodiment, a gate wiring 3C having a different shape from the gate wiring 3 in the first embodiment and a gate pad 4C having a different shape from the gate pad 4 in the first embodiment are provided.

[0149] As shown in FIG. 11, in the gate pad 4C, a pad side contact region 40I is provided along the X direction in the pad main region 4M, and in the gate wiring 3C, a wiring side contact region 30I is provided along the X direction in the peripheral wiring region 3P.

[0150] In this manner, the wiring-side contact region 30I and the pad-side contact region 40I are both provided along the X direction, which is the contact region formation direction. That is, the contact region formation direction coincides with the X direction, which is the formation length direction of the gate wiring 3C and the gate pad 4C.

[0151] The wiring-side contact region 30I and the pad-side contact region 40I are disposed at an inter-pad wiring distance Wm in the Y direction in which they face each other. The Y direction intersects with the X direction at a right angle.

[0152] The pad-side contact region 40I overlaps, in plan view, one end on the +Y direction side of each of the M internal gate resistor trenches 85, and the wiring-side contact region 30I overlaps, in plan view, the other end on the -Y direction side of each of the M internal gate resistor trenches 85. In the example shown in FIG. 11, {M=3}.

[0153] Similar to the internal gate resistor trench 8 of the first embodiment, each of the three internal gate resistor trenches 85 includes a trench insulating film 8a and a trench electrode 8b as main components.

[0154] 11, all three built-in gate resistor trenches 85 function as practical built-in gate resistor trenches. That is, of M built-in gate resistor trenches 85, K (M≧K≧2) function as practical built-in gate resistor trenches. In the example shown in FIG. 11, {K=M=3}.

[0155] Each of the three internal gate resistor trenches 85 functioning as a practical internal gate resistor trench has a first formation region extending in the X direction and a second formation region extending in the Y direction, and is partially bent in plan view.

[0156] 11, one end of each of the three internal gate resistor trenches 85 is electrically connected to pad-side contact region 40I via pad contact 9P. The other end of each of the three internal gate resistor trenches 85 is electrically connected to pad-side contact region 40I via wiring contact 9L.

[0157] Therefore, in each of the three built-in gate resistor trenches 85, a bent gate current path is provided between pad contact 9P and wiring contact 9L.

[0158] The resistor trench width Wr of each of the three built-in gate resistor trenches 85 is set to be the same. The resistor trench width Wr of each built-in gate resistor trench 85 is constant even in the regions before and after bending. Furthermore, the bent contact distance Lr between pad contact 9P and wiring contact 9L of each of the three built-in gate resistor trenches 85 is also set to be the same. The distance between wiring contact 9L and pad contact 9P in the gate current path is specified as the contact distance Lr.

[0159] The semiconductor device 105 of the fifth embodiment provides the same effects as the semiconductor device 101 of the first embodiment, and further provides the following effects.

[0160] In the semiconductor device 105 of embodiment 5, the wiring side contact region 30I and the pad side contact region 40I are arranged at a pad wiring distance Wm apart in the Y direction, which is the opposing direction, so that the pad wiring distance Wm can be set relatively long.

[0161] This is because the wiring-side contact region 30I is provided in the peripheral wiring region 3P, and the pad-side contact region 40I is provided in the pad main region 4M. This is clear from a comparison between the pad-to-wire distance Wm in the first embodiment shown in FIG. 6 and the pad-to-wire distance Wm in the fifth embodiment shown in FIG.

[0162] Therefore, the semiconductor device 105 of the fifth embodiment can effectively suppress the short-circuit phenomenon in which the gate wiring 3C and the gate pad 4C are electrically connected due to variations in the manufacturing process.

[0163] Furthermore, each of the three built-in gate resistor trenches 85, which function as a practical built-in gate resistor trench, has a first formation region along the X direction and a second formation region along the Y direction, so that a contact-to-contact distance Lr of a length that can be set to a significant resistance value can be secured.

[0164] Furthermore, in the semiconductor device 105, by making the pad wiring distance Wm sufficiently long, it is possible to improve the embeddability of the sealing material when sealing the space between the gate pad 4C and the gate wiring 3C of the semiconductor device 105 with a sealing material such as resin or gel.

[0165] Each of the three internal gate resistor trenches 85 may be formed in a serpentine shape, or the intermediate region may be disposed under the non-contact region of gate wiring 3C or gate pad 4C. The intermediate region of internal gate resistor trench 85 refers to a region in which internal gate resistor contact 9 is not formed, and the non-contact region refers to a region of gate wiring 3C excluding wiring-side contact region 30I, or a region of gate pad 4C excluding pad-side contact region 40I.

[0166] <Sixth embodiment> The overall structure of semiconductor device 106 of the sixth embodiment is similar to that of the first embodiment shown in Figures 1 to 4. The structure of gate pad peripheral region A1 is also substantially similar to that of the first embodiment shown in Figure 5. However, the structure in internal gate resistor peripheral region B1 of Figure 5 is different from that of the first embodiment shown in Figure 6.

[0167] Fig. 12 is an enlarged plan view of the internal gate resistor peripheral region B1 of Fig. 5 in the semiconductor device 106 of the sixth embodiment. An XYZ orthogonal coordinate system is shown in Fig. 12.

[0168] Hereinafter, structures similar to those of the first embodiment shown in FIG. 6 and the fifth embodiment shown in FIG. 11 will be denoted by the same reference numerals and explanations thereof will be omitted as appropriate, and the features of the sixth embodiment will be mainly described.

[0169] As shown in FIG. 12, in the gate pad 4C, a pad side contact region 40I is provided along the X direction in the pad main region 4M, and in the gate line 3, a line side contact region 30I is provided along the X direction in the peripheral line region 3P.

[0170] In this manner, both the wiring-side contact region 30I and the pad-side contact region 40I are provided along the X direction, which is the contact region forming direction.

[0171] The wiring-side contact region 30I and the pad-side contact region 40I are disposed at an inter-pad wiring distance Wm in the Y direction in which they face each other. The Y direction intersects with the X direction at a right angle.

[0172] The pad-side contact region 40I overlaps, in plan view, one end on the +Y direction side of each of the M internal gate resistor trenches 85, and the wiring-side contact region 30I overlaps, in plan view, the other end on the -Y direction side of each of the M internal gate resistor trenches 85. In the example shown in FIG. 12, {M=3}.

[0173] Similar to the internal gate resistor trench 8 of the first embodiment, each of the three internal gate resistor trenches 86 includes a trench insulating film 8a and a trench electrode 8b as main components.

[0174] 12, all three built-in gate resistor trenches 86 function as practical built-in gate resistor trenches. That is, of M built-in gate resistor trenches 86, K (M≧K≧2) function as practical built-in gate resistor trenches. Here, {K=M=3}.

[0175] Each of the three built-in gate resistor trenches 86, which function as a practical built-in gate resistor trench, has a parallelogram shape in a plan view with its short side in the X direction and its long side in the diagonal direction D8. In each of the three built-in gate resistor trenches 86, the short side direction is the X direction, and the long side direction is the diagonal direction D8. The diagonal direction D8 intersects with both the X direction and the Y direction.

[0176] As shown in FIG. 12, one end of each of the three built-in gate resistor trenches 86 is electrically connected to the pad side contact region 40I via a pad contact 9P, and the other end of each of the three built-in gate resistor trenches 86 is electrically connected to the wiring side contact region 30I via a wiring contact 9L.

[0177] Therefore, in each of the three built-in gate resistor trenches 86, a gate current path is provided between pad contact 9P and wiring contact 9L.

[0178] The resistor trench width Wr is set to be the same among the three built-in gate resistor trenches 86, and the inter-contact distance Lr along the diagonal direction D8 between the pad contact 9P and the wiring contact 9L is also set to be the same. In this manner, the distance between the wiring contact 9L and the pad contact 9P in the gate current path is defined as the inter-contact distance Lr.

[0179] The semiconductor device 106 of the sixth embodiment has the same effects as the semiconductor device 101 of the first embodiment, and further has the following effects.

[0180] In the semiconductor device 106 of the sixth embodiment, the wiring side contact region 30I and the pad side contact region 40I are arranged at a pad wiring distance Wm apart in the Y direction, which is the opposing direction, so that the pad wiring distance Wm can be set relatively long, as in the fifth embodiment.

[0181] Therefore, the semiconductor device 106 of the sixth embodiment can effectively suppress the short-circuit phenomenon in which the gate wiring 3C and the gate pad 4C are electrically connected due to variations in the manufacturing process.

[0182] Furthermore, each of the three built-in gate resistor trenches 86, which function as a practical built-in gate resistor trench, has a parallelogram shape in a plan view, and does not have any bent portions like built-in gate resistor trench 85 of the fifth embodiment.

[0183] Therefore, in the semiconductor device 106 of the sixth embodiment, the embedding property of the trench electrode 8b can be improved, and accordingly, the accuracy of the resistance value of the internal gate resistor trench 86 can be improved.

[0184] In addition, the three built-in gate resistor trenches 86, each of which functions as a practical built-in gate resistor trench, have their long sides oriented in the diagonal direction D8, so that a contact-to-contact distance Lr of a length that can be set to a significant resistance value can be secured.

[0185] In the sixth embodiment, the three internal gate resistor trenches 86 are provided in a parallelogram shape in the narrow sense of the term in plan view, but may be provided in a rectangular shape in plan view. In this case, the long side direction of the rectangle is the diagonal direction D8. Note that a rectangle is a special parallelogram, and is included in the parallelogram shape in the broad sense of the term.

[0186] <Embodiment 7> The overall structure of a semiconductor device 107 according to the seventh embodiment is similar to that of the first embodiment shown in FIGS.

[0187] 13 is an explanatory diagram showing a schematic detailed structure of a gate pad peripheral region A1 in a semiconductor device 107 according to the seventh embodiment. The structure in an internal gate resistor peripheral region B2 in the semiconductor device 107 is similar to the structure in the first embodiment shown in FIGS.

[0188] Hereinafter, structures similar to those of the first embodiment shown in FIG. 5 are denoted by the same reference numerals, and explanations thereof will be omitted as appropriate, and the features of the seventh embodiment will be mainly explained.

[0189] Of the four wiring-side contact regions 30 and the four pad-side contact regions 40, any one of the built-in gate resistor units 71-74 is provided between the corresponding wiring-side contact regions 30 and pad-side contact regions 40. Therefore, the four built-in gate resistor units 71-74 are provided in one-to-one correspondence with the four wiring-side contact regions 30 and the four pad-side contact regions 40.

[0190] Internal gate resistor unit 71 is located on the left side of the figure and is set to a resistance value R1, internal gate resistor unit 72 is located on the upper side of the figure and is set to a resistance value R2, internal gate resistor unit 73 is located on the right side of the figure and is set to a resistance value R3, and internal gate resistor unit 74 is located on the lower side of the figure and is set to a resistance value R4.

[0191] Internal gate resistor units 71-74 electrically connect corresponding wiring-side contact region 30 and pad-side contact region 40 to each other.

[0192] Internal gate resistor units 71-74 function as N partial internal gate resistor regions, are provided facing the four sides of pad main region 4M in plan view, and are classified into first to fourth partial internal gate resistor regions. That is, internal gate resistor unit 71 serves as the first partial internal gate resistor region, internal gate resistor unit 72 serves as the second partial internal gate resistor region, internal gate resistor unit 73 serves as the third partial internal gate resistor region, and internal gate resistor unit 74 serves as the fourth partial internal gate resistor region.

[0193] Semiconductor device 107 of the seventh embodiment is characterized in that resistance values ​​R1 to R4 of internal gate resistor units 71 to 74 are set to different values.

[0194] The semiconductor device 107 of the seventh embodiment provides the same effects as the semiconductor device 101 of the first embodiment, and further provides the following effects.

[0195] In the semiconductor device 107 of the seventh embodiment, the resistance values ​​R1 to R4 of the internal gate resistor units 71 to 74, which form the first to fourth partial internal gate resistor regions, are set to different values ​​from each other, thereby making it possible to relatively widen the adjustment range of the resistance value of the internal gate resistor region 5.

[0196] Although resistance values ​​R1 to R4 of internal gate resistor units 71 to 74 are set to different values, some of resistance values ​​R1 to R4 may be set to the same resistance value.

[0197] <Embodiment 8> The overall structure of the semiconductor device 108 of the eighth embodiment is similar to that of the first embodiment shown in FIGS.

[0198] 14 is an explanatory diagram showing a schematic detailed structure of a gate pad peripheral region A1 in a semiconductor device 108 according to an eighth embodiment. The structure in an internal gate resistor peripheral region B3 in the semiconductor device 108 is substantially similar to the structure in the first embodiment shown in FIGS.

[0199] Hereinafter, structures similar to those of the first embodiment shown in FIG. 5 are denoted by the same reference numerals, and explanations thereof will be omitted as appropriate, and the features of the eighth embodiment will be mainly explained.

[0200] In the eighth embodiment, a gate line 3D having a different shape from the gate line 3 in the first embodiment is provided.

[0201] 14, gate wiring 3D has a peripheral wiring region 3P provided along the outer periphery of gate pad 4, and four internal gate resistance measurement pads 12 provided at four corners of peripheral wiring region 3P. Each of the four internal gate resistance measurement pads 12 is provided in contact with peripheral wiring region 3P. Each of the four internal gate resistance measurement pads 12 functions as a wiring-side contact region 30. There is a one-to-one correspondence between the four internal gate resistance measurement pads 12 and the four pad-side contact regions 40.

[0202] Each of the four internal gate resistance measurement pads 12 has a measurement area with an exposed surface, where electrical connection with the outside can be established.

[0203] Of the four internal gate resistance measurement pads 12 and four pad-side contact regions 40, internal gate resistor units 7 are provided between corresponding internal gate resistance measurement pads 12 and pad-side contact regions 40. Therefore, four internal gate resistor units 7 are provided corresponding to the four internal gate resistance measurement pads 12 and four pad-side contact regions 40.

[0204] In the eighth embodiment, the four internal gate resistor units 7 have the same resistance value R0, similarly to the first embodiment. Note that the resistance values ​​of some of the four internal gate resistor units 7 may be set to different values.

[0205] Internal gate resistor unit 7 electrically connects corresponding internal gate resistance measurement pad 12 and pad-side contact region 40. With regard to the electrical connection of internal gate resistor unit 7, internal gate resistance measurement pad 12 functions as wiring-side contact region 30.

[0206] Four internal gate resistor units 7 are provided facing the four sides of pad main region 4M in plan view. The four internal gate resistor units 7 function as N partial internal gate resistor regions.

[0207] The semiconductor device 108 of the eighth embodiment provides the same effects as the semiconductor device 101 of the first embodiment, and further provides the following effects.

[0208] Semiconductor device 108 of the eighth embodiment can measure the resistance value of internal gate resistance region 5 by utilizing internal gate resistance measurement pad 12 which functions as wiring-side contact region 30 and also as a measurement region for external connection.

[0209] Specifically, by measuring the voltage between gate pad 4 and internal gate resistance measurement pad 12 or the current flowing between gate pad 4 and internal gate resistance measurement pad 12, the resistance value of internal gate resistance area 5, i.e., the combined resistance value of four internal gate resistor units 7, each having a resistance value R0, can be measured.

[0210] In the eighth embodiment, four internal gate resistance measurement pads 12 are provided, but the above effect can be achieved by providing at least one internal gate resistance measurement pad 12 corresponding to at least one of the four internal gate resistance units 7.

[0211] <Embodiment 9> The overall structure of semiconductor device 109 of embodiment 9 is similar to that of embodiment 1 shown in Figures 1 to 4. The structure of gate pad peripheral region A1 is also similar to that of embodiment 1 shown in Figure 5. The planar structure in internal gate resistor peripheral region B1 of Figure 5 is also similar to that of embodiment 1 shown in Figure 6. However, the cross-sectional structure in internal gate resistor peripheral region B1 of Figure 5 differs from that of embodiment 1.

[0212] Fig. 15 is a cross-sectional view of the semiconductor device 109 according to the ninth embodiment, showing the cross-sectional structure taken along line AA in Fig. 6. An XYZ orthogonal coordinate system is shown in Fig. 15.

[0213] Hereinafter, structures similar to those of the first embodiment shown in FIG. 7 are denoted by the same reference numerals, and explanations thereof will be omitted as appropriate, and the features of the ninth embodiment will be mainly explained.

[0214] 15, p-type well layer 13, which is a second conductivity type, is provided in an upper layer portion on the first main surface side of n-type semiconductor substrate 11. Built-in gate resistor trench 8 is provided in well layer 13. In FIG. 15, semiconductor substrate 11 corresponds to n-type drift layer 21, to be precise.

[0215] Internal gate resistor trench 8 is buried in well layer 13 of semiconductor substrate 11, and the bottom of internal gate resistor trench 8 exists in well layer 13. As in the first embodiment, internal gate resistor trench 8 includes trench insulating film 8a and trench electrode 8b as main components. Trench insulating film 8a is provided so as to cover the entire periphery of trench electrode 8b. Therefore, trench electrode 8b is not electrically connected to well layer 13.

[0216] 15 is common to M internal gate resistor trenches 8. Therefore, semiconductor device 109 of embodiment 9 is characterized in that the bottoms of M internal gate resistor trenches 8 are present in p-type well layer 13. That is, M internal gate resistor trenches 8 are covered with well layer 13. Note that in embodiment 9, as in embodiment 1, {M=K=4}.

[0217] The semiconductor device 109 of the ninth embodiment has the same effects as the semiconductor device 101 of the first embodiment, and further has the following effects.

[0218] The semiconductor device 109 of the ninth embodiment further includes a well layer 13 of the second conductivity type, that is, p-type, so that the well layer 13 can reduce the electric field generated at the bottom of the four internal gate resistor trenches 8, thereby improving the reliability of the resistance values ​​of the four internal gate resistor trenches 8.

[0219] This is because, when well layer 13 is present, the electric field strength is maximized at the pn junction interface between well layer 13 of the second conductivity type, p-type, and semiconductor substrate 11 of the first conductivity type, n-type, and the electric field at the bottom of four built-in gate resistor trenches 8 can be relaxed.

[0220] <Embodiment 10> The overall structure of semiconductor device 110 of embodiment 10 is similar to that of embodiment 1 shown in Figures 1 to 4. The structure of gate pad peripheral region A1 is also similar to that of embodiment 1 shown in Figure 5. The planar structure in internal gate resistor peripheral region B1 of Figure 5 is also similar to that of embodiment 1 shown in Figure 6. However, the cross-sectional structure in internal gate resistor peripheral region B1 of Figure 5 differs from that of embodiment 1 shown in Figure 7.

[0221] Fig. 16 is a cross-sectional view of the semiconductor device 110 according to the tenth embodiment, showing the cross-sectional structure taken along the line AA in Fig. 6. An XYZ orthogonal coordinate system is shown in Fig. 16.

[0222] Hereinafter, structures similar to those of the first embodiment shown in FIG. 7 will be denoted by the same reference numerals, and explanations thereof will be omitted as appropriate, and the features of the tenth embodiment will be mainly explained.

[0223] As shown in Fig. 16, well layer 13B of p-type, which is a second conductivity type, is provided in an upper layer portion of semiconductor substrate 11. Internal gate resistor trench 8 penetrates well layer 13B and is embedded in semiconductor substrate 11. That is, the formation depth of well layer 13B is shallower than the formation depth of the internal gate resistor trench. In Fig. 16, semiconductor substrate 11 corresponds to n-type drift layer 21, to be precise.

[0224] A barrier layer 14 of p-type, which is a second conductivity type, is selectively formed in semiconductor substrate 11. Barrier layer 14 is provided so as to cover the bottom of internal gate resistor trench 8. Therefore, the bottom of internal gate resistor trench 8 exists within barrier layer 14.

[0225] The internal gate resistor trench 8 includes a trench insulating film 8a and a trench electrode 8b as main components, similarly to the first embodiment. The trench insulating film 8a is provided so as to cover the entire periphery of the trench electrode 8b. Therefore, the trench electrode 8b is not electrically connected to the barrier layer 14.

[0226] 16 is common to M internal gate resistor trenches 8. Therefore, semiconductor device 110 of the tenth embodiment is characterized in that the formation depth of well layer 13B is shallower than the formation depth of M internal gate resistor trenches 8, and the bottoms of M internal gate resistor trenches 8 are present in barrier layer 14. Note that in the tenth embodiment, as in the first embodiment, {M=K=4}.

[0227] The semiconductor device 110 of the tenth embodiment has the same effects as the semiconductor device 101 of the first embodiment, and further has the following effects.

[0228] The semiconductor device 110 of the tenth embodiment further includes a barrier layer 14 of the second conductivity type, that is, p-type, so that the barrier layer 14 can reduce the electric field generated at the bottom of the four internal gate resistor trenches 8, thereby improving the reliability of the resistance values ​​of the four internal gate resistor trenches.

[0229] In addition, the formation depth of well layer 13B can be made shallower than the formation depth of four internal gate resistor trenches 8, thereby enabling a reduction in the manufacturing cost of semiconductor device 110.

[0230] <Embodiment 11> The overall structure of semiconductor device 111 of embodiment 11 is similar to that of embodiment 1 shown in Figures 1 to 4. The structure of gate pad peripheral region A1 is also similar to that of embodiment 1 shown in Figure 5. The planar structure and AA cross-sectional structure in internal gate resistor peripheral region B1 of Figure 5 are also similar to those of embodiment 1 shown in Figures 6 and 7.

[0231] A semiconductor device 111 according to the eleventh embodiment is characterized by a cross-sectional structure taken along line B--B in an internal gate resistor peripheral region B1 in FIG.

[0232] Fig. 17 is a cross-sectional view of a semiconductor device 111 according to the eleventh embodiment, showing a cross-sectional structure taken along line BB in Fig. 6. An XYZ orthogonal coordinate system is depicted in Fig. 17.

[0233] As shown in Fig. 17, buried gate electrode 2b of each of the four internal gate resistor trenches has a constant resistance trench depth Dr. Although Fig. 17 shows three internal gate resistor trenches 8, in reality there are four.

[0234] 17, in each of the four internal gate resistor trenches 8, the surface on the first main surface side of trench electrode 8b has a resistor surface width Wt, and the bottom surface on the second main surface side of trench electrode 8b has a resistor bottom width Wb. The resistor surface width Wt is the first formation width, and the resistor bottom width Wb is the second formation width.

[0235] In the first to tenth embodiments, it is assumed that the trench electrode 8b has a rectangular parallelepiped structure, but in the eleventh embodiment, it is assumed that, when forming the trench for the internal gate resistor trench 8, a taper is formed that slopes inward as it goes downward.

[0236] In the eleventh embodiment, taking into consideration the case where a taper is formed, the trench electrode 8b is formed so that the difference (Wt-Wb) between the resistor surface width Wt and the resistor bottom width Wb satisfies the following formula (2).

[0237] (Wt-Wb)≦Wt / 10…(2)

[0238] The structure shown in FIG. 17 is common to M internal gate resistor trenches 8. Therefore, in the semiconductor device 111 of the eleventh embodiment, in each of the M internal gate resistor trenches 8, the trench electrode 8b has a constant resistor trench depth Dr, the surface of the trench electrode 8b has a resistor surface width Wt, and the bottom surface of the trench electrode 8b has a resistor bottom width Wb. The resistor surface width Wt and the resistor bottom width Wb satisfy the above-mentioned formula (2). In the eleventh embodiment, as in the first embodiment, {M=K=4}.

[0239] Semiconductor device 111 of the eleventh embodiment is characterized in that in each of four internal gate resistor trenches 8, resistor surface width Wt and resistor bottom width Wb satisfy the above-mentioned formula (2).

[0240] A trench for internal gate resistor trench 8 satisfying formula (2) can be realized, for example, by using anisotropic dry etching.

[0241] Since trench insulating film 8a is sufficiently thin, equation (2) can be applied by assuming that the formation width of the surface of internal gate resistor trench 8 is resistor surface width Wt and that the formation width of the bottom of internal gate resistor trench 8 is resistor bottom width Wb. That is, the parameters {Wt, Wb} relating to equation (2) can be regarded as the same between internal gate resistor trench 8 and trench electrode 8b.

[0242] In the eleventh embodiment, resistance value R0 of one internal gate resistor unit 7 has a characteristic that satisfies the following equation (3) using the above-mentioned parameters {Lr, K, Wt, Wb, Dr}.

[0243] R0 ∝ Lr / (K × Sr2)…(3) In addition, in formula (3), {Sr2=Dr×(Wt+Wb) / 2}, and Sr2 is the cross-sectional area of ​​the trapezoid in the YZ plane.

[0244] From formula (3), the resistance value R0 of one unit of internal gate resistor unit 7 is inversely proportional to the cross-sectional area Sr2. When forming a trench for internal gate resistor trench 8, an inward taper angle is generated during etching, and accordingly, resistor bottom width Wb tends to be shorter than resistor surface width Wt.

[0245] On the other hand, whether the cross-sectional area Sr is a rectangle in equation (1) or the cross-sectional area Sr2 is a trapezoid in equation (3), if the cross-sectional areas Sr and Sr2 can be made to approach constant values, the variation in the resistance value R0 obtained from equations (1) and (3) can be minimized.

[0246] Therefore, by providing internal gate resistor trench 8 that satisfies equation (2), the variation in resistance value R0 obtained by applying equation (3) can be minimized.

[0247] In the semiconductor device 111 of embodiment 11, the resistor surface width Wt and resistor bottom width Wb for each of the four internal gate resistor trenches 8 are set so as to satisfy equation (2), thereby minimizing the variation in the resistance value R0 shown in equation (3).

[0248] <Manufacturing method> The semiconductor devices 101 to 111 according to the first to eleventh embodiments can be manufactured by the following steps (a) to (c).

[0249] Step (a): Among the M built-in gate resistor trenches 8, the number K that functions as a practical built-in gate resistor trench is determined. Step (b): The contact distance Lr of each of the K practical built-in gate resistor trenches is determined. Step (c): One of the semiconductor devices 101 to 111 is formed so as to satisfy the number K determined in step (a) and the contact-to-contact distance Lr of each of the K practical built-in gate resistor trenches determined in step (b).

[0250] Step (c) is a step of forming any one of the semiconductor devices 101 to 111 so as to satisfy the contents determined in the above steps (a) and (b).

[0251] The contact distance Lr may be set to the same length among the K practical internal gate resistor trenches, or may be set to different lengths at least in part among the K practical internal gate resistor trenches.

[0252] The manufacturing methods of the semiconductor device in embodiments 1 to 11 can relatively easily adjust the resistance value of the internal gate resistor region 5 in any one of the semiconductor devices 101 to 111 based on the number K of practical internal gate resistor trenches and the contact distance Lr by performing the above-mentioned steps (a) to (c).

[0253] Furthermore, the step (c) includes the following step (c-1). (c-1) An interlayer insulating film 10 is formed on the first main surface of a semiconductor substrate 11 to a thickness of about 0.1 μm to 0.8 μm by using a CVD method.

[0254] The CVD film that becomes the interlayer insulating film 10 may be at least one of a TEOS oxide film, a BPTEOS oxide film, a PSG film, a BPSG film, an aluminum oxide, and a hafnium oxide. The CVD film made of these materials has stress suppression properties as described above.

[0255] Since step (c) of the method for manufacturing a semiconductor device includes step (c-1), in the first to eleventh embodiments, fluctuations in the resistance characteristics of each internal gate resistor unit 7 caused by interlayer insulating film 10 can be suppressed.

[0256] In step (c-1), a CVD film made of a material other than those mentioned above may be formed, provided that the interlayer insulating film 10 thus formed has the above-mentioned stress suppression characteristics.

[0257] <Other> Although the first to eleventh embodiments have been described above, various developments are possible beyond the structures of the above-mentioned embodiments.

[0258] For example, in the above-described embodiment, the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type.

[0259] Although the IGBT 50 is shown as a switching element having an insulated gate structure, other power devices such as MOSFETs and RC-IGBTs can be used in addition to the IGBT 50. In addition, although the trench type IGBT 50 is shown in the above-described embodiment, a planar type switching element such as a planar type IGBT may also be used.

[0260] Also, various substrates such as a high-voltage class semiconductor substrate, an FZ substrate, an MCZ substrate, and an epitaxial substrate can be applied as the semiconductor substrate 11. Note that an FZ substrate is a semiconductor substrate manufactured by the FZ (Floating Zone) method, an MCZ substrate is a semiconductor substrate manufactured by the MCZ (Magnetic field applied Czochralski) method, and an epitaxial substrate is a semiconductor substrate manufactured using an epitaxial growth method.

[0261] In addition, within the scope of the present disclosure, it is possible to freely combine the respective embodiments, and to appropriately modify or omit the respective embodiments. [Explanation of symbols]

[0262] 1 cell region, 2 trench gate, 2a gate insulating film, 2b buried gate electrode, 3,3B to 3D gate wiring, 3P peripheral wiring region, 4,4B,4C gate pad, 4M pad main region, 5 built-in gate resistor region, 6 termination region, 7,71 to 74 built-in gate resistor unit, 11 semiconductor substrate, 12 built-in gate resistor measurement pad, 13,13B well layer, 14 barrier layer, 8,85,86 built-in gate resistor trench, 8a trench insulating film, 8b trench electrode, 8X unused built-in gate resistor trench, 9 built-in gate resistor contact, 9L,9L1,9L2 wiring contact, 9P,9P1,9P2 pad contact, 30 to 32,30I wiring side contact region, 40 to 42,40I pad side contact region, 101 to 111,101A to 101C semiconductor device.

Claims

1. A semiconductor device including a switching element having an insulated gate structure, the switching element being provided on a semiconductor substrate of a first conductivity type, a gate wiring provided on the semiconductor substrate via an interlayer insulating film and electrically connected to a gate electrode of the switching element; a gate pad provided on the semiconductor substrate via the interlayer insulating film and having an electrical connection region with an exposed surface; an internal gate resistor region electrically connecting the gate wiring and the gate pad; the internal gate resistor region includes N (N≧2) partial internal gate resistor regions connected in parallel between the gate wiring and the gate pad, Each of the N partial internal gate resistor regions includes M (M≧2) internal gate resistor trenches connected in parallel between the gate wiring and the gate pad, the gate wiring has a wiring-side contact region overlapping with the M internal gate resistor trenches in a plan view; the gate pad has a pad-side contact region overlapping with the M internal gate resistor trenches in a plan view; The M built-in gate resistor trenches are embedded in the semiconductor substrate; Among the M internal gate resistor trenches, K (M≧K≧2) trenches function as practical internal gate resistor trenches; The K practical built-in gate resistor trenches are the gate wiring is electrically connected to the wiring-side contact region of the gate wiring via a wiring contact provided through the interlayer insulating film; the gate pad is electrically connected to the pad-side contact region of the gate pad via a pad contact provided through the interlayer insulating film; a gate current path is provided between the wiring contact and the pad contact in each of the K practical built-in gate resistor trenches, and a distance between the wiring contact and the pad contact in the gate current path is defined as an inter-contact distance; the K practical built-in gate resistor trenches are physically connected to the wiring contacts and the pad contacts, respectively; M>K, Each of the M internal gate resistor trenches has a rectangular shape in a plan view, a first direction being a long side, and a second direction being a short side, the M internal gate resistor trenches include first to Mth internal gate resistor trenches arranged in the second direction in the order of first, second, . . . Mth; at least one of the M internal gate resistor trenches is an unused internal gate resistor trench, and the first internal gate resistor trench and the Mth internal gate resistor trench do not correspond to at least one unused internal gate resistor trench; the at least one unused built-in gate resistor trench has no electrical connection with the gate line and the gate pad; Semiconductor device.

2. 2. The semiconductor device according to claim 1, The interlayer insulating film may be a TEOS oxide film, a BPTEOS oxide film, a PSG film, a BPSG film, an oxide film, or a at least one of aluminum oxide and hafnium oxide, Semiconductor device.

3. 3. The semiconductor device according to claim 1, K≧3; In each of the K practical built-in gate resistor trenches, The distance between the contacts is 100 μm or more. Semiconductor device.

4. A semiconductor device according to any one of claims 1 to 3, the wiring-side contact region includes a plurality of wiring-side contact regions, the pad side contact area includes a plurality of pad side contact areas; the wiring contact includes a plurality of wiring contacts, the plurality of wiring contacts corresponding one-to-one to the plurality of wiring contact regions; the pad contact includes a plurality of pad contacts, the plurality of pad contacts corresponding one-to-one to the plurality of pad contact regions; the gate current path includes a plurality of partial gate current paths connected in parallel between the gate wiring and the gate pad; each of the plurality of partial gate current paths is provided between one of the plurality of wiring contacts and one of the plurality of pad contacts; Semiconductor device.

5. A semiconductor device including a switching element having an insulated gate structure, the switching element being provided on a semiconductor substrate of a first conductivity type, a gate wiring provided on the semiconductor substrate via an interlayer insulating film and electrically connected to a gate electrode of the switching element; a gate pad provided on the semiconductor substrate via the interlayer insulating film and having an electrical connection region with an exposed surface; an internal gate resistor region electrically connecting the gate wiring and the gate pad; the internal gate resistor region includes N (N≧2) partial internal gate resistor regions connected in parallel between the gate wiring and the gate pad, Each of the N partial internal gate resistor regions includes M (M≧2) internal gate resistor trenches connected in parallel between the gate wiring and the gate pad, the gate wiring has a wiring-side contact region overlapping with the M internal gate resistor trenches in a plan view; the gate pad has a pad-side contact region overlapping with the M internal gate resistor trenches in a plan view; The M built-in gate resistor trenches are embedded in the semiconductor substrate; Among the M internal gate resistor trenches, K (M≧K≧2) trenches function as practical internal gate resistor trenches; The K practical built-in gate resistor trenches are the gate wiring is electrically connected to the wiring-side contact region of the gate wiring via a wiring contact provided through the interlayer insulating film; the gate pad is electrically connected to the pad-side contact region of the gate pad via a pad contact provided through the interlayer insulating film; a gate current path is provided between the wiring contact and the pad contact in each of the K practical built-in gate resistor trenches, and a distance between the wiring contact and the pad contact in the gate current path is defined as an inter-contact distance; the K practical built-in gate resistor trenches are physically connected to the wiring contacts and the pad contacts, respectively; the gate pad further has a pad main region having a rectangular shape in a plan view, the pad main region including the electrical connection region, N=4, the N partial internal gate resistance regions are provided opposite to four sides of the pad main region in a plan view; Semiconductor device.

6. 6. The semiconductor device according to claim 5, the wiring-side contact region and the pad-side contact region are both provided along a contact region forming direction, the wiring-side contact region and the pad-side contact region are disposed at a pad wiring distance apart in an opposing direction, the opposing direction intersecting a contact region forming direction; Each of the K practical internal gate resistor trenches has a first formation region extending in a contact region formation direction and a second formation region extending in the opposite direction. Semiconductor device.

7. 6. The semiconductor device according to claim 5, the wiring-side contact region and the pad-side contact region are both provided along a contact region forming direction, the wiring-side contact region and the pad-side contact region are disposed at a pad wiring distance apart in an opposing direction, the opposing direction intersecting a contact region forming direction; each of the K practical internal gate resistor trenches has a parallelogram shape in a plan view, and a direction intersecting the contact region forming direction and the opposing direction is a direction of a long side; Semiconductor device.

8. A semiconductor device according to any one of claims 5 to 7, the N partial internal gate resistance regions are classified into first to fourth partial internal gate resistance regions; the first to fourth partial internal gate resistance regions are set to have resistance values ​​different from one another; Semiconductor device.

9. A semiconductor device according to any one of claims 5 to 8, the gate wiring has an internal gate resistance measurement pad having a measurement region with an exposed surface, the internal gate resistance measurement pad functions as the wiring-side contact region corresponding to at least one of the N partial internal gate resistance regions; Semiconductor device.

10. A semiconductor device according to any one of claims 1 to 9, Further comprising a well layer of a second conductivity type provided in an upper layer portion of the semiconductor substrate; a bottom of the M internal gate resistor trenches is present in the well layer; Semiconductor device.

11. A semiconductor device including a switching element having an insulated gate structure, the switching element being provided on a semiconductor substrate of a first conductivity type, a gate wiring provided on the semiconductor substrate via an interlayer insulating film and electrically connected to a gate electrode of the switching element; a gate pad provided on the semiconductor substrate via the interlayer insulating film and having an electrical connection region with an exposed surface; an internal gate resistor region electrically connecting the gate wiring and the gate pad; the internal gate resistor region includes N (N≧2) partial internal gate resistor regions connected in parallel between the gate wiring and the gate pad, Each of the N partial internal gate resistor regions includes M (M≧2) internal gate resistor trenches connected in parallel between the gate wiring and the gate pad, the gate wiring has a wiring-side contact region overlapping with the M internal gate resistor trenches in a plan view; the gate pad has a pad-side contact region overlapping with the M internal gate resistor trenches in a plan view; The M built-in gate resistor trenches are embedded in the semiconductor substrate; Among the M internal gate resistor trenches, K (M≧K≧2) trenches function as practical internal gate resistor trenches; The K practical built-in gate resistor trenches are the gate wiring is electrically connected to the wiring-side contact region of the gate wiring via a wiring contact provided through the interlayer insulating film; the gate pad is electrically connected to the pad-side contact region of the gate pad via a pad contact provided through the interlayer insulating film; a gate current path is provided between the wiring contact and the pad contact in each of the K practical built-in gate resistor trenches, and a distance between the wiring contact and the pad contact in the gate current path is defined as an inter-contact distance; the K practical built-in gate resistor trenches are physically connected to the wiring contacts and the pad contacts, respectively; The semiconductor device includes: a well layer of a second conductivity type provided in an upper layer portion of the semiconductor substrate; a barrier layer of a second conductivity type selectively provided in the semiconductor substrate; a formation depth of the well layer is shallower than a formation depth of the M internal gate resistor trenches; a bottom of the M internal gate resistor trenches is in the barrier layer; Semiconductor device.

12. A semiconductor device including a switching element having an insulated gate structure, the switching element being provided on a semiconductor substrate of a first conductivity type, a gate wiring provided on the semiconductor substrate via an interlayer insulating film and electrically connected to a gate electrode of the switching element; a gate pad provided on the semiconductor substrate via the interlayer insulating film and having an electrical connection region with an exposed surface; an internal gate resistor region electrically connecting the gate wiring and the gate pad; the internal gate resistor region includes N (N≧2) partial internal gate resistor regions connected in parallel between the gate wiring and the gate pad, Each of the N partial internal gate resistor regions includes M (M≧2) internal gate resistor trenches connected in parallel between the gate wiring and the gate pad, the gate wiring has a wiring-side contact region overlapping with the M internal gate resistor trenches in a plan view; the gate pad has a pad-side contact region overlapping with the M internal gate resistor trenches in a plan view; The M built-in gate resistor trenches are embedded in the semiconductor substrate; Among the M internal gate resistor trenches, K (M≧K≧2) trenches function as practical internal gate resistor trenches; The K practical built-in gate resistor trenches are the gate wiring is electrically connected to the wiring-side contact region of the gate wiring via a wiring contact provided through the interlayer insulating film; the gate pad is electrically connected to the pad-side contact region of the gate pad via a pad contact provided through the interlayer insulating film; a gate current path is provided between the wiring contact and the pad contact in each of the K practical built-in gate resistor trenches, and a distance between the wiring contact and the pad contact in the gate current path is defined as an inter-contact distance; the K practical built-in gate resistor trenches are physically connected to the wiring contacts and the pad contacts, respectively; Each of the M internal gate resistor trenches has a trench electrode and a trench insulating film covering the trench electrode, the trench electrode of each of the M internal gate resistor trenches has a constant resistor trench depth; a surface of the trench electrode of each of the M internal gate resistor trenches has a first formation width; a bottom surface of the trench electrode of each of the M internal gate resistor trenches has a second formation width; a difference between the first formation width and the second formation width is set to 1 / 10 or less of the first formation width; Semiconductor device.

13. A semiconductor device according to any one of claims 1 to 12, The switching element having an insulated gate structure is a MOSFET. Semiconductor device.

14. A method for manufacturing a semiconductor device, comprising the steps of: The semiconductor device includes: A semiconductor device including a switching element having an insulated gate structure, the switching element being provided on a semiconductor substrate of a first conductivity type, a gate wiring provided on the semiconductor substrate via an interlayer insulating film and electrically connected to a gate electrode of the switching element; a gate pad provided on the semiconductor substrate via the interlayer insulating film and having an electrical connection region with an exposed surface; an internal gate resistor region electrically connecting the gate wiring and the gate pad; the internal gate resistor region includes N (N≧2) partial internal gate resistor regions connected in parallel between the gate wiring and the gate pad, Each of the N partial internal gate resistor regions includes M (M≧2) internal gate resistor trenches connected in parallel between the gate wiring and the gate pad, the gate wiring has a wiring-side contact region overlapping with the M internal gate resistor trenches in a plan view; the gate pad has a pad-side contact region overlapping with the M internal gate resistor trenches in a plan view; The M built-in gate resistor trenches are embedded in the semiconductor substrate; Among the M internal gate resistor trenches, K (M≧K≧2) trenches function as practical internal gate resistor trenches; The K practical built-in gate resistor trenches are the gate wiring is electrically connected to the wiring-side contact region of the gate wiring via a wiring contact provided through the interlayer insulating film; the gate pad is electrically connected to the pad-side contact region of the gate pad via a pad contact provided through the interlayer insulating film; a gate current path is provided between the wiring contact and the pad contact in each of the K practical built-in gate resistor trenches, and a distance between the wiring contact and the pad contact in the gate current path is defined as an inter-contact distance; the K practical built-in gate resistor trenches are physically connected to the wiring contacts and the pad contacts, respectively; The method for manufacturing a semiconductor device includes: (a) determining a number K of the M internal gate resistor trenches that function as practical internal gate resistor trenches; (b) determining the contact distance for each of the K practical internal gate resistor trenches; (c) forming the semiconductor device so as to satisfy the determinations of steps (a) and (b). A method for manufacturing a semiconductor device.

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