Solid-state imaging device and imaging device using the same

Abstract

This solid-state imaging device is provided with: a pixel circuit (3); and a negative feedback circuit (21). The pixel circuit (3) is provided with a photodiode (PD), a charge storage unit (FD0) that holds a signal charge generated in the photodiode (PD), an amplification transistor (SF) that outputs a pixel signal corresponding to the signal charge of the charge storage unit (FD0), a first reset transistor (RS) that resets the charge storage unit (FD0), a first storage capacitive element (C1) for holding the signal charge, and a first transistor (GC1) that controls connection between the charge storage unit (FD0) and the first storage capacitive element (C1). The negative feedback circuit (21) negatively feeds back a feedback signal corresponding to a reset output of the amplification transistor (SF) to the charge storage unit (FD0) via the first reset transistor (RS).

Description

[Technical field]

[0001] The present invention relates to a solid-state imaging device and an imaging apparatus using the same. [Background technology]

[0002] Patent Document 1 discloses a negative feedback circuit that reduces reset noise. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 6,777,660 Summary of the Invention [Problem to be solved by the invention]

[0004] However, according to the conventional technology, it is difficult to expand the dynamic range and improve the signal-to-noise ratio at the same time.

[0005] Therefore, the present disclosure provides a solid-state imaging device and an imaging apparatus that achieve both an expansion of the dynamic range and an improvement in the signal-to-noise ratio. [Means for solving the problem]

[0006] In order to solve the above problems, the solid-state imaging device disclosed herein includes a pixel circuit and a negative feedback circuit, the pixel circuit including a photodiode, a charge storage section, a transfer transistor for transferring a signal charge generated in the photodiode to the charge storage section, an amplifying transistor for outputting a pixel signal corresponding to the signal charge of the charge storage section, a first reset transistor for resetting the charge storage section, a first storage capacitance element, and a first transistor for controlling a connection between the charge storage section and the first storage capacitance element, and the negative feedback circuit negatively feeds back a feedback signal corresponding to the reset output of the amplifying transistor to the charge storage section (FD0) via the first reset transistor. Transistor (TG)A switch element is provided between the photodiode (PD) and the storage capacitance element C, and at low illuminance, the first storage capacitance element is turned OFF to improve low illuminance image quality through CDS (correlated double sampling), and at high illuminance, the first storage capacitance element is turned ON to improve high illuminance image quality, while the negative feedback circuit reduces reset noise. Effect of the Invention

[0007] According to the solid-state imaging device and imaging device of the present disclosure, it is possible to achieve both an expansion of the dynamic range and an improvement in the signal-to-noise ratio. [Brief description of the drawings]

[0008] [Figure 1A] FIG. 1A is a diagram showing a first configuration example of a main part of a solid-state imaging device according to an embodiment of the present disclosure. [Figure 1B] FIG. 1B is a diagram showing a second configuration example of a main part of a solid-state imaging device according to an embodiment of the present disclosure. [Figure 1C] FIG. 1C is a diagram illustrating a third configuration example of a main part of a solid-state imaging device according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a block diagram showing an example of a configuration of a solid-state imaging device according to embodiment 1A. [Diagram 3] FIG. 3 is a diagram showing a plurality of regions in a pixel array portion. [Figure 4] FIG. 4 is a diagram showing a plurality of regions in a pixel array portion. [Diagram 5] FIG. 5 is a diagram showing an example of a main circuit including a pixel circuit and a negative feedback circuit according to the embodiment 1A. [Figure 6A] FIG. 6A is a diagram showing an example in which the solid-state imaging device in the embodiment 1A is configured as a stacked back-illuminated image sensor. [Figure 6B] FIG. 6B is a diagram showing an example in which the solid-state imaging device in embodiment 1A is configured as a stacked back-illuminated image sensor. [Figure 6C]FIG. 6C is a diagram showing an example in which the solid-state imaging device in the embodiment 1A is configured as a stacked back-illuminated image sensor. [Figure 6D] FIG. 6D is a diagram showing an example in which the solid-state imaging device in accordance with the embodiment 1A is configured as a stacked back-illuminated image sensor. [Figure 7] FIG. 7 is a time chart showing n-times exposure operations of the solid-state imaging device by the HCG readout operation in the embodiment 1A. [Figure 8] FIG. 8 is a diagram showing an example of timing of an LCG read operation in the embodiment 1A. [Figure 9] FIG. 9 is a diagram showing the read order of CDS in an LCG read operation. [Figure 10A] FIG. 10A is a diagram showing the waveform of a slope signal. [Figure 10B] FIG. 10B is a diagram showing the relationship between the slope period and the reset noise level. [Figure 11] FIG. 11 is a diagram showing the timing of charge accumulation in the photodiode and the storage capacitor element. [Figure 12A] FIG. 12A is a diagram showing a horizontal scanning row that is a unit for calculating the variation in reset noise. [Figure 12B] FIG. 12B is a diagram showing the variation (standard deviation) of reset noise in units of horizontal scanning rows. [Figure 13] FIG. 13 is a flowchart illustrating an example of a process for generating a slope signal. [Figure 14] FIG. 14 is a flowchart showing another example of a process for generating a slope signal. [Figure 15] FIG. 15 is a flowchart showing yet another example of a process for generating a slope signal. [Figure 16] FIG. 16 is a diagram showing an overview of how WDR is implemented within a pixel. [Figure 17] FIG. 17 is a diagram showing the FD potential in an HCG read operation for a low illuminance frame and an LCG read operation for a high illuminance frame. [Figure 18A]FIG. 18A is a diagram showing, as a comparative example, the relationship between the illuminance of the subject and the gain (SN ratio) in LCG readout when no negative feedback circuit is provided. [Figure 18B] FIG. 18B is a diagram showing the relationship between the illuminance of a subject and gain (SN ratio) in HCG readout according to the embodiment 1A. [Figure 18C] FIG. 18C is a diagram showing, as a comparative example, the relationship between the illuminance of the subject and the gain (SN ratio) in LCG readout when no negative feedback circuit is provided. [Figure 18D] FIG. 18D is a diagram showing the relationship between the illuminance of the subject and the gain (S / N ratio) in HCG readout according to the embodiment 1A. [Figure 19] FIG. 19 is a diagram showing the timing of charge accumulation in the photodiode and the storage capacitor element. [Figure 20A] FIG. 20A is a diagram showing an example of read timing in a state where a storage capacitance element is connected (that is, an LCG read operation). [Figure 20B] FIG. 20B is a diagram showing the read order of the reset components and signal components in the LCG read operation of FIG. 20A. [Figure 21] FIG. 21 is a diagram showing an example of a main circuit including a pixel circuit and a negative feedback circuit according to embodiment 2A. In FIG. [Figure 22] FIG. 22 is a diagram showing an example of the timing of an LCG read operation in a state in which the storage capacitance element according to the embodiment 2A is connected. [Diagram 23] FIG. 23 is a diagram showing an example of read timing in a state in which a storage capacitance element according to the embodiment 2B is connected. [Figure 24] FIG. 24 is a diagram showing an example of a main circuit including a pixel circuit and a negative feedback circuit according to embodiment 3A. In FIG. [Diagram 25] FIG. 25 is a diagram showing an example of the timing of an LCG read operation in a state in which the storage capacitance element according to the embodiment 3A is connected. [Figure 26] FIG. 26 is a diagram showing an example of the timing of an LCG read operation in a state in which a storage capacitance element according to the embodiment 3B is connected. [Figure 27] FIG. 27 is a diagram showing an example of a main circuit including a pixel circuit and a negative feedback circuit according to the fourth embodiment. In FIG. [Figure 28A] FIG. 28A is a time chart showing the read order of one frame in the fourth embodiment. [Figure 28B] FIG. 28B is a diagram showing the readout order of the reset components and signal components in the HCG readout and LCG readout of FIG. 28A. [Figure 29] FIG. 29 is a diagram illustrating a configuration example of a signal processing unit that performs WDR synthesis using two frames. [Figure 30A] FIG. 30A is a diagram showing, as a comparative example, the relationship between the illuminance of the subject and the gain (SN ratio) in LCG readout when no negative feedback circuit is provided. [Figure 30B] FIG. 30B is a diagram showing, as a comparative example, the relationship between the subject illuminance and the gain (SN ratio) in LCG readout when no negative feedback circuit is provided. [Figure 30C] FIG. 30C is a diagram showing the relationship between the subject illuminance and gain (SN ratio) in LCG readout according to the fourth embodiment. [Figure 30D] FIG. 30D is a diagram showing the relationship between the subject illuminance and gain (SN ratio) in LCG readout according to the fourth embodiment. [Figure 31A] FIG. 31A is a diagram showing, as a comparative example, the relationship between the subject illuminance and the signal output level (LSB) in LCG readout when no negative feedback circuit is provided. [Figure 31B] FIG. 31B is a diagram showing, as a comparative example, the relationship between the subject illuminance and the signal output level (LSB) in LCG readout when no negative feedback circuit is provided. [Figure 31C] FIG. 31C is a diagram showing the relationship between the subject illuminance and the signal output level (LSB) in LCG readout according to the fourth embodiment. [Figure 31D] FIG. 31D is a diagram showing the relationship between the subject illuminance and the signal output level (LSB) in LCG readout according to the fourth embodiment. [Diagram 32]FIG. 32 is a diagram showing an example of a main circuit including a pixel circuit and a negative feedback circuit according to the fifth embodiment. In FIG. [Figure 33A] FIG. 33A is a time chart showing the read order of one frame in the fifth embodiment. [Figure 33B] FIG. 33B is a diagram showing the readout order of the reset components and signal components in the HCG readout and LCG readout of FIG. 33A. [Figure 34A] FIG. 34A is a diagram showing an example of a circuit of a main part including a pixel circuit and a negative feedback circuit according to Embodiment 6. In FIG. [Figure 34B] FIG. 34B is a diagram showing a configuration example of a signal processing unit that performs WDR synthesis using three frames. [Figure 35A] FIG. 35A is a time chart showing the read order of one frame in the sixth embodiment. [Figure 35B] FIG. 35B is a diagram showing the readout order of reset components and signal components in the HCG readout, MCG readout, and LCG readout of FIG. 35A. [Diagram 36] FIG. 36 is a diagram showing an example of the timing relating to the accumulation of charges in the photodiode and two storage capacitor elements. [Figure 37] FIG. 37 is an explanatory diagram showing an overview of a synthesis method within a pixel of WDR. [Figure 38] FIG. 38 is a diagram showing the FD potential in the HCG readout, MCG readout, and LCG readout of FIG. [Figure 39A] FIG. 39A is a diagram showing, as a comparative example, the relationship between the illuminance of the subject and the gain (SN ratio) in LCG readout when no negative feedback circuit is provided. [Figure 39B] FIG. 39B is a diagram showing, as a comparative example, the relationship between the subject illuminance and the gain (SN ratio) in LCG readout when no negative feedback circuit is provided. [Figure 39C] FIG. 39C is a diagram showing the relationship between the subject illuminance and the gain (SN ratio) in LCG readout according to the sixth embodiment. [Figure 39D]FIG. 39D is a diagram showing the relationship between the subject illuminance and the gain (SN ratio) in LCG readout according to the sixth embodiment. [Diagram 40] FIG. 40 is a diagram showing an example of a main circuit including a pixel circuit and a negative feedback circuit according to the seventh embodiment. In FIG. [Figure 41A] FIG. 41A is a time chart showing the read order of one frame in the seventh embodiment. [Figure 41B] FIG. 41B is a diagram showing the read order of reset components and signal components in the HCG readout, MCG readout, and LCG readout of FIG. 41A. [Diagram 42] FIG. 42 is a diagram showing an example of a main circuit including a pixel circuit and a negative feedback circuit according to the eighth embodiment. In FIG. [Figure 43A] FIG. 43A is a time chart showing the read order of one frame in the eighth embodiment. [Figure 43B] FIG. 43B is a diagram showing the readout order of reset components and signal components in the HCG readout, MCG readout, and LCG readout of FIG. 43A. [Diagram 44] FIG. 44 is a diagram showing an example of the timing relating to the accumulation of charges in the photodiode and two storage capacitor elements. [Diagram 45] FIG. 45 is a diagram showing an example of a main circuit including a pixel circuit and a negative feedback circuit according to the ninth embodiment. In FIG. [Figure 46A] FIG. 46A is a time chart showing the read order of one frame in the ninth embodiment. [Figure 46B] FIG. 46B is a diagram showing the readout order of reset components and signal components in the HCG readout, MCG readout, and LCG readout of FIG. 46A. [Figure 47] FIG. 47 is a block diagram showing an example of a configuration of an imaging device according to the tenth embodiment. As shown in FIG. [Figure 48] FIG. 48 is a block diagram showing another example of the configuration of the imaging device according to the tenth embodiment. As shown in FIG. [Figure 49] FIG. 49 is a diagram showing an example of mounting the imaging device according to the tenth embodiment on an automobile. [Figure 50] FIG. 50 is a diagram showing an example of an imaging range in the mounting example of FIG. 49 according to the tenth embodiment. [Figure 51A] FIG. 51A is a diagram showing the relationship between the illuminance of the subject and the SN ratio when the FD capacitance directly connected to the photodiode is small in Patent Document 1. [Figure 51B] FIG. 51B is a diagram showing the relationship between the subject illuminance and the SN when the FD capacity is larger than that in FIG. 51A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] (Findings on which this disclosure is based) The present inventors have found that the solid-state imaging device described in the Background of the Invention has the following problems.

[0010] The solid-state imaging device disclosed in Patent Document 1 accumulates the signal charge generated in the photodiode directly in a floating diffusion layer (hereinafter referred to as FD capacitance), and reduces reset noise by a feedback circuit that inputs the reset level output from the source follower circuit to the reset transistor RS via a feedback amplifier and a feedback line.

[0011] Fig. 51A is a diagram showing the relationship between subject illuminance and signal-to-noise ratio (SN) when the FD capacitance directly connected to the photodiode in Patent Document 1 is small. The horizontal axis indicates subject illuminance, and the vertical axis indicates SN. min indicates the minimum subject illuminance at which imaging is possible, and max indicates the maximum subject illuminance. It can be seen that if the FD capacitance is made small, the minimum subject illuminance improves (becomes lower), but the maximum subject illuminance worsens (becomes lower) (Problem 1).

[0012] Conversely, Figure 51B shows the relationship between the subject illumination and the SN ratio when the FD capacity is large. It can be seen that if the FD capacity is increased, the minimum subject illumination becomes worse (higher), but the maximum subject illumination becomes better (higher) (Problem 2).

[0013] The dynamic range cannot be significantly expanded by increasing or decreasing the FD capacity.

[0014] Moreover, a configuration may be considered that allows the addition of another capacitive element to the FD capacitance in order to substantially expand or make the FD capacitance variable. However, adding a capacitive element would cause another problem in that reset noise would be more likely to occur (problem 3).

[0015] Therefore, the present disclosure provides a solid-state imaging device and an imaging apparatus that achieve both an expansion of the dynamic range and an improvement in the signal-to-noise ratio.

[0016] (Overview of a solid-state imaging device according to one embodiment of the present disclosure) A solid-state imaging device according to an embodiment of the present disclosure is provided with a group of storage circuits for overflow signal charge, each of which is a group of storage circuits, each of which is a switch element serving as an overflow gate and a storage capacitance element, arranged in series in multiple stages (m≧1) in order to hold signal charge overflowing from a photodiode. Here, there are a configuration in which the above-mentioned storage circuit groups are arranged in series in the horizontal direction relative to the photodiode PD, and a configuration in which the above-mentioned storage circuit groups are arranged in series in the vertical direction.

[0017] During the exposure period, when m=1, the charge that overflows from the photodiode PD is received by the storage capacitance element of the storage circuit. When m>2, the charge that overflows from this storage capacitance element is further received by a storage capacitance element in a subsequent storage circuit.

[0018] Furthermore, since the storage capacitance element in the storage circuit cannot completely transfer the signal charge, reset noise occurs when the signal is shuttered and reset. Here, reset noise refers to kTC noise. The noise level is expressed in terms of charge amount as √(kTC)(C) or √(kTC) / e(ele), and in terms of voltage as √(kT / C)(V). In order to suppress such reset noise, the solid-state imaging device according to one aspect of the present disclosure further includes a negative feedback circuit that negatively feeds back the reset signal.

[0019] Next, three configuration examples of a solid-state imaging device according to one embodiment of the present disclosure will be described with reference to FIGS. 1A to 1C.

[0020] [0.1 First configuration example of solid-state imaging device] First, a first configuration example will be described. The first configuration example shows a configuration in which the above-mentioned storage circuits are connected in two stages (m=2) in the vertical direction.

[0021] FIG. 1A is a diagram showing a first configuration example of a main part of a solid-state imaging device 100 according to an embodiment of the present disclosure.

[0022] The solid-state imaging device 100 in FIG. 1A includes a pixel circuit 3 and a negative feedback circuit 21.

[0023] In the figure, one of a plurality of pixel circuits 3 arranged in a matrix is ​​shown. The pixel circuit 3 includes a photodiode PD, a transfer transistor TG, a charge storage unit FD0, , Increase The pixel circuit includes a width transistor SF, a reset transistor RS, a first storage capacitance element C1, a first transistor GC1, a second storage capacitance element C2, a second transistor GC2, and a selection transistor SEL.

[0024] The photodiode PD is a photoelectric conversion element that converts incident light into a signal charge. The signal charge that overflows the photodiode PD during exposure is transferred to and held in the first storage capacitor element C1, as indicated by the dotted arrow in the figure. Furthermore, the signal charge that overflows from the first storage capacitor element C1 is transferred to and held in the second storage capacitor element C2.

[0025] The charge storage unit FD0 is formed as, for example, a floating diffusion layer, and holds the signal charge generated in the photodiode PD. In the figure, the capacitance of the charge storage unit FD0, or the charge storage unit FD0 as a capacitive element, is denoted as C0.

[0026] The amplification transistor SF outputs a pixel signal corresponding to the signal charge in the charge storage unit FD0 to the vertical signal line 19 via the selection transistor SEL.

[0027] The reset transistor RS resets the charge storage unit FD0. Specifically, the reset transistor RS can perform three types of resetting by controlling the first transistor GC1 and the second transistor GC2. That is, the reset transistor RS can (i) reset the floating diffusion layer FD0, the first storage capacitance element C1, and the second storage capacitance element C2, (ii) reset the first storage capacitance element C1 and the second storage capacitance element C2, and (iii) reset the second storage capacitance element C2.

[0028] The first storage capacitor C1 holds the signal charge overflowing from the photodiode PD. For example, the first storage capacitor C1 accumulates the signal charge overflowing from the photodiode PD during exposure via the transfer transistor TG and the first transistor GC1.

[0029] The first transistor GC1 is a transistor that controls the connection between the charge storage unit FD0 and the first storage capacitance element C1. The first transistor GC1 is in an on state and an off state as a switch element. Furthermore, the gate voltages of the transfer transistor TG and the first transistor GC1 do not have to be in a completely off state during exposure, and are set so that the signal charge overflowing from the photodiode PD can be transmitted from the transfer transistor TG to the first storage capacitance element C1 via the charge storage unit FD0 and the first transistor GC1.

[0030] The second storage capacitor C2 holds the signal charge overflowing from the first storage capacitor C1. For example, the second storage capacitor C2 stores the signal charge overflowing from the first storage capacitor C1 via the second transistor GC2.

[0031] The second transistor GC2 is a gain control transistor that controls the connection between the first storage capacitor element C1 and the second storage capacitor element C2. The second transistor GC2 is a switching element that can be in an on state or an off state. Furthermore, the gate voltage of the second transistor GC2 does not have to be in a completely off state during exposure, and is set so that the signal charge overflowing from the first storage capacitor element C1 can be transmitted to the second storage capacitor element C2 via the second transistor GC2.

[0032] The selection transistor SEL is a switch element that selects whether or not to output a pixel signal from the amplification transistor SF to the vertical signal line 19. There are at least two types of pixel signals: a reset level and a signal level.

[0033] One negative feedback circuit 21 is provided for each column of pixel circuits 3. Alternatively, one negative feedback circuit 21 is provided for each pixel circuit 3. The negative feedback circuit 21 negatively feeds back a feedback signal corresponding to the reset output of the amplification transistor SF from the vertical signal line 19 to the charge storage unit FD0 via the feedback line 20 and the first reset transistor RS. Specifically, the negative feedback circuit 21 has a feedback amplifier FA. The reset output of the amplification transistor SF is input to the negative input terminal of the feedback amplifier FA via the vertical signal line 19. A reference voltage VREF, which is a reference for the reset level, is input to the positive input terminal of the feedback amplifier FA. The output terminal of the feedback amplifier FA negatively feeds back the difference between the reference voltage VREF and the reset output to the charge storage unit FD0 via the feedback line 20 and the first reset transistor RS.

[0034] In the first configuration example of the solid-state imaging device 100 shown in FIG. 1A, in order to hold the signal charge overflowing from the photodiode PD, a group of storage circuits for overflow is provided, each group consisting of a switch element and a storage capacitance element, and configured in series in multiple stages (m≧1). FIG. 1A shows an example where m=2. The first-stage storage circuit is a group of a first transistor GC1 and a first storage capacitance element C1. The second-stage storage circuit is a group of a second transistor GC2 and a second storage capacitance element C2. The group of a transfer transistor TG and a charge storage unit FD0 may be regarded as the 0th-stage storage circuit. The storage circuit group is a source of reset noise, but is reset by the negative feedback circuit 21. This makes it possible to suppress the reset noise.

[0035] With this configuration, it is possible to achieve both an expansion of the dynamic range and an improvement in the signal-to-noise ratio.

[0036] [0.2 Second configuration example of solid-state imaging device] Next, a second configuration example will be described below. The second configuration example shows a configuration in which the above-mentioned storage circuits are connected in two stages (m=2) in the horizontal direction.

[0037] Fig. 1B is a diagram showing a second configuration example of a main part of a solid-state imaging device 100 according to an embodiment of the present disclosure. The second configuration example in Fig. 1B is different from the first configuration example in Fig. 1A in the circuit configuration inside the pixel circuit 3. The following mainly describes the differences.

[0038] The pixel circuit 3 differs from that of FIG. 1A in that a first storage capacitance element C3, a first transistor GC, a second storage capacitance element C4, and a second transistor TGC are added instead of the first storage capacitance element C1, the first transistor GC1, the second storage capacitance element C2, and the second transistor GC2.

[0039] The signal charge that overflows the photodiode PD during exposure is transferred to and stored in the second storage capacitor element C4, as indicated by the dotted arrow in the figure. Although there is no overflow element OF between the photodiode PD and the second storage capacitor element C4, the potential structure ensures that the charge is transferred through this path.

[0040] The reset transistor RS can be reset in three ways by controlling the first transistor GC and the second transistor TGC: (i) the reset transistor RS can reset the floating diffusion layer FD0, the first storage capacitance element C3, and the second storage capacitance element C4, (ii) the first storage capacitance element C3 and the second storage capacitance element C4, and (iii) the first storage capacitance element C3.

[0041] When the transfer transistor TG is in an on state, the charge overflowing from the charge storage unit FD0 is transferred to and held in the first storage capacitor element C3 as indicated by the dotted arrow in the figure.

[0042] The first transistor GC is a transistor that controls the connection between the charge storage unit FD0 and the first storage capacitance element C3. The first transistor GC serves as a switching element and is in an on state or an off state.

[0043] The signal charge that overflows the photodiode PD during exposure is transferred to and held in the second storage capacitor element C4, as indicated by the dotted arrows in the figure.

[0044] The second transistor TGC is a transistor for gain control that controls the connection between the first storage capacitor element C3 and the second storage capacitor element C4. The second transistor TGC serves as a switching element and is in an on state and an off state.

[0045] In the second configuration example of the solid-state imaging device 100 shown in FIG. 1B, in order to hold the signal charge overflowing from the photodiode PD, a group of storage circuits for overflow is provided, each group consisting of a switch element and a storage capacitance element, and configured in series in multiple stages (m≧1). FIG. 1B shows an example where m=2. The first-stage storage circuit is a group consisting of a first transistor GC and a first storage capacitance element C3. The second-stage storage circuit is a group consisting of a second transistor TGC and a second storage capacitance element C4. The group consisting of a transfer transistor TG and a charge storage unit FD0 may be regarded as the 0th-stage storage circuit.

[0046] This second configuration example makes it possible to achieve both an expansion of the dynamic range and an improvement in the signal-to-noise ratio.

[0047] [0.3 Third configuration example of solid-state imaging device] Next, a third configuration example will be described. The third configuration example shows a configuration in which an overflow element is added to the second configuration example in which the above-mentioned storage circuits are connected in two stages (m=2) in the horizontal direction.

[0048] Fig. 1C is a diagram showing a third configuration example of a main part of a solid-state imaging device 100 according to an embodiment of the present disclosure. The third configuration example in Fig. 1C differs from the second configuration example in Fig. 1B in that an overflow element OF is added to the pixel circuit 3. The following mainly describes the differences.

[0049] The overflow element OF does not transmit the signal charge overflowing from the photodiode PD to the second storage capacitor element C3 via the transfer transistor TG, but transmits it to the first storage capacitor element C4 via the overflow element OF.

[0050] Furthermore, the signal charge that has overflowed from the first storage capacitor element C4 is transferred to the second storage capacitor element C3 via the first transistor TGC.

[0051] In the third configuration example of Fig. 1C, as shown by the dotted arrow, the direction in which the signal charge overflowing from the photodiode PD flows is the same as in the second configuration example of Fig. 1B. In the third configuration example, the signal charge overflowing from the photodiode PD is accumulated in the accumulation capacitance C4 without passing through the charge accumulation section FD0, so that the dark current component can be reduced more than in the first configuration example. In addition, since there is an overflow element OF, it is possible to control the overflow level more than in the second configuration example.

[0052] In the above first to third configuration examples, an operation of capturing an image of a low-illuminance frame, an operation of capturing an image of a high-illuminance frame, an operation of combining a low-illuminance frame and a high-illuminance frame, an operation of combining a low-illuminance frame, a medium-illuminance frame and a high-illuminance frame, etc. are performed.

[0053] Here, the low illuminance frame refers to a frame captured with all m-stage storage circuits turned off, for example, and is suitable for low illuminance environments. The high illuminance frame refers to a frame captured with all m-stage storage circuits turned on, for example, and is suitable for high illuminance environments. The medium illuminance frame refers to a frame captured with some of the m-stage storage circuits turned on, for example, and is suitable for medium illuminance environments. Note that high illuminance, medium illuminance, and low illuminance do not mean absolute illuminance, but rather mean a relative relationship.

[0054] For example, in capturing an image of a low-illuminance frame, the image is captured with the m-stage storage circuit in an OFF state, so that the signal charge completely transferred from the photodiode PD to the charge storage unit FD0 is read out by CDS (=signal component-reset component).

[0055] In addition, when capturing a high-illuminance frame, a gentle slope signal is applied to the control voltage of the switch element in each storage circuit to transition from the ON state to the OFF state, while negative feedback via the feedback amplifier FA reduces the reset noise of the storage capacitance element. Furthermore, it is possible to read out and combine the signal from the photodiode PD and the signal from the storage capacitance element separately.

[0056] This makes it possible to further expand the dynamic range by matching and synthesizing the signal components read out in low-illumination areas with the signal components read out in high-illumination areas, or by selectively reading out appropriate frames depending on the illuminance.

[0057] According to this method, when capturing an image of a low-illumination frame, by using only the signal charge transferred from the photodiode PD to the charge storage unit FD0, the in-pixel gain, that is, the gain by which the signal charge is converted into a voltage by the amplifying transistor SF, can be increased, and the voltage (pixel signal) according to the amount of received light can be increased against the noise generated by the amplifying transistor SF and the analog circuit. In other words, for a dark subject, it is possible to output a high-quality image with a high SN (Signal to Noise Ratio).

[0058] On the other hand, in capturing high-illumination frames, the dynamic range is expanded by using an m-stage storage circuit to lower the gain in the pixel, making it possible to receive high-illumination light. Furthermore, the signal-to-noise ratio can be improved by the negative feedback circuit 21. In other words, for bright subjects, the gradation according to the subject is accurately reproduced, making it possible to output an image without overexposure.

[0059] Therefore, the inventors have developed a technique for expanding the dynamic range and improving the S / N ratio by adding storage capacitance elements (C1, C2, C3, C4) to the photodiode PD and further comprising switch elements (transistors (GC1, GC2, GC) and a transfer element for stored charge (TGC)). This makes it possible to expand the dynamic range and improve the S / N ratio. Furthermore, although increasing the signal level normally deteriorates the S / N ratio, it is possible to suppress the deterioration of the S / N ratio even when the signal level is increased.

[0060] Furthermore, the three frames used for WDR (Wide Dynamic Range) - low-illumination, medium-illumination, and high-illumination - can be generated at exactly the same time using exactly the same pixels, which makes it possible to eliminate false colors, discoloration, and blurring.

[0061] In addition to the rolling shutter method, it can also be expanded to the global shutter method, which allows it to be deployed as a TOF (Time Of Flight) distance measuring device.

[0062] In addition, the number of frames for WDR can be expanded from two or three to five depending on the number of stages m of the storage circuit, thereby expanding the dynamic range.

[0063] Generally, it is very difficult to use a highly saturated pixel, but this embodiment makes it possible to increase the saturation level with a small capacitance of the photodiode PD. In order to increase the storage capacitance in the storage circuit, the voltage amplitude between the capacitance terminals must be increased, and in order to increase the capacitance area within a limited pixel cell, a solid-state imaging Device The semiconductor chips constituting the device may be three-dimensional or multi-layered.

[0064] For example, the storage capacitance element in the storage circuit may be disposed on a semiconductor chip having pixels, or on a semiconductor chip having a logic circuit. Even if disposed on a semiconductor chip having pixels, the storage capacitance element may be formed on the top layer or on the bottom layer of the metal layer.

[0065] In addition, the contact or plug section for connecting the wiring of the storage capacitance element to the silicon substrate can be a source of dark characteristics (dark current, noise, fixed roughness).In addition, the pixel chip and logic chip can also be a source of dark characteristics (dark current, noise, fixed roughness) at the TSV connection section and hybrid connection section.

[0066] When these noises are superimposed on the reset noise, they can be reduced by the negative feedback circuit 21, and lower noise can be achieved compared to when the negative feedback circuit 21 is not used.

[0067] As described in the above overview, a solid-state imaging device according to one embodiment of the present disclosure includes a pixel circuit 3 and a negative feedback circuit 21. The pixel circuit 3 includes a photodiode PD, a charge storage unit FD0, a transfer transistor TG that transfers signal charge generated in the photodiode PD to the charge storage unit FD0, an amplification transistor SF that outputs a pixel signal corresponding to the signal charge of the charge storage unit FD0, a first reset transistor RS that resets the charge storage unit FD0, a first storage capacitance element C1 / C4, and a first transistor GC1 / TGC that controls the connection between the charge storage unit FD0 and the first storage capacitance element C1 / C4. The negative feedback circuit 21 negatively feeds back a feedback signal corresponding to the reset output of the amplification transistor SF to the charge storage unit FD0 via the first reset transistor RS.

[0068] According to this, the dynamic range can be expanded by expanding and switching the saturated signal charge amount by the first storage capacitance element C1 or C4 and the first transistor GC1 / TGC. In addition, since the charge storage unit FD0 and the first storage capacitance element C1 or C4 can be reset to the reset level by the negative feedback circuit 21, the kTC noise at the time of resetting can be suppressed and the image quality can be improved.

[0069] Here, the gate voltages of the transfer transistor TG and the first transistors GC1 / TGC may be set so that signal charges overflowing from the photodiode PD during exposure can be transferred to the first storage capacitor elements C1 / C4.

[0070] According to this, it is possible to generate a pixel signal for low illuminance and a pixel signal for high illuminance by utilizing the overflowing signal charge, and the dynamic range can be easily expanded.

[0071] Here, the first transistor GC1 may be connected in series with the first reset transistor RS between the first reset transistor RS and the charge storage unit FD0, and the first storage capacitance element C1 may be connected to the connection point between the first reset transistor RS and the first transistor GC1.

[0072] This allows the storage circuit shown in the first configuration example of Fig. 1A to be configured with at least one stage in the vertical direction. For example, it becomes possible to selectively or simultaneously generate pixel signals for low-illuminance frames and pixel signals for high-illuminance frames.

[0073] Here, the first transistor TGC may connect the connection point between the first reset transistor RS and the charge storage unit FD0 to the first storage capacitance element C4.

[0074] This allows the storage circuit shown in the second configuration example of Fig. 1C to be configured with at least one stage in the horizontal direction. For example, it becomes possible to selectively or simultaneously generate pixel signals for low-illuminance frames and pixel signals for high-illuminance frames.

[0075] Here, the solid-state imaging device may further include an overflow element OF that transfers signal charges overflowing from the photodiode PD to the first storage capacitor element C4.

[0076] 1C in the third configuration example, at least one stage can be provided in the horizontal direction, and an overflow element OF can be provided. For example, the overflowed signal charge can be transmitted to the first storage capacitance element without passing through the charge storage unit FD0, so that noise due to dark current, etc. can be suppressed.

[0077] Here, the solid-state imaging device may further include a second transistor GC2 inserted in series between the first reset transistor RS and the first transistor GC1, and a second storage capacitance element C2 connected to the connection point between the first reset transistor RS and the second transistor GC2 and connected to the charge storage section FD0 via the first transistor GC1 and the second transistor GC2.

[0078] According to this, it is possible to configure the storage circuit shown in the first configuration example of Fig. 1A to have at least two stages in the vertical direction. For example, it becomes possible to selectively or simultaneously generate pixel signals for low illuminance frames, pixel signals for medium illuminance frames, and pixel signals for high illuminance frames. It is also possible to expand the dynamic range by synthesizing low illuminance frames and medium illuminance frames.

[0079] Here, the solid-state imaging device may further include a second transistor GC inserted between the connection point between the first reset transistor RS and the first transistor TGC and the charge storage section FD0, and a second storage capacitance element C3 connected to the connection point between the first reset transistor RS and the first transistor TGC.

[0080] According to this, it is possible to configure the storage circuit shown in the second and third configuration examples of Figures 1B and 1C to have at least two stages in the horizontal direction. For example, it becomes possible to selectively or simultaneously generate pixel signals for low illuminance frames, pixel signals for medium illuminance frames, and pixel signals for high illuminance frames. It is also possible to expand the dynamic range by synthesizing low illuminance frames and medium illuminance frames.

[0081] Here, the solid-state imaging device may include a plurality of pixel circuits 3, a drive section that drives the plurality of pixel circuits 3 to perform simultaneous exposure, and a control circuit that scans the plurality of pixel circuits 3 to read out pixel signals.

[0082] This enables a global shutter that exposes all pixels simultaneously, expands the dynamic range, and suppresses kTC noise during reset, improving image quality.

[0083] Here, the solid-state imaging device includes a control circuit that reads out from the pixel circuit 3 a first pixel signal for constituting a first frame and a second pixel signal for constituting a second frame for a higher illuminance than the first frame, the first pixel signal corresponding to a signal charge transferred from the photodiode PD to the charge accumulation unit FD0, the second pixel signal corresponding to a signal charge transferred and mixed from the photodiode PD to the charge accumulation unit FD0 and the first storage capacitance element C1, and the first pixel signal and the second pixel signal may be based on signal charges generated in the photodiode PD of one pixel circuit 3 during the same exposure period.

[0084] This makes it possible to simultaneously generate a first frame for low illuminance and a second frame for high illuminance within one frame period, thereby expanding the dynamic range and suppressing kTC noise during reset.

[0085] Here, the solid-state imaging device includes a control circuit that reads out from the pixel circuit 3 a first pixel signal for constituting a first frame, a second pixel signal for constituting a second frame for an illuminance higher than that of the first frame, and a third pixel signal for constituting a third frame for an illuminance higher than that of the second frame, wherein the first pixel signal corresponds to a signal charge transferred from the photodiode PD to the charge accumulation unit FD0, the second pixel signal corresponds to a signal charge transferred and mixed from the photodiode PD to the charge accumulation unit FD0 and the first storage capacitance element C1, and the third pixel signal corresponds to a signal charge transferred and mixed from the photodiode PD to the charge accumulation unit FD0, the first storage capacitance element C1, and the second storage capacitance element C2, and the first pixel signal, the second pixel signal, and the third pixel signal may be based on signal charges generated in the photodiode PD of one pixel circuit 3 during the same exposure period.

[0086] This makes it possible to simultaneously expose and generate a first frame for low illumination, a second frame for medium illumination, and a third frame for high illumination within one frame period, thereby further expanding the dynamic range and suppressing noise during reset.

[0087] Here, the solid-state imaging device includes a control circuit that reads out from the pixel circuit 3 a first pixel signal constituting a first frame, a second pixel signal constituting a second frame for an illuminance higher than that of the first frame, and a third pixel signal constituting a third frame for an illuminance higher than that of the second frame, wherein the first pixel signal corresponds to a signal charge transferred from the photodiode PD to the charge accumulation unit FD0, the second pixel signal corresponds to a signal charge transferred and mixed from the photodiode PD to the charge accumulation unit FD0 and the first storage capacitance element C1, and the third pixel signal corresponds to a signal charge transferred and mixed from the photodiode PD to the charge accumulation unit FD0, the first storage capacitance element C1, and the second storage capacitance element C2, and the first pixel signal, the second pixel signal, and the third pixel signal may be based on signal charges generated in the photodiode PD of one pixel circuit 3 during different exposure periods.

[0088] This makes it possible to generate a first frame for low illuminance, a second frame for medium illuminance, and a third frame for high illuminance by exposing them at different times within one frame period, thereby further expanding the dynamic range and suppressing kTC noise during reset.

[0089] Here, the control signal input to at least the first reset transistor RS of the first transistor and the first reset transistor RS may have a slope-shaped voltage waveform that gradually transitions from an on state to an off state.

[0090] According to this, by resetting using the negative feedback circuit 21, the occurrence of reset noise can be further suppressed.

[0091] Here, the solid-state imaging device may further include a measurement unit that measures the reset noise level for pixel circuits 3 that belong to a predetermined region among the multiple pixel circuits 3, and a determination unit that determines the inclination of the sloping voltage waveform so as to reduce the variation in the reset noise level based on the measurement results.

[0092] This makes it possible to suppress the reset noise level in accordance with the characteristics of the solid-state imaging device.

[0093] Here, the measurement unit may measure the reset level while changing the slope of the voltage waveform for each row of pixel circuits belonging to the specified region, and the determination unit may determine an optimal slope of the voltage waveform based on the variation for each row of pixel circuits belonging to the specified region.

[0094] According to this, even if the characteristics of the solid-state imaging device change, the reset noise level can be appropriately suppressed.

[0095] Here, the solid-state imaging device may include a negative feedback circuit 21 for each column of a plurality of pixel circuits 3 arranged in a matrix, or for each pixel circuit 3, and the negative feedback circuit 21 may include a first feedback amplifier that outputs a feedback signal to the first reset transistor RS of the pixel circuit 3 belonging to the corresponding column, or to the first reset transistor RS of the corresponding pixel circuit 3.

[0096] According to this, the negative feedback circuit 21 can be provided for each column of pixel circuits 3 or for each pixel circuit 3.

[0097] Here, the negative feedback circuit 21 is provided for each column, the pixel circuit (3) further includes a second reset transistor RS2 that resets the charge storage unit FD0, and the negative feedback circuit 21 may further include a second feedback amplifier that outputs a feedback signal to the second reset transistor RS2 of the pixel circuit 3 belonging to the corresponding column.

[0098] This allows two different pixel rows to be reset by the negative feedback circuit 21. For example, it is possible to execute reset at the start of exposure on one row, and execute reset at the time of readout on the other row.

[0099] Here, the solid-state imaging device may include a first semiconductor chip and a second semiconductor chip bonded together, the first semiconductor chip having a photodiode PD and a first storage capacitance element C1 / C4 of each pixel circuit, and the second semiconductor chip having a first feedback amplifier corresponding to each column of the pixel circuits or corresponding to each pixel circuit.

[0100] This increases the degree of freedom in the design of the layout of the negative feedback circuit 21 and the first storage capacitance element C1, and enables negative feedback to be applied for each column or each pixel, thereby making it possible to relatively reduce parasitic resistance and parasitic capacitance. By increasing the speed, high-frequency noise can also be reduced, and reset noise can be reduced.

[0101] Here, the negative feedback circuit 21 may be provided for each pixel circuit, and the solid-state imaging device may include a first semiconductor chip and a second semiconductor chip bonded together, the first semiconductor chip may include a photodiode PD for each pixel circuit, and the second semiconductor chip may include a first feedback amplifier and a first storage capacitance element C1 / C4 corresponding to each pixel circuit.

[0102] According to this, negative feedback is applied to each pixel, which increases the speed, so that high frequency noise can be reduced and reset noise can be significantly reduced.

[0103] Here, the solid-state imaging device may include a first semiconductor chip and a second semiconductor chip bonded together, the first semiconductor chip having a photodiode PD and a charge storage unit FD0 of each pixel circuit, and the second semiconductor chip having a first storage capacitance element C1 / C4 of each pixel circuit.

[0104] According to this, the first semiconductor chip can be equipped with a photodiode PD and a storage capacitance element C for each pixel, and the second semiconductor chip can be equipped with a storage capacitance element for each pixel, thereby significantly expanding the dynamic range.

[0105] Moreover, an imaging device according to one embodiment of the present disclosure is an imaging device including the above-mentioned solid-state imaging device, wherein the imaging device corresponds to at least one of a view system for use in transportation equipment, a sensing system for an ADAS advanced driver assistance system, and a sensing system for autonomous driving, and the imaging device is mounted on at least one of the front, surround, side, rear, and room mirror of the transportation equipment.

[0106] Hereinafter, a solid-state imaging device according to an embodiment of the present disclosure will be described with reference to the drawings.

[0107] (Embodiment 1A) First, a configuration example of a solid-state imaging device according to the present embodiment will be described. In embodiment 1A, a configuration example in which one storage circuit is provided in the vertical direction in the first configuration example of FIG.

[0108] [1A.1 Configuration example of solid-state imaging device 100] FIG. 2 is a block diagram showing an example of a configuration of the solid-state imaging device 100 according to the embodiment 1A.

[0109] The solid-state imaging device 100 shown in the figure includes a pixel array section 10, a horizontal scanning circuit 12, a vertical scanning circuit 14, a plurality of vertical signal lines 19, a timing control section 200, a column processing section 26, a reference signal generating section 27, an output circuit 28, and signal processing sections 70 and 80. The solid-state imaging device 100 also includes an MCLK terminal for receiving an input of a master clock signal from the outside, a DATA terminal for transmitting commands or data to and from the outside, a D1 terminal for transmitting video data to the outside, and other terminals to which a power supply voltage and a ground voltage are supplied.

[0110] The pixel array section 10 has a plurality of pixel circuits 3 arranged in a matrix. In Fig. 2, the plurality of pixel circuits 3 are arranged in n rows and m columns. Each pixel circuit 3 includes a high sensitivity pixel, a storage capacitance element (C1, C2, C3, C4), an overflow element (OF), a gain control element (GC1, GC2, GC), a storage charge transfer element (TGC), and a charge transfer element (TG). The overflow element is also called an overflow gate.

[0111] The horizontal scanning circuit 12 sequentially scans the memories 256 in the multiple column AD circuits 25 to output AD converted pixel signals to the signal processing units 70 and 80 via horizontal signal lines. This scanning may be performed in the same order as the arrangement of the column AD circuits 25.

[0112] The vertical scanning circuit 14 scans horizontal scanning line groups (also called row control line groups) 15 provided for each row of pixel circuits 3 in the pixel array section 10, on a row-by-row basis. In this way, the vertical scanning circuit 14 selects pixel circuits 3 on a row-by-row basis, and causes pixel circuits 3 belonging to the selected row to simultaneously output pixel signals to m vertical signal lines 19. The number of horizontal scanning line groups 15 provided is the same as the number of rows of pixel circuits 3.

[0113] 2, n horizontal scanning line groups 15 (V1, V2, . . . , Vn in FIG. 2) are provided. Each of the horizontal scanning line groups 15 includes a reset control line φRS, a transfer control line φ(TG)C for accumulated charges, gain control lines φGC1, φGC2, φGC, a selection control line φSEL, and an overflow control line φOF.

[0114] The vertical signal line 19 is provided for each column of pixel circuits 3 in the pixel array unit 10, and transmits pixel signals from pixel circuits 3 belonging to a selected row to the column AD circuit 25. The multiple vertical signal lines 19 are made up of m+1 vertical signal lines (H0, . . . , Hm) in Fig. 2. The multiple ADC input lines are made up of m+1 ADC input lines (ADIN0, . . . , ADINm) in Fig. 2.

[0115] The slope signal generating unit 30 determines the slopes of the control signals of at least the reset control line φRS, which are the control signal switching elements of the pixel transistors, as well as the accumulated charge transfer control line φTGC, the gain control lines φGC1, φGC2, φGC, and the overflow control line φOF, to generate an optimal slope signal and reduce reset noise.

[0116] The output signals supplied from the slope signal generating unit 30 are supplied to the vertical scanning circuit 14 as pixel control signals (V1, V2, . . . , Vn) based on the control signal group CN1.

[0117] The timing control section 200 generates various control signals to control the entire solid-state imaging device 100. The various control signals include control signals CN1, CN2, CN4, CN5, and CN8, and counter clock signals CK0 and CK1. For example, the timing control section 200 receives a master clock MCLK via a terminal, generates various internal clocks, and controls the horizontal scanning circuit 12, the vertical scanning circuit 14, etc.

[0118] The column processing unit 26 includes a column AD circuit 25 provided for each column. Each column AD circuit 25 performs AD conversion on the pixel signal from the vertical signal line 19.

[0119] Each of the column AD circuits 25 includes a feedback amplifier FA, a voltage comparator 252, a counter unit 254, and a memory 256.

[0120] The feedback amplifier FA compares the analog pixel signal from the vertical signal line 19 with a reference signal VREF generated by a reference signal generator 29, and when the reference signal VREF becomes larger than the pixel signal, for example, the output signal is fed back to the pixel so that the pixel signal becomes larger, thereby forming a negative feedback circuit 21. The feedback lines 20, which are the multiple output signal lines of the feedback amplifier FA, consist of (m+1) lines, which is the same as the number of columns (H0, . . . , Hm) in Fig. 2, or twice that number, 2x(m+1) lines. Note that here, when shuttering and resetting are performed simultaneously, there are (m+1) lines, and when shuttering and resetting are not performed simultaneously, there are 2x(m+1) lines.

[0121] The voltage comparator 252 compares the analog pixel signal from the vertical signal line 19 with a reference signal RAMP including a ramp waveform (i.e., a triangular wave) generated by the reference signal generation unit 27, and inverts an output signal indicating the comparison result, for example, when the former becomes larger than the latter.

[0122] The counter unit 254 counts the time from when the triangular wave in the reference signal RAMP starts to change until the output signal of the voltage comparator 252 inverts. Since the time until inversion is determined according to the value of the analog pixel signal, the count value becomes the value of the digitized pixel signal.

[0123] The memory 256 holds the count value of the counter unit 254, that is, the digital pixel signal.

[0124] The reference signal generating unit 27 generates a reference signal RAMP including a triangular wave, and outputs the reference signal RAMP to the positive input terminal of the voltage comparator 252 in each column AD circuit 25 .

[0125] The output circuit 28 outputs the digital pixel signal to a video data terminal D1.

[0126] The signal processing unit 70 includes a WDR synthesis circuit 76, a memory 77, and a low-illumination signal Generate Circuit 71, medium illuminance signal Generate Circuit 72, high intensity signal GenerateIt is composed of a circuit 73 and a WDR synthesis circuit 76.

[0127] The signal processing unit 80 detects the reset noise in the reset noise detection region by the noise calculation circuit 86, and stores the optimum value of the noise in the optimum value holding circuit 87. The reset noise detection region is, for example, the OB region in FIG. A 14, or the pre-OB region in Fig. 4 A 3 and 4 are diagrams showing a plurality of regions in the pixel array section 10. The OB region A14 is a region including optical black pixels. The pre-OB region A15 is a region of the OB region that is designated for a specific purpose such as reset noise detection. The effective region A16 is a region including pixel circuits 3 for forming an image by imaging. Then, as soon as the signal processing section 80 finishes searching in the reset noise detection region, it transmits the optimal value to the timing control circuit, and the slope signal generating section 30 generates the optimal slope voltage, i.e., the effective region A16 in FIG. A 16, OB region in Fig. 4 A 14 and the effective area A Read out the signal at 16.

[0128] As a result, in the signal processing units 70 and 80, it is possible to achieve both an expansion of the dynamic range and an improvement in the S / N ratio.

[0129] The vertical scanning circuit 14, the reference signal generating unit 27, the standard signal generating unit 29, the slope signal generating unit 30, and the feedback line 20 may be collectively referred to as a driving unit. The column processing unit 26 and the horizontal scanning circuit 12 may be collectively referred to as a control unit. The noise calculation circuit 86 may be referred to as a measurement unit. The optimal value holding circuit 87 may be referred to as a determination unit.

[0130] [1A.2 Example of pixel circuit configuration] Next, a configuration example of the pixel circuit 3 will be described.

[0131] 5 is a diagram showing an example of a main circuit including a pixel circuit 3 according to embodiment 1A and a negative feedback circuit 21. The pixel circuit 3 in the diagram includes a photodiode PD, a transfer transistor TG, a storage capacitance element C1, a floating diffusion layer FD1, a parasitic capacitance C0, a floating diffusion layer FD0, a reset transistor RS, a gain control transistor GC1, an amplification transistor SF, and a selection transistor SEL.

[0132] The horizontal scanning line group 15 includes a reset control line φRS, a readout control line φTG, a gain control line φGC1, and a selection control line φSEL.

[0133] The photodiode PD is a photoelectric conversion element such as a photodiode, and performs photoelectric conversion with a predetermined sensitivity, that is, generates an electric charge according to the amount of received light.

[0134] Furthermore, the capacitance C0 connected to the floating diffusion layer FD0 holds the signal charge (e.g., electrons) transferred from the photodiode PD, converts the held signal charge into a voltage, and supplies the converted voltage to the gate of the amplifying transistor SF. The substantial capacitance of the floating diffusion layer FD0 includes not only the capacitance of the floating diffusion layer FD0 itself, but also the gate capacitance of the amplifying transistor SF, the gate-drain capacitance of the amplifying transistor SF, and the floating capacitance of the source wiring of the gain control transistor GC1 when the gain control transistor GC1 is off.

[0135] The transfer transistor (TG) is a switch transistor that is turned on and off in response to a read control signal φTG. T.G. When the signal charge generated by the photodiode PD is at a high level, the signal charge is transferred to the floating diffusion layer FD.

[0136] When the signal charge photoelectrically converted by the photodiode PD overflows, the signal charge is transferred to the storage capacitor element C1 by adjusting the control voltage of the gain control element GC1, or when the signal charge exceeds a preset potential.

[0137] The reset transistor RS is a switch transistor that is turned on and off in response to a reset control signal φRS. When the reset control signal φRS is at a high level, the reset transistor RS sets the power supply voltage applied to the drain as a reset level to the floating diffusion layer FD0 via the gain control transistor GC1. In other words, when the reset control signal φRS is at a high level, the reset transistor RS resets the floating diffusion layer FD0 to the reset level.

[0138] The gain control transistor GC1 electrically disconnects or connects the floating diffusion layer FD0 and the floating diffusion layer FD1 in response to a gain control signal φGC1. This changes the conversion gain to convert the signal charge in the floating diffusion layer FD0 into a voltage. That is, when the signal charge is transferred from the photodiode PD to the floating diffusion layer FD0, turning off the gain control transistor GC1 increases the conversion gain of the floating diffusion layer FD0, which becomes C0. Conversely, turning on the gain control transistor GC1 connects the floating diffusion layers FD0 and FD1, which decreases the conversion gain, which becomes C0+C1.

[0139] The amplifying transistor SF configures a source follower together with a load current source 30 connected to the vertical signal line 19, and outputs the gate voltage, that is, the voltage of the floating diffusion layer FD0, to the vertical signal line 19 as an analog pixel signal.

[0140] The selection transistor SEL is a switch transistor that is turned on and off in response to a selection control signal φSEL. When the selection control signal φSEL is at a high level, the selection transistor SEL electrically connects the source of the amplification transistor SF to the vertical signal line 19.

[0141] [1A.3 Example of a pixel circuit and negative feedback circuit using stacked BSI] When pixel cells are miniaturized, or when the dynamic range is expanded, this can be achieved by providing a MIM capacitor or a MOS capacitor on the wiring layer side opposite the light receiving side of the photodiode PD to increase the aperture area of ​​the photodiode. It is also possible to provide a trench capacitor within the cell.

[0142] The solid-state imaging device 100 can also be configured as a stacked back-illuminated image sensor.

[0143] 6A is a diagram showing an example in which the solid-state imaging device according to embodiment 1A is configured as a stacked back-illuminated image sensor. The solid-state imaging device in the figure includes a first semiconductor chip and a second semiconductor chip that are bonded together. The first semiconductor chip and the second semiconductor chip are bonded together on their wiring layer sides. In the figure, PD denotes a photodiode PD, C denotes a first storage capacitance element C1, and amp denotes a feedback amplifier FA.

[0144] The first semiconductor chip is indicated as a top chip in the figure, and includes a main portion of the solid-state imaging device 100 as a back-illuminated CMOS image sensor. The first semiconductor chip includes the photodiode PD and the first storage capacitor element C1 of each pixel circuit 3.

[0145] The second semiconductor chip is indicated as a bottom chip in the figure, and includes main logic circuits such as signal processing units 70 and 80. The second semiconductor chip includes feedback amplifiers FA corresponding to each column of the pixel circuits 3.

[0146] In such a solid-state imaging device 100, each pixel is mounted on the top chip as a stacked BSI type CIS, and a feedback amplifier FA corresponding to each pixel column is mounted on the bottom chip. In other words, the top chip is equipped with a PD and a storage capacitance element C for each pixel, and the bottom chip can configure a feedback amplifier for each column, and negative feedback can be applied for each column, so that parasitic resistance and parasitic capacitance can be relatively reduced, and high-frequency noise can be reduced by increasing the speed, thereby reducing reset noise. Specifically, the top chip and the bottom chip may be provided with connection points A, B, and B' as shown in FIG. 5.

[0147] 6B is a diagram showing an example in which the solid-state imaging device in embodiment 1A is configured as a stacked back-illuminated image sensor. A stacked BSI type CIS is used, and each pixel of the pixel chip (top chip) is mounted, and a feedback amplifier corresponding to each pixel is mounted on the logic chip (bottom chip). A photodiode PD and a storage capacitance element C are mounted on each pixel on the top chip, and a feedback amplifier can be configured for each pixel on the bottom chip, and negative feedback can be applied to each pixel, so that parasitic resistance and parasitic capacitance can be reduced, and high-frequency noise can be reduced by increasing the speed, and reset noise can be significantly reduced.

[0148] 6C is a diagram showing an example in which the solid-state imaging device in embodiment 1A is configured as a stacked back-illuminated image sensor. A stacked BSI type CIS is used, and each pixel of the pixel chip (top chip) is mounted, and a feedback amplifier corresponding to each pixel is mounted on the logic chip (bottom chip). A photodiode PD is mounted on each pixel on the top chip, and a storage capacitance element C and a feedback amplifier can be configured on each pixel on the bottom chip, and negative feedback is applied to each pixel to increase speed, so high-frequency noise can be reduced and reset noise can be significantly reduced.

[0149] 6D is a diagram showing an example in which the solid-state imaging device in embodiment 1A is configured as a stacked back-illuminated image sensor. A stacked BSI type CIS is used, and each pixel of the pixel chip (top chip) is mounted, and a feedback amplifier corresponding to each pixel is mounted on the logic chip (bottom chip). A photodiode PD and a storage capacitance element C are mounted for each pixel on the top chip, and a storage capacitance element C can be configured for each pixel on the bottom chip, allowing the dynamic range to be significantly expanded.

[0150] [1A.4 Improving characteristics with poly plugs] Next, a description will be given of an example of a pixel configuration when the solid-state imaging device 100 is configured as a stacked back-illuminated image sensor as shown in FIGS. 6A to 6D.

[0151] Generally, if the wiring at one end of an MIM (Metal Insulator Metal) capacitor or MOS (Metal Oxide Semiconductor) capacitor is made into a normal contact with the substrate, damage will occur during the formation of the contact, and dark characteristics (dark current, noise, and fixed roughness) will become an issue.

[0152] On the other hand, if the wiring connecting one end of the MIM capacitor or MOS capacitor to the substrate is a poly plug using polysilicon wiring rather than metal wiring, damage to the connection is reduced and dark characteristics (dark current, noise, and fixed roughness) can be suppressed.

[0153] Furthermore, if the wiring that connects one end of the gate wiring of the amplification transistor SF to the substrate is a polyplug (polysilicon contact (n)) that uses polysilicon wiring instead of metal wiring, damage to the connection part is reduced and the dark characteristics (dark current, noise, and fixed roughness) can be suppressed.

[0154] In addition, the potential (A, B, C) of the plug part that accumulates the signal charge (negative charge) that constitutes the capacitance element increases the dark characteristics (dark current, noise, fixed roughness) when the potential relative to GND is high. Therefore, the dark characteristics can be improved by setting the potential (VC1) on the opposite side of the storage capacitance element C1 to an intermediate potential between GND and the pixel potential during exposure.

[0155] [1A.5 HCG read operation example] Next, the HCG (High Control Gain) readout operation in the solid-state imaging device 100 of Fig. 5 will be described. The HCG readout operation is an imaging operation in which the first transistor GC1 is turned off and the first storage capacitance element C1 is not used, and only the floating diffusion layer FD0 is used to store signal charges, thereby increasing the conversion gain of the amplifying transistor SF. Therefore, the HCG operation is a high-sensitivity imaging operation, and is suitable for imaging in low-illumination environments. In the CDS (Correlated Double Sampling) in the HCG readout operation, the reset level of the analog pixel signal is read out, and then the signal level is read out. In the CDS, the difference between the reset level and the signal level is calculated.

[0156] FIG. 7 is a time chart showing n exposure operations of the solid-state imaging device 100 in the HCG readout operation according to the embodiment 1A.

[0157] The down-count period is a period for AD-converting the level of the reset component of the analog pixel signal output from the amplification transistor SF. The counter unit 254 counts down the time from the start of the down-count period (the start of the change in the triangular wave) until the output of the voltage comparator 252 is inverted. This count value is the AD conversion result of the reset component Vrst of the analog pixel signal itself.

[0158] The up-count period is a period for AD conversion of the level of the data component of the analog pixel signal output from the amplification transistor SF. The counter unit counts up the time from the start of the up-count period (the start of the change in the triangular wave) to the inversion of the output of the voltage comparator 252. This up-counting converts the data component of the analog pixel signal into a digital value.

[0159] Since the initial value of this up-count is the down-count value indicating the reset component, the count value at the end of the up-count period represents the result of CDS (Correlated Double Sampling), which subtracts the reset component from the data component. In other words, the count value at the end of the up-count period is a digital value that represents the signal component. In this way, the column AD circuit 25 eliminates variations such as clock skew and counter delay of each column that cause errors, and extracts only the true signal component, that is, performs digital CDS.

[0160] [1A.6 LCG read operation example] Next, the LCG (Low Control Gain) read operation will be described in 100 of FIG. 5. The LCG read operation is an imaging operation in which the first transistor GC1 is turned on and the first storage capacitor element C1 is used, and the floating diffusion layer FD0 and the first storage capacitor element C1 are both used to store signal charges, thereby lowering the conversion gain of the amplifying transistor SF. Therefore, the LCG operation is a low-sensitivity imaging operation, and is suitable for imaging in a high-illumination environment. In the CDS (correlated double sampling) in the LCG read operation, the signal level is read, and then the reset level by the feedback amplifier FA is read. In other words, in the LCG read operation, the read order of the signal level and the reset level is reverse to that in the HCG read operation.

[0161] FIG. 8 shows the read order of one frame in the LCG read operation in the embodiment 1A.

[0162] The gain for converting the signal charge in the floating diffusion layer FD1 into a voltage can be selectively switched between a high gain and a low gain by turning on and off the gain control transistor GC1.

[0163] In the case of HCG readout operation, the normal CDS sequence for 1H is HCG (R: reset component) → HCG (S: signal component) as shown in Figure 7. This transition is the reading of signal charge from the photodiode PD to the floating diffusion layer FD0 when the conversion gain of the floating diffusion layer FD0 is high. This transition is normal CDS, so the reset noise can be canceled and reduced to zero.

[0164] 9 is a diagram showing the readout order of pixel signals for CDS in an LCG readout operation. In the case of LCG, it is LCG (S: signal component) → LCG (R: reset component). This transition is the readout of signal charges from the storage capacitor element C0 and the storage capacitor element C1 to the floating diffusion layer FD0 when the conversion gain of the floating diffusion layer FD1 is low.

[0165] This transition can remove DC offsets (reset coupling), but the pixel reset noise cannot be canceled and remains as kTC noise.

[0166] Here, the terms long exposure, middle exposure, and short exposure are defined. Originally, long exposure is for low illumination with a long exposure time, middle exposure is for medium illumination with a medium exposure time, and short exposure is for high illumination with a short exposure time. In this specification, when the same exposure time is used for all frames, the terms long, middle, and short do not mean differences in the length of exposure time, and are defined as long exposure for low illumination, middle exposure for medium illumination, and short exposure for high illumination.

[0167] This kTC noise in short exposure (high illumination) appears on the low illumination side. For example, it is shown in Figure 18B. Here, kTC noise is expressed in terms of charge amount as √(kTC). This noise must be set to be sufficiently smaller than the signal level. In this way, at the boundary between short exposure (high illumination) and long exposure (low illumination), the SN of the latter must be sufficiently better than the SN of the former.

[0168] [1A.7 Configuration and operation example of negative feedback circuit] At high illuminance, the storage capacitance element C is turned on, and the maximum subject illuminance can be increased while reducing reset noise by the negative feedback circuit 21. In general, when the control voltage of the reset transistor and the control voltage of the gain control element GC1 are abruptly turned off, reset noise (kTC noise) occurs in the storage capacitance element (C1) and capacitance C0.

[0169] The solution is to provide a switch element between the photodiode PD and the storage capacitance element (C1), and connect one end of this switch element to the negative input end of the feedback amplifier via the SF element and the vertical signal line, and the feedback line 20, which is the feedback output signal, is connected to the other end of the switch element to configure negative feedback. Here, the switch element is a reset transistor and a gain control element GC1. A DC voltage reference voltage VREF is connected to the positive input terminal of the feedback amplifier.

[0170] Furthermore, a control signal input to at least the first reset transistor RS among the first transistor GC1, the transfer transistor TG, and the first reset transistor RS has a sloping voltage waveform that gradually transitions the transistor from an on state to an off state. Hereinafter, a signal having a sloping voltage waveform is referred to as a slope signal.

[0171] FIG. 10A is a diagram showing the waveform of a slope signal. As shown in FIG. 10A, the control voltage of the reset transistor and the control voltage of the gain control element GC1 change gradually as a slope signal. FIG. 10B is a diagram showing the relationship between the slope period and the reset noise level. As shown in FIG. 10B, the reset noise gradually approaches the input voltage at one end of the feedback amplifier to the reference voltage VREF while negative feedback is applied. As the two potentials become closer, the rate of change of the voltage of the FD section becomes smaller. When the two potentials become equal, the potential of the FD section is fixed.

[0172] Finally, the feedback amplifier is disconnected from the negative feedback circuit 21, thereby completing the operation.

[0173] Finally, by subtracting the reset component from the signal component, the reset noise can be reduced and the signal can be extracted with good signal-to-noise ratio.

[0174] Here, it is preferable that the bandwidth of the feedback amplifier is wider than the bandwidth of the pixel section, in which case the high frequency components of the reset noise can be efficiently cancelled.

[0175] As described above, in this embodiment, it is possible to achieve both an expansion of the dynamic range and an improvement in the S / N ratio.

[0176] Figure 11 is a diagram showing the timing of charge accumulation in the photodiode PD and the storage capacitor element C1. The photodiode PD continues to be exposed for a 1V period (one vertical synchronization period) and the amount of charge is Q0. The storage capacitor element C1, which receives the charge overflowing from this photodiode PD, becomes the Q1 signal. Q0 and Q1 are exposed at exactly the same timing.

[0177] In the rolling shutter method, resetting is performed row by row by row scanning. After that, exposure starts, and the exposure time is expressed as T_Q0 = T_Q1. Next, charge is read out from the photodiode to the storage capacitor element C1 row by row. After that, the signal charge in the storage capacitor element C1 is read out using the rolling shutter method.

[0178] An example of the timing of the HCG read operation when the storage capacitance element C1 is not connected is the same as that in FIG.

[0179] FIG. 8 shows an example of the timing of an LCD read operation with the storage capacitor C1 connected.

[0180] First, from time t1 to t2, the photodiode PD, FD0, and FD1 are reset and exposure is awaited to start. Then, from time t3 to t4, the shutter operates and exposure starts. The exposure time ends at time t5. From time t5 to t6, the signal charge accumulated in the photodiodes is transferred to FD0 and FD1 by the transfer signal (TG). The signal components are read out between times t6 and t7. Next, a reset operation is performed between times t7 and t8. The reset components are read out between times t8 and t9.

[0181] Here, reset noise occurs during the shutter period from time t3 to t4, and during the reset period from time t7 to t8. Therefore, during this period, the negative feedback circuit 21 operates to gradually turn off the reset control signal RS, thereby reducing the reset noise. At this time, a slope-shaped signal is applied to the reset transistor (RS).

[0182] Conventionally, there is a photodiode PD and a storage capacitance element C, but the transfer Transistor TG Since there was no switch element, it was not possible to select between low and high illumination.

[0183] In this embodiment, during low illuminance, the signal charge accumulated in the photodiode is transferred by the transfer Tr, CDSed and read out, so reset noise can be completely eliminated. On the other hand, during high illuminance, the signal charge accumulated in the photodiode and the signal charge accumulated in the storage capacitance element are read out via the switch element, but the reset noise is reduced by the negative feedback circuit 21 during shutter and reset, so the SN can be significantly improved. In this way, it becomes possible to select and switch between low illuminance and high illuminance.

[0184] [1A.8 Example of a circuit for a slope signal that serves as a control signal for a switch element] This embodiment is composed of a photodiode PD, a transfer transistor (TG), and a negative feedback circuit 21. The negative feedback circuit 21 includes a reset transistor, a switch element, storage capacitance elements (C1, C2), and an amplifier. Transistor It is composed of SF and a feedback amplifier. The switch element is composed of gain control elements (GC1, GC2, GC) and a transfer element for accumulated charge (TGC). An overflow element (OF) is also added.

[0185] As described above, the control signals for these reset transistors and switch elements are turned off by applying a gently sloping signal during shuttering and readout, so that the negative feedback circuit 21 operates well and the reset noise is reduced. For example, FIG. 10A shows how this slope signal is turned off gently during the slope period. FIG. 10B shows the relationship between this slope period and the reset noise level. It can be seen that the noise level drops sharply at the beginning of the slope period, but after a while the noise level drops gently.

[0186] The issue here is the variation in the switching element due to the process, power supply voltage, and temperature. Process variations can be fixed to optimal values ​​during shipping inspection. On the other hand, variations in power supply voltage and temperature fluctuate during actual operation, so they must be corrected during operation.

[0187] 2 shows a circuit as a countermeasure. The slope signal generating unit 30 has a built-in DAC circuit, and first generates a slope signal using a clock CK1 and a control signal CN5 sent from the timing control unit 200. The slope signal is generated in the reset noise detection region (OB region in FIG. 3). A 14, or the pre-OB region in Fig. 4 A When the noise component of 15 is read out, a signal is read out every 1H by a control signal CN5, and the inclination of the slope is determined by a clock CK1.

[0188] Fig. 12A is a diagram showing a horizontal scanning row that is a unit for calculating the variation of reset noise. Fig. 12B is a diagram showing the variation (standard deviation) of reset noise in units of horizontal scanning rows. For the read signal in the reset noise detection region, the noise calculation circuit 86 in the signal processing unit 80 calculates the normal distribution of Fig. 12B for every 1H (i.e., one horizontal scan) shown in Fig. 12A, calculates the σ (standard deviation) of the noise signal, and the most optimal slope setting is held by the optimal value holding circuit 87.

[0189] Here, the optimum value is the minimum value of the signal read from the reset noise detection region, or the value when the difference between before and after the gradient of the sloping voltage changes is equal to or less than a desired value.

[0190] In addition, the inclination of the slope of the reset transistor, overflow element OF, gain control elements GC1 and GC2, and accumulated charge transfer element TGC that constitute the switch element may be determined by selecting the optimum value for each element every 1H, or by selecting all the optimum values ​​every 1H.

[0191] The signal processing unit 80 measures the reset level while changing the slope of the voltage waveform for each row of pixel circuits belonging to a reset noise detection area as a specified region, calculates the variation σ (standard deviation), and determines the optimal slope of the voltage waveform based on the variation for each row of pixel circuits belonging to the specified region.

[0192] [1A.9 Example of operation of slope signal as control signal for switch element] In this embodiment, the OB region in FIG. A 14, or generate a slope signal using the pre-OB region of FIG.

[0193] FIG. 13 is a flowchart showing an example of a process for generating a slope signal. <s1>Start scanning the first line of a frame with <s2>In the OB area A 14 or pre-OB region A Read out the signal of 15. Here, <s3>The slope signal is initialized to generate the mHth reset control signal. <s4>Then, the standard deviation σ of the sHth reset noise as shown in FIG. 12B is calculated. <s5>Then, following the algorithm to search for the optimal noise level σ, we perform row scanning and <s4> <s5>The above operation is repeated to select the slope signal that provides the optimum noise level σ. <s6>So, in Figure 3, the effective area A 16, or in Fig. 4 Puri OB area A The 15th signal is controlled by the selection signal. Here, the mHth and sHth values ​​are set by the algorithm.

[0194] FIG. 14 is a flowchart showing another example of a process for generating a slope signal. <s1>Start scanning the first line of a frame with <s2>In the OB area A 14 or pre-OB region A Read out the signal of 15. Here, <s3>The slope signal is initialized and the reset control signal for 1H is generated. <s4>Then, the standard deviation σ of the reset noise in the first H as shown in FIG. 12B is calculated. <s5>Now, this slope signal is adjusted to generate the reset control signal for the 2nd H. <s6>The slope signal is initialized to the initial value in and the reset control signal for 1H is generated. In this way, the standard deviation σ of the reset noise is calculated for each 1H. <s7>Now, this slope signal is adjusted to generate the nHth reset control signal. <s8>The slope signal is initialized to generate the nHth reset control signal. <s9>The slope at which the standard deviation σ of the reset noise becomes the optimum value is determined. <s10>So, in Figure 3, the effective area A 16, or in Fig. 4 Puri OB area A The 15 signals are controlled by the selection signal.

[0195] FIG. 15 is a flowchart showing yet another example of a process for generating a slope signal. <s1>Start scanning the first line of a frame with <s2>In the OB area A 14 or pre-OB region A Read out the signal of 15. Here, <s3>The slope signal is initialized and the reset control signal for 1H is generated. <s4>Then, the standard deviation σ of the reset noise in the first H as shown in FIG. 12B is calculated. <s5>Now, this slope signal is adjusted to generate the reset control signal for the 2nd H.

[0196] <s6>Calculate the noise level σ of the 2nd H, calculate the difference with the previous line, and compare it with the desired value. If the difference is less than the desired value, consider that value as the optimal value. <s10>In this case, the signal of the effective area in FIG. 3 or the signal of the OB area in FIG. 4 is controlled by the selection signal.

[0197] Conversely, when the difference is equal to or greater than the desired value, this operation is repeated up to nH.

[0198] <s7>Now, this slope signal is adjusted to generate the nHth reset control signal.

[0199] <s8>Calculate the noise level σ of the nHth row, calculate the difference with the previous row, and compare it with the desired value. If the difference is less than the desired value, consider that value as the optimal value. <s10>In this case, the signal of the effective area in FIG. 3 or the signal of the OB area in FIG. 4 is controlled by the selection signal.

[0200] Conversely, when the difference is greater than or equal to the desired value, <s9>select the slope signal whose noise level σ is closest to the desired value. <s10>So, in Figure 3, the effective area A 16, or in Fig. 4 Puri OB area A15 Belief No. It is controlled by the selection signal.

[0201] In Figure 3, the OB region A 14 is the reset noise detection area. The advantage is that it can suppress the expansion of the chip area. However, the OB area A A gain of 14 is in the effective range. A Since the gain is set to the same value as that of 16, there is an issue that the precision of detection is poor when the gain is low. Also, there is a possibility that large reset noise may be superimposed on the OB region.

[0202] In Figure 4, the pre-OB region A The reset noise detection range is 15. The advantage is that the reset noise can be detected with the measurement gain always kept constant, so if the gain is increased for detection, the accuracy increases and stable detection becomes possible.

[0203] [1A.10 Expanding the dynamic range] The feature of this embodiment is that WDR synthesis is not performed, and a low illuminance area or a high illuminance area is selected according to the illuminance situation to expand the dynamic range.

[0204] For example, a low-illuminance frame may be used at night and a high-illuminance frame may be used during the day, or a low-illuminance frame or a high-illuminance frame may be selected depending on the illuminance at the moment when driving.

[0205] At this time, the two frames, Long and Short, are exposed at exactly the same time and use exactly the same pixels, so false colors, coloring, and blurring do not occur.

[0206] Fig. 16 is a diagram showing an outline of a method for implementing WDR within a pixel. Fig. 29 is a diagram showing a configuration example of a signal processing unit 70 that performs WDR synthesis using two frames. However, since synthesis is not performed in this embodiment, it is not necessary to install a WDR synthesis circuit 76. WDR is performed by using a signal charge of Q0 for long exposure (low illuminance) and a signal charge of (Q0+Q1) for short exposure (high illuminance).

[0207] The horizontal axis of [1][2][3][4] in Figure 16 indicates the product of illuminance and exposure time, illuminance for a certain period of time, or exposure time at a certain illuminance. The vertical axis indicates [1] the charge accumulation level, [2] the FD potential, [3] the value after AD conversion, and [4] the SN.

[0208] 17 is a diagram showing the FD potential in an HCG read operation for a low illuminance frame and an LCG read operation for a high illuminance frame. Hereinafter, the HCG read operation may be referred to as Read1, and the LCG read operation may be referred to as Read2.

[0209] 18A to 18D are diagrams showing the relationship between the illuminance of the subject and the gain (S / N ratio) according to the embodiment 1A. Fig. 18A is a diagram showing the relationship between the illuminance of the subject and the gain (S / N ratio) in LCG readout in a case where the negative feedback circuit 21 is not provided as a comparative example. Fig. 18B is a diagram showing the relationship between the illuminance of the subject and the gain (S / N ratio) according to the embodiment 1A. HCG FIG. 11 is a diagram showing the relationship between subject illuminance and gain (SN ratio) during readout.

[0210] FIG. 18C shows a comparative example in which the negative feedback circuit 21 is not provided. LCG 18D is a diagram showing the relationship between the illuminance of a subject and gain (S / N ratio) during readout.Figure 18D is a diagram showing the relationship between the illuminance of a subject and gain (S / N ratio) during HCG readout according to embodiment 1A.

[0211] 18B and 18D are Long frames of Read1 (i.e., HCG readout for a low-illumination frame), and are equivalent since no reset noise occurs.

[0212] Figures 18A and 18C show the short frame of Read2 (i.e., LCG readout for a high-illumination frame), and although reset noise occurs as shown in Figure 18A, it can be seen that the SN on the low-illumination side is improved by reducing the reset noise as shown in Figure 18C. The dynamic range is expanded from very dim illuminance (0.1 Lux) to very bright illuminance (100,000 Lux: equivalent to sunlight) depending on the storage capacity, and it can be seen that the dynamic range is 120 dB or more, and the SN at the frame joints is 20 dB or more.

[0213] Without WDR synthesis, the dynamic range can be expanded by selecting low-light or high-light areas depending on the lighting conditions, and it is also possible to improve noise in low light and expand the dynamic range in high light.

[0214] In this way, according to this embodiment, it is possible to improve both the dynamic range and the SNR while reducing the reset noise of the storage capacitance element.

[0215] (Embodiment 1B) Although the embodiment 1A describes a rolling shutter type readout, the embodiment 1B also supports a global shutter type readout.

[0216] Compared to the rolling shutter, the global shutter method can suppress distortion when capturing an image of an object moving at high speed.

[0217] The solid-state imaging device 100 in the embodiment 1B may be the same as that in the embodiment 1A, but differs mainly in that the driving of the vertical scanning circuit 14 also corresponds to a global shutter. The following description will focus on the differences.

[0218] [1B.1 Configuration and operation example of negative feedback circuit] Figure 19 is a diagram showing the timing of charge accumulation in the photodiode PD and the storage capacitor element C1. The photodiode PD continues to be exposed for a 1V period (one vertical synchronization period) and the amount of charge is Q0. The storage capacitor element C1, which receives the charge overflowing from this photodiode PD, becomes the Q1 signal. Q0 and Q1 are exposed at exactly the same timing.

[0219] In the global shutter method, a global reset is performed on all pixels at once. After that, exposure starts, and the exposure time is expressed as T_Q0+Q1. Next, the charge from the photodiode is read out to the storage capacitor element C1 at once. After that, the signal charge in the storage capacitor element C1 is read out using the rolling shutter method.

[0220] An example of read timing when the storage capacitance element C1 is connected (that is, LCG read operation) is shown in FIG. 20A.

[0221] The timing will be explained with reference to FIG. 20A.

[0222] First, from time t1 to t2, the photodiode PD, FD0, and FD1 are reset and exposure is awaited to start. Then, from time t2 to t3, the global shutter is operated and exposure is started. The exposure time ends at time t4. From time t4 to t5, the signal charge accumulated in the photodiode is transferred to FD0 and FD1 by the transfer signal (TG). At time t5, the gain control transistor GC1 is turned on, allowing the conversion gain to be set low so that more signal charge can be received. From time t5 to t6, the time to wait for the reading of the relevant row in the rolling shutter method is reached. Then, when the relevant row is reached, the signal component is read out between times t6 and t7. Next, a reset operation is performed between times t7 and t8. The reset component is read out between times t8 and t9.

[0223] Here, reset noise occurs during the global shutter period at times t2 and t3, and during the reset period at times t7 and t8. Therefore, during these periods, the negative feedback circuit 21 operates to gradually turn off the reset control signal RS, thereby reducing the reset noise. At this time, a slope-shaped signal is applied to the reset transistor (RS).

[0224] Fig. 20B is a diagram showing the read order of the reset component and the signal component in the LCG read operation of Fig. 20A. As shown in the figure, in the LCG read operation, the signal component and the reset component are read out in that order.

[0225] (Embodiment 2A) In the embodiment 2A, a detailed description will be given of a configuration example in which one stage of storage circuits is provided in the horizontal direction in the second configuration example of Fig. 1B. The following description will focus on the differences from the embodiment 1A.

[0226] [2A.1 Example of pixel circuit configuration] Next, a configuration example of the pixel circuit 3 will be described.

[0227] 21 is a diagram showing an example of a main circuit including a pixel circuit 3 according to embodiment 2A and a negative feedback circuit 21. The pixel circuit 3 in the diagram includes a photodiode PD, a transfer transistor TG, a storage capacitance element C2, a storage transfer transistor TGC, a floating diffusion layer FD0, a parasitic capacitance C0, a floating diffusion layer FD2, a reset transistor RS, an amplification transistor SF, and a selection transistor SEL.

[0228] The horizontal scanning line group 15 includes a reset control line φRS, a readout control line φTG, a storage transfer transistor control line φTGC, and a selection control line φSEL.

[0229] The photodiode PD is a photoelectric conversion element such as a photodiode, and performs photoelectric conversion with a predetermined sensitivity, that is, generates an electric charge according to the amount of received light.

[0230] Furthermore, the capacitance C0 connected to the floating diffusion layer FD0 holds the signal charge (e.g., electrons) transferred from the photodiode PD, converts the held signal charge into a voltage, and supplies the converted voltage to the gate of the amplification transistor SF. The substantial capacitance of the floating diffusion layer FD0 includes not only the capacitance of the floating diffusion layer FD0 itself, but also the gate capacitance of the amplification transistor SF and the floating capacitance of the gate-drain capacitance of the amplification transistor SF.

[0231] The transfer transistor TG is a switch transistor that is turned on and off in response to a read control signal φTG. T.G. When the signal charge generated by the photodiode PD is at a high level, the signal charge is transferred to the floating diffusion layer FD.

[0232] The accumulation transfer transistor TGC is a switch transistor that is turned on and off in response to a read control signal φTGC. When the read control signal φTGC is at a high level, the accumulation transfer transistor TGC transfers the signal charge accumulated in the accumulation capacitance element C4 to the floating diffusion layer FD0.

[0233] When the signal charge photoelectrically converted by the photodiode PD overflows, the charge is transferred to the storage capacitor element C4 by adjusting the control voltage φTGC of the storage transfer transistor TGC, or when the charge exceeds a preset potential.

[0234] Also, the storage capacitance element C0 changes the conversion gain to convert the signal charge in the floating diffusion layer FD0 into a voltage. That is, when the signal charge is transferred from the photodiode PD to the floating diffusion layer FD0, if the storage transfer transistor TGC is turned off, the conversion gain of the floating diffusion layer FD0 can be made higher, and becomes C0. Conversely, if the storage transfer transistor TGC is turned on, the conversion gain of the floating diffusion layer FD0 and FD2 is connected, the conversion gain can be lowered so that more signal charge can be accumulated, resulting in C0+C4.

[0235] The reset transistor RS is a switch transistor that is turned on and off in response to a reset control signal φRS. When the reset control signal φRS is at a high level, the reset transistor RS sets the floating diffusion layer FD0 to the reset level, with the power supply voltage applied to the drain being the reset level. In other words, when the reset control signal φRS is at a high level, the reset transistor RS resets the floating diffusion layer FD0 to the reset level.

[0236] The amplifying transistor SF configures a source follower together with a load current source 30 connected to the vertical signal line 19, and outputs the gate voltage, that is, the voltage of the floating diffusion layer FD0, to the vertical signal line 19 as an analog pixel signal.

[0237] The selection transistor SEL is a switch transistor that is turned on and off in response to a selection control signal φSEL. When the selection control signal φSEL is at a high level, the selection transistor SEL electrically connects the source of the amplification transistor SF to the vertical signal line 19.

[0238] [2A.2 Configuration and operation example of negative feedback circuit] The timing of charge accumulation in the photodiode PD and the storage capacitor element C2 shown in FIG. 11 is the same as in the embodiment 1A.

[0239] An example of the timing of the HCG read operation when the storage capacitor element C4 according to the embodiment 2A is not connected is the same as that shown in FIG.

[0240] FIG. 22 shows an example of the timing of an LCG read operation when the storage capacitor element C4 is connected.

[0241] First, from time t1 to t2, the photodiode PD, FD0, and FD1 are reset and exposure is awaited to start. Then, from time t3 to t4, the shutter operates and exposure starts. The exposure time ends at time t5. At time t5, the accumulation transfer transistor TGC is turned ON, allowing the conversion gain to be set low so that more signal charge can be received. From time t5 to t6, the signal charge accumulated in the photodiodes is transferred to FD0 and FD1 by the transfer signal TG. The signal components are read out between times t6 and t7. Next, a reset operation is performed between times t7 and t8. The reset components are read out between times t8 and t9.

[0242] Here, reset noise occurs during the shutter period at times t3 and t4 and during the reset period at times t7 and t8. Therefore, during these periods, the negative feedback circuit 21 operates to gradually turn off the reset control signal RS and the accumulated charge transfer element TGC, thereby reducing the reset noise. The solid line shows how a slope-shaped signal is applied to the reset transistor (RS) and the accumulated charge transfer element (TGC) at this time. Alternatively, as another method, the negative feedback circuit 21 operates during the shutter period at times t3 and t4 to gradually turn off the reset control signal RS and steeply turn off the accumulated charge transfer element TGC, which is shown by the broken line. At this time, due to the law of charge accumulation, the reset noise of the storage capacitance element C4 is not reduced, but reset noise of the opposite positive and negative directions is generated in FD0. Since the FD section is not reset until the signal readout (LCG), the reset noise of the storage capacitance element C4 and the FD section can be canceled and reduced to zero at this time.

[0243] (Embodiment 2B) Although the embodiment 2A describes a rolling shutter type readout, the embodiment 2B also supports a global shutter type readout.

[0244] Compared to the rolling shutter, the global shutter method can suppress distortion when capturing an image of an object moving at high speed.

[0245] The solid-state imaging device 100 in the embodiment 2B may be the same as that in the embodiment 2A, but differs mainly in that the driving of the vertical scanning circuit 14 also corresponds to a global shutter. The following mainly describes the differences.

[0246] [2B.1 Configuration and operation example of negative feedback circuit] The timing of charge accumulation in the photodiode PD and the storage capacitor element C1 shown in FIG. 19 is the same as in the embodiment 1B.

[0247] FIG. 23 shows an example of read timing when the storage capacitance element C4 according to the embodiment 2B is connected.

[0248] The timing will be described with reference to FIG.

[0249] First, from time t1 to t2, the photodiode PD, FD0, and FD1 are reset and exposure is started. Then, from time t2 to t3, the global shutter is operated and exposure starts. The exposure time ends at time t4. From time t4 to t5, the signal charge accumulated in the photodiode is transferred to FD0 and FD2 by the transfer signal TG. At time t4, the accumulation transfer transistor TGC is turned on, so that the conversion gain can be set low so that more signal charge can be received. From time t5 to t6, the time to wait for the reading of the relevant row in the rolling shutter method. Then, when the relevant row is reached, the signal component is read out between times t6 and t7. Next, a reset operation is performed between times t7 and t8. The reset component is read out between times t8 and t9.

[0250] Here, reset noise occurs during the global shutter period at times t2 and t3, and during the reset period at times t7 and t8. For this reason, the negative feedback circuit 21 operates during these periods, and the reset control signal RS and the accumulated charge transfer element TGC are gradually turned off, thereby reducing the reset noise. The solid line shows how a slope-shaped signal is applied to the reset transistor (RS) and the accumulated charge transfer element (TGC) at this time. Alternatively, as another method, the negative feedback circuit 21 operates during the shutter period at times t2 and t3, the reset control signal RS is gradually turned off, and the accumulated charge transfer element TGC is steeply turned off, as shown by the broken line. At this time, due to the charge accumulation law, the reset noise of the storage capacitance element C4 is not reduced, but reset noise of the opposite positive and negative directions is generated in FD0. Since the FD section is not reset until the signal readout (LCG), the reset noise of the storage capacitance element C4 and the FD section is canceled and can be reduced to zero at this time.

[0251] (Embodiment 3A) In the embodiment 3A, a detailed description will be given of a configuration example in which one stage of storage circuits is provided in the horizontal direction in the third configuration example in Fig. 1C. The following description will focus on the differences from the embodiment 1A.

[0252] A solid-state imaging device 100 in embodiment 3A will be described in terms of differences from embodiment 1. The configuration example of solid-state imaging device 100 is the same except for the number of horizontal scanning line groups 15 that are controlled.

[0253] In this embodiment, the charge overflowing from the photodiode PD is stored directly in the storage capacitor C4 without passing through the FD portion or near the surface, so that the dark current component can be reduced.

[0254] [3A.1 Example of pixel circuit configuration] Next, a configuration example of the pixel circuit 3 will be described.

[0255] 24 is a diagram showing an example of a main circuit including a pixel circuit 3 according to embodiment 3A and a negative feedback circuit 21. The pixel circuit 3 in the diagram includes a photodiode (PD), a transfer transistor TG, an overflow gate OF1, a storage capacitance element C4, a storage transfer transistor TGC, a floating diffusion layer FD0, a parasitic capacitance C0, a floating diffusion layer FD2, a reset transistor RS, an amplification transistor SF, and a selection transistor SEL.

[0256] The horizontal scanning line group 15 also includes a reset control line φRS, a read control line φTG, an overflow control line φOF1, and a selection control line φSEL.

[0257] The photodiode PD is a photoelectric conversion element such as a photodiode, and performs photoelectric conversion with a predetermined sensitivity, that is, generates an electric charge according to the amount of received light.

[0258] Furthermore, the capacitance C0 connected to the floating diffusion layer FD0 holds the signal charge (e.g., electrons) transferred from the photodiode PD, converts the held signal charge into a voltage, and supplies the converted voltage to the gate of the amplifying transistor SF. The substantial capacitance of the floating diffusion layer FD0 includes not only the capacitance of the floating diffusion layer FD0 itself, but also the gate capacitance of the amplifying transistor SF, the gate-drain capacitance of the amplifying transistor SF, and the floating capacitance of the source wiring of the gain control transistor GC1 when the gain control transistor GC1 is off.

[0259] The transfer transistor TG is a switch transistor that is turned on and off in response to a read control signal φTG. T.G. When the signal charge generated by the photodiode PD is at a high level, the signal charge is transferred to the floating diffusion layer FD.

[0260] The accumulation transfer transistor TGC is a switch transistor that is turned on and off in response to a read control signal φTGC. When the read control signal φTGC is at a high level, the transfer transistor TGC transfers the signal charge accumulated in the accumulation capacitance element C4 to the floating diffusion layer FD.

[0261] The overflow gate OF1 is an overflow gate and a switch transistor that is turned on and off in response to a read control signal φOF. When the read control signal φOF is at a high level, the overflow gate OF1 transfers the signal charge photoelectrically converted by the photodiode PD to the storage capacitance element C4 via the overflow gate OF1.

[0262] When the signal charge photoelectrically converted by the photodiode PD overflows, the charge is transferred to the storage capacitor element C4 by adjusting the control voltage φTGC of the storage transfer transistor TGC, or when the charge exceeds a preset potential.

[0263] Also, the storage capacitance element C4 changes the conversion gain to convert the signal charge in the floating diffusion layer FD0 into a voltage. That is, when the signal charge is transferred from the photodiode PD to the floating diffusion layer FD0, if the storage transfer transistor TGC is turned off, the conversion gain of the floating diffusion layer FD0 can be made higher, and becomes C0. Conversely, if the storage transfer transistor TGC is turned on, the floating diffusion layers FD0 and FD1 are connected, and the conversion gain can be lowered to allow more signal charge to be stored, and becomes C0+C4.

[0264] The reset transistor RS is a switch transistor that is turned on and off in response to a reset control signal φRS. When the reset control signal φRS is at a high level, the reset transistor RS sets the floating diffusion layer FD0 to the reset level, with the power supply voltage applied to the drain being the reset level. In other words, when the reset control signal φRS is at a high level, the reset transistor RS resets the floating diffusion layer FD0 to the reset level.

[0265] The amplifying transistor SF configures a source follower together with a load current source 30 connected to the vertical signal line 19, and outputs the gate voltage, that is, the voltage of the floating diffusion layer FD0, to the vertical signal line 19 as an analog pixel signal.

[0266] The selection transistor SEL is a switch transistor that is turned on and off in response to a selection control signal φSEL. When the selection control signal φSEL is at a high level, the selection transistor SEL electrically connects the source of the amplification transistor SF to the vertical signal line 19.

[0267] [3A.2 Configuration and operation example of negative feedback circuit] The timing of charge accumulation in the photodiode PD and the storage capacitor element C1 shown in FIG. 11 is the same as in the embodiment 1A.

[0268] An example of the timing of the HCG read operation when the storage capacitor element C4 is not connected is the same as that in FIG.

[0269] FIG. 25 shows an example of the timing of an LCG read operation when the storage capacitor element C4 is connected.

[0270] First, from time t1 to t2, the photodiode PD, FD0, and FD2 are reset and exposure is awaited to start. Then, from time t3 to t4, the shutter operates and exposure starts. The exposure time ends at time t5. At time t5, the accumulation transfer transistor TGC is turned ON, allowing the conversion gain to be set low so that more signal charge can be received. From time t5 to t6, the signal charge accumulated in the photodiodes is transferred to FD0 and FD1 by the transfer signal TG. The signal components are read out between times t6 and t7. Next, a reset operation is performed between times t7 and t8. The reset components are read out between times t8 and t9.

[0271] Here, reset noise occurs during the shutter period at times t3 and t4 and during the reset period at times t7 and t8. Therefore, during these periods, the negative feedback circuit 21 operates to gradually turn off the reset control signal RS and the accumulated charge transfer element TGC, thereby reducing the reset noise. The solid line shows how a slope-shaped signal is applied to the reset transistor (RS) and the accumulated charge transfer element (TGC) at this time. Alternatively, as another method, the negative feedback circuit 21 operates during the shutter period at times t3 and t4 to gradually turn off the reset control signal RS and steeply turn off the accumulated charge transfer element TGC, which is shown by the broken line. At this time, due to the law of charge accumulation, the reset noise of the storage capacitance element C4 is not reduced, but reset noise of the opposite positive and negative directions is generated in FD0. Since the FD section is not reset until the signal readout (LCG), the reset noise of the storage capacitance element C4 and the FD section can be canceled and reduced to zero at this time.

[0272] (Embodiment 3B) The solid-state imaging device 100 in the embodiment 1B may be the same as that in the embodiment 1A, but differs mainly in that the driving of the vertical scanning circuit 14 also corresponds to a global shutter. The following description will focus on the differences.

[0273] [3B.1 Configuration and operation example of negative feedback circuit] The timing of charge accumulation in the photodiode PD and the storage capacitor element C1 shown in Fig. 19 is the same as in embodiment 1B. However, the photodiode PD continues to be exposed for a 1V period (one vertical synchronization period) and the amount of charge is Q0. The storage capacitor element C receives the charge overflowing from this photodiode PD via the overflow gate OF1 and becomes the Q1 signal. Q0 and Q1 are exposed at exactly the same timing.

[0274] In the global shutter method, a global reset is performed on all pixels at once. After that, exposure starts, and the exposure time is expressed as T_Q0+Q1. Next, the charge from the photodiode is transferred to the storage capacitor element C4 at once by adjusting the control voltage of the overflow gate OF1. After that, in the rolling shutter method, the signal charge in the storage capacitor element C2 is read out by turning on the storage transfer transistor TGC.

[0275] FIG. 26 shows an example of the timing of an LCG read operation when the storage capacitor element C4 according to the embodiment 3B is connected.

[0276] The timing will be described with reference to FIG.

[0277] First, from time t1 to t2, the photodiode PD, FD0, and FD1 are reset and exposure is started. Then, from time t2 to t3, the global shutter operation is performed and exposure is started. Then, from time t3 to t4, the overflow gate is turned ON so that all the photoelectrically converted charges are stored in the storage capacitance element C4. At time t4, the exposure time ends, so the overflow gate is turned OFF. At time t6, the storage transfer transistor TGC is turned ON, so that the conversion gain can be set low so that more signal charges can be received. From time t5 to t6, the time to wait for reading up to the relevant row in the rolling shutter method. Then, when the relevant row is reached, the signal component is read out between times t6 and t7. Next, a reset operation is performed between times t7 and t8. The reset component is read out between times t8 and t9.

[0278] Here, reset noise occurs during the global shutter period at times t2 and t3, and during the reset period at times t7 and t8. For this reason, the negative feedback circuit 21 operates during these periods, and the reset control signal RS and the accumulated charge transfer element TGC are gradually turned off, thereby reducing the reset noise. The solid line shows how a slope-shaped signal is applied to the reset transistor (RS) and the accumulated charge transfer element (TGC) at this time. Alternatively, as another method, the negative feedback circuit 21 operates during the shutter period at times t2 and t3, the reset control signal RS is gradually turned off, and the accumulated charge transfer element TGC is steeply turned off, as shown by the broken line. At this time, due to the charge accumulation law, the reset noise of the storage capacitance element C4 is not reduced, but reset noise of the opposite positive and negative directions is generated in FD0. Since the FD section is not reset until the signal readout (LCG), the reset noise of the storage capacitance element C4 and the FD section is canceled and can be reduced to zero at this time.

[0279] (Embodiment 4) A solid-state imaging device 100 according to the fourth embodiment will be described from the viewpoint of differences from the embodiment 1A. The configuration example of the solid-state imaging device 100 is the same except for the number of horizontal scanning line groups 15 that are controlled.

[0280] While the embodiment 1A has a means for selecting a signal in the high illuminance region and a signal in the low illuminance region, the embodiment 4 reads out two types of pixel signals, a pixel signal for a high illuminance frame configuration and a pixel signal for a low illuminance frame configuration, during one frame period and synthesizes them, thereby expanding the dynamic range.

[0281] [4.1 Example of pixel circuit configuration] Next, a configuration example of the pixel circuit 3 will be described.

[0282] Fig. 27 is a diagram showing an example of a circuit including a pixel circuit 3 and a negative feedback circuit 21 according to embodiment 4. This figure is equivalent to Fig. 24 of embodiment 3A, and is also equivalent to the example of the configuration in which one stage of a storage circuit is provided in the horizontal direction in the third example of configuration in Fig. 1C. The following mainly describes the differences.

[0283] [4.2 Example of read operation in this embodiment] FIG. 28A is a time chart showing the read order of one frame in the fourth embodiment.

[0284] The gain for converting the signal charge in the floating diffusion layer FD1 into a voltage can be selectively switched between a high gain and a low gain by turning on and off the gain control transistor GC1.

[0285] The normal CDS sequence for 1H is HCG (R: reset component) → HCG (S: signal component) in the case of HCG. This transition is the readout of signal charge from the photodiode PD to the floating diffusion layer FD0 when the conversion gain of the floating diffusion layer FD0 is high.

[0286] Since this transition is a normal CDS, the reset noise can be canceled and made zero.

[0287] Fig. 28B is a diagram showing the readout order of the reset component and the signal component in the HCG readout and the LCG readout of Fig. 28A. The figure shows the CDS order of 1H, and in the case of LCG, it is LCG (S: signal component) → LCG (R: reset component). This transition is the readout of the signal charge from the storage capacitance element C0 and the storage capacitance element C1 to the floating diffusion layer FD0 when the conversion gain of the floating diffusion layer FD1 is low.

[0288] In this transition, in the LCG, the DC offset (reset coupling) can be removed, but the pixel reset noise cannot be canceled and remains as kTC noise.

[0289] This kTC noise in short exposure (high illuminance) appears on the low illuminance side. For example, it is shown in Figure 30C. Here, kTC noise is expressed in terms of charge amount as √(kTC). This noise must be set so that it is sufficiently smaller than the signal level. In this way, at the boundary between short exposure (high illuminance) and long exposure with low illuminance, the SN of the latter must be sufficiently better than the SN of the former.

[0290] [4.3 Configuration and operation example of negative feedback circuit] The timing of charge accumulation in the photodiode PD and the storage capacitor element C1 shown in FIG. 11 is the same as in the embodiment 1A.

[0291] The timing will be explained with reference to FIG. 28A.

[0292] First, from time t1 to t2, the photodiodes PD, FD0, and FD1 are reset and exposure is started. Then, from time t3 to t4, the shutter is operated and exposure starts. The exposure time ends at time t5.

[0293] In the HCG, a reset operation is performed between times t5 and t6. The reset component is read out between times t8 and t9. Next, the signal charge accumulated in the photodiode is transferred to FD0 by the transfer signal TG between times t7 and t8. The signal component is read out between times t8 and t9.

[0294] In the LCG, the signal charge accumulated in the photodiode is transferred to FD0 by the transfer signal TG from time t9 to t10. The signal component is read out from time t10 to t11. Next, a reset operation is performed from time t11 to t12. The reset component is read out from time t12 to t13.

[0295] Here, reset noise occurs during the shutter period from time t3 to t4, and during the reset period from time t11 to t12. Therefore, during this period, the negative feedback circuit 21 operates to gradually turn off the reset control signal RS, thereby reducing the reset noise. At this time, a slope-shaped signal is applied to the reset transistor (RS).

[0296] [4.4 Expanding the dynamic range] The feature of this embodiment is that the two frames, Long and Short, used to synthesize the WDR, are exposed at exactly the same timing and use exactly the same pixels, so false colors, coloring, and blurring do not occur.

[0297] Figure 16 shows an overview of the WDR in-pixel synthesis method. Figure 29 shows an example of the configuration of a signal processing unit that performs WDR synthesis using two frames. For WDR, Long exposure (low illuminance) is treated as a signal charge of Q0, and Short exposure (high illuminance) is treated as a signal charge of (Q0+Q1).

[0298] The horizontal axis of [1][2][3][4] in Figure 16 indicates the product of illuminance and exposure time, illuminance for a certain period of time, or exposure time at a certain illuminance. The vertical axis indicates [1] the charge accumulation level, [2] the FD potential, [3] the value after AD conversion, and [4] the SN.

[0299] FIG. 17 is a diagram showing the signal charge amount and the FD potential in the first Read1 for reading out a low-illumination frame and the second Read2 for reading out a high-illumination frame.

[0300] 30A to 30D are diagrams showing the relationship between the object illuminance and the gain (SN ratio) according to the fourth embodiment.

[0301] 30A and 30B are diagrams showing, as a comparative example, the relationship between the subject illuminance and the gain (SNR) in LCG readout in the absence of the negative feedback circuit 21. In Fig. 30A, the analog gain is 0 dB, and in Fig. 30B, the analog gain is 12 dB.

[0302] Figures 30C and 30D are diagrams showing the relationship between the subject illuminance and gain (SN ratio) in LCG readout according to embodiment 4. In Figure 30C, the analog gain is 0 dB, and in Figure 30D, the analog gain is 18 dB.

[0303] Figure 30A shows the first Read1 synthesized as a WDR Long frame (low illuminance frame) and the second Read2 synthesized as a WDR Short frame (high illuminance frame). The signal-to-noise ratio at the frame joint is 20 dB or more, and the dynamic range is 120 dB or more. The dynamic range is expanded from very dim illuminance (0.1 Lux) to very bright illuminance (100,000 Lux: equivalent to sunlight) depending on the storage capacity.

[0304] The details of the WDR synthesis circuit 76 constituting the signal processing unit 70 are shown in Fig. 29. The pixel signal of the first low-illuminance frame (long exposure) and the pixel signal of the second high-illuminance frame (short exposure) are synthesized. This synthesis realizes a wide dynamic range function (WDR function), that is, the dynamic range is expanded.

[0305] The pixel gain is set high for pixel signals of frames in low-illumination areas (long exposure), and the pixel gain is set low for pixel signals of frames in high-illumination areas (short exposure), thereby improving noise in low illumination and expanding the dynamic range in high illumination.

[0306] In this way, according to this embodiment, it is possible to improve both the dynamic range and the SNR while reducing the reset noise of the storage capacitance element.

[0307] The correspondence between SN and signal output level is shown in Figures 30A and 31A, Figures 30B and 31B, Figures 30C and 31C, and Figures 30D and 31D.

[0308] 31A and 31B are diagrams showing, as a comparative example, the relationship between the subject illuminance and the signal output level (LSB) in LCG readout when there is no negative feedback circuit 21. In Fig. 31A, the analog gain is 0 dB, and in Fig. 31B, the analog gain is 12 dB.

[0309] Figures 31C and 31D are diagrams showing the relationship between the subject illuminance and the signal output level (LSB) in LCG readout according to embodiment 4. In Figure 31C, the analog gain is 0 dB, and in Figure 31D, the analog gain is 18 dB.

[0310] In this example, the column ADC is 12-bit, and the signal output level is restricted to 4095 LSB (MSB). First, a low-illumination frame is used for the signal in the low-illumination area, and it increases in proportion to the illuminance and is restricted to 4095 LSB (MSB). Next, a high-illumination frame is used for the signal in the high-illumination area, and it increases in proportion to the illuminance and is restricted to 4095 LSB (MSB), and this value determines the maximum subject illuminance.

[0311] Here, the dynamic range is expressed by the maximum subject illuminance minus the minimum subject illuminance, and the minimum subject illuminance is often defined as SN=1 dB.

[0312] In other words, the range in which low-illumination frames are used is when the signal level is below the MSB when the analog gain is increased, and the range in which high-illumination frames are used is when the signal level is below the MSB when the analog gain is increased.

[0313] For this reason, when the gain is increased, the signal level rises, and the maximum subject illuminance corresponding to this MSB falls on the low-illuminance side. The issue at this time is the deterioration of the signal-to-noise ratio at the boundary between the low-illuminance frame and the high-illuminance frame, which is caused by reset noise in the high-illuminance frame.

[0314] In this embodiment, this reset noise is reduced by the negative feedback circuit 21, so it can be used with a higher gain than in the prior art. For example, when no countermeasure is taken, the analog gain can only be increased to 12 dB as shown in FIG. 30B. However, when countermeasures are taken to reduce the reset noise, the analog gain can be used up to 18 dB as shown in FIG. 30D. The allowable value for use is SN20 dB or more.

[0315] (Embodiment 5) A solid-state imaging device 100 according to the fifth embodiment will be described from the viewpoint of differences from the embodiment 1C. The configuration example of the solid-state imaging device 100 is the same except for the number of horizontal scanning line groups 15 that are controlled.

[0316] In the second and third embodiments, a means is provided for selecting a signal from a high-illuminance region and a signal from a low-illuminance region, whereas the fifth embodiment is provided for combining two frames of a signal from a high-illuminance region and a signal from a low-illuminance region, thereby expanding the dynamic range.

[0317] [5.1 Example of pixel circuit configuration] Next, a configuration example of the pixel circuit 3 will be described.

[0318] Fig. 32 is a diagram showing an example of a circuit including a pixel circuit 3 and a negative feedback circuit 21 according to embodiment 5. This figure is equivalent to Fig. 5 of embodiment 1A, and is also equivalent to the example of a configuration in which one storage circuit is provided in the vertical direction in the first example of configuration in Fig. 1A. The following mainly describes the differences.

[0319] [5.2 Example of read operation in this embodiment] FIG. 33A is a time chart showing the read order of one frame in the fifth embodiment.

[0320] The gain for converting the signal charge in the floating diffusion layer FD1 into a voltage can be selectively switched between a high gain and a low gain by turning on and off the gain control transistor GC1.

[0321] The normal CDS sequence for 1H is HCG (R: reset component) → HCG (S: signal component) in the case of HCG. This transition is the readout of signal charge from the photodiode (PD) to the floating diffusion layer FD0 when the conversion gain of the floating diffusion layer FD0 is high.

[0322] Since this transition is a normal CDS, the reset noise can be canceled and made zero.

[0323] Fig. 33B is a diagram showing the readout order of the reset component and the signal component in the HCG readout and the LCG readout of Fig. 33A. The figure shows the CDS order of 1H, and in the case of LCG, it is LCG (S: signal component) → LCG (R: reset component). This transition is the readout of the signal charge from the storage capacitance element C0 and the storage capacitance element C4 to the floating diffusion layer FD0 when the conversion gain of the floating diffusion layer FD1 is low.

[0324] In this transition, in the LCG, the DC offset (reset coupling) can be removed, but the pixel reset noise cannot be canceled and remains as kTC noise.

[0325] This kTC noise in short exposure (high illuminance) appears on the low illuminance side. For example, it is shown in Figure 30C. Here, kTC noise is expressed in terms of charge amount as √(kTC). This noise must be set so that it is sufficiently smaller than the signal level. In this way, at the boundary between short exposure (high illuminance) and long exposure with low illuminance, the SN of the latter must be sufficiently better than the SN of the former.

[0326] [5.3 Configuration and operation example of negative feedback circuit] The timing of charge accumulation in the photodiode PD and the storage capacitor element C1 shown in FIG.

[0327] The timing will be explained with reference to FIG. 33A.

[0328] First, from time t1 to t2, the photodiodes PD, FD0, and FD1 are reset and exposure is started. Then, from time t3 to t4, the shutter is operated and exposure starts. The exposure time ends at time t5.

[0329] In the HCG, a reset operation is performed between times t5 and t6. The reset component is read out between times t8 and t9. Next, the signal charge accumulated in the photodiode is transferred to FD0 by the transfer signal TG between times t7 and t8. The signal component is read out between times t8 and t9.

[0330] In the LCG, the signal charge accumulated in the photodiode is transferred to FD0 by the transfer signal TG from time t9 to t10. The signal component is read out from time t10 to t11. Next, a reset operation is performed from time t11 to t12. The reset component is read out from time t12 to t13.

[0331] Here, reset noise occurs during the shutter period from time t3 to t4, and during the reset period from time t11 to t12. For this reason, the negative feedback circuit 21 operates during these periods, gradually turning off the reset control signal RS and the accumulated charge transfer element TGC, thereby reducing the reset noise. The solid lines show how a slope-shaped signal is applied to the reset transistor (RS) and the accumulated charge transfer element (TGC) at this time.

[0332] [5.4 Expanding the dynamic range] The feature of this embodiment is that the two frames, Long and Short, used to synthesize the WDR, are exposed at exactly the same timing and use exactly the same pixels, so false colors, coloring, and blurring do not occur.

[0333] Figure 16 shows an overview of the WDR in-pixel synthesis method. Figure 29 shows an example of the configuration of a signal processing unit that performs WDR synthesis using two frames. For WDR, Long exposure (low illuminance) is treated as a signal charge of Q0, and Short exposure (high illuminance) is treated as a signal charge of (Q0+Q1).

[0334] The horizontal axis of [1][2][3][4] in Figure 16 indicates the product of illuminance and exposure time, illuminance for a certain period of time, or exposure time at a certain illuminance. The vertical axis indicates [1] the charge accumulation level, [2] the FD potential, [3] the value after AD conversion, and [4] the SN.

[0335] FIG. 16 is a diagram showing the signal charge amount and the FD potential in the first Read1 for reading out a low-illumination frame and the second Read2 for reading out a high-illumination frame.

[0336] Figure 30A ~Figure 30D 13 is a diagram showing the relationship between the object illuminance and the gain (SN ratio) according to the fifth embodiment.

[0337] Figure 30A shows the first Read1 synthesized as a WDR Long frame (low illuminance frame) and the second Read2 synthesized as a WDR Short frame (high illuminance frame). The signal-to-noise ratio at the joint between the frames is 20 dB or more, and the dynamic range is 120 dB or more. The dynamic range is expanded by the storage capacity from very dim illuminance (0.1 Lux) to very bright illuminance (100,000 Lux: equivalent to sunlight).

[0338] The details of the WDR synthesis circuit 76 constituting the signal processing unit 70 are shown in Fig. 29. The pixel signal of the first low-illuminance frame (long exposure) and the pixel signal of the second high-illuminance frame (short exposure) are synthesized. This synthesis realizes a wide dynamic range function (WDR function), that is, the dynamic range is expanded.

[0339] The pixel gain is set high for pixel signals of frames in low-illumination areas (long exposure), and the pixel gain is set low for pixel signals of frames in high-illumination areas (short exposure), thereby improving noise in low illumination and expanding the dynamic range in high illumination.

[0340] In this way, according to this embodiment, it is possible to improve both the dynamic range and the SNR while reducing the reset noise of the storage capacitance element.

[0341] In this embodiment, this reset noise is reduced by the negative feedback circuit 21, so it can be used with a higher gain than in the prior art. For example, without any countermeasure, the analog gain could only be increased to 12 dB as shown in FIG. 30B. However, with a countermeasure to reduce the reset noise, the analog gain can be used up to 18 dB as shown in FIG. 30D. The allowable value for use is SN20 dB or more.

[0342] (Embodiment 6) A solid-state imaging device 100 according to the sixth embodiment will be described from the viewpoint of differences from the embodiment 1A. The configuration example of the solid-state imaging device 100 is different in that a gain control transistor MCG of a pixel is added and the number of horizontal scanning line groups 15 to be controlled is different, but otherwise the configuration is the same.

[0343] Whereas embodiment 1A is provided with a means for selecting a signal in the high illuminance region and a signal in the low illuminance region, embodiment 6 is provided with a means for synthesizing three frames of a signal in the high illuminance region, a signal in the medium illuminance region, and a signal in the low illuminance region. This makes it possible to improve the signal-to-noise ratio at the boundaries of each frame, and also makes it possible to use a higher analog gain due to the effect of reducing reset noise, thereby improving low illuminance characteristics.

[0344] [6.1 Example of pixel circuit configuration] Next, a configuration example of the pixel circuit 3 will be described.

[0345] Fig. 34A is a diagram showing an example of a circuit including a pixel circuit 3 and a negative feedback circuit 21 according to embodiment 6. This diagram is equivalent to the first configuration example in Fig. 1A, that is, equivalent to a configuration example having two stages of storage circuits in the vertical direction. The following mainly describes the differences.

[0346] [6.2 Example of read operation in this embodiment] FIG. 35A shows the read order of one frame in the sixth embodiment.

[0347] The gain for converting the signal charge in the floating diffusion layer FD1 into a voltage can be selectively switched among a high gain, a medium gain (MCG), and a low gain by turning on and off the gain control transistors GC1 and GC2.

[0348] The normal CDS sequence for 1H is HCG (R: reset component) → HCG (S: signal component) in the case of HCG. This transition is the readout of signal charge from the photodiode (PD) to the floating diffusion layer FD0 when the conversion gain of the floating diffusion layer FD0 is high.

[0349] Since this transition is a normal CDS, the reset noise can be canceled and made zero.

[0350] Fig. 35B is a diagram showing the read order of the reset component and signal component in the HCG readout, MCG readout, and LCG readout of Fig. 35A. The diagram shows the CDS order of 1H, and after HCG readout, in the case of MCG(S: signal component) → LCG, the order becomes LCG(S: signal component) → LCG(R: reset component) → MCG(R: reset component).

[0351] In the medium gain (MCG), this transition is the readout of signal charges from the storage capacitor element C0 and the storage capacitor element C1 to the floating diffusion layer FD0 when the conversion gain of the floating diffusion layer FD1 is low.

[0352] In the low gain (LCG) case, this transition occurs when the conversion gain of the floating diffusion layer FD2 is low, and the storage capacitance elements C0, C1, and C2 are C2 The signal charge is read out from this to the floating diffusion layer FD0.

[0353] This transition can remove DC offsets (reset coupling) in MCG and LCG, but pixel reset noise cannot be canceled and remains as kTC noise.

[0354] The kTC noise in this middle exposure (middle illuminance) appears on the middle illuminance side. For example, it is shown in Figure 39A. Here, the kTC noise is expressed as √(kTC) in charge amount. This noise must be set to be sufficiently smaller than the signal level. Medium Light ) and long exposure with low illumination, the SN of the latter needs to be significantly better than the SN of the former.

[0355] The kTC noise in this short exposure (high illumination) appears on the low illumination side. For example, see FIG. 39A. Here, the kTC noise is expressed as √(kTC) in terms of the charge amount. This noise must be set to be sufficiently smaller than the signal level. Medium Light ) and long exposure with low illumination, the SN of the latter needs to be significantly better than the SN of the former.

[0356] [6.3 Configuration and operation example of negative feedback circuit] Figure 36 shows an example of the timing of charge accumulation in the photodiode PD and storage capacitor C1. The photodiode PD continues to be exposed for a 1V period (one vertical synchronization period) and the amount of charge is Q0. The storage capacitor C1, which receives charge that has overflowed from this photodiode PD, becomes the Q1 signal. Furthermore, the storage capacitor C2, which receives charge that has overflowed from the storage capacitor C1, becomes the Q2 signal. Q0, Q1, and Q2 are exposed at exactly the same timing.

[0357] In the rolling shutter method, reset is performed row by row scanning. After that, exposure starts, and the exposure time is expressed as T_Q0 = T_Q1 = T_Q2.

[0358] An example of the timing will be described with reference to FIG. 35A.

[0359] First, from time t1 to t2, the photodiode PD and FD0, FD1, and FD2 are reset and exposure is started. Then, from time t3 to t4, the shutter operation is performed and exposure starts. The exposure time ends at time t5.

[0360] A reset operation is performed between times t5 and t6. The reset component of HCG is read out between times t6 and t7. Next, the signal charge accumulated in the photodiode is transferred to FD0 by a transfer signal TG between times t7 and t8. The signal component of HCG is read out between times t8 and t9.

[0361] At t9, the signal charge accumulated in the photodiode is transferred to FD1 by turning on the transfer signal GC1. Between times t9 and t10, the signal charge accumulated in the photodiode is transferred to FD1 by the transfer signal TG. Between times t10 and t11, the signal component of LCG is read out.

[0362] At t11, the signal charge accumulated in the photodiode is transferred to FD2 by turning on transfer signal GC2. Between time t11 and t12, the signal charge accumulated in the photodiode is transferred to FD1 by transfer signal TG. Between time t12 and t13, the signal component of LCG is read out.

[0363] The LCG reset operation is performed between times t13 and t14. The reset components of the LCG are read out between times t14 and t15.

[0364] At time t15, GC2 is turned off. Between times t15 and t16, the MCG is reset. Between times t16 and t17, the reset components of the MCG are read out.

[0365] Here, reset noise occurs during the shutter period between times t3 and t4, the reset period between times t13 and t14, and the reset period between times t15 and t16. Therefore, during these periods, the negative feedback circuit 21 operates to gradually turn off the reset control signal RS and the gain control signal GC2, thereby reducing the reset noise. At this time, a slope-shaped signal is applied to the reset transistor (RS) and the gain control signal (GC2).

[0366] [6.4 Expanding the dynamic range] The feature of this embodiment is that the three frames, Long, Middle, and Short, that combine the WDR are exposed at exactly the same timing and use exactly the same pixels, so false colors, coloring, and blurring do not occur.

[0367] Figure 37 shows an overview of the WDR in-pixel synthesis method. Figure 34B shows an example of the configuration of a signal processing unit that performs WDR synthesis using three frames. WDR is synthesized by using Q0 signal charge for long exposure (low illuminance), (Q0+Q1) signal charge for middle exposure (medium illuminance), and (Q0+Q1+Q2) signal charge for short exposure (high illuminance).

[0368] The horizontal axis of [1][2][3][4] in Figure 37 indicates the product of illuminance and exposure time, illuminance for a certain period of time, or exposure time at a certain illuminance. The vertical axis indicates [1] the charge accumulation level, [2] the FD potential, [3] the value after AD conversion, and [4] the SN.

[0369] Fig. 38 is a diagram showing the FD potential in the HCG readout, MCG readout, and LCG readout of Fig. 37. That is, it is a diagram showing the signal charge amount and the FD potential in the first Read1 for reading out a low illuminance frame, the second Read2 for reading out a medium illuminance frame, and the third Read3 for reading out a high illuminance frame.

[0370] 39A to 39D are diagrams showing the relationship between the object illuminance and the gain (SN ratio) according to the sixth embodiment.

[0371] 39A and 39B are diagrams showing, as a comparative example, the relationship between the subject illuminance and the gain (SNR) in LCG readout in the absence of the negative feedback circuit 21. In Fig. 39A, the analog gain is 0 dB, and in Fig. 39B, the analog gain is 24 dB.

[0372] Figures 39C and 39D are diagrams showing the relationship between the subject illuminance and gain (SN ratio) in LCG readout according to embodiment 6. In Figure 39C, the analog gain is 0 dB, and in Figure 39D, the analog gain is 30 dB.

[0373] Figure 39A shows a composite image of the first Read1 as a WDR Long frame (low illuminance frame), the second Read2 as a WDR Middle frame (medium illuminance frame), and the third Read3 as a WDR Short frame (high illuminance frame). The signal-to-noise ratio at the joints between the frames is 20 dB or more, and the dynamic range is 120 dB or more. The dynamic range is expanded by the storage capacity from very dim illuminance (0.1 Lux) to very bright illuminance (100,000 Lux: equivalent to sunlight).

[0374] The details of the WDR synthesis circuit 76 constituting the signal processing unit 70 are shown in Fig. 34B. The pixel signal of the first low illuminance frame (long exposure), the pixel signal of the second medium illuminance frame (middle exposure), and the pixel signal of the third high illuminance frame (short exposure) are synthesized. This synthesis realizes a wide dynamic range function (WDR function), that is, the dynamic range is expanded.

[0375] The pixel signal for a frame in a low-illumination region (long exposure) has a high in-pixel gain set, the pixel signal for a frame in a medium-illumination region (middle exposure) has an intermediate in-pixel gain set, and the pixel signal for a frame in a high-illumination region (short exposure) has a low in-pixel gain set, thereby improving noise in low illumination and expanding the dynamic range in high illumination.

[0376] In this way, according to this embodiment, it is possible to improve both the dynamic range and the SNR while reducing the reset noise of the storage capacitance element.

[0377] In this embodiment, this reset noise is reduced by the negative feedback circuit 21, so it can be used with a higher gain than in the prior art. For example, without any countermeasure, the analog gain could only be increased to 24 dB as shown in FIG. 39B. However, with a countermeasure to reduce the reset noise, the analog gain can be used up to 30 dB as shown in FIG. 39D. The allowable value for use is SN20 dB or more.

[0378] (Embodiment 7) The solid-state imaging device 100 according to the seventh embodiment will be described from the viewpoint of the difference from the third embodiment. The configuration example of the solid-state imaging device 100 is different in that the gain control transistor MCG of the pixel is added and the number of the horizontal scanning line group 15 to be controlled is different, but otherwise the configuration is the same.

[0379] Whereas embodiment 3A is provided with a means for selecting a signal in the high illuminance region and a signal in the low illuminance region, embodiment 7 is provided with a means for synthesizing three frames of a signal in the high illuminance region, a signal in the medium illuminance region, and a signal in the low illuminance region. This makes it possible to improve the signal-to-noise ratio at the boundaries of each frame, and also makes it possible to use a higher analog gain due to the effect of reducing reset noise, thereby improving low illuminance characteristics.

[0380] [7.1 Example of pixel circuit configuration] Next, a configuration example of the pixel circuit 3 will be described.

[0381] Fig. 40 is a diagram showing an example of a circuit including a pixel circuit 3 and a negative feedback circuit 21 according to embodiment 7. This diagram is equivalent to the third configuration example in Fig. 1C, that is, equivalent to a configuration example having two stages of storage circuits in the horizontal direction. The following mainly describes the differences.

[0382] [7.2 Example of read operation in this embodiment] FIG. 41A is a time chart showing the read order of one frame in the seventh embodiment.

[0383] The gain for converting the signal charge in the floating diffusion layer FD1 into a voltage can be selectively switched among a high gain, a medium gain (MCG), and a low gain by turning on and off the gain control transistor GC and the accumulation transfer transistor TGC1.

[0384] The normal CDS sequence for 1H is HCG (R: reset component) → HCG (S: signal component) in the case of HCG. This transition is the readout of signal charge from the photodiode (PD) to the floating diffusion layer FD0 when the conversion gain of the floating diffusion layer FD0 is high.

[0385] Since this transition is a normal CDS, the reset noise can be canceled and made zero.

[0386] Fig. 41B is a diagram showing the read order of the reset component and the signal component in the HCG readout, MCG readout, and LCG readout of Fig. 41A. The diagram shows the CDS order of 1H, and the read order is MCG (R: reset component) → HCG (R: reset component) → HCG (S: signal component) → MCG (S: signal component) → LCG (S: signal component) → LCG (R: reset component).

[0387] In the medium gain (MCG), this transition is the readout of signal charges from the storage capacitor elements C0 and C3 to the floating diffusion layer FD0 when the conversion gain of the floating diffusion layer FD1 is low.

[0388] In the low gain (LCG), this transition results in the reading out of signal charges from the storage capacitors C0, C3, and C4 to the floating diffusion layer FD0 when the conversion gain of the floating diffusion layer FD2 is low.

[0389] In this transition, in the LCG, the DC offset (reset coupling) can be removed, but the pixel reset noise cannot be canceled and remains as kTC noise.

[0390] Also, the kTC noise in this short exposure (high illumination) appears on the low illumination side. For example, see FIG. 18B. Here, the kTC noise is expressed as √(kTC) in terms of the charge amount. This noise must be set to be sufficiently smaller than the signal level. Medium Light ) and long exposure with low illumination, the SN of the latter needs to be significantly better than the SN of the former.

[0391] [7.3 Configuration and operation example of negative feedback circuit] 36 is a diagram showing an example of the timing of charge accumulation in the photodiode PD and the two storage capacitor elements C1 and C2. The photodiode PD continues to be exposed for a 1V period (one vertical synchronization period) and has a charge amount of Q0. The storage capacitor element C1, which receives charge overflowing from this photodiode PD, becomes a Q1 signal. Furthermore, the storage capacitor element C4, which receives charge overflowing from the storage capacitor element C1, becomes a Q2 signal. Q0, Q1, and Q2 are exposed at exactly the same timing.

[0392] In the rolling shutter method, reset is performed row by row scanning. After that, exposure starts, and the exposure time is expressed as T_Q0 = T_Q1 = T_Q2.

[0393] An example of the timing will be described with reference to FIG. 41A.

[0394] First, from time t1 to t2, the photodiode PD and FD0, FD1, and FD2 are reset and exposure is started. Then, from time t3 to t4, the shutter operation is performed and exposure starts. The exposure time ends at time t5.

[0395] First, at time t5, the gain control signal GC1 is turned ON to transfer the signal to FD1. A reset operation is performed between times t5 and t6. The reset component of HCG is read out between times t6 and t7.

[0396] Next, a reset operation is performed between times t7 and t8, and the reset component of the HCG is read out between times t8 and t9.

[0397] Next, from time t9 to t10, the signal charge accumulated in the photodiode is transferred to FD0 by a transfer signal TG. Between time t10 and t11, the signal component of HCG is read out.

[0398] At time t11, the signal charge accumulated in the photodiode is transferred to FD1 by turning on the transfer signal GC1. Between time t11 and t12, the signal charge accumulated in the photodiode is transferred to FD1 by the transfer signal TG. Between time t12 and t13, the signal component of HCG is read out.

[0399] At time t13, the signal charge accumulated in the photodiode is transferred to FD2 by turning on the accumulation transfer transistor TGC. Between times t13 and t14, the signal charge accumulated in the storage capacitance element C2 is transferred to FD2 by the transfer signal TGC. Between times t14 and t15, the signal component of LCG is read out.

[0400] A reset operation is performed between times t15 and t16. The reset components of the MCG are read out between times t16 and t17.

[0401] At time t16, each transistor is turned OFF.

[0402] Here, reset noise occurs during the shutter period from time t3 to t4, and during the reset period from time t15 to t16. For this reason, the negative feedback circuit 21 operates during these periods, gradually turning off the reset control signal RS and the accumulated charge transfer element TGC, thereby reducing the reset noise. The solid lines show how a slope-shaped signal is applied to the reset transistor (RS) and the accumulated charge transfer element (TGC) at this time.

[0403] [7.4 Expanding the dynamic range] The feature of this embodiment is that the three frames, Long, Middle, and Short, that combine the WDR are exposed at exactly the same timing and use exactly the same pixels, so false colors, coloring, and blurring do not occur.

[0404] Fig. 37 is an explanatory diagram showing an overview of a WDR in-pixel synthesis method. Fig. 34B is a diagram showing an example of the configuration of a signal processing unit that performs WDR synthesis using three frames. WDR is synthesized by using a signal charge of Q0 for long exposure (low illuminance), a signal charge of (Q0+Q1) for middle exposure (medium illuminance), and a signal charge of (Q0+Q1+Q2) for short exposure (high illuminance).

[0405] The horizontal axis of [1][2][3][4] in Figure 37 indicates the product of illuminance and exposure time, illuminance for a certain period of time, or exposure time at a certain illuminance. The vertical axis indicates [1] the charge accumulation level, [2] the FD potential, [3] the value after AD conversion, and [4] the SN.

[0406] FIG. 37 is a diagram showing the signal charge amount and FD potential of the first Read1 for reading out a low illuminance frame, the second Read2 for reading out a medium illuminance frame, and the third Read3 for reading out a high illuminance frame.

[0407] 39A to 39D are diagrams showing the relationship between the object illuminance and the gain (SN ratio) according to the seventh embodiment.

[0408] 39A and 39B are diagrams showing, as a comparative example, the relationship between the subject illuminance and the gain (SNR) in LCG readout in the absence of the negative feedback circuit 21. In Fig. 39A, the analog gain is 0 dB, and in Fig. 39B, the analog gain is 24 dB.

[0409] Figures 39C and 39D are diagrams showing the relationship between the subject illuminance and gain (SN ratio) in LCG readout according to embodiment 6. In Figure 39C, the analog gain is 0 dB, and in Figure 39D, the analog gain is 30 dB.

[0410] Figure 39A shows a composite image of the first Read1 as a WDR Long frame (low illuminance frame), the second Read2 as a WDR Middle frame (medium illuminance frame), and the third Read3 as a WDR Short frame (high illuminance frame). The signal-to-noise ratio at the joints between the frames is 20 dB or more, and the dynamic range is 120 dB or more. The dynamic range is expanded by the storage capacity from very dim illuminance (0.1 Lux) to very bright illuminance (100,000 Lux: equivalent to sunlight).

[0411] The details of the WDR synthesis circuit 76 constituting the signal processing unit 70 are shown in Fig. 34B. The pixel signal of the first low illuminance frame (long exposure), the pixel signal of the second medium illuminance frame (middle exposure), and the pixel signal of the third high illuminance frame (short exposure) are synthesized. This synthesis realizes a wide dynamic range function (WDR function), that is, the dynamic range is expanded.

[0412] The pixel signal for a frame in a low-illumination region (long exposure) has a high in-pixel gain set, the pixel signal for a frame in a medium-illumination region (middle exposure) has an intermediate in-pixel gain set, and the pixel signal for a frame in a high-illumination region (short exposure) has a low in-pixel gain set, thereby improving noise in low illumination and expanding the dynamic range in high illumination.

[0413] In this way, according to this embodiment, it is possible to improve both the dynamic range and the SNR while reducing the reset noise of the storage capacitance element.

[0414] (Embodiment 8) In the sixth embodiment, there is a 1V exposure, so the read row and the shutter row are the same readout, so there is one feedback amplifier, and in the eighth embodiment, the read row and the shutter row are not the same, so there are two feedback amplifiers. Negative feedback can be configured independently for each, and the exposure time can be freely set multiple times within one frame period.

[0415] [8.1 Example of pixel circuit configuration] Next, a configuration example of the pixel circuit 3 will be described.

[0416] Fig. 42 is a diagram showing an example of a circuit of a main part including a pixel circuit 3 and a negative feedback circuit 21 according to embodiment 8. This diagram differs from the first configuration example in Fig. 1A or the configuration example in Fig. 32 of embodiment 5 in that a second reset transistor RS2, a selection transistor SEL2, a current source, and a negative feedback circuit 21a are added.

[0417] This allows resetting two different pixel rows by negative feedback using the negative feedback circuits 21 and 21a. For example, it is possible to execute resetting at the start of exposure on one row and resetting at the time of readout on the other row.

[0418] The following will mainly explain the differences.

[0419] [8.2 Example of read operation in this embodiment] FIG. 43A is a time chart showing the read order of one frame in the embodiment 8A.

[0420] The gain for converting the signal charge in the floating diffusion layer FD1 into a voltage can be selectively switched between a high gain, a medium gain (MCG), and a low gain (LCG) by turning on and off the gain control transistors GC1 and GC2.

[0421] The normal CDS sequence for 1H is HCG (R: reset component) → HCG (S: signal component) in the case of HCG. This transition is the reading of signal charge from the photodiode PD to the floating diffusion layer FD0 when the conversion gain of the floating diffusion layer FD0 is high. This transition is normal CDS, so the reset noise can be canceled and reduced to zero.

[0422] In the case of MCG, it becomes MCG (R: reset component) → MCG (S: signal component). This transition is the readout of signal charge from the photodiode PD to the floating diffusion layer FD0 when the conversion gain of the floating diffusion layers FD0 and FD1 is in the intermediate state.

[0423] In the case of LCG, it goes from LCG (R: reset component) to LCG (S: signal component). This transition is the reading of signal charge from the photodiode PD to the floating diffusion layer FD0 when the conversion gain of the floating diffusion layers FD0, FD1, and FD2 is in an intermediate state. This transition is not a normal CDS, so the reset noise cannot be canceled, and the negative feedback circuit 21 is used to reduce the reset noise.

[0424] Fig. 43B is a diagram showing the read order of the reset component and the signal component in the HCG readout, MCG readout, and LCG readout of Fig. 43A. The diagram shows the CDS order of 1H, which is HCG (R: reset component) → HCG (S: signal component) → MCG (S: signal component) → MCG (R: reset component) → LCG (S: signal component) → LCG (R: reset component).

[0425] This transition between MCG and LCG can remove DC offsets (reset coupling), but the pixel reset noise cannot be canceled and remains as kTC noise.

[0426] The kTC noise in this middle exposure (medium illuminance) appears at middle illuminance. Here, the kTC noise is expressed as √(kTC) in charge. This noise must be set to be sufficiently smaller than the signal level. Medium Light ) and long exposure with low illumination, the SN of the latter needs to be significantly better than the SN of the former.

[0427] The kTC noise in this short exposure (high illumination) appears on the low illumination side. Here, the kTC noise is expressed as √(kTC) in terms of the charge amount. This noise must be set to be sufficiently smaller than the signal level. Medium Light ) and long exposure with low illumination, the SN of the latter needs to be significantly better than the SN of the former.

[0428] [8.3 Configuration and operation example of negative feedback circuit] FIG. 44 shows an example of the timing of charge accumulation in the photodiode PD, the storage capacitor element C1, and the storage capacitor element C2. With the accumulation times of PD, C1, and C2 set to the same, the first exposure time is T_Q0, the second exposure time is T_Q1, 3 The second exposure time is T_ Q2 Then, the pixels are exposed continuously for 1V period (1 vertical synchronization period) with the relationship T_Q0>T_Q1>T_Q2.

[0429] If the charge of the photodiode PD is Q0, the charge of the storage capacitor C1 is Q1, and the charge of the storage capacitor C2 is Q2, then a signal charge of Q0 is accumulated at T_Q0, a signal charge of Q0+Q1 is accumulated at T_Q1, and a signal charge of Q0+Q1+Q2 is accumulated at T_Q2.

[0430] In the rolling shutter method, resetting is performed row by row by row scanning. The charge from the photodiode is read out to the storage capacitor elements C1 and C2 row by row. After that, the signal charge in the storage capacitor elements C1 and C2 is read out by the rolling shutter method.

[0431] An example of the timing will be described with reference to FIG. 43A.

[0432] First, from time t1 to t2, the photodiode PD and FD0, FD1, and FD2 are reset and exposure is started. Then, from time t3 to t4, the shutter operation is performed and exposure starts. The exposure time ends at time t5.

[0433] A reset operation is performed between times t5 and t6. The reset component of HCG is read out between times t6 and t7. Next, the signal charge accumulated in the photodiode is transferred to FD0 by a transfer signal (TG) between times t7 and t8. The signal component of HCG is read out between times t8 and t9.

[0434] At time t9, the signal charge accumulated in the photodiode is transferred to FD1 by turning on the transfer signal GC1. Between times t9 and t10, the signal charge accumulated in the photodiode is transferred to FD1 by the transfer signal (TG). Between times t10 and t11, the signal component of LCG is read out.

[0435] Next, from time t9 to t10, the photodiode PD and FD0, FD1, and FD2 are reset and exposure is started. Then, from time t11 to t12, the shutter operation is performed and exposure is started. The exposure time ends at time t13.

[0436] At time t13, the signal charge accumulated in the storage capacitor element C1 is transferred to FD1 by turning on the transfer signal GC1. Between times t13 and t14, the signal charge accumulated in the photodiode and the charge accumulated in the storage capacitor element C1 are transferred to FD1 by the transfer signal (TG). Between times t14 and t15, the signal component of LCG is read out.

[0437] The reset operation is performed between times t15 and t16. The reset component of the HCG is read out between times t16 and t17.

[0438] Next, from time t17 to t18, the photodiode PD and FD0, FD1, and FD2 are reset and exposure is started. Then, from time t19 to t20, the shutter operation is performed and exposure is started. The exposure time ends at time t21.

[0439] At time t21, the signal charge accumulated in the storage capacitor element C2 is transferred to FD1 by turning on the transfer signal GC2. From time t23 to t24, the signal charge accumulated in the photodiode, the charge accumulated in the storage capacitor element C1, and the charge accumulated in the storage capacitor element C2 are transferred to FD1 by the transfer signal (TG). Between time t22 and t23, the signal component of LCG is read out.

[0440] A reset operation is performed between times t23 and t24. The reset component of HCG is read out between times t24 and t25.

[0441] Here, reset noise occurs during the shutter period between times t11 and t12, the reset period between times t15 and t16, the shutter period between times t19 and t20, and the reset period between times t23 and t24. For this reason, the negative feedback circuit 21 operates during these periods, gradually turning off the reset control signal RS and the gain control signal GC2, thereby reducing the reset noise. At this time, a slope-shaped signal is applied to the reset transistor (RS) and the gain control signal (GC2).

[0442] [8.4 Expanding the dynamic range] In the first to seventh embodiments, the three frames of Long, Middle, and Short that combine the WDR are exposed at exactly the same timing and use exactly the same pixels, so that false colors, coloring, and blurring do not occur.

[0443] The feature of the eighth embodiment is that the three frames Long, Middle, and Short that combine WDR are provided with two negative feedback circuits 21 and 21a for the shutter and the lead, so that the time can be changed independently. Therefore, for example, the dynamic range can be expanded by shortening the exposure time.

[0444] The relationship between the object illuminance and the gain (SN ratio) according to the eighth embodiment is the same as that shown in FIG. 39A in the sixth and seventh embodiments. ~ Figure 39D However, by varying the exposure time, the dynamic range can be expanded.

[0445] With the accumulation times of PD, C1, and C2 set to the same, for example, the first exposure time is T_Q0, the second exposure time is T_Q1, 3 The second exposure time is T_ Q2 Then, the pixels are exposed continuously for 1V period (1 vertical synchronization period) with the relationship T_Q0>T_Q1>T_Q2.

[0446] In this case, if the charge in the photodiode PD is Q0, the charge in the storage capacitance element C1 is Q1, and the charge in the storage capacitance element C2 is Q2, then a signal charge of Q0 is accumulated at T_Q0, a signal charge of Q0+Q1 is accumulated at T_Q1, and a signal charge of Q0+Q1+Q2 is accumulated at T_Q2.

[0447] For pixel signals of frames in low-illumination regions (long exposure), the intra-pixel gain x exposure time is set high, for pixel signals of frames in medium-illumination regions (middle exposure), the intra-pixel gain x exposure time is set intermediate, and for pixel signals of frames in high-illumination regions (short exposure), the intra-pixel gain x exposure time is set low, thereby improving noise in low illumination and expanding the dynamic range in high illumination.

[0448] In this way, according to this embodiment, it is possible to improve both the dynamic range and the SNR while reducing the reset noise of the storage capacitance element.

[0449] Here, as an example, Line-by-Line control for three-sheet exposure is used, but it can also be realized for three or more sheets of exposure.

[0450] (Embodiment 9) In the seventh embodiment, there is 1V exposure, so the read row and the shutter row are the same readout, so there is one feedback amplifier, and in the ninth embodiment, the read row and the shutter row are not the same, so there are two feedback amplifiers. Negative feedback can be configured independently for each, and the exposure time can be freely set multiple times within one frame period.

[0451] [9.1 Example of pixel circuit configuration] Next, a configuration example of the pixel circuit 3 will be described.

[0452] Fig. 45 is a diagram showing an example of a circuit of a main part including a pixel circuit 3 and a negative feedback circuit 21 according to embodiment 9. This diagram differs from the third configuration example in Fig. 1C or the configuration example in Fig. 40 of embodiment 7 in that a second reset transistor RS2, a selection transistor SEL2, a current source, and a negative feedback circuit 21a are added.

[0453] This allows resetting of two different pixel rows by the negative feedback circuits 21, 21a. For example, it is possible to execute resetting at the start of exposure on one row, and execute resetting at the time of readout on the other row.

[0454] [9.2 Example of read operation in this embodiment] FIG. 46A is a time chart showing the read order of one frame in the ninth embodiment.

[0455] The gain for converting the signal charge in the floating diffusion layer FD1 into a voltage can be selectively switched between a high gain, a medium gain (MCG), and a low gain by turning on and off the gain control transistor GC1 and the accumulation transfer transistor (TG) C.

[0456] The normal CDS sequence for 1H is HCG (R: reset component) → HCG (S: signal component) in the case of HCG. This transition is the reading of signal charge from the photodiode PD to the floating diffusion layer FD0 when the conversion gain of the floating diffusion layer FD0 is high. This transition is normal CDS, so the reset noise can be canceled and reduced to zero.

[0457] In the case of MCG, it becomes MCG (R: reset component) → MCG (S: signal component). This transition is the readout of the signal charge from the photodiode (PD) to the floating diffusion layer FD0 when the conversion gain of the floating diffusion layers FD0 and FD1 is in the intermediate state.

[0458] In the case of LCG, it goes from LCG (R: reset component) to LCG (S: signal component). This transition is the readout of signal charge from the photodiode PD to the floating diffusion layer FD0 when the conversion gain of the floating diffusion layers FD0, FD1, and FD2 is in an intermediate state. This transition is not a normal CDS, so the reset noise cannot be canceled, and a negative feedback circuit is used to reduce the reset noise.

[0459] Fig. 46B is a diagram showing the read order of the reset component and the signal component in the HCG readout, MCG readout, and LCG readout of Fig. 46A. The diagram shows the CDS order of 1H, which is HCG (R: reset component) → HCG (S: signal component) → MCG (S: signal component) → MCG (R: reset component) → LCG (S: signal component) → LCG (R: reset component).

[0460] This transition between MCG and LCG can remove DC offsets (reset coupling), but the pixel reset noise cannot be canceled and remains as kTC noise.

[0461] The kTC noise in this middle exposure (medium illuminance) appears at middle illuminance. Here, the kTC noise is expressed as √(kTC) in charge. This noise must be set to be sufficiently smaller than the signal level. Medium Light ) and long exposure with low illumination, the SN of the latter needs to be significantly better than the SN of the former.

[0462] The kTC noise in this short exposure (high illumination) appears on the low illumination side. Here, the kTC noise is expressed as √(kTC) in terms of the charge amount. This noise must be set to be sufficiently smaller than the signal level. Medium Light ) and long exposure with low illumination, the SN of the latter needs to be significantly better than the SN of the former.

[0463] [9.3 Configuration and operation example of negative feedback circuit] FIG. 44 is a diagram showing an example of the timing of charge accumulation in the photodiode PD, the storage capacitor element C1, and the storage capacitor element C2. With the accumulation times of these PD, C1, and C2 set to the same, the first exposure time is T_Q0, the second exposure time is T_Q1, 3 The second exposure time is T_ Q2 Then, the pixels are exposed continuously for 1V period (1 vertical synchronization period) with the relationship T_Q0>T_Q1>T_Q2.

[0464] If the charge of the photodiode PD is Q0, the charge of the storage capacitor C3 is Q1, and the charge of the storage capacitor C4 is Q2, then a signal charge of Q0 is accumulated at T_Q0, a signal charge of Q0+Q1 is accumulated at T_Q1, and a signal charge of Q0+Q1+Q2 is accumulated at T_Q2.

[0465] An example of the timing will be described with reference to FIG. 46A.

[0466] First, from time t1 to t2, the photodiode PD and FD0, FD1, and FD2 are reset and exposure is started. Then, from time t3 to t4, the shutter operation is performed and exposure starts. The exposure time ends at time t5.

[0467] A reset operation is performed between times t5 and t6. The reset component of HCG is read out between times t6 and t7. Next, the signal charge accumulated in the photodiode is transferred to FD0 by a transfer signal (TG) between times t7 and t8. The signal component of HCG is read out between times t8 and t9.

[0468] At time t9, the signal charge accumulated in the photodiode is transferred to FD1 by turning on the transfer signal GC1. Between times t9 and t10, the signal charge accumulated in the photodiode is transferred to FD1 by the transfer signal (TG). Between times t10 and t11, the signal component of LCG is read out.

[0469] Next, from time t9 to t10, the photodiode PD and FD0, FD1, and FD2 are reset and exposure is started. Then, from time t11 to t12, the shutter operation is performed and exposure is started. The exposure time ends at time t13.

[0470] At time t13, the signal charge accumulated in the storage capacitor element C1 is transferred to FD1 by turning on the transfer signal GC1. Between times t13 and t14, the signal charge accumulated in the photodiode and the charge accumulated in the storage capacitor element C1 are transferred to FD1 by the transfer signal (TG). Between times t14 and t15, the signal component of LCG is read out.

[0471] The reset operation is performed between times t15 and t16. The reset component of the HCG is read out between times t16 and t17.

[0472] Next, from time t17 to t18, the photodiode PD and FD0, FD1, and FD2 are reset and exposure is started. Then, from time t19 to t20, the shutter operation is performed and exposure is started. The exposure time ends at time t21.

[0473] At time t21, the signal charge accumulated in the storage capacitance element C4 is transferred to FD1 by turning on the storage transfer transistor (TG) C. From time t23 to t24, the signal charge accumulated in the photodiode, the charge accumulated in the storage capacitance element C1, and the charge accumulated in the storage capacitance element C2 are transferred to FD1 by the transfer signal (TG) and the storage transfer transistor (TG) C. Between time t22 and t23, the signal component of the LCG is read out.

[0474] A reset operation is performed between times t23 and t24. The reset component of HCG is read out between times t24 and t25.

[0475] Here, reset noise occurs during the shutter period of time t11 and t12 and the reset period of time t15 and t16. Also, reset noise occurs during the shutter period of time t19 and t20 and the reset period of time t23 and t24. Therefore, during these periods, the negative feedback circuit 21 operates to gradually turn off the reset control signal RS and the accumulated charge transfer element TGC, thereby reducing the reset noise. The solid line shows how a slope-shaped signal is applied to the reset transistor (RS) and the accumulated charge transfer element (TGC) at this time. Alternatively, as another method, the negative feedback circuit 21 operates during the shutter period of time t11 and t12 and the shutter period of time t19 and t20, gradually turning off the reset control signal RS, and sharply turning off the accumulated charge transfer element TGC, as shown by the broken line. At this time, the reset noise of the storage capacitance element C4 is not reduced due to the law of charge storage, but reset noise of the opposite positive and negative directions is generated in FD0. Since the FD section is not reset until the signal is read out (LCG), at this time, the reset noise of the storage capacitance element C4 and the FD section can be cancelled out and made zero.

[0476] [9.4 Expanding the dynamic range] In the first to seventh embodiments, the three frames of Long, Middle, and Short that combine the WDR are exposed at exactly the same timing and use exactly the same pixels, so that false colors, coloring, and blurring do not occur.

[0477] The feature of the ninth embodiment is that the three frames Long, Middle, and Short that combine WDR can be changed independently in time because two negative feedback circuits 21 are provided for the shutter and the lead. Therefore, for example, the dynamic range can be expanded by shortening the exposure time.

[0478] The relationship between the object illuminance and the gain (SN ratio) according to the ninth embodiment is the same as that shown in FIG. 39A in the sixth and seventh embodiments. ~ Figure 39D However, by varying the exposure time, the dynamic range can be expanded.

[0479] With the accumulation times of PD, C1, and C2 set to the same, for example, the first exposure time is T_Q0, the second exposure time is T_Q1, 3 The second exposure time is T_ Q2 Then, the pixels are exposed continuously for 1V period (1 vertical synchronization period) with the relationship T_Q0>T_Q1>T_Q2.

[0480] In this case, if the charge in the photodiode PD is Q0, the charge in the storage capacitance element C3 is Q1, and the charge in the storage capacitance element C4 is Q2, then a signal charge of Q0 is accumulated at T_Q0, a signal charge of Q0+Q1 is accumulated at T_Q1, and a signal charge of Q0+Q1+Q2 is accumulated at T_Q2.

[0481] For pixel signals of frames in low-illumination regions (long exposure), the intra-pixel gain x exposure time is set high, for pixel signals of frames in medium-illumination regions (middle exposure), the intra-pixel gain x exposure time is set intermediate, and for pixel signals of frames in high-illumination regions (short exposure), the intra-pixel gain x exposure time is set low, thereby improving noise in low illumination and expanding the dynamic range in high illumination.

[0482] In this way, according to this embodiment, it is possible to improve both the dynamic range and the SNR while reducing the reset noise of the storage capacitance element.

[0483] Here, as an example, Line-by-Line control for three-sheet exposure is used, but it can also be realized for three or more sheets of exposure.

[0484] (Embodiment 10) Hereinafter, the embodiments will be described with reference to the drawings. 10 An imaging device according to the present embodiment includes one or more solid-state imaging devices 100 according to the first to ninth embodiments. Details will be described below.

[0485] The view system in Fig. 47 is a block diagram showing a configuration example of an imaging device according to the tenth embodiment. The imaging device in the figure includes a CIS (CMOS Image Sensor) 91, an ISP (Image Signal Processor) 92, and a monitor 9, and is, for example, a digital camera or a smartphone camera. The CIS 91 is the solid-state imaging device 100 shown in each embodiment. The ISP 92 receives an image signal from the CIS 91 and performs image processing such as enlargement, reduction, compression encoding, and decoding of the image. The monitor 93 is a monitor for user confirmation during imaging.

[0486] The CIS 91 and the ISP 92 may be a single-chip SoC (System on Chip) 90, or may be separate chips. When the CIS 91 and the ISP 92 are separate chips, the signal processing unit 70 may be provided in the CIS 91 or in the CIS 92. Furthermore, a part of the signal processing unit 70 may be realized by software rather than a circuit.

[0487] Also, a sensing system in an ADAS (Advanced Driver Assistance System) or autonomous driving in Fig. 48 is a block diagram showing another example of the configuration of an imaging device according to the tenth embodiment. The imaging device in the figure includes a CIS (CMOS Image Sensor) 91, an ISP (Image Signal Processor) 92, a sensor 94, a sensor ECU (Electronic Control Unit) 95, a warning unit 96, and a control unit 97, and is, for example, a camera system mounted on an automobile. The CIS 91 and the ISP 92 are similar to the signal processing unit 70. The sensor 94 is, for example, a radar sensor for distance measurement or a Lidar (Light Detection and Ranging) sensor for distance measurement.

[0488] The sensor ECU 95 controls a warning unit 96 and a control unit 97 that receive signals from the ISP 92 and the sensor 94. The warning unit 96 is, for example, various status indicator lights and warning lights in the instrument panel of the automobile. The control unit 97 controls, for example, actuators that operate the steering wheel, brakes, etc. of the automobile.

[0489] The imaging device in FIG. 2 may be connected to a monitor in a view system and correspond to a sensing system such as an ADAS (Advanced Driver Assistance System) or autonomous driving, and the sensing system may provide warnings or control (steering, braking, etc.) via a sensor ECU.

[0490] Fig. 49 is a diagram showing an example of mounting an imaging device according to embodiment 10 on an automobile M1. Fig. 50 is a diagram showing an example of an imaging range in the mounting example of Fig. 49 according to embodiment 10.

[0491] In FIG. 49, for example, the imaging device in FIG. 2 is mounted at multiple locations. C1 ~ C9 Each of the following can be attached to the C1 is the front part of the car M1. C2 This is the left side of the car M1. C3 This is the right side of the car M1. C4 is the left door mirror. C5 is the right door mirror. C6 is the rearview mirror. C7 is the rear center part of the car M1. C8 is the rear left part of the car M1. C9 is the rear right part of the vehicle M1.

[0492] Also, the imaging ranges S1 to S9 shown in FIG. C1 ~ C9 It is compatible with the following imaging cameras.

[0493] As shown in Figures 49 and 50, imaging devices such as view cameras or sensing cameras can be installed in the front, surround, side, rear, or intelligent rear of transportation equipment (vehicles, automobiles) depending on the range of imaging to be performed.

[0494] As described above, the imaging device in embodiment 10 includes the imaging device of FIG. 47 or FIG. 48 above, and constitutes one of a view system, an ADAS (advanced driver assistance system) sensing system, and an autonomous driving sensing system.

[0495] Here, the imaging device may be mounted on one or more of the front, left side, right side, and rearview mirror of the transportation device.

[0496] In addition, the imaging device is an imaging device equipped with the above-mentioned solid-state imaging device 100, and corresponds to at least one of a view system for transportation equipment, a sensing system for ADAS (advanced driver assistance system), and a sensing system for autonomous driving, and the imaging device is mounted on at least one of the front, surround, side, rear, and room mirror of the transportation equipment.

[0497] (Other embodiments) Although the solid-state imaging device of the present disclosure and the imaging device using the same have been described based on the above embodiment, the solid-state imaging device of the present disclosure and the imaging device using the same are not limited to the above embodiment. The present invention also includes other embodiments realized by combining any of the components in the above embodiment, modified examples obtained by applying various modifications to the above embodiment that a person skilled in the art can think of without departing from the gist of the present disclosure, and various devices incorporating the solid-state imaging device of the present disclosure and the imaging device using the same. [Industrial Applicability]

[0498] The present disclosure is applicable to solid-state imaging devices and imaging devices. [Explanation of symbols]

[0499] 3. Pixel circuit 21 Negative feedback circuit C1, C4 First storage capacitance element C2, C3 Second storage capacitance element GC1, TGC First transistor GC, GC2 Second transistor FA 1st feedback amplifier FA2 Second Feedback Amplifier FD0 Charge storage section OF Overflow element PD Photodiode RS First reset transistor RS2 Second reset transistor SF Amplification Transistor TG transfer transistor < / s4>

Claims

1. A pixel circuit; a negative feedback circuit; The pixel circuit includes: A photodiode; A charge storage unit; a transfer transistor that transfers the signal charge generated in the photodiode to the charge accumulation section; an amplifying transistor that outputs a pixel signal corresponding to the signal charge of the charge storage unit; a first reset transistor that resets the charge storage unit; A first storage capacitance element; a first transistor that controls a connection between the charge storage unit and the first storage capacitance element; the negative feedback circuit negatively feeds back a feedback signal corresponding to a reset output of the amplifying transistor to the charge storage unit via the first reset transistor; The first transistor connects a connection point between the first reset transistor and the charge storage unit and the first storage capacitance element. Solid-state imaging device.

2. The gate voltages of the transfer transistor and the first transistor are set so as to enable the signal charge overflowing from the photodiode to be transferred to the first storage capacitor element during exposure. The solid-state imaging device according to claim 1 .

3. the first transistor is connected in series with the first reset transistor between the first reset transistor and the charge storage unit; The first storage capacitance element is connected to a connection point between the first reset transistor and the first transistor. The solid-state imaging device according to claim 1 .

4. Further, an overflow element is provided for transmitting the signal charge overflowing from the photodiode to the first storage capacitor element. The solid-state imaging device according to claim 1 .

5. A pixel circuit; a negative feedback circuit; The pixel circuit includes: A photodiode; A charge storage unit; a transfer transistor that transfers the signal charge generated in the photodiode to the charge accumulation section; an amplifying transistor that outputs a pixel signal corresponding to the signal charge of the charge storage unit; a first reset transistor that resets the charge storage unit; A first storage capacitance element; a first transistor that controls a connection between the charge storage unit and the first storage capacitance element; the negative feedback circuit negatively feeds back a feedback signal corresponding to a reset output of the amplifying transistor to the charge storage unit via the first reset transistor; the first transistor is connected in series with the first reset transistor between the first reset transistor and the charge storage unit; the first storage capacitance element is connected to a connection point between the first reset transistor and the first transistor; moreover, a second transistor inserted in series between the first transistor and the charge storage section; a second storage capacitance element connected to a connection point between the first transistor and the second transistor and connected to the charge storage section via the second transistor; Solid-state imaging device.

6. moreover, a second transistor inserted between a connection point between the first reset transistor and the first transistor and the charge storage unit; a second storage capacitance element connected to the connection point between the first reset transistor and the first transistor; The solid-state imaging device according to claim 1 .

7. The solid-state imaging device includes a plurality of the pixel circuits, A driving unit that drives a plurality of the pixel circuits to perform simultaneous exposure; a control circuit that reads out the pixel signals by scanning the plurality of pixel circuits. The solid-state imaging device according to claim 1 .

8. A pixel circuit; a negative feedback circuit; The pixel circuit includes: A photodiode; A charge storage unit; a transfer transistor that transfers the signal charge generated in the photodiode to the charge accumulation section; an amplifying transistor that outputs a pixel signal corresponding to the signal charge of the charge storage unit; a first reset transistor that resets the charge storage unit; A first storage capacitance element; a first transistor that controls a connection between the charge storage unit and the first storage capacitance element; the negative feedback circuit negatively feeds back a feedback signal corresponding to a reset output of the amplifying transistor to the charge storage unit via the first reset transistor; a control circuit that reads out, from the pixel circuit, a first pixel signal for constituting a first frame and a second pixel signal for constituting a second frame for an illuminance higher than that of the first frame; the first pixel signal corresponds to a signal charge transferred from the photodiode to the charge storage unit; the second pixel signal corresponds to a signal charge transferred from the photodiode to the charge storage unit and the first storage capacitor element and mixed therewith; The first pixel signal and the second pixel signal are based on signal charges generated in the photodiode of one pixel circuit during the same exposure period. Solid-state imaging device.

9. a control circuit that reads out, from the pixel circuit, a first pixel signal for constituting a first frame, a second pixel signal for constituting a second frame for an illuminance higher than that of the first frame, and a third pixel signal for constituting a third frame for an illuminance higher than that of the second frame; the first pixel signal corresponds to a signal charge transferred from the photodiode to the charge storage unit; the second pixel signal corresponds to a signal charge transferred from the photodiode to the charge storage unit and the first storage capacitor element and mixed therewith; the third pixel signal corresponds to a signal charge transferred from the photodiode to the charge storage unit, the first storage capacitance element, and the second storage capacitance element and mixed therewith; The first pixel signal, the second pixel signal, and the third pixel signal are based on signal charges generated in the photodiode of one pixel circuit during the same exposure period.

7. The solid-state imaging device according to claim 5.

10. a control circuit that reads out from the pixel circuit a first pixel signal constituting a first frame, a second pixel signal constituting a second frame for an illuminance higher than that of the first frame, and a third pixel signal constituting a third frame for an illuminance higher than that of the second frame; the first pixel signal corresponds to a signal charge transferred from the photodiode to the charge storage unit; the second pixel signal corresponds to a signal charge transferred from the photodiode to the charge storage unit and the first storage capacitor element and mixed therewith; the third pixel signal corresponds to a signal charge transferred from the photodiode to the charge storage unit, the first storage capacitance element, and the second storage capacitance element and mixed therewith; The first pixel signal, the second pixel signal, and the third pixel signal are based on signal charges generated in the photodiode of one pixel circuit during different exposure periods.

7. The solid-state imaging device according to claim 5.

11. A pixel circuit; a negative feedback circuit; The pixel circuit includes: A photodiode; A charge storage unit; a transfer transistor that transfers the signal charge generated in the photodiode to the charge accumulation section; an amplifying transistor that outputs a pixel signal corresponding to the signal charge of the charge storage unit; a first reset transistor that resets the charge storage unit; A first storage capacitance element; a first transistor that controls a connection between the charge storage unit and the first storage capacitance element; the negative feedback circuit negatively feeds back a feedback signal corresponding to a reset output of the amplifying transistor to the charge storage unit via the first reset transistor; A control signal input to at least the first reset transistor of the first transistor has a slope-shaped voltage waveform that gradually transitions the first reset transistor from an on state to an off state. Solid-state imaging device.

12. a measurement unit that measures a reset noise level of pixel circuits that belong to a predetermined region among the plurality of pixel circuits; A determination unit that determines the gradient of the sloping voltage waveform so as to reduce the variation in the reset noise level based on the measurement result. The solid-state imaging device according to claim 11.

13. the measurement unit measures the reset noise level for each row of pixel circuits belonging to the predetermined region while changing a slope of the voltage waveform; The determination unit determines an optimal slope of the voltage waveform based on the variation for each row of pixel circuits belonging to the predetermined region. The solid-state imaging device according to claim 12.

14. the negative feedback circuit is provided for each column of the pixel circuits arranged in a matrix, or for each pixel circuit; The negative feedback circuit includes a first feedback amplifier that outputs the feedback signal to a first reset transistor of the pixel circuit belonging to a corresponding column or to a first reset transistor RS of the corresponding pixel circuit.

12. The solid-state imaging device according to claim 1, wherein the first and second electrodes are arranged parallel to each other.

15. A pixel circuit, a negative feedback circuit; The pixel circuit includes: A photodiode; A charge storage unit; a transfer transistor that transfers the signal charge generated in the photodiode to the charge accumulation section; an amplifying transistor that outputs a pixel signal corresponding to the signal charge of the charge storage unit; a first reset transistor that resets the charge storage unit; A first storage capacitance element; a first transistor that controls a connection between the charge storage unit and the first storage capacitance element; the negative feedback circuit negatively feeds back a feedback signal corresponding to a reset output of the amplifying transistor to the charge storage unit via the first reset transistor; the negative feedback circuit is provided for each column of the pixel circuits arranged in a matrix, or for each pixel circuit; the negative feedback circuit includes a first feedback amplifier that outputs the feedback signal to a first reset transistor of the pixel circuit belonging to a corresponding column or to a first reset transistor RS of the corresponding pixel circuit; The negative feedback circuit is provided for each of the columns, the pixel circuit further includes a second reset transistor that resets the charge storage unit; The negative feedback circuit further includes a second feedback amplifier that outputs the feedback signal to a second reset transistor of the pixel circuit that belongs to a corresponding column. Solid-state imaging device.

16. the solid-state imaging device includes a first semiconductor chip and a second semiconductor chip bonded together; the first semiconductor chip includes the photodiode and a first storage capacitance element of each pixel circuit; The second semiconductor chip includes a first feedback amplifier corresponding to each column of the pixel circuits or corresponding to each of the pixel circuits. The solid-state imaging device according to claim 14.

17. the negative feedback circuit is provided for each of the pixel circuits, the solid-state imaging device includes a first semiconductor chip and a second semiconductor chip bonded together; the first semiconductor chip includes the photodiode of each pixel circuit; The second semiconductor chip includes a first feedback amplifier and a first storage capacitance element corresponding to each pixel circuit. The solid-state imaging device according to claim 14.

18. the solid-state imaging device includes a first semiconductor chip and a second semiconductor chip bonded together; the first semiconductor chip includes the photodiode and a charge storage unit of each pixel circuit, The second semiconductor chip includes a first storage capacitance element for each pixel circuit. The solid-state imaging device according to claim 14.

19. An imaging device comprising the solid-state imaging device according to claim 1 , The imaging device corresponds to at least one of a view system for transportation equipment, a sensing system for an advanced driver assistance system (ADAS), and a sensing system for autonomous driving; The imaging device is mounted on at least one of the front, surround, side, rear, and room mirrors of the transportation device. Imaging device.

Images