Semiconductor device and method for manufacturing the same

Abstract

Provided is a semiconductor device which has a MOS gate structure and comprises: a semiconductor substrate; a first interlayer insulating film that is provided above the upper surface of the semiconductor substrate and that has a first opening; and a second interlayer insulating film that is laminated on the first interlayer insulating film and that has a second opening overlapping the first opening in a top view. The width of the first opening in a first direction is different from the width of the second opening in the first direction at the height of the boundary between the first interlayer insulating film and the second interlayer insulating film.

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Conventionally, in a semiconductor device in which a MOS gate structure having a trench gate structure is formed at a desired interval on the surface of a semiconductor substrate, an upper electrode is formed, and a pattern and an electrode of a desired conductivity type are further formed on the back side, a configuration in which a contact part is formed on a mesa part is known. Known examples of the formation of the contact part include a configuration in which a contact region is formed by ion implantation on the mesa part (see, for example, Patent Document 1) and a configuration in which a contact metal layer is formed on the mesa part (see, for example, Patent Document 2). Patent Document 1: International Publication No. 2016-133027 Patent Document 2: JP 2007-35841 A

[0003] In forming the contact portion of the mesa portion, it is preferable to form a contact portion having a low resistance.

[0004] In order to solve the above problems, a first aspect of the present invention provides a semiconductor device having a MOS gate structure. The semiconductor device may include a semiconductor substrate. The semiconductor device may include a first interlayer insulating film. In any of the above semiconductor devices, the first interlayer insulating film may be provided above an upper surface of the semiconductor substrate. In any of the above semiconductor devices, the first interlayer insulating film may have a first opening. In any of the above semiconductor devices, the second interlayer insulating film may be stacked on the first interlayer insulating film. In any of the above semiconductor devices, the second interlayer insulating film may have a second opening overlapping the first opening in a top view. In any of the above semiconductor devices, the width of the first opening in the first direction and the width of the second opening in the first direction may be different at the boundary height between the first interlayer insulating film and the second interlayer insulating film.

[0005] In any of the semiconductor devices described above, at the boundary height, the width of the second opening in the first direction may be greater than the width of the first opening in the first direction.

[0006] In any of the above semiconductor devices, at least a portion of the upper surface of the first interlayer insulating film may not be covered with the second interlayer insulating film.

[0007] In any of the above semiconductor devices, the width of the second opening in the first direction at the boundary height may be smaller than the width of the first opening in the first direction.

[0008] Any of the above semiconductor devices may include a gate trench portion provided from an upper surface of the semiconductor substrate to an interior of the semiconductor substrate. In any of the above semiconductor devices, the gate trench portion may have a gate conductive portion provided within the semiconductor substrate. In any of the above semiconductor devices, the gate trench portion may have a gate insulating film that insulates the gate conductive portion from the semiconductor substrate. In any of the above semiconductor devices, the first interlayer insulating film may cover at least a portion of an upper surface of the gate conductive portion.

[0009] Any of the above semiconductor devices may include a plurality of gate trench portions. In any of the above semiconductor devices, the plurality of gate trench portions may be arranged in a first direction.

[0010] Any of the above semiconductor devices may include a mesa portion. In any of the above semiconductor devices, the mesa portion may be provided between a plurality of gate trench portions. In any of the above semiconductor devices, the thickness of the first interlayer insulating film may be equal to or smaller than the width of the mesa portion in the first direction.

[0011] Any of the above semiconductor devices may include a first plug metal. In any of the above semiconductor devices, at least a portion of the first plug metal may be provided in the first opening. Any of the above semiconductor devices may include a second plug metal. In any of the above semiconductor devices, at least a portion of the second plug metal may be provided in the second opening.

[0012] Any of the above semiconductor devices may include a barrier metal. In any of the above semiconductor devices, the barrier metal may be provided between the first plug metal and the second plug metal. In any of the above semiconductor devices, the barrier metal may include titanium.

[0013] In any of the above semiconductor devices, a sidewall of the first opening may be steeper than a sidewall of the second opening.

[0014] In any of the above semiconductor devices, the second interlayer insulating film may have a thickness greater than that of the first interlayer insulating film.

[0015] In any of the above semiconductor devices, the first openings may be arranged at intervals in the first direction different from the intervals in the second openings in the first direction.

[0016] Any of the above semiconductor devices may include a plurality of first openings. At least one of the first openings in any of the above semiconductor devices may be covered with a second interlayer insulating film.

[0017] In any one of the above semiconductor devices, the second openings may be provided discretely when viewed from above.

[0018] Any of the above semiconductor devices may further include a plug metal provided inside the semiconductor substrate below the first opening.

[0019] Any of the above semiconductor devices may include a plurality of gate trench portions provided from an upper surface of the semiconductor substrate to an interior of the semiconductor substrate. Any of the above semiconductor devices may include a mesa portion provided between two gate trench portions and extending in an extension direction on the upper surface of the semiconductor substrate. In any of the above semiconductor devices, the plug metal may have a first portion and a second portion provided alongside the first portion in the extension direction and having a width greater than that of the first portion. In any of the above semiconductor devices, at least a part of the first portion of the plug metal may be disposed at a position not overlapping with the second opening.

[0020] Any of the above semiconductor substrates may have a drift region of a first conductivity type. In any of the above semiconductor devices, the mesa portion may have an emitter region of the first conductivity type exposed on an upper surface of the semiconductor substrate. In any of the above semiconductor devices, the mesa portion may have a region of a second conductivity type exposed on an upper surface of the semiconductor substrate and arranged alternately with the emitter regions in the extension direction. In any of the above semiconductor devices, at least a part of the second portion of the plug metal may overlap with the region of the second conductivity type.

[0021] In a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device having a MOS gate structure. The method for manufacturing the semiconductor device may include a first interlayer insulating film forming step. In the first interlayer insulating film forming step, a first interlayer insulating film may be formed above a semiconductor substrate. The method for manufacturing the semiconductor device may include a first opening forming step. In the first opening forming step, a first opening may be formed in the first interlayer insulating film. The method for manufacturing the semiconductor device may include a contact part forming step. In the contact part forming step, a contact part may be formed through the first opening. The method for manufacturing the semiconductor device may include a second interlayer insulating film forming step. In the second interlayer insulating film forming step, a second interlayer insulating film may be formed to be stacked on the first interlayer insulating film. The method for manufacturing the semiconductor device may include a second opening forming step. In the second opening forming step, a second opening may be formed in the second interlayer insulating film. At the boundary height between the first interlayer insulating film and the second interlayer insulating film, the width of the first opening in the first direction and the width of the second opening in the first direction may be different.

[0022] The above summary of the invention does not list all of the features of the present invention. Also, subcombinations of these features may also be inventions. [Brief description of the drawings]

[0023] [Figure 1] FIG. 1 is a top view showing an example of a semiconductor device 100. [Diagram 2] FIG. 2 is a diagram showing a comparative example of region D in FIG. [Diagram 3] FIG. 3 is a diagram showing an example of the gg cross section in FIG. 2. [Figure 4] FIG. 3 is a diagram showing an example of a-a cross section in FIG. 2. [Diagram 5] FIG. 3 is a diagram showing an example of a bb cross section in FIG. 2. [Figure 6] FIG. 3 is a perspective view of a semiconductor substrate 10 of the semiconductor device 100 in FIG. [Figure 7] FIG. 3 is a diagram showing another example of the gg cross section in FIG. 2. [Figure 8] FIG. 3 is a diagram showing another example of the gg cross section in FIG. 2. [Figure 9] FIG. 2 is a diagram showing an example of an area D in FIG. [Figure 10] FIG. 10 is a diagram showing an example of the hh cross section in FIG. [Figure 11] 10 is a diagram showing another example of the hh cross section in FIG. 9. FIG. [Figure 12] 10 is a diagram showing another example of the hh cross section in FIG. 9. FIG. [Figure 13] 10 is a diagram showing another example of the hh cross section in FIG. 9. FIG. [Figure 14] 10 is a diagram showing another example of the hh cross section in FIG. 9. FIG. [Figure 15] 10 is a diagram showing another example of the hh cross section in FIG. 9. FIG. [Figure 16] 10 is a diagram showing another example of the hh cross section in FIG. 9. FIG. [Figure 17] 10 is a diagram showing another example of the hh cross section in FIG. 9. FIG. [Figure 18] FIG. 2 is a diagram showing another embodiment of the region D in FIG. [Figure 19] FIG. 19 is a diagram showing an example of a cross section ii in FIG. 18. [Figure 20] FIG. 20 is a perspective view of the semiconductor device 100 in FIG. [Figure 21] 19 is a diagram showing another example of the ii cross section in FIG. 18. FIG. [Figure 22] 19 is a diagram showing another example of the ii cross section in FIG. 18. FIG. [Diagram 23]FIG. 2 is a diagram showing another embodiment of the region D in FIG. [Figure 24] FIG. 24 is a diagram showing an example of the jj cross section in FIG. 23. [Diagram 25] 16 is a diagram illustrating an example of a flowchart of a method for manufacturing the semiconductor device 100 shown in FIG. [Figure 26] FIG. 13 is a diagram showing an example of a gate trench portion forming step S101. [Figure 27] FIG. 13 is a diagram showing an example of a first interlayer insulating film forming step S102. [Figure 28] FIG. 11 is a diagram showing an example of a first opening forming step S103. [Figure 29] 11A and 11B are diagrams illustrating an example of a first contact portion forming step S104. [Diagram 30] FIG. 13 is a diagram showing an example of a second interlayer insulating film forming step S105. [Diagram 31] FIG. 11 is a diagram showing an example of a second opening forming step S106. [Diagram 32] 13A and 13B are diagrams illustrating an example of a second contact portion forming step S107. [Diagram 33] FIG. 11 is a diagram showing an example of an emitter electrode forming step S108. [Diagram 34] 11 is a diagram showing in detail the semiconductor device 100 shown in FIG. [Diagram 35] FIG. 2 is a diagram showing another embodiment of the region D in FIG. [Diagram 36] FIG. 36 is a diagram showing an example of the kk cross section of FIG. 35. [Figure 37] FIG. 2 is a diagram showing another embodiment of the region D in FIG. [Figure 38] FIG. 2 is a diagram showing another embodiment of the region D in FIG. [Figure 39] FIG. 2 is a diagram showing another embodiment of the region D in FIG. [Diagram 40] 13 is a diagram showing another example of the structure of the first portion 54-1-1 of the contact hole 54-1 and the first portion 62-1-1 of the plug metal 62-1. FIG. [Diagram 41]13 is a diagram showing another example of the structure of the first portion 54-1-1 of the contact hole 54-1 and the first portion 62-1-1 of the plug metal 62-1. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0025] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0026] In this specification, technical matters may be explained using orthogonal coordinate axes of X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components, and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without indicating positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.

[0027] In this specification, the orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are the X-axis and the Y-axis. The axis perpendicular to the upper and lower surfaces of the semiconductor substrate is the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. In this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and the Y-axis, may be referred to as the horizontal direction.

[0028] The region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate may be referred to as the top surface side. Similarly, the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate may be referred to as the bottom surface side.

[0029] In this specification, when the term "same" or "equal" is used, it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0030] In this specification, the conductivity type of a doped region doped with impurities is described as P type or N type. In this specification, the impurity may particularly mean either an N type donor or a P type acceptor, and may be described as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to make it a semiconductor exhibiting an N type conductivity type or a semiconductor exhibiting a P type conductivity type.

[0031] In this specification, the doping concentration means the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration means the net concentration obtained by adding up the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, including the polarity of the charge. As an example, the donor concentration is N D , acceptor concentration N A Then, the net doping concentration at any position is N D -N A In this specification, the net doping concentration may be simply referred to as the doping concentration.

[0032] A donor has the function of supplying electrons to a semiconductor. An acceptor has the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, a VOH defect, which is a combination of a vacancy (V), oxygen (O), and hydrogen (H) present in a semiconductor, functions as a donor that supplies electrons. In this specification, a VOH defect may be referred to as a hydrogen donor.

[0033] In this specification, when P+ type or N+ type is described, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is described, it means that the doping concentration is lower than that of P type or N type. The unit system in this specification is the SI unit system unless otherwise specified. The unit of length may be expressed in cm, but various calculations may be performed after converting to meters (m).

[0034] In this specification, the chemical concentration refers to the atomic density of an impurity measured regardless of the state of electrical activation. The chemical concentration (atomic density) can be measured, for example, by secondary ion mass spectrometry (SIMS). The above-mentioned net doping concentration can be measured by voltage-capacitance measurement (CV). The carrier concentration measured by spreading resistance measurement (SR) may be the net doping concentration. The carrier concentration measured by CV or SR may be a value in a thermal equilibrium state. In addition, in an N-type region, since the donor concentration is sufficiently larger than the acceptor concentration, the carrier concentration in that region may be the donor concentration. Similarly, in a P-type region, the carrier concentration in that region may be the acceptor concentration. In this specification, the doping concentration in an N-type region may be referred to as the donor concentration, and the doping concentration in a P-type region may be referred to as the acceptor concentration.

[0035] In addition, when the concentration distribution of the donor, acceptor or net doping has a peak, the peak value may be taken as the concentration of the donor, acceptor or net doping in the region. In cases where the concentration of the donor, acceptor or net doping is almost uniform, the average value of the concentration of the donor, acceptor or net doping in the region may be taken as the concentration of the donor, acceptor or net doping. In this specification, the concentration per unit volume is expressed in atoms / cm. 3 , or / cm 3 This unit is used for donor or acceptor concentration or chemical concentration in a semiconductor substrate. The atom count notation may be omitted.

[0036] The carrier concentration measured by the SR method may be lower than the concentration of the donor or acceptor. In the range where the current flows when measuring the spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The reduction in carrier mobility occurs when the carriers are scattered due to a disorder in the crystal structure caused by lattice defects, etc.

[0037] The concentration of the donor or acceptor calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element indicating the donor or acceptor. As an example, the donor concentration of phosphorus or arsenic, which serves as a donor in a silicon semiconductor, or the acceptor concentration of boron, which serves as an acceptor, is about 99% of the chemical concentration. On the other hand, the donor concentration of hydrogen, which serves as a donor in a silicon semiconductor, is about 0.1% to 10% of the chemical concentration of hydrogen. Each concentration in this specification may be a value at room temperature. As an example of the value at room temperature, a value at 300 K (Kelvin) (about 26.9° C.) may be used.

[0038] Fig. 1 is a top view showing an example of a semiconductor device 100. Fig. 1 shows the positions of each component projected onto the top surface of a semiconductor substrate 10. Fig. 1 shows only some of the components of the semiconductor device 100, and some components are omitted.

[0039] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate made of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate, but the material of the semiconductor substrate 10 is not limited to silicon.

[0040] The semiconductor substrate 10 has a first end side 161 and a second end side 162 in a top view. When simply referred to as a top view in this specification, it means that the semiconductor substrate 10 is viewed from the top surface side. The semiconductor substrate 10 of this example has two pairs of first end sides 161 that face each other in a top view. The semiconductor substrate 10 of this example also has two pairs of second end sides 162 that face each other in a top view. In FIG. 1, the first end sides 161 are parallel to the X-axis direction. The second end sides 162 are parallel to the Y-axis direction. The Z-axis is perpendicular to the top surface of the semiconductor substrate 10. The first end sides 161 are perpendicular to the extension direction of the gate trench portion described later. The second end sides 162 are parallel to the extension direction of the gate trench portion described later.

[0041] An active portion 160 is provided on the semiconductor substrate 10. The active portion 160 is a region through which a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode is provided above the active portion 160, but is omitted in FIG.

[0042] In this example, the active section 160 is provided with a transistor section 70 including a transistor element such as an IGBT (Insulated Gate Bipolar Transistor). In another example, the transistor section 70 and a diode section including a diode element such as an FWD (Free Wheel Diode) may be alternately arranged along a predetermined direction on the upper surface of the semiconductor substrate 10. In this example, one transistor section 70 is provided, but multiple transistor sections 70 may be provided. A P+ type well region or a gate runner, which will be described later, may be provided between the multiple transistor sections 70.

[0043] The transistor section 70 has a P+ type collector region in a region in contact with the lower surface of the semiconductor substrate 10. Also, the transistor section 70 has MOS gate structures having an N+ type emitter region, a P- type base region, a gate conductive portion, and a gate insulating film periodically arranged on the upper surface side of the semiconductor substrate 10. In other words, the semiconductor device 100 of this example has a MOS gate structure.

[0044] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 164. The semiconductor device 100 may have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad may be disposed in the vicinity of a first end edge 161. The vicinity of the first end edge 161 refers to the region between the first end edge 161 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire.

[0045] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to a conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes a gate wiring 130 that connects the gate pad 164 and the gate trench portion. In FIG. 1, the gate wiring 130 is hatched with oblique lines.

[0046] The gate wiring 130 is disposed between the active portion 160 and the first end side 161 or the second end side 162 in a top view. The gate wiring 130 of this example surrounds the active portion 160 in a top view. The area surrounded by the gate wiring 130 in a top view may be the active portion 160. The gate wiring 130 is also connected to a gate pad 164. The gate wiring 130 is disposed above the semiconductor substrate 10. The gate wiring 130 may be a metal wiring containing aluminum or the like.

[0047] The peripheral well region 11 is provided so as to overlap with the gate wiring 130. That is, similar to the gate wiring 130, the peripheral well region 11 surrounds the active portion 160 in a top view. The peripheral well region 11 is also provided so as to extend by a predetermined width into an area where it does not overlap with the gate wiring 130. The peripheral well region 11 is a region of the second conductivity type. In this example, the peripheral well region 11 is of P+ type (see FIG. 2). The impurity concentration of the peripheral well region 11 is 5.0×10 17 atoms / cm 3 Above 5.0 x 10 19 atoms / cm3 The impurity concentration of the peripheral well region 11 may be 2.0×10 18 atoms / cm 3 Above 2.0×10 19 atoms / cm 3 It may be the following:

[0048] The semiconductor device 100 may also include a temperature sensor (not shown) that is a PN junction diode made of polysilicon or the like, and a current detector (not shown) that simulates the operation of the transistor section 70 provided in the active section 160. The temperature sensor may be connected to the anode pad and the cathode pad via wiring. When a temperature sensor is provided, it is preferably provided in the center of the semiconductor substrate 10 in the X-axis direction and the Y-axis direction.

[0049] In the present embodiment, the semiconductor device 100 includes an edge termination structure 90 between the active section 160 and the first edge 161 or the second edge 162 when viewed from above. The edge termination structure 90 in the present embodiment is disposed between the peripheral gate wiring 130 and the first edge 161 or the second edge 162. The edge termination structure 90 relieves electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 may include at least one of a guard ring, a field plate, and a resurf that are provided in an annular shape surrounding the active section 160. Furthermore, a p-type region may be provided on the entire sidewall of the semiconductor substrate 10 and connected to the collector region of the IGBT to form a reverse blocking IGBT.

[0050] Fig. 2 is a diagram showing a comparative example of region D in Fig. 1. Fig. 2 is an enlarged view of region D in Fig. 1. Region D is a region including a transistor portion 70 near a gate wiring 130. The semiconductor device 100 of this example includes a gate trench portion 40, a peripheral well region 11, an emitter region 12, and a base region 14 provided inside the upper surface side of a semiconductor substrate 10.

[0051] The semiconductor device 100 of this example includes an emitter electrode 52 and a gate wiring 130 provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the gate wiring 130 are provided separately from each other. An interlayer insulating film is provided between the emitter electrode 52 and the upper surface of the semiconductor substrate 10, and between the gate wiring 130 and the upper surface of the semiconductor substrate 10. The interlayer insulating film is omitted in FIG. 2.

[0052] The emitter electrode 52 is provided above the gate trench portion 40, the peripheral well region 11, the emitter region 12, and the base region 14. The emitter electrode 52 passes through a contact hole 54 and comes into contact with the emitter region 12 and the base region 14 on the upper surface of the semiconductor substrate 10. Note that FIG. 2 shows the shape of the contact hole 54 on the upper surface of the semiconductor substrate 10.

[0053] The gate wiring 130 is connected to the gate runner 46 through a contact hole 58 provided in the interlayer insulating film. The gate runner 46 is connected to the gate trench portion 40. That is, the gate wiring 130 is connected to the gate trench portion 40 through the gate runner 46. The gate runner 46 is connected to the gate conductive portion of the gate trench portion 40 through a contact hole 56 (see FIG. 4 and FIG. 5) provided in the interlayer insulating film. The contact hole 56 may be provided in a range where the gate conductive portion of the gate trench portion 40 and the gate runner 46 overlap. The gate wiring 130 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction. The gate runner 46 is formed of polysilicon, which is a conductive material. The gate runner 46 may be provided above the semiconductor substrate 10. The gate runner 46 is provided along the direction in which the gate wiring 130 extends (the X-axis direction in FIG. 2).

[0054] The emitter electrode 52 is made of a material containing a metal. For example, at least a portion of the emitter electrode 52 is made of a metal alloy such as aluminum or an aluminum-silicon alloy, for example, AlSi or AlSiCu.

[0055] The transistor section 70 has a plurality of gate trench portions 40 arranged in an arrangement direction. The arrangement direction in FIG. 2 is the X-axis direction. The arrangement direction is an example of a first direction. In this example, the gate trench portions 40 are provided in the active portion 160 and the peripheral well region 11 on the upper surface of the semiconductor substrate 10. The gate trench portions 40 are provided in a striped pattern in the transistor section 70 when viewed from above.

[0056] The gate trench portion 40 in this example may have two straight line portions 39 (portions of the trench that are straight along the extension direction) extending along an extension direction perpendicular to the arrangement direction, and a tip portion 41 connecting the two straight line portions 39. The extension direction in FIG. 2 is the Y-axis direction.

[0057] At least a part of the tip portion 41 is preferably curved in a top view. By connecting the ends of the two straight portions 39 in the Y-axis direction with each other by the tip portion 41, electric field concentration at the ends of the straight portions 39 can be alleviated.

[0058] A dummy trench portion may be provided between each straight portion 39 of the gate trench portion 40. The dummy trench portion may have a straight portion. The conductive portion of the dummy trench portion may be connected to the emitter electrode 52.

[0059] The diffusion depth of the peripheral well region 11 may be deeper than the depth of the gate trench portion 40. The end of the gate trench portion 40 in the Y-axis direction is provided in the peripheral well region 11 in top view. That is, at the end of the gate trench portion 40 in the Y-axis direction, the bottom of the gate trench portion 40 in the depth direction is covered by the peripheral well region 11. This makes it possible to alleviate electric field concentration at the bottom of the gate trench portion 40. The semiconductor device 100 may also include a gate trench portion 40 whose entirety is provided in the peripheral well region 11 in top view.

[0060] A mesa portion is provided between the gate trench portions 40 in the arrangement direction. The mesa portion refers to a region inside the semiconductor substrate 10 that is sandwiched between the trench portions. As an example, the upper end of the mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the trench portion. The mesa portion in this example is provided on the upper surface of the semiconductor substrate 10, extending in the extension direction (Y-axis direction) along the trench portion. In this example, the mesa portion 60 is provided in the transistor portion 70.

[0061] At least one of an emitter region 12 of a first conductivity type and a base region 14 of a second conductivity type may be provided in each mesa portion 60. In this example, the emitter region 12 is N+ type, and the base region 14 is P- type. The emitter region 12 may be provided between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction.

[0062] The mesa portion 60 of the transistor section 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 may be provided with a base region 14 exposed on the upper surface of the semiconductor substrate 10. In this example, the region of the mesa portion 60 that is exposed on the upper surface of the semiconductor substrate 10 and is disposed closest to the gate wiring 130 is the base region 14.

[0063] The base region 14 and the emitter region 12 in the mesa portion 60 are provided on the upper surface 21 of the semiconductor substrate 10 from one gate trench portion 40 to the other gate trench portion 40 in the arrangement direction. As an example, the base region 14 and the emitter region 12 in the mesa portion 60 are alternately arranged along the extension direction (Y-axis direction) of the trench portion. Note that a P+ type contact region may be provided instead of the base region 14 in a region sandwiched between the emitter regions 12 in the extension direction.

[0064] In another example, the base region 14 and the emitter region 12 of the mesa portion 60 may be provided in a stripe shape along the extension direction of the gate trench portion 40 on the upper surface 21 of the semiconductor substrate 10. For example, the emitter region 12 is provided in a region in contact with the gate trench portion 40, and the base region 14 is provided in a region sandwiched between the emitter regions 12 in the arrangement direction.

[0065] Fig. 3 is a diagram showing an example of the gg cross section in Fig. 2. The gg cross section is an XZ plane passing through the emitter region 12. Note that the dimensions in Fig. 3 do not necessarily match those in Fig. 2. In this cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24.

[0066] The interlayer insulating film 38 is provided on the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and other insulating films. The interlayer insulating film 38 is provided with the contact hole 54 described in FIG. 2.

[0067] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 is in contact with the upper surface 21 of the semiconductor substrate 10 via a plug metal 62 provided in a contact hole 54 of the interlayer insulating film 38. The emitter electrode 52 may be provided above the peripheral well region 11. A gate wiring 130 may be provided above the peripheral well region 11. In this example, a gate runner 46 is provided below the gate wiring 130.

[0068] A plug metal 62 is provided in the contact hole 54. The plug metal 62 electrically connects the semiconductor substrate 10 and the emitter electrode 52. By providing the plug metal 62, it is possible to reduce the contact resistance between the semiconductor substrate 10 and the emitter electrode 52. The plug metal 62 is formed of, for example, Ta, W, Mo, or the like. The plug metal 62 is an example of a contact portion.

[0069] Collector electrode 24 is provided on lower surface 23 of semiconductor substrate 10. Emitter electrode 52 and collector electrode 24 are formed of a metal material such as aluminum or nickel. A conductive material other than metal may also be used. In this specification, the direction connecting emitter electrode 52 and collector electrode 24 (Z-axis direction) is referred to as the depth direction or height direction.

[0070] The semiconductor substrate 10 has a drift region 18 of a first conductivity type. In this example, the drift region 18 is N-type.

[0071] In the mesa portion 60, an N+ type emitter region 12 and a P- type base region 14 are provided in this order from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. In addition, the mesa portion 60 may be provided with an N+ type accumulation region (not shown).

[0072] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10, and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The emitter region 12 has a higher doping concentration than the drift region 18.

[0073] The base region 14 is provided below the emitter region 12. In this example, the base region 14 is provided in contact with the emitter region 12. The base region 14 may be in contact with the trench portions on both sides of the mesa portion 60. The peak impurity concentration of the base region 14 is, for example, 2.5×10 17 atoms / cm 3 The impurity concentration of the base region 14 is 5.0×10 16 atoms / cm 3 Above and 1.0×10 18 atoms / cm 3 It may be the following:

[0074] An N+ type buffer region 20 may be provided under the drift region 18. The doping concentration of the buffer region 20 is higher than that of the drift region 18. The buffer region 20 may have a concentration peak with a higher doping concentration than the drift region 18. The doping concentration of the concentration peak refers to the doping concentration at the apex of the concentration peak. The doping concentration of the drift region 18 may be the average value of the doping concentration in a region where the doping concentration distribution is approximately flat.

[0075] The buffer region 20 may be formed by ion implantation of an N-type dopant such as hydrogen (protons) or phosphorus. In this example, the buffer region 20 is formed by ion implantation of hydrogen. The buffer region 20 may function as a field stop layer that prevents a depletion layer extending from the lower end of the base region 14 from reaching the P+ type collector region 22.

[0076] A P+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than the acceptor concentration of the base region 14. The collector region 22 may contain the same acceptor as the base region 14, or may contain a different acceptor. The acceptor of the collector region 22 is, for example, boron. The element serving as the acceptor is not limited to the above example.

[0077] The collector region 22 is exposed on the lower surface 23 of the semiconductor substrate 10, and is connected to a collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum or nickel.

[0078] One or more gate trench portions 40 are provided on the upper surface 21 side of the semiconductor substrate 10. In this example, a plurality of gate trench portions 40 are provided on the upper surface 21 side of the semiconductor substrate 10. The gate trench portions 40 are provided from the upper surface 21 of the semiconductor substrate 10 to the inside of the semiconductor substrate 10. The gate trench portions 40 reach the drift region 18 from the upper surface 21 of the semiconductor substrate 10 through the base region 14. In a region where at least one of the emitter region 12 and the base region 14 is provided, each gate trench portion 40 also penetrates these doping regions and reaches the drift region 18. The trench portion penetrating the doping region is not limited to a case where the trench portion is formed in the order of forming the doping region and then the trench portion. A case where the trench portion is formed and then the doping region is formed between the trench portions is also included in the case where the trench portion penetrates the doping region.

[0079] The gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate conductive portion 44 is formed of polysilicon, which is a conductive material. The gate conductive portion 44 may be formed of the same material as the gate runner 46. The gate conductive portion 44 is provided inside the semiconductor substrate 10. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. In FIG. 3, the gate conductive portion 44 is provided inside the gate insulating film 42 inside the gate trench. That is, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The thickness of the gate insulating film 42 may be 50 nm or more and 150 nm or less.

[0080] The gate conductive portion 44 in the gate trench portion 40 may be provided longer in the depth direction than the base region 14. The gate trench portion 40 in this cross section is covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring 130. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench portion 40.

[0081] The gate trench portion 40 of this example is covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottom of the gate trench portion 40 may have a downwardly convex curved shape (curved in cross section).

[0082] A protective film (not shown) may be provided on the upper surface of the emitter electrode 52. By providing the protective film on the upper surface of the emitter electrode 52, the electrode can be protected. The protective film may be provided by patterning. One example of the protective film is a polyimide film.

[0083] FIG. 4 is a diagram showing an example of the aa cross section in FIG. 2. The aa cross section is a YZ plane passing through the contact holes 54 and 56. The dimensions in FIG. 4 do not necessarily match those in FIG. 2. The semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in the cross section. In FIG. 4, the vicinity of the lower surface 23 of the semiconductor substrate 10 is omitted. In the cross section, the upper surface 21 of the semiconductor substrate 10 is connected to the emitter electrode 52 through the contact hole 54. Also, in the cross section, the gate runner 46 is connected to the gate conductive portion 44 of the gate trench portion 40 through the contact hole 56.

[0084] 5 is a diagram showing an example of the bb cross section in FIG. 2. The bb cross section is a YZ plane passing through the contact hole 56. The dimensions in FIG. 5 do not necessarily match those in FIG. 2. The semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in this cross section. In FIG. 5, the vicinity of the lower surface 23 of the semiconductor substrate 10 is omitted. In this cross section as well, the gate runner 46 is connected to the gate conductive portion 44 of the gate trench portion 40 via the contact hole 56.

[0085] Fig. 6 is a perspective view of the semiconductor substrate 10 of the semiconductor device 100 in Fig. 2. Fig. 6 shows the arrangement of the emitter regions 12 and the base regions 14 in the semiconductor substrate 10. Note that Fig. 6 omits the illustration of the vicinity of the lower surface 23 of the semiconductor substrate 10. As shown in Fig. 6, the base regions 14 and the emitter regions 12 are alternately arranged along the extension direction (Y-axis direction) of the gate trench portion 40. As also shown in Fig. 6, the base region 14 is provided below the emitter region 12.

[0086] Fig. 7 is a diagram showing another example of the gg cross section in Fig. 2. In the cross section of Fig. 7, the width D1 of the mesa portion 60 is narrower than that in the cross section of Fig. 3. The width D1 of the mesa portion 60 may be the distance between adjacent gate trench portions 40. Note that in Fig. 7, the vicinity of the lower surface 23 of the semiconductor substrate 10 is omitted.

[0087] In order to advance miniaturization of the semiconductor device 100, it is necessary to narrow not only the width of the gate conductive portion 44 of the gate trench portion 40 but also the width D1 of the mesa portion 60. However, narrowing the width D1 of the mesa portion 60 narrows the opening width D2 of the contact hole 54. In FIG. 7, the opening width D2 of the contact hole 54 is the width of the contact hole 54 on the upper surface 21 of the semiconductor substrate 10. When the opening width D2 of the contact hole is narrowed, it becomes difficult to form a uniform film of the plug metal 62, and a formation defect 72 may occur. The formation defect 72 may cause outgassing due to heating, for example, and may become the starting point of fracture due to stress, which may cause a characteristic defect of the semiconductor device 100.

[0088] Fig. 8 is a diagram showing another example of the gg cross section in Fig. 2. In the cross section of Fig. 8, the width D1 of the mesa portion 60 is narrower than that in the cross section of Fig. 3. Note that in Fig. 8, the vicinity of the lower surface 23 of the semiconductor substrate 10 is not shown.

[0089] When the width D1 of the mesa portion 60 is narrowed, the width of the region that can contact the emitter electrode 52 is narrowed. In order to obtain sufficient contact, it is preferable to match the opening pattern of the contact hole 54 with the pattern of the mesa portion 60 as much as possible. However, the interlayer insulating film 38 needs to be, for example, 1 μm or thicker in order to reliably cover the steps of the structure and ensure insulation and barrier properties. When the opening is formed in the thick interlayer insulating film 38 by etching, high alignment accuracy is required, and there may be a portion where the gate conductive portion 44 is exposed as shown in FIG. 8. In this case, the semiconductor device 100 will have poor characteristics. In addition, the contact hole 54 must be tapered in order to perform ion implantation and electrode formation after the formation of the contact hole 54, making it difficult to miniaturize the contact hole 54.

[0090] Furthermore, as the diameter of the semiconductor substrate 10 increases, the flatness of the surface of the semiconductor substrate 10 decreases, and the photolithography resolution varies within the surface of the semiconductor substrate 10. This makes it difficult to achieve reliable and uniform electrical contact between the mesa portion 60 and the contact portion, and makes it difficult to form a low-resistance contact portion.

[0091] Fig. 9 is a diagram showing an example of region D in Fig. 1. Fig. 9 is an enlarged view of region D in Fig. 1. The semiconductor device 100 in Fig. 9 differs from the semiconductor device 100 in Fig. 2 in the configuration of contact hole 54. Other configurations of the semiconductor device 100 in Fig. 9 may be the same as those of the semiconductor device 100 in Fig. 2. The semiconductor device 100 in Fig. 9 has contact hole 54-1 and contact hole 54-2.

[0092] FIG. 10 is a diagram showing an example of the hh cross section in FIG. 9. The hh cross section is an XZ plane passing through the emitter region 12. The dimensions in FIG. 10 do not necessarily match those in FIG. 9. In this cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24. The semiconductor device 100 in FIG. 10 differs from the semiconductor device 100 in FIG. 3 in the configurations of the contact hole 54 and the interlayer insulating film 38. Other configurations of the semiconductor device 100 in FIG. 10 may be the same as those of the semiconductor device 100 in FIG. 3.

[0093] In this example, the semiconductor device 100 includes an interlayer insulating film 38-1 and an interlayer insulating film 38-2. The interlayer insulating film 38-1 is provided above the upper surface 21 of the semiconductor substrate 10. In this example, the interlayer insulating film 38-1 is provided on the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38-2 is provided above the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38-1 covers at least a part of the upper surface 45 of the gate conductive portion 44. In the cross section, the interlayer insulating film 38-1 covers the entire upper surface 45 of the gate conductive portion 44. In this example, the interlayer insulating film 38-2 is stacked on the interlayer insulating film 38-1. In FIG. 10, the entire interlayer insulating film 38-2 is provided on the upper surface 43 of the interlayer insulating film 38-1. The interlayer insulating film 38-1 is an example of a first interlayer insulating film. The interlayer insulating film 38-2 is an example of a second interlayer insulating film.

[0094] The interlayer insulating film 38-1 has a contact hole 54-1. The contact hole 54-1 may be provided in the gate insulating film 42. The interlayer insulating film 38-2 has a contact hole 54-2. FIG. 9 shows the shape of the contact hole 54-1 on the upper surface of the semiconductor substrate 10 and the shape of the contact hole 54-2 at the boundary height between the interlayer insulating film 38-1 and the interlayer insulating film 38-2. As shown in FIG. 9, the contact hole 54-2 overlaps with the contact hole 54-1 in a top view. The contact hole 54-2 may overlap with the entire contact hole 54-1. The contact hole 54-1 is an example of a first opening, and the contact hole 54-2 is an example of a second opening.

[0095] At least a portion of the plug metal 62-1 is provided in the contact hole 54-1. In this example, the entire plug metal 62-1 is provided in the contact hole 54-1. The plug metal 62-1 is provided in the entire contact hole 54-1. The plug metal 62-1 may be formed of a high melting point metal material such as Ta, W, or Mo. The plug metal 62-1 is an example of a contact portion. By providing the plug metal 62-1, the contact resistance between the emitter electrode 52 and the mesa portion 60 can be reduced.

[0096] 10, at the boundary height between interlayer insulating film 38-1 and interlayer insulating film 38-2, width D3 of contact hole 54-1 and width D4 of contact hole 54-2 in the arrangement direction are different. That is, in top view, the pattern of contact hole 54-1 at the boundary height is different from the pattern of contact hole 54-2 at the boundary height. By making width D3 of contact hole 54-1 and width D4 of contact hole 54-2 different, the shape of the trench portion can be changed in response to miniaturization, and a low-resistance contact portion can be easily formed.

[0097] In this example, at the boundary height, the width D4 of the contact hole 54-2 in the arrangement direction is larger than the width D3 of the contact hole 54-1 in the arrangement direction. That is, in this example, at least a part of the upper surface 43 of the interlayer insulating film 38-1 is not covered by the interlayer insulating film 38-2. The width D4 of the contact hole 54-2 may be 1.1 times or more the width D3 of the contact hole 54-1. The width D4 of the contact hole 54-2 may be 1.2 times or more the width D3 of the contact hole 54-1. The width D4 of the contact hole 54-2 may be 1.5 times or more the width D3 of the contact hole 54-1. The width D4 of the contact hole 54-2 may be 3.0 times or less the width D3 of the contact hole 54-1. The width D4 of the contact hole 54-2 may be 2.0 times or less the width D3 of the contact hole 54-1. By making the width D4 of the contact hole 54-2 larger than the width D3 of the contact hole 54-1, it is possible to ensure contact between the contact portion (plug metal 62-1) and the emitter electrode 52. Therefore, a low-resistance contact portion can be easily formed.

[0098] The width D3 of the contact hole 54-1 at the boundary height may be 0.5 μm or more and 1.5 μm or less, and the width D4 of the contact hole 54-2 at the boundary height may be 0.6 μm or more and 2.0 μm or less.

[0099] The thickness H1 of the interlayer insulating film 38-1 may be equal to or less than the width D1 of the mesa portion 60 in the arrangement direction. By making the thickness H1 of the interlayer insulating film 38-1 equal to or less than the width D1 of the mesa portion 60 in the arrangement direction, the aspect ratio of the contact hole 54-1 can be reduced, and the alignment accuracy of the mesa portion 60 and the contact hole 54-1 can be improved. It is more preferable that the sum of the thickness H1 of the interlayer insulating film 38-1 and the thickness of the gate insulating film 42 is equal to or less than the width D1 of the mesa portion 60 in the arrangement direction.

[0100] The thickness H2 of the interlayer insulating film 38-2 may be larger than the thickness H1 of the interlayer insulating film 38-1. By making the thickness H2 of the interlayer insulating film 38-2 larger than the thickness H1 of the interlayer insulating film 38-1, the thickness of the interlayer insulating film 38-2 can be increased, and the insulation between the gate conductive portion 44 and the emitter electrode 52 can be ensured.

[0101] The thickness H1 of the interlayer insulating film 38-1 may be 0.1 μm or more. The thickness H1 of the interlayer insulating film 38-1 may be 0.2 μm or more. The thickness H1 of the interlayer insulating film 38-1 may be 0.3 μm or more. The thickness H1 of the interlayer insulating film 38-1 may be 0.8 μm or less. The thickness H1 of the interlayer insulating film 38-1 may be 0.5 μm or less. The thickness H2 of the interlayer insulating film 38-2 may be 0.5 μm or more. The thickness H2 of the interlayer insulating film 38-2 may be 1.0 μm or more. The width D1 of the mesa portion 60 may be 0.5 μm or more and 1.5 μm or less. The sum of the thickness H1 of the interlayer insulating film 38-1 and the thickness H2 of the interlayer insulating film 38-2 may be 1.0 μm or more and 2.0 μm or less.

[0102] The interlayer insulating film 38-1 is preferably processed with higher accuracy than the interlayer insulating film 38-2. By processing the interlayer insulating film 38-1 with higher accuracy than the interlayer insulating film 38-2, the contact resistance between the emitter electrode 52 and the mesa portion 60 can be reduced. In addition, the interlayer insulating film 38-2 is preferably more insulating than the interlayer insulating film 38-1. By having the insulating property of the interlayer insulating film 38-2 higher than that of the interlayer insulating film 38-1, the insulation property between the gate conductive portion 44 and the emitter electrode 52 can be ensured. As an example, the interlayer insulating film 38-1 is a HTO (High Temperature Oxidation) film, and the interlayer insulating film 38-2 is a BPSG (Boro Phospho Silicate Glass) film.

[0103] Fig. 11 is a diagram showing another example of the h-h cross section in Fig. 9. Fig. 11 differs from Fig. 10 in the configuration of the plug metal 62-1 and in the presence of a diffusion region 16. Other configurations in Fig. 11 may be the same as those in Fig. 10.

[0104] In this example, the plug metal 62-1 is provided inside the semiconductor substrate 10. The plug metal 62-1 may be provided inside a trench provided in the mesa portion 60 of the semiconductor substrate 10.

[0105] In this example, a diffusion region 16 is provided below the plug metal 62-1. The diffusion region 16 may be provided between the base region 14 and the plug metal 62-1. The diffusion region 16 may be provided so as not to contact the gate trench portion 40. The diffusion region 16 is, for example, a P+ type. When the semiconductor device 100 is turned off, a current flows from the lower surface 23 side toward the emitter region 12. hole can flow to the plug metal 62-1 through the diffusion region 16. hole This reduces the resistance of the path through which the current passes, thereby suppressing latch-up.

[0106] 12 is a diagram showing another example of the cross section taken along the line h-h in FIG. 9. FIG. 12 differs from FIG. 10 in that a barrier metal 50 is included. 12 The rest of the configuration may be the same as that in FIG.

[0107] A barrier metal 50 may be provided below the emitter electrode 52. In this example, the barrier metal 50 is provided between the emitter electrode 52 and the plug metal 62-1. Also in this example, the barrier metal 50 is provided between the emitter electrode 52 and the interlayer insulating film 38-2. The barrier metal 50 may be provided between the emitter electrode 52 and the interlayer insulating film 38-1. The barrier metal 50 may contain titanium. The barrier metal 50 may be made of titanium, a titanium compound, or the like. By providing the barrier metal 50, it is possible to prevent the metal elements contained in the emitter electrode 52 from diffusing into the interlayer insulating film 38 or the plug metal 62-1.

[0108] Fig. 13 is a diagram showing another example of the hh cross section in Fig. 9. Fig. 13 differs from Fig. 10 in the width D4 of the contact hole 54-2. Other configurations in Fig. 13 may be the same as those in Fig. 10.

[0109] In this example, at the boundary height, the width D4 of the contact hole 54-2 in the arrangement direction is smaller than the width D3 of the contact hole 54-1 in the arrangement direction. That is, in this example, the entire upper surface 43 of the interlayer insulating film 38-1 is covered with the interlayer insulating film 38-2. The width D4 of the contact hole 54-2 may be 0.9 times or less the width D3 of the contact hole 54-1. The width D4 of the contact hole 54-2 may be 0.8 times or less the width D3 of the contact hole 54-1. The width D4 of the contact hole 54-2 may be 0.5 times or more the width D3 of the contact hole 54-1. When the width D1 of the mesa portion 60 is large, even if the width D4 of the contact hole 54-2 is made smaller than the width D3 of the contact hole 54-1, it is possible for the contact portion (plug metal 62-1) and the emitter electrode 52 to be in reliable contact with each other. Therefore, the shape of the interlayer insulating film 38 can be flexibly changed.

[0110] Fig. 14 is a diagram showing another example of the cross section taken along line hh in Fig. 9. Fig. 14 differs from Fig. 10 in the shape of the interlayer insulating film 38-2. Other configurations in Fig. 14 may be the same as those in Fig. 10.

[0111] In this example, the sidewall 64-1 of the contact hole 54-1 is steeper than the sidewall 64-2 of the contact hole 54-2. Side wall 64-1 and the upper surface 21 of the semiconductor substrate 10 form an angle Side wall 64-2 and the upper surface 21 of the semiconductor substrate 10. Since the sidewall 64-1 of the contact hole 54-1 is steeper than the sidewall 64-2 of the contact hole 54-2, the contact portion (plug metal 62-1) and the emitter electrode 52 can be reliably contacted with each other while ensuring the insulation between the gate conductive portion 44 and the emitter electrode 52.

[0112] The inclination of the sidewall 64-1 of the contact hole 54-1 may be the inclination of the sidewall 64-1 of the contact hole 54-1 at the boundary height. In other words, the inclination of the sidewall 64-1 of the contact hole 54-1 may be the inclination of the sidewall 64-1 of the contact hole 54-1 at the upper end of the contact hole 54-1. The inclination of the sidewall 64-1 of the contact hole 54-1 may be the average inclination of the sidewall 64-1 of the contact hole 54-1 from the lower end to the upper end of the sidewall 64-1 of the contact hole 54-1. Furthermore, the inclination of the sidewall 64-1 of the contact hole 54-1 may be the inclination of the sidewall 64-1 at the center in the height direction. The inclination of the sidewall 64-2 of the contact hole 54-2 may be the inclination of the sidewall 64-2 of the contact hole 54-2 at the boundary height. In other words, the inclination of the sidewall 64-2 of the contact hole 54-2 may be the inclination of the sidewall 64-2 of the contact hole 54-2 at the bottom end of the contact hole 54-2. The inclination of the sidewall 64-2 of the contact hole 54-2 may be the average inclination of the sidewall 64-2 of the contact hole 54-2 from the bottom end to the top end of the sidewall 64-2 of the contact hole 54-2. Furthermore, the inclination of the sidewall 64-2 of the contact hole 54-2 may be the inclination of the sidewall 64-2 at the center in the height direction.

[0113] Fig. 15 is a diagram showing another example of the hh cross section in Fig. 9. Fig. 15 differs from Fig. 10 in that a plug metal 62-2 is included. Other configurations in Fig. 15 may be the same as those in Fig. 10.

[0114] At least a portion of the plug metal 62-2 is provided in the contact hole 54-2. In this example, the entire plug metal 62-2 is provided in the contact hole 54-2. In this example, the emitter electrode 52 is provided inside the contact hole 54-2 above the plug metal 62-2. The plug metal 62-2 may be provided above the plug metal 62-1. In this example, the plug metal 62-2 is provided on the upper surface of the plug metal 62-1. The plug metal 62-2 may be formed of a high melting point material such as Ta, W, or Mo, similar to the plug metal 62-1. The plug metal 62-2 is an example of a contact portion. By providing the plug metal 62-2, the contact resistance between the emitter electrode 52 and the mesa portion 60 can be reduced.

[0115] Instead of the plug metal 62-1, polysilicon may be provided in the contact hole 54-1. The polysilicon may be provided when the gate conductive portion 44 and the gate runner 46 are formed.

[0116] Fig. 16 is a diagram showing another example of the h-h cross section in Fig. 9. Fig. 16 differs from Fig. 15 in that a plug metal 62-1 is configured and a diffusion region 16 is provided. Specifically, the diffusion region 16 is provided at the bottom of a trench provided in a mesa portion 60 of a semiconductor substrate 10, and a plug metal 62-1 is provided inside the trench. Other configurations in Fig. 16 may be the same as those in Fig. 15. Descriptions of the same reference numerals will be omitted.

[0117] Fig. 17 is a diagram showing another example of the hh cross section in Fig. 9. Fig. 17 differs from Fig. 15 in that a barrier metal 50 is included. Other configurations in Fig. 17 may be the same as those in Fig. 15. Descriptions of the same reference numerals will be omitted.

[0118] A barrier metal 50 may be provided below the emitter electrode 52. In this example, the barrier metal 50 is provided between the plug metal 62-1 and the plug metal 62-2. Also in this example, the barrier metal 50 is provided between the emitter electrode 52 and the interlayer insulating film 38-2. The barrier metal 50 may be provided between the emitter electrode 52 and the interlayer insulating film 38-1.

[0119] Fig. 18 is a diagram showing another embodiment of region D in Fig. 1. The semiconductor device 100 in Fig. 18 differs from the semiconductor device 100 in Fig. 9 in the configuration of the contact hole 54. Other configurations of the semiconductor device 100 in Fig. 18 may be the same as those of the semiconductor device 100 in Fig. 9. Fig. 18 shows the shape of the contact hole 54-1 on the upper surface 21 of the semiconductor substrate 10 and the shape of the contact hole 54-2 at the boundary height between the interlayer insulating film 38-1 and the interlayer insulating film 38-2.

[0120] FIG. 19 is a diagram showing an example of a cross section ii in FIG. 18. The cross section ii is an XZ plane passing through the emitter region 12. The dimensions in FIG. 19 do not necessarily match those in FIG. 18. In this cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24. The semiconductor device 100 in FIG. 19 differs from the semiconductor device 100 in FIG. 15 in the configurations of the contact hole 54-2, the interlayer insulating film 38-2, and the plug metal 62-2. Other configurations of the semiconductor device 100 in FIG. 19 may be the same as those of the semiconductor device 100 in FIG. 15.

[0121] In this example, the interval at which the contact holes 54-1 are arranged in the arrangement direction is different from the interval at which the contact holes 54-2 are arranged in the arrangement direction. The interval at which the contact holes 54-1 are arranged is the width of one mesa portion 60. That is, the contact holes 54-1 and the plug metals 62-1 are provided in each mesa portion 60. The interval at which the contact holes 54-2 are arranged is the width of two mesa portions 60. That is, the mesa portions 60 with the contact holes 54-2 and the plug metals 62-2 provided thereon and the mesa portions 60 without the contact holes 54-2 and the plug metals 62-2 provided thereon are alternately arranged. The mesa portions 60 with the interlayer insulating film 38-2 provided thereon and the mesa portions 60 without the interlayer insulating film 38-2 provided thereon may be alternately arranged. At least one contact hole 54-1 may be covered with the interlayer insulating film 38-2. With this configuration, the width of the plug metal 62-2 in the arrangement direction can be increased, and the contact portion (plug metal 62-1) and the emitter electrode 52 can be reliably contacted with each other.

[0122] 18, the contact holes 54-2 are provided discretely in a top view. The contact holes 54-2 may be provided discretely in the arrangement direction. The contact holes 54-2 may be provided discretely in the extension direction. By providing the contact holes 54-2 discretely, each mesa portion 60 can be connected to the emitter electrode 52 even if the width of the plug metal 62-2 is increased.

[0123] FIG. 20 is a perspective view of the semiconductor device 100 in FIG. 18. FIG. 20 shows the arrangement of the interlayer insulating film 38-1 and the interlayer insulating film 38-2 in the semiconductor substrate 10. In FIG. 20, the vicinity of the lower surface 23 of the semiconductor substrate 10 is omitted. As also shown in FIG. 20, the contact holes 54-2 are provided discretely in a top view. In this example, the contact holes 54-2 and the plug metals 62-2 are provided discretely in both the X-axis direction and the Y-axis direction. In a certain XY cross section, a plurality of plug metals 62-1 are provided side by side in the X-axis direction. The plug metal 62-2 is provided above a part of the plurality of plug metals 62-1. The plug metal 62-2 is not provided above the other part of the plurality of plug metals 62-1, and the interlayer insulating film 38-2 is provided above the other part of the plurality of plug metals 62-1. More specifically, the plug metals 62-1 on which the plug metals 62-2 are provided and the plug metals 62-1 on which the plug metals 62-2 are not provided are alternately arranged in the X-axis direction. In the Y-axis direction, the plug metals 62-1 are continuously disposed, and the plug metals 62-2 are discretely disposed above the plug metals 62-1.

[0124] Fig. 21 is a diagram showing another example of the cross section ii in Fig. 18. Fig. 21 differs from Fig. 19 in the configuration of a plug metal 62-1 and in the presence of a diffusion region 16. Other configurations in Fig. 21 may be the same as those in Fig. 19. Descriptions of the same reference numerals will be omitted.

[0125] Fig. 22 is a diagram showing another example of the cross section ii in Fig. 18. Fig. 22 differs from Fig. 19 in that a barrier metal 50 is included. Other configurations in Fig. 22 may be the same as those in Fig. 19. Descriptions of the same reference numerals will be omitted.

[0126] Fig. 23 is a diagram showing another embodiment of region D in Fig. 1. The semiconductor device 100 in Fig. 23 differs from the semiconductor device 100 in Fig. 18 in the configuration of contact hole 54-1. Other configurations of the semiconductor device 100 in Fig. 23 may be the same as those of the semiconductor device 100 in Fig. 18. Fig. 23 shows the shape of contact hole 54-1 on the upper surface 21 of semiconductor substrate 10 and the shape of contact hole 54-2 at the boundary height between interlayer insulating film 38-1 and interlayer insulating film 38-2.

[0127] 23, the contact holes 54-1 are provided discretely in a top view. The contact holes 54-1 may be provided discretely in the arrangement direction. The contact holes 54-1 may be provided discretely in the extension direction. The contact holes 54-1 may be provided only in regions that overlap with the contact holes 54-2 in a top view. By arranging the contact holes 54-1 discretely, many side walls of the contact holes 54-1 are provided in the extension direction, and the contact area can be increased.

[0128] FIG. 24 is a diagram showing an example of the jj cross section in FIG. 23. The jj cross section is an XZ plane passing through the emitter region 12. The dimensions in FIG. 24 do not necessarily match those in FIG. 23. The semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in the cross section. The semiconductor device 100 in FIG. 24 differs from the semiconductor device 100 in FIG. 19 in the configurations of the contact hole 54-1, the interlayer insulating film 38-1, the plug metal 62-1, and the gate insulating film 42. The other configurations of the semiconductor device 100 in FIG. 24 may be the same as those of the semiconductor device 100 in FIG. 19.

[0129] The contact holes 54-1 are arranged at intervals equal to the width of two mesa portions 60. In other words, the mesa portions 60 with the contact holes 54-1 and the plug metal 62-1 provided thereon and the mesa portions 60 without the contact holes 54-1 and the plug metal 62-1 provided thereon are arranged alternately. RThe mesa portion 60 has a contact hole 54-1 and a plug metal 62-1 above it. May be provided .

[0130] Fig. 25 is a diagram illustrating an example of a flowchart of a method for manufacturing the semiconductor device 100 shown in Fig. 15. The method for manufacturing the semiconductor device 100 includes a gate trench portion forming step S101, a first interlayer insulating film forming step S102, a first opening forming step S103, a first contact portion forming step S104, a second interlayer insulating film forming step S105, a second opening forming step S106, a second contact portion forming step S107, and an emitter electrode forming step S108.

[0131] FIG. 26 is a diagram showing an example of the gate trench portion forming step S101. In the gate trench portion forming step S101, a gate trench portion 40 is formed on the upper surface 21 of the semiconductor substrate 10. In the gate trench portion forming step S101, a gate trench is first provided on the upper surface 21 of the semiconductor substrate 10. The gate trench may be formed by a known method such as etching. Then, a gate insulating film 42 and a gate conductive portion 44 are formed inside the gate trench. The gate insulating film 42 may be formed by oxidizing the semiconductor substrate 10 by a known method. The gate insulating film 42 may be provided above the mesa portion 60. The gate conductive portion 44 may be formed by forming a film of polysilicon or the like by a known method such as a CVD method.

[0132] 27 is a diagram showing an example of the first interlayer insulating film forming step S102. In the first interlayer insulating film forming step S102, an interlayer insulating film 38-1 is formed above the semiconductor substrate 10. The interlayer insulating film 38-1 is, for example, an HTO film. The interlayer insulating film 38-1 may be a BPSG film. The interlayer insulating film 38-1 may be formed by a known method.

[0133] 28 is a diagram showing an example of the first opening formation step S103. In the first opening formation step S103, a contact hole 54-1 is formed in the interlayer insulating film 38-1. In the first opening formation step S103, the contact hole 54-1 may be formed by etching the interlayer insulating film 38-1 and the gate insulating film 42 by a known method.

[0134] 29 is a diagram showing an example of the first contact portion forming step S104. In the first contact portion forming step S104, a plug metal 62-1 is formed through the contact hole 54-1. In the first contact portion forming step S104, the plug metal 62-1 is formed in at least a part of the contact hole 54-1. In this example, the plug metal 62-1 is formed in the entire contact hole 54-1. The plug metal 62-1 may be formed by depositing a high melting point metal material such as Ta, W, Mo, etc. by a known method such as sputtering.

[0135] FIG. 30 is a diagram showing an example of the second interlayer insulating film forming step S105. In the second interlayer insulating film forming step S105, an interlayer insulating film 38-2 is formed above the semiconductor substrate 10. In this example, the interlayer insulating film 38-2 is formed to be laminated on the interlayer insulating film 38-1 and the plug metal 62-1. The interlayer insulating film 38-2 is, for example, a BPSG film. The interlayer insulating film 38-2 may be an HTO film. The interlayer insulating film 38-2 may be formed by a known method. The interlayer insulating film 38-2 may have a lower heat-resistant temperature than the interlayer insulating film 38-1.

[0136] 31 is a diagram showing an example of the second opening formation step S106. In the second opening formation step S106, a contact hole 54-2 is formed in the interlayer insulating film 38-2. In the first opening formation step S106, the contact hole 54-1 may be formed by etching the interlayer insulating film 38-2 by a known method. The contact hole 54-2 is formed in the interlayer insulating film 38-2 such that the width D3 of the contact hole 54-1 and the width D4 of the contact hole 54-2 in the arrangement direction are different at the boundary height between the interlayer insulating films 38-1 and 38-2.

[0137] 32 is a diagram showing an example of the second contact portion forming step S107. In the second contact portion forming step S107, a plug metal 62-2 is formed in at least a part of the contact hole 54-2. The plug metal 62-2 may be formed by depositing a metal material such as Ta, W, Mo, etc. by a known method such as sputtering, similar to the plug metal 62-1. A barrier metal 50 may be provided between the plug metal 62-1 and the plug metal 62-2.

[0138] 33 is a diagram showing an example of emitter electrode formation step S108. In emitter electrode formation step S108, an emitter electrode 52 is formed above the semiconductor substrate 10. In this example, the emitter electrode 52 is formed above the interlayer insulating film 38-2 and the plug metal 62-2. The emitter electrode 52 may be provided inside a contact hole 54-2.

[0139] Fig. 34 is a detailed diagram of the semiconductor device 100 shown in Fig. 10. Fig. 34 shows one mesa portion 60 and two gate trench portions 40. Note that Fig. 34 omits the plug metal 62-1 and the emitter electrode 52.

[0140] In FIG. 34, the contact hole 54-1 is a region surrounded by a thick line. The contact hole 54-1 is sandwiched between the interlayer insulating films 38-1 in the arrangement direction. In this example, at least a portion of the contact hole 54-1 is sandwiched between the interlayer insulating films 38-1 in the arrangement direction. The contact hole 54-1 is also sandwiched between the gate insulating films 42 in the arrangement direction. In this example, at least a portion of the contact hole 54-1 is sandwiched between the gate insulating films 42 in the arrangement direction. In FIG. Contact Hole The contact hole 54-2 is a region surrounded by a thick dotted line. The contact hole 54-2 is sandwiched between the interlayer insulating film 38-2 in the arrangement direction. In this example, the entire contact hole 54-2 is sandwiched between the interlayer insulating film 38-2 in the arrangement direction.

[0141] FIG. 35 is a diagram showing another embodiment of the region D in FIG. 1. The semiconductor device 100 in FIG. 35 differs from the examples described in FIG. 1 to FIG. 34 in the structure of the contact hole 54-1 and the plug metal 62-1. The configuration other than the contact hole 54-1 and the plug metal 62-1 may be the same as the semiconductor device 100 in any of the embodiments described in FIG. 1 to FIG. 34. FIG. 35 shows the shape of the contact hole 54-1 and the shape of the plug metal 62-1 on the upper surface 21 of the semiconductor substrate 10, and the shape of the contact hole 54-2 at the boundary height between the interlayer insulating film 38-1 and the interlayer insulating film 38-2. As shown in FIG. 21 and the like, the plug metal 62-1 is provided inside the contact hole 54-1 and inside the semiconductor substrate 10 below the contact hole 54-1. The shape of the contact hole 54-1 and the shape of the plug metal 62-1 on the upper surface 21 may be the same.

[0142] As described with reference to FIG. 2 etc., the semiconductor device 100 has a plurality of mesa portions 60. In this example, each mesa portion 60 is provided between two gate trench portions 40. The mesa portion 60 extends in an extension direction (the Y-axis direction in FIG. 35) on the upper surface 21 of the semiconductor substrate 10. That is, the Y-axis direction is the longitudinal direction of the mesa portion 60.

[0143] The contact hole 54-1 has a first portion 54-1-1 and a second portion 54-1-2. The first portion 54-1-1 and the second portion 54-1-2 are arranged side by side in the Y-axis direction. In the example of FIG. 35, the first portion 54-1-1 and the second portion 54-1-2 are arranged alternately along the Y-axis direction.

[0144] The plug metal 62-1 has a first portion 62-1-1 and a second portion 62-1-2. The first portion 62-1-1 and the second portion 62-1-2 are arranged side by side in the Y-axis direction. In the example of FIG. 35, the first portion 62-1-1 and the second portion 62-1-2 are arranged alternately along the Y-axis direction.

[0145] The width of the first portion 54-1-1 of the contact hole 54-1 in the X-axis direction and the width of the first portion 62-1-1 of the plug metal 62-1 are defined as W1. The width of the second portion 54-1-2 of the contact hole 54-1 in the X-axis direction and the width of the second portion 62-1-2 of the plug metal 62-1 are defined as W2. The width W2 is greater than the width W1. The width W2 may be 30% or more and 60% or less of the width Wm of the mesa portion 60 in the X-axis direction. The width W1 may be 10% or more and 40% or less of the mesa portion 60 in the X-axis direction. The widths W1, W2, and Wm may be widths at the upper surface 21 of the semiconductor substrate 10.

[0146] At least a part of the first portion 62-1-1 of the plug metal 62-1 may be disposed at a position that does not overlap with the contact hole 54-2. The entire first portion 62-1-1 may be disposed so as not to overlap with the contact hole 54-2. In this example, the second portion 62-1-2 of the plug metal is provided in the range that overlaps with the contact hole 54-2. In this example, the range in the Y-axis direction where the second portion 62-1-2 of the plug metal is provided coincides with the range in the Y-axis direction where the second portion 54-1-2 of the contact hole 54-1 is provided. Providing the second portion 62-1-2 with a larger width makes it easier to pull out the hole.

[0147] FIG. 36 is a diagram showing an example of the kk cross section of FIG. 35. The kk cross section is an XZ plane passing through the emitter region 12. The dimensions of FIG. 36 do not necessarily match those of FIG. 35. As described in FIG. 35, the width of the second portion 62-1-2 of the plug metal 62-1 in the X-axis direction is larger than the width of the first portion 62-1-1 in the X-axis direction. This can reduce the resistance between the plug metal 62-1 and the plug metal 62-2, and can efficiently extract holes. In addition, by reducing the width of the first portion 62-1-1 that is not connected to the plug metal 62-2, the distance between the first portion 62-1-1 and the gate trench portion 40 can be maintained, and the influence of the plug metal 62-1 on the channel can be reduced.

[0148] The first portion 54-1-1 and the second portion 54-1-2 of the contact hole 54-1 may be formed in a common process by patterning a photomask. The first portion 62-1-1 and the second portion 62-1-2 of the plug metal 62-1 may be formed in a common process. The contact hole 54-1 and the plug metal 62-1 may have the same shape. The first portion 54-1-1 and the first portion 62-1-1 may have the same shape. The second portion 54-1-2 and the second portion 62-1-2 may have the same shape.

[0149] The lengths in the Z-axis direction of the first portion 62-1-1 and the second portion 62-1-2 of the plug metal 62-1 may be the same or different. As an example, the second portion 62-1-2 of the plug metal 62-1 may be longer than the first portion 62-1-1. Similarly, the depths in the Z-axis direction of the first portion 54-1-1 and the second portion 54-1-2 of the contact hole 54-1 may be the same or different. As an example, the second portion 54-1-2 of the contact hole 54-2 may be formed deeper than the first portion 54-1-1. By lengthening the second portion 62-1-2 of the plug metal 62-1, the contact area between the second portion 62-1-2 and the semiconductor substrate 10 can be increased, and the contact resistance between the second portion 62-1-2 and the semiconductor substrate 10 can be reduced. This further improves the hole extraction efficiency.

[0150] 37 is a diagram showing another embodiment of the region D in FIG. 1. In the semiconductor device 100 in FIG. 37, the structures of the contact hole 54-1 and the plug metal 62-1 are different from those of the examples described in FIG. 1 to FIG. 36. The configuration other than the contact hole 54-1 and the plug metal 62-1 may be the same as that of the semiconductor device 100 in any of the aspects described in FIG. 1 to FIG. 37 shows the shape of the contact hole 54-1 and the shape of the plug metal 62-1 on the upper surface 21 of the semiconductor substrate 10, and the shape of the contact hole 54-2 at the boundary height between the interlayer insulating film 38-1 and the interlayer insulating film 38-2.

[0151] The contact hole 54-1 of this example has a first portion 54-1-1 and a second portion 54-1-2, similar to the example of FIG. 35. The plug metal 62-1 of this example has a first portion 62-1-1 and a second portion 62-1-2, similar to the example of FIG. 35. However, the arrangement of each portion in the Y-axis direction differs from that of the example of FIG. 35. The other structures may be similar to the example described in FIG. 35.

[0152] Each mesa portion 60 has an emitter region 12 and a P-type region exposed on the upper surface 21 of the semiconductor substrate 10. The emitter regions 12 and the P-type regions are alternately arranged in the Y-axis direction. In the example of FIG. 37, the base region 14 corresponds to the P-type region.

[0153] At least a part of the second portion 54-1-2 of the contact hole 54-1 is disposed so as to overlap with the base region 14. In the example of FIG. 37, the entire second portion 54-1-2 is disposed so as to overlap with the base region 14. At least a part of the first portion 54-1-1 of the contact hole 54-1 is disposed so as to overlap with the emitter region 12. In the example of FIG. 37, the first portion 54-1-1 is provided over the entire emitter region 12 in the Y-axis direction. The first portion 54-1-1 may also be provided in a part of the base region 14.

[0154] The arrangement of the first portion 62-1-1 of the plug metal 62-1 is similar to the arrangement of the first portion 54-1-1 of the contact hole 54-1, and the arrangement of the second portion 62-1-2 is similar to the arrangement of the second portion 54-1-2. According to this example, the second portion 54-1-2 and the second portion 62-1-2 having a larger width are arranged so as not to overlap with the emitter region 12. Therefore, the distance between the second portion 54-1-2 and the second portion 62-1-2 and the channel formed below the emitter region 12 can be secured, and the influence of the second portion 54-1-2 and the second portion 62-1-2 on the channel can be reduced. The second portion 54-1-2 and the second portion 62-1-2 may be provided away from the emitter region 12 in the Y-axis direction.

[0155] The second portion 54-1-2 and the second portion 62-1-2 may be provided in all the base regions 14 on the upper surface of the mesa portion 60, or may be provided in some of the base regions 14. In the example of FIG. 37, the second portion 54-1-2 and the second portion 62-1-2 are provided only in some of the base regions 14 among the multiple base regions 14 arranged along the Y-axis direction. The second portion 54-1-2 and the second portion 62-1-2 may be arranged at equal intervals in the Y-axis direction, or may be arranged at unequal intervals. With such an arrangement, the number of the second portions 54-1-2 and the second portions 62-1-2 can be reduced, thereby reducing the influence of the second portions 54-1-2 and the second portions 62-1-2 on the channel. In two mesa portions 60 adjacent to each other in the X-axis direction, the positions in the Y-axis direction at which the second portions 54-1-2 and the second portions 62-1-2 are provided may be different. This allows the second portions 54-1-2 and 62-1-2 to be arranged more evenly within the XY plane, and the hole extraction efficiency within the XY plane can be made uniform.

[0156] Fig. 38 is a diagram showing another embodiment of region D in Fig. 1. In the semiconductor device 100 in Fig. 38, the structures of contact hole 54-1 and plug metal 62-1 are different from those of the examples described in Fig. 1 to Fig. 37. In the example shown in Fig. 38, the shapes of contact hole 54-1 and plug metal 62-1 in the example shown in Fig. 37 are changed.

[0157] The second portion 54-1-2 of the contact hole 54-1 and the second portion 62-1-2 of the plug metal 62-1 in this example have an N-sided shape on the upper surface 21 of the semiconductor substrate 10. Here, N is an integer of 5 or more. The second portion 54-1-2 and the second portion 62-1-2 shown in FIG. 37 and the like have a rectangular shape. In contrast, the second portion 54-1-2 and the second portion 62-1-2 in this example have a shape with the corners of a rectangle chamfered. By having such a shape, it is easy to ensure the distance between the second portion 54-1-2 and the second portion 62-1-2 and the channel. As described above, a channel is formed in the surface layer of the base region 14 that contacts the gate trench portion 40 below the emitter region 12.

[0158] Fig. 39 is a diagram showing another embodiment of the region D in Fig. 1. In the semiconductor device 100 in Fig. 39, the structures of the contact hole 54-1 and the plug metal 62-1 are different from those in the examples described in Fig. 1 to Fig. 38. In the example shown in Fig. 39, the shapes of the contact hole 54-1 and the plug metal 62-1 in the example shown in Fig. 37 are changed.

[0159] The second portion 54-1-2 of the contact hole 54-1 and the second portion 62-1-2 of the plug metal 62-1 in this example have a curved outer shape on the upper surface 21 of the semiconductor substrate 10. The second portion 54-1-2 and the second portion 62-1-2 shown in FIG. 37 and the like have a rectangular shape. In contrast, the second portion 54-1-2 and the second portion 62-1-2 in this example may have a shape with rounded corners of a rectangle. The shape of the second portion 54-1-2 and the second portion 62-1-2 may include a part of a circle, a part of an oval, a part of an ellipse, or may have other curves. By having such a shape, it is easy to ensure the distance between the second portion 54-1-2 and the second portion 62-1-2 and the channel.

[0160] FIG. 40 is a diagram showing another structural example of the first portion 54-1-1 of the contact hole 54-1 and the first portion 62-1-1 of the plug metal 62-1. Although FIG. 40 shows one mesa portion 60, the other mesa portions 60 may have a similar structure. In the examples of FIG. 35 to FIG. 39, the shapes of the multiple first portions 54-1-1 provided in one mesa portion 60 are the same as each other, and the shapes of the multiple first portions 62-1-1 are the same as each other. In this example, multiple first portions 54-1-1 with different shapes are provided in one mesa portion 60, and multiple first portions 62-1-1 with different shapes are provided.

[0161] Among the multiple first parts 54-1-1 provided in one mesa section 60, the one arranged at the center in the extension direction (Y-axis direction) of the mesa section 60 is referred to as the first part 54-1-1c. Similarly, among the multiple first parts 62-1-1 provided in one mesa section 60, the one arranged at the center in the extension direction (Y-axis direction) of the mesa section 60 is referred to as the first part 62-1-1c. The width W3 of the first part 54-1-1c may be larger than the width W1 of the first part 54-1-1 arranged at the end in the Y-axis direction. Similarly, the width W3 of the first part 62-1-1c may be larger than the width W1 of the first part 62-1-1 arranged at the end in the Y-axis direction. This makes it easier to extract holes near the center of the mesa section 60 where holes tend to concentrate.

[0162] In this example, the widths of the first portion 54-1-1 and the first portion 62-1-1 are made different between the center and the ends of the mesa portion 60. In another example, the widths of the second portion 54-1-2 and the second portion 62-1-2 in the center of the mesa portion 60 may be made larger than the widths of the second portion 54-1-2 and the second portion 62-1-2 at the ends of the mesa portion 60.

[0163] Fig. 41 is a diagram showing another structural example of the first portion 54-1-1 of the contact hole 54-1 and the first portion 62-1-1 of the plug metal 62-1. Fig. 41 shows a plurality of mesas 60 arranged in the X-axis direction. Of the plurality of mesas 60, the one arranged in the center in the X-axis direction is referred to as mesa portion 60c.

[0164] 35 to 40, the first portions 54-1-1 provided in the mesas 60 have the same shape, and the first portions 62-1-1 have the same shape. In this example, the first portions 54-1-1 with different shapes are provided in different mesas 60, and the first portions 62-1-1 with different shapes are provided.

[0165] A width W5 of the first portion 54-1-1c in the mesa portion 60c may be larger than a width W4 of the first portion 54-1-1 of the mesa portion 60 arranged at the endmost position in the X-axis direction. Similarly, a width W5 of the first portion 62-1-1c in the mesa portion 60c may be larger than a width W4 of the first portion 62-1-1 of the mesa portion 60 arranged at the endmost position in the X-axis direction. This makes it easier to extract holes near the center of the semiconductor substrate 10 where holes tend to concentrate.

[0166] In this example, the widths of the first portion 54-1-1 and the first portion 62-1-1 are made different between different mesa portions 60. In another example, the widths of the second portion 54-1-2 and the second portion 62-1-2 of the mesa portion 60c may be made larger than the widths of the second portion 54-1-2 and the second portion 62-1-2 at the end of the mesa portion 60 arranged at the end in the X-axis direction. In addition, the interval in the Y-axis direction at which the second portion 54-1-2 and the second portion 62-1-2 are provided may be made different between different mesa portions 60. The interval in the Y-axis direction at which the second portion 54-1-2 and the second portion 62-1-2 are provided in the mesa portion 60c may be smaller than the interval in the Y-axis direction at which the second portion 54-1-2 and the second portion 62-1-2 are provided in the mesa portion 60 arranged at the end in the X-axis direction. This arrangement also makes it easier to extract holes near the center of the semiconductor substrate 10 where holes tend to be concentrated.

[0167] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included in the technical scope of the present invention.

[0168] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically indicated as "before," "prior to," etc., and may be realized in any order unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is explained using "first," "next," etc. for convenience, it does not mean that it is essential to perform the process in this order. [Explanation of symbols]

[0169] 10 semiconductor substrate, 11 peripheral well region, 12 emitter region, 14 base region, 16 diffusion region, 18 drift region, 20 buffer region, 21 upper surface, 22 collector region, 23 lower surface, 24 collector electrode, 38 interlayer insulating film, 39 straight portion, 40 gate trench portion, 41 tip portion, 42 gate insulating film, 43 upper surface, 44 gate conductive portion, 45 upper surface, 46 gate runner, 50 barrier metal, 52 emitter a gate electrode, 54 contact hole, 54-1-1 first portion, 54-1-2 second portion, 56 contact hole, 58 contact hole, 60 mesa portion, 62 plug metal, 62-1-1 first portion, 62-1-2 second portion, 64 sidewall, 70 transistor portion, 72 formation defect, 90 edge termination structure portion, 100 semiconductor device, 130 gate wiring, 160 active portion, 161 first edge, 162 second edge, 164 gate pad

Claims

1. A semiconductor device having a MOS gate structure, A semiconductor substrate; a first interlayer insulating film provided above an upper surface of the semiconductor substrate and having a first opening; a second interlayer insulating film laminated on the first interlayer insulating film and having a second opening overlapping the first opening in a top view; a first plug metal, at least a portion of which is provided in the first opening; a second plug metal, at least a portion of which is provided in the second opening; a barrier metal including titanium provided between the first plug metal and the second plug metal; Equipped with The semiconductor device, wherein the width of the first opening in a first direction is different from the width of the second opening in the first direction at a boundary height between the first interlayer insulating film and the second interlayer insulating film.

2. A semiconductor device having a MOS gate structure, A semiconductor substrate; a first interlayer insulating film provided above an upper surface of the semiconductor substrate and having a first opening; a second interlayer insulating film laminated on the first interlayer insulating film and having a second opening overlapping the first opening in a top view; Equipped with a width of the first opening in a first direction and a width of the second opening in the first direction are different at a boundary height between the first interlayer insulating film and the second interlayer insulating film; an interval at which the first openings are arranged in the first direction and an interval at which the second openings are arranged in the first direction are different from each other; A plurality of the first openings are provided, At least one of the first openings is covered with the second interlayer insulating film. Semiconductor device.

3. A semiconductor device having a MOS gate structure, A semiconductor substrate; a first interlayer insulating film provided above an upper surface of the semiconductor substrate and having a first opening; a second interlayer insulating film laminated on the first interlayer insulating film and having a second opening overlapping the first opening in a top view; a plug metal provided inside the semiconductor substrate below the first opening; a plurality of gate trench portions provided from the upper surface of the semiconductor substrate to an inside of the semiconductor substrate; a mesa portion provided between the two gate trench portions and extending in an extension direction of the upper surface of the semiconductor substrate; Equipped with a width of the first opening in a first direction and a width of the second opening in the first direction are different at a boundary height between the first interlayer insulating film and the second interlayer insulating film; The plug metal has a first portion and a second portion that is provided alongside the first portion in the extension direction and has a width larger than that of the first portion, At least a part of the first portion of the plug metal is disposed at a position not overlapping with the second opening. Semiconductor device.

4. A semiconductor device having a MOS gate structure, A semiconductor substrate; a first interlayer insulating film provided above an upper surface of the semiconductor substrate and having a first opening; a second interlayer insulating film laminated on the first interlayer insulating film and having a second opening overlapping the first opening in a top view; a plug metal, at least a portion of which is provided in the first opening and not provided in the second opening; Equipped with a width of the first opening in a first direction and a width of the second opening in the first direction are different at a boundary height between the first interlayer insulating film and the second interlayer insulating film; Only one of the first openings overlaps with one of the second openings. Semiconductor device.

5. A semiconductor device having a MOS gate structure, A semiconductor substrate; a first interlayer insulating film provided above an upper surface of the semiconductor substrate and having a first opening; a second interlayer insulating film laminated on the first interlayer insulating film and having a second opening overlapping the first opening in a top view; a plug metal, at least a portion of which is provided in the first opening and not provided in the second opening; Equipped with a width of the first opening in a first direction and a width of the second opening in the first direction are different at a boundary height between the first interlayer insulating film and the second interlayer insulating film; The width of the upper end of the second interlayer insulating film is smaller than the width of the second interlayer insulating film at the boundary height. Semiconductor device.

6. A semiconductor device having a MOS gate structure, A semiconductor substrate; a first interlayer insulating film provided above an upper surface of the semiconductor substrate and having a first opening; a second interlayer insulating film laminated on the first interlayer insulating film and having a second opening overlapping the first opening in a top view; Equipped with At a boundary height between the first interlayer insulating film and the second interlayer insulating film, a width of the second opening in a first direction is larger than a width of the first opening in the first direction; The sidewall of the second opening is steeper than the sidewall of the first opening. Semiconductor device.

7. A semiconductor device having a MOS gate structure, A semiconductor substrate; a first interlayer insulating film provided above an upper surface of the semiconductor substrate and having a first opening; a second interlayer insulating film laminated on the first interlayer insulating film and having a second opening overlapping the first opening in a top view; Equipped with At a boundary height between the first interlayer insulating film and the second interlayer insulating film, a width of the second opening in a first direction is smaller than a width of the first opening in the first direction; The second interlayer insulating film is not in contact with the upper surface of the semiconductor substrate. Semiconductor device.

8. At least a portion of the upper surface of the first interlayer insulating film is not covered with the second interlayer insulating film. The semiconductor device according to claim 6.

9. A gate trench portion is provided from the upper surface of the semiconductor substrate to an inside of the semiconductor substrate, The gate trench portion is a gate conductive portion provided inside the semiconductor substrate; a gate insulating film insulating the gate conductive portion from the semiconductor substrate; having The first interlayer insulating film covers at least a part of an upper surface of the gate conductive portion.

9. The semiconductor device according to claim 1, 2, or 4 to 8.

10. A plurality of the gate trench portions are provided, The gate trench portions are arranged in the first direction. The semiconductor device according to claim 9.

11. Further comprising a mesa portion provided between the plurality of gate trench portions, The thickness of the first interlayer insulating film is equal to or smaller than the width of the mesa portion in the first direction. The semiconductor device according to claim 10.

12. The sidewall of the first opening is steeper than the sidewall of the second opening. The semiconductor device according to claim 1 .

13. The second interlayer insulating film has a thickness greater than that of the first interlayer insulating film. The semiconductor device according to claim 1 .

14. The second openings are provided discretely when viewed from above. The semiconductor device according to claim 2 .

15. the semiconductor substrate has a drift region of a first conductivity type; The mesa portion is an emitter region of a first conductivity type exposed on the top surface of the semiconductor substrate; a second conductivity type region exposed on the upper surface of the semiconductor substrate and arranged alternately with the emitter region in the extension direction; having At least a portion of the second portion of the plug metal overlaps the second conductivity type region. The semiconductor device according to claim 3 .

16. A method for manufacturing a semiconductor device having a MOS gate structure, comprising the steps of: forming a first interlayer insulating film above a semiconductor substrate; forming a first opening in the first interlayer insulating film; forming a contact portion through the first opening; forming a second interlayer insulating film on the first interlayer insulating film after the contact portion forming step; forming a second opening in the second interlayer insulating film; Equipped with At a boundary height between the first interlayer insulating film and the second interlayer insulating film, a width of the first opening in a first direction and a width of the second opening in the first direction are different. A method for manufacturing a semiconductor device.

Images