Improved filled confined cell PCM device

Abstract

A method for fabricating a phase change memory device includes providing a substrate including a plurality of bottom electrodes; patterning the substrate to form a plurality of pores in the substrate extending from a surface of the substrate to the bottom electrodes; depositing a phase change material over the substrate; implanting the phase change material with at least one of Ge, Sb, and Te to amorphize at least a portion of the phase change material within the pores; planarizing the device to expose a surface of the substrate; and forming a plurality of top electrodes over the pores in contact with the phase change material.

Description

[Technical field]

[0001] The present invention relates to semiconductor devices, and more particularly to a method for improved fill-inconfined cell phase change memory (PCM) devices. [Background technology]

[0002] Chemical vapor deposition (CVD) / atomic layer deposition (ALD) Ge2Sb2Te5 alloy (GST)-based packed confined cell devices are being explored for neuromorphic computing, particularly as synaptic elements, to achieve faster and more energy-efficient vector-matrix multiplications useful in training and inference operations in neural networks.

[0003] These devices are attractive compared to other pillar cell designs due to their low resistance drift coefficient.

[0004] To fabricate these devices, it is important to deposit GST inside the pores as either nanocrystals or crystals, but shrinkage of the deposited amorphous GST can lead to defects during downstream processing. This shrinkage can be attributed to phase transformation.

[0005] Alternatively, the roughness of the deposited crystalline (or nanocrystalline) GST (c-GST) can lead to non-uniform recesses into the pores and grain pull-out during the chemical mechanical polishing (CMP) planarization process. In some cases, delamination of crystalline GST has also been observed.

[0006] These issues can lead to problems with the top-contact interface and can result in significant device-to-device variability. Summary of the Invention

[0007] According to one embodiment of the present invention, a method for fabricating a phase change memory device includes providing a substrate including a plurality of bottom electrodes, patterning the substrate to form a plurality of pores in the substrate extending from a surface of the substrate to the bottom electrodes, depositing a phase change material on the substrate, implanting the phase change material with at least one of Ge, Sb, and Te to amorphize at least a portion of the phase change material within the pores, planarizing the device to expose a surface of the substrate, and forming a plurality of top electrodes over the pores in contact with the phase change material.

[0008] In some embodiments, a method for fabricating a phase change memory device includes providing a substrate including a plurality of bottom electrodes; patterning the substrate to form a plurality of pores in the substrate extending from a surface of the substrate to the bottom electrodes; depositing a phase change material over the substrate; planarizing the device to expose a surface of the substrate; implanting the phase change material with at least one of Ge, Sb, and Te to amorphize at least a portion of the phase change material within the pores; planarizing the device to expose a surface of the substrate; and forming a plurality of top electrodes over the pores in contact with the phase change material.

[0009] In accordance with one or more embodiments of the present invention, a phase change memory device includes a bottom electrode, a substrate formed on the bottom electrode, a pore formed in the substrate and extending to the bottom electrode, a phase change material disposed in the pore and electrically connected to the bottom electrode, the phase change material including an amorphous portion disposed in contact with a top electrode and a crystalline portion disposed below the amorphous portion, where the amorphous portion includes implanted ions, and a top electrode disposed over the substrate and in contact with the amorphous portion of the phase change material, where an interface between the phase change material and the top electrode is free of voids.

[0010] As used herein, "facilitating" an action includes performing an action, making an action easier, helping to perform an action, or having an action performed. Thus, by way of example and not limitation, instructions executed on one processor may facilitate an action performed by instructions executed on a remote processor by sending appropriate data or commands to cause or assist in the action being performed. For the avoidance of doubt, where an actor facilitates an action by other than performing the action, the action is nevertheless performed by some entity or combination of entities.

[0011] One or more embodiments of the present invention or elements thereof may be embodied in the form of a computer program product including a computer-readable storage medium having computer usable program code for performing the illustrated method steps. Furthermore, one or more embodiments of the present invention or elements thereof may be embodied in the form of a system (or apparatus) including a memory and at least one processor coupled to the memory and operable to perform the illustrated method steps. Furthermore, in another aspect, one or more embodiments of the present invention or elements thereof may be embodied in the form of a means for performing at least one of the method steps described herein, which may include (i) a hardware module, (ii) a software module stored in a computer-readable storage medium (or multiple such media) and executed on a hardware processor, or (iii) a combination of (i) and (ii), any of (i)-(iii) implementing certain techniques described herein.

[0012] The techniques of the present invention can provide substantial beneficial technical effects. For example, one or more embodiments can provide the following: A method for amorphizing deposited GST films using Ge, Sb, or Te implantation without changing the composition of the GST; A method for achieving good contact between the deposited GST and the top electrode metal; and A method for forming a GST film that reduces or eliminates delamination defects during CMP.

[0013] These and other features and advantages of this invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.

[0014] Preferred embodiments of the invention are explained in more detail below with reference to the accompanying drawings. [Brief description of the drawings]

[0015] [Figure 1] FIG. 2 illustrates a method for manufacturing a PCM device according to one or more embodiments of the present invention. [Diagram 2] FIG. 2 illustrates a method for manufacturing a PCM device according to one or more embodiments of the present invention. [Diagram 3] FIG. 2 illustrates a method for manufacturing a PCM device according to one or more embodiments of the present invention. [Figure 4] FIG. 2 illustrates a method for manufacturing a PCM device according to one or more embodiments of the present invention. [Diagram 5] FIG. 2 illustrates a method for manufacturing a PCM device according to one or more embodiments of the present invention. [Figure 6] FIG. 2 illustrates a method for manufacturing a PCM device according to one or more embodiments of the present invention. [Figure 7] 1 is a flow diagram of a method for manufacturing a PCM device in accordance with one or more embodiments of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Phase-Change Memory (PCM) is a chalcogenide glass-based material that can change its phase from crystalline to amorphous and back again when an appropriate electric current is applied. GST alloy (germanium-antimony-tellurium or Ge2Sb2Te5) is one such chalcogenide glass material. Each phase has a different resistance level that is stable until the phase is changed. The maximum and minimum resistance levels in a PCM device are the basis for the binary values ​​of 1 or 0.

[0017] Embodiments of the invention include methods for amorphizing GST films using an implantation process prior to CMP planarization. According to some embodiments, Ge, Sb or Te implants are used to amorphize the GST film without substantially changing the composition of the GST (e.g., less than 1% of the material). Embodiments of the invention achieve good contact between the GST and the top electrode metal (not shown) and do not exhibit delamination defects.

[0018] In some embodiments, the containment cells 101 are formed by void-free filling of the phase change material 102 (see FIG. 1). Embodiments of the invention achieve good interfacial contact between the phase change material 102 and the top electrode 103. In at least one embodiment, a first portion 104 of the phase change material (e.g., near the top electrode) is amorphous and a second portion 105 (e.g., near the bottom electrode) is crystalline.

[0019] It should be understood that confined cells refer to a general category of PCM cells and can be compared to contact-minimized PCM cells. In confined cells, current flow is most confined to the phase change material (e.g., it is the phase change material that has the smallest cross-sectional area for current flow). In contact-minimized cells, the electrodes that connect to the phase change material have the smallest cross-sectional area for current flow (e.g., the current is most confined by the contacts to the phase change material).

[0020] In accordance with at least one embodiment, a method of fabricating a PCM device is described with reference to Figures 2-7 and includes providing a substrate 201 (e.g., an interlayer dielectric (ILD)) that is patterned to form a plurality of pores (e.g., pores 202) therein. In some embodiments, a liner 203 is formed on the substrate 201. In some embodiments, the pores extend through the substrate 201 to a bottom electrode 204 disposed beneath the substrate 201.

[0021] It will be appreciated that the substrate is patterned such that the pores correspond to the locations of a number of bottom electrodes, and the bottom electrodes can be formed by depositing a bottom electrode metal on the underside of the substrate and patterning the bottom electrode metal.

[0022] In some embodiments, the substrate is formed of silicon nitride (SiN). The bottom electrode 204 can be formed of, for example, a metal or metal nitride. In some embodiments, the liner 203 is a metal liner formed by a CVD or ALD process. The liner can be formed of, for example, titanium nitride (TiN), titanium carbide (TiC), tungsten carbide (WC), tungsten nitride (WN), carbon (C), hafnium nitride (HfN), hafnium carbide (HfC), vanadium nitride (VN), vanadium carbide (VC), tantalum nitride (TaN), tantalum carbide (TaC), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum silicon nitride (TaSiN), or tantalum aluminum nitride (TaAlN), or other transition metal or refractory metal carbides or nitrides.

[0023] In some embodiments, a phase change material 301, such as a crystalline (polycrystalline) or nanocrystalline GST film, is deposited on the substrate 201 and liner 203 using a CVD / ALD process, as shown in Figure 3. Depositing the phase change material in an amorphous state followed by crystallization avoids the potential for void formation in the material due to shrinkage / density changes associated with the phase transition, in some embodiments, by depositing the phase change material 301 in a polycrystalline state. In some embodiments, the phase change material 301 is deposited by a physical vapor deposition (PVD) process or a combination of CVD / ALD and PVD processes.

[0024] In some embodiments, the phase change material 301 can be a single element (such as Sb only), or a binary compound such as GeTe or SbTe with various stoichiometric ratios, or a ternary alloy including Ge, Te, and Sb. Additionally, the phase change material can be doped or mixed with less than about 20% nitrogen (N), carbon (C), oxygen (O), silicon (Si), or selenium (Se), or alloys containing these elements.

[0025] 4, in some embodiments, a beamline implant 401 of Ge, Sb, or Te is used to amorphize the overburden film 402 (i.e., the portion above the substrate 201 and liner 203) and at least a portion 403 of the phase change material 301 inside the pores. In some embodiments, the entire phase change material 301 inside the pores is amorphized. In some embodiments, the (film / compound based) implant can be used to amorphize the phase change material without changing its composition.

[0026] In some embodiments, the implant dose of Ge, Sb, or Te, or a combination thereof, is about 5×10 15 cm -2According to at least one embodiment, implantation 401 is performed at low temperature (e.g., cold chuck, -20°C) to produce a sharp amorphous / crystalline boundary. According to some embodiments, the ion implanter current (ion flux) is controlled such that excessive self-heating does not occur and recrystallization is avoided. For example, the temperature rise due to ion implantation can be kept below the crystallization temperature of the phase change material (e.g., below about 165°C for GST225). Thus, one skilled in the art will understand how to achieve the dose required to amorphize GST.

[0027] In one or more embodiments, Ge, Sb, and / or Te are used during implantation 401 to avoid introducing impurities beyond those atoms already in the GST alloy. In some embodiments, other elements can be implanted for amorphization purposes. For example, the noble gas Xe (54) can be used to achieve a substantially similar amorphization effect as Te (52).

[0028] It should be appreciated that ion implantation 401 can have the effect of transforming a polycrystalline material into an amorphous material without substantially changing the overall composition of the material.

[0029] According to one or more embodiments, the device 500 is planarized, for example by CMP, to remove the overburden film 402 and the top of the liner 203, as shown in FIG.

[0030] In some embodiments, some dopant atoms are implanted into the dielectric layer in the case of planar implantation, as shown in Figure 5. The dose in the dielectric layer does not change the stoichiometry of the dielectric material.

[0031] In some embodiments, a first CMP process is performed to partially remove the overburden film 402, followed by implantation 401, and then a second CMP process is performed to fully planarize the structure (e.g., to remove the top of the liner 203 on the substrate 201).

[0032] In some embodiments, the CMP process is performed on the phase change material in the amorphous phase, allowing the phase change material to be removed from the top of the pores since the CMP is substantially prevented from pulling out or destroying crystalline mass. In one or more embodiments, the phase change material is deposited in polycrystalline form and amorphized prior to the CMP process. In some embodiments, subsequent processes have a high temperature budget and the phase change material becomes polycrystalline by the time wafer processing is complete.

[0033] In some embodiments, a top electrode 601 in contact with the phase change material 301 is deposited over the pores (see FIG. 6). In one or more embodiments, the top electrode 601 is patterned after deposition for downstream integration of subsequent wiring levels (not shown).

[0034] During electrical programming of a phase change memory cell, at least a portion (or possibly all) of the phase change material undergoes a phase transformation, thereby changing the electrical resistance of the phase change memory cell.

[0035] In some embodiments, the PCM devices are arranged in a 3D crossbar array, and in at least one embodiment, each PCM device in the array is connected to a selector device, such as an ovonic threshold switch or a select transistor.

[0036] Referring to FIG. 7, a method 700 for fabricating a PCM device includes providing a substrate, such as an interlayer dielectric (ILD), on a plurality of bottom electrodes 701 and patterning the substrate to form a plurality of pores or vias in the substrate extending from a surface of the substrate to the bottom electrodes 702. The method further includes depositing a liner on a surface of the substrate 703. Block 703 may further include etching the liner (such as by reactive ion etching). The method includes depositing a phase change material, such as a crystalline or nanocrystalline GST film, on the substrate and the liner 704. According to some embodiments, block 704 includes an anneal to densify the deposited phase change material. The method further includes implanting the phase change material with at least one of Ge, Sb, or Te to amorphize at least a portion of the phase change material inside the pores 706. According to some embodiments, the method further includes planarizing the device to expose a surface of the substrate 707, removing the overburden film and a top portion of the liner.

[0037] In some embodiments, a first CMP process 705 is performed to partially remove the overburden film, followed by an implant 706, and then a second CMP process 707 is performed to fully planarize the structure and remove the top of the liner on the substrate.

[0038] In some embodiments, a top electrode is formed by depositing a top electrode metal over the pore in contact with the phase change material and patterning the top electrode metal (708). In at least one embodiment, downstream integration of a subsequent wiring level (not shown) is performed (709).

[0039] According to at least one embodiment, the method further includes a wet clean between amorphization 706 and planarization 707 .

[0040] summary: A method 700 for fabricating a phase change memory device includes providing a substrate 701 including a plurality of bottom electrodes, patterning the substrate 702 to form a plurality of pores in the substrate extending from a surface of the substrate to the bottom electrodes, depositing a phase change material on the substrate 704, implanting the phase change material with at least one of Ge, Sb, and Te to amorphize at least a portion of the phase change material within the pores 706, planarizing the device to expose a surface of the substrate 707, and forming a plurality of top electrodes over the pores in contact with the phase change material 708.

[0041] In some embodiments, a method 700 for fabricating a phase change memory device includes providing a substrate including a plurality of bottom electrodes 701, patterning the substrate to form a plurality of pores in the substrate extending from a surface of the substrate to the bottom electrodes 702, depositing a phase change material on the substrate 704, planarizing the device to expose a surface of the substrate 705, implanting the phase change material with at least one of Ge, Sb, and Te to amorphize at least a portion of the phase change material within the pores 706, planarizing the device to expose a surface of the substrate 707, and forming a plurality of top electrodes over the pores in contact with the phase change material 708.

[0042] In accordance with one or more embodiments of the present invention, a phase change memory device includes a bottom electrode 204, a substrate 201 formed on the bottom electrode, a pore 202 formed in the substrate and extending to the bottom electrode, a phase change material 301 disposed in the pore and including an amorphous portion 104 disposed in contact with the top electrode and a crystalline portion 105 disposed below the amorphous portion, where the amorphous portion includes implanted ions, and a top electrode 601 disposed over the substrate and in contact with the amorphous portion of the phase change material, wherein an interface between the phase change material and the top electrode is free of voids.

[0043] References herein to "one embodiment" or "an embodiment" of the present principles, as well as other variations, mean that a particular feature, structure, characteristic, etc. described in connection with the embodiment is included in at least one embodiment of the present principles. Thus, the appearances of the phrases "in one embodiment" or "an embodiment" in various places throughout this specification, as well as any other variations, are not necessarily all referring to the same embodiment.

[0044] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions, which includes one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions shown in the blocks may occur out of the order shown in the figures. For example, two blocks shown in succession may in fact be executed substantially simultaneously, or the blocks may sometimes be executed in the reverse order, depending on the functionality involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified functions or acts, or executes a combination of dedicated hardware and computer instructions.

[0045] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", as used herein, specify the presence of stated features, integers, steps, operations, elements, or components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof, or combinations thereof.

[0046] Corresponding structures, materials, acts, and equivalents of all means or step-plus-function elements in the following claims are intended to include any structure, material, or act for performing a function in combination with other claimed elements as specifically claimed. The description of various embodiments of the present invention has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein have been selected to best explain the principles of the embodiments, practical applications or technical improvements to the technology found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. A method for manufacturing a phase change memory device, comprising: Providing a substrate including a plurality of bottom electrodes; patterning the substrate to form a plurality of pores in the substrate extending from a surface of the substrate to the bottom electrode; depositing a phase change material, which is a GST film, in a polycrystalline state on the substrate to fill the pores and form an overburden film on a surface of the substrate; implanting at least one of Ge, Sb and Te into the phase change material to amorphize the overburden film and at least a portion of the phase change material in the upper part of the pore without changing the composition of the GST film and avoiding the introduction of impurities other than atoms already in the GST film, and controlling the ion flux applied during the implantation so as not to reach the crystallization temperature of the phase change material due to self-annealing caused by the implantation; CMP planarizing the device to expose the surface of the substrate; forming a plurality of top electrodes over the pores in contact with the phase change material; A method comprising:

2. The method of claim 1 , wherein the substrate is an inter-layer dielectric (ILD), further comprising depositing a liner on the surface of the substrate prior to depositing the phase change material.

3. The method of claim 1 , wherein the deposited phase change material is one of a crystalline GST-based film and a nanocrystalline GST-based film.

4. The implantation dose of the at least one of Ge, Sb, and Te is about 5×10 １５ cm －２ The method of claim 1 , wherein the

5. The method of claim 1 , further comprising annealing the phase change material prior to said implanting.

6. forming the top electrode depositing a top electrode metal over the pores in contact with the phase change material; patterning the top electrode metal to form the plurality of top electrodes; The method of claim 1 further comprising:

7. The method of claim 1 , further comprising providing at least one wiring level on the substrate.

8. 1. A method for manufacturing a phase change memory device, comprising: Providing a substrate including a plurality of bottom electrodes; patterning the substrate to form a plurality of pores in the substrate extending from a surface of the substrate to the bottom electrode; depositing a phase change material, which is a GST film, in a polycrystalline state on the substrate to fill the pores and form an overburden film on a surface of the substrate; CMP planarizing the device to partially remove the overburden film; implanting at least one of Ge, Sb and Te into the phase change material to amorphize the remainder of the overburden film and at least a portion of the phase change material in the upper part of the pore without changing the composition of the GST film and avoiding the introduction of impurities other than atoms already in the GST film, controlling the ion flux applied during the implantation so as not to reach the crystallization temperature of the phase change material due to self-annealing caused by the implantation; CMP planarizing the device to expose the surface of the substrate; forming a plurality of top electrodes over the pores in contact with the phase change material; A method comprising:

9. 10. The method of claim 8, wherein the substrate is an inter-layer dielectric (ILD), further comprising depositing a liner on the surface of the substrate prior to depositing the phase change material.

10. The method of claim 8 , wherein the deposited phase change material is one of a crystalline GST-based film and a nanocrystalline GST-based film.

11. The implantation dose of the at least one of Ge, Sb, and Te is about 5×10 １５ cm －２ The method of claim 8, wherein the

12. The method of claim 8 , further comprising annealing the phase change material prior to said implanting.

13. 10. The method of claim 8, further comprising one of doping and mixing the phase change material with less than about 20% N, C, O, Si, or Se, or alloys thereof.

14. forming the top electrode depositing a top electrode metal over the pores in contact with the phase change material; patterning the top electrode metal to form the plurality of top electrodes; The method of claim 8 further comprising:

15. The method of claim 8 further comprising providing at least one wiring level on the substrate.

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