Photoelectric conversion device

Abstract

To provide a technique for increasing the degree of freedom in setting an exposure time in a photoelectric conversion device comprising pixels each having a plurality of photoelectric conversion units sharing a floating diffusion unit.SOLUTION: A photoelectric conversion device has: a plurality of pixels that each have a plurality of photoelectric conversion units and a floating diffusion unit to which electric charges of the plurality of photoelectric conversion units are transferred; a vertical scanning unit that executes read-out processing of reading out signals of the pixels and reset processing for the plurality of pixels while switching the photoelectric conversion unit to be processed and the floating diffusion unit to be processed; and a control unit that controls the vertical scanning unit. The control unit has a read-out row address generation unit that generates a row address to be processed, and a reset row address generation unit. A first period for switching the photoelectric conversion unit to be processed is shorter than a second period for switching the floating diffusion unit to be processed. An update period of the row address is equal to the second period. A setting unit of the update timing of the row address is equal to the length of one period of the first period.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a photoelectric conversion device. [Background technology]

[0002] Patent Document 1 describes an image sensor having pixels in which a single floating diffusion region is shared by multiple photoelectric conversion units. Patent Document 2 describes a method for reading out electric charges from a photoelectric conversion unit or resetting the photoelectric conversion unit in a general image sensor, in which pixels to be subjected to each process are designated row by row and each process is performed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2013-118698 A [Patent Document 2] JP 2008-288946 A Summary of the Invention [Problem to be solved by the invention]

[0004] When the technology described in Patent Document 2 is applied to Patent Document 1, one floating diffusion is selected over multiple horizontal periods, multiple photoelectric conversion units sharing the floating diffusion are selected in sequence, and readout and reset processes are performed row by row in sequence. Therefore, the degree of freedom in setting the exposure time of the photoelectric conversion units is not necessarily high.

[0005] An object of the present invention is to provide a technique for improving the degree of freedom in setting exposure time in a photoelectric conversion device including pixels having a plurality of photoelectric conversion units that share a floating diffusion unit. [Means for solving the problem]

[0006] According to one disclosure of the present specification, a pixel unit includes a plurality of pixels arranged in a plurality of rows and a plurality of columns, each of the pixels including three or more photoelectric conversion units, a floating diffusion unit to which charges of the photoelectric conversion units are transferred, and an output unit that outputs a signal according to a voltage of the floating diffusion unit; a vertical scanning unit that performs a read process for reading out signals from the pixels arranged in the pixel unit and a reset process for resetting the pixels while switching between the photoelectric conversion units that are the subject of the process and the floating diffusion unit that is the subject of the process; and a control unit that controls the vertical scanning unit, wherein the control unit includes a read row address generation unit that generates row addresses of pixels from which signals are read during the read process and outputs the row addresses to the vertical scanning unit, and a reset process that resets the pixels. a reset row address generation unit that generates row addresses of pixels to be reset during a readout process and outputs the row addresses to the vertical scanning unit, wherein a first period that is a period for switching the photoelectric conversion units to be processed during the readout process and the reset process is shorter than a second period that is a period for switching the floating diffusion units to be processed during the readout process and the reset process, an update period of the row addresses in the readout row address generation unit and the reset row address generation unit is equal to the second period, and a setting unit for update timing of the row addresses in the readout row address generation unit and the reset row address generation unit is equal to the length of one period of the first period. Effect of the Invention

[0007] According to the present invention, in a photoelectric conversion device including pixels each having a plurality of photoelectric conversion units sharing a floating diffusion unit, it is possible to improve the degree of freedom in setting the exposure time. [Brief description of the drawings]

[0008] [Figure 1] 1 is a block diagram showing a schematic configuration of a photoelectric conversion device according to a first embodiment of the present invention. [Diagram 2] 1 is a circuit diagram showing an example of the configuration of a pixel in a photoelectric conversion device according to a first embodiment of the present invention. [Diagram 3]2 is a block diagram showing an example of the configuration of a control unit in the photoelectric conversion device according to the first embodiment of the present invention. FIG. [Figure 4] 3 is a block diagram showing an example of the configuration of a read row / reset row address generation section in the photoelectric conversion device according to the first embodiment of the present invention. FIG. [Diagram 5] 4 is a timing chart showing an example of operation of a read row / reset row address generation section in the photoelectric conversion device according to the first embodiment of the present invention. FIG. [Figure 6] 4 is a timing chart showing an example of operation of the vertical scanning timing control section in the photoelectric conversion device according to the first embodiment of the present invention. FIG. [Figure 7] 2 is a block diagram showing an example of the configuration of a vertical scanning unit in the photoelectric conversion device according to the first embodiment of the present invention. FIG. [Figure 8A] 4 is a timing chart (part 1) showing an example of the operation of a pixel control signal generation section and a pixel section in the photoelectric conversion device according to the first embodiment of the present invention. FIG. [Figure 8B] FIG. 2 is a timing chart (part 2) showing an example of the operation of the pixel control signal generation unit and the pixel unit in the photoelectric conversion device according to the first embodiment of the present invention. [Figure 8C] FIG. 4 is a timing chart (part 3) showing an example of the operation of the pixel control signal generation unit and the pixel unit in the photoelectric conversion device according to the first embodiment of the present invention. [Figure 9] 4 is a timing chart illustrating the transition of row addresses during vertical scanning in the photoelectric conversion device according to the first embodiment of the present invention. FIG. [Figure 10] FIG. 11 is a block diagram showing an example of the configuration of a read row / reset row address generation section in a photoelectric conversion device according to a second embodiment of the present invention. [Figure 11] 10 is a timing chart showing an example of the operation of a read row / reset row address generation section in the photoelectric conversion device according to the second embodiment of the present invention. FIG. [Figure 12] 10 is a timing chart showing an example of operation of a vertical scanning timing control section in the photoelectric conversion device according to the second embodiment of the present invention. FIG. [Figure 13] FIG. 11 is a circuit diagram showing an example of the configuration of a pixel in a photoelectric conversion device according to a third embodiment of the present invention. [Figure 14] 13 is a timing chart showing an example of operation of a read row / reset row address generation section in the photoelectric conversion device according to the third embodiment of the present invention. FIG. [Figure 15A] FIG. 11 is a timing chart (part 1) showing an example of the operation of a pixel control signal generation section and a pixel section in a photoelectric conversion device according to a third embodiment of the present invention. [Figure 15B] FIG. 11 is a timing chart (part 2) showing an example of the operation of the pixel control signal generation unit and the pixel unit in the photoelectric conversion device according to the third embodiment of the present invention. [Figure 15C] FIG. 11 is a timing chart (part 3) showing an example of the operation of the pixel control signal generation unit and the pixel unit in the photoelectric conversion device according to the third embodiment of the present invention. [Figure 16A] FIG. 11 is a timing chart (part 1) illustrating the transition of row addresses during vertical scanning in a photoelectric conversion device according to a third embodiment of the present invention. [Figure 16B] FIG. 11 is a timing chart (part 2) illustrating the transition of row addresses during vertical scanning in the photoelectric conversion device according to the third embodiment of the present invention. [Figure 17] 13 is a timing chart showing an example of the operation of a read row / reset row address generation section in the photoelectric conversion device according to the fourth embodiment of the present invention. FIG. [Figure 18A] FIG. 11 is a timing chart (part 1) showing an example of the operation of a pixel control signal generation section and a pixel section in a photoelectric conversion device according to a fourth embodiment of the present invention. [Figure 18B] FIG. 13 is a timing chart (part 2) showing an example of the operation of the pixel control signal generation section and the pixel section in the photoelectric conversion device according to the fourth embodiment of the present invention. [Figure 18C] FIG. 13 is a timing chart (part 3) showing an example of the operation of the pixel control signal generation unit and the pixel unit in the photoelectric conversion device according to the fourth embodiment of the present invention. [Figure 19A] FIG. 13 is a timing chart (part 1) illustrating the transition of row addresses during vertical scanning in a photoelectric conversion device according to a fourth embodiment of the present invention. [Figure 19B]FIG. 13 is a timing chart (part 2) illustrating transition of row addresses during vertical scanning in the photoelectric conversion device according to the fourth embodiment of the present invention. [Figure 20] FIG. 13 is a block diagram showing a schematic configuration of an imaging system according to a fifth embodiment of the present invention. [Figure 21] FIG. 13 is a diagram showing an example of the configuration of an imaging system and a moving object according to a sixth embodiment of the present invention. [Figure 22] FIG. 13 is a block diagram showing a schematic configuration of an apparatus according to a seventh embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] [First embodiment] A schematic configuration of a photoelectric conversion device according to a first embodiment of the present invention will be described with reference to Fig. 1. Fig. 1 is a block diagram showing a schematic configuration of a photoelectric conversion device according to this embodiment.

[0010] The photoelectric conversion device 100 according to this embodiment may be configured with a processing device (processor) 1, a control unit 2, a vertical scanning unit 3, a pixel unit 4, a column circuit unit 5, a horizontal scanning unit 6, and a signal output unit 7, as shown in Fig. 1, for example. The vertical scanning unit 3 and the column circuit unit 5 are connected to the pixel unit 4. The horizontal scanning unit 6 is connected to the column circuit unit 5. The signal output unit 7 is connected to the horizontal scanning unit 6. The control unit 2 is connected to the vertical scanning unit 3, the column circuit unit 5, the horizontal scanning unit 6, and the signal output unit 7. The processing device 1 is connected to the control unit 2.

[0011] The processing device 1 is, for example, a CPU (Central Processing Unit), and controls the overall operation of the photoelectric conversion device 100. The processing device 1 outputs control signals such as a synchronization signal and setting signals such as an operation mode to the control unit 2. Note that the processing device 1 may be provided within a system in which the photoelectric conversion device 100 is mounted, that is, outside the photoelectric conversion device 100.

[0012] The control unit 2 is a control circuit that receives control signals such as synchronization signals and setting signals such as operating modes from the processing device 1, and outputs control signals to the vertical scanning unit 3, column circuit unit 5, horizontal scanning unit 6 and signal output unit 7 to control their operation and timing.

[0013] In the pixel section 4, a plurality of pixels P each including a photoelectric conversion section are two-dimensionally arranged in a plurality of rows and a plurality of columns. Each of the plurality of pixels P is configured to output a pixel signal according to the amount of light incident on the photoelectric conversion section. FIG. 1 shows the pixel section 4 composed of pixels P arranged in a matrix of M columns by N rows. Coordinates represented by (m, n) are added to the reference symbol P of some of the pixels P. Here, m is a column number represented by an integer from 1 to M, and n is a row number represented by an integer from 1 to N. In this specification, the direction in which each row extends (row direction) is defined as the horizontal direction, and the direction in which each column extends (column direction) is defined as the vertical direction. In addition, the row number of the first row is the first row, and the column number of the first column is the first column.

[0014] Two vertical output lines Vline1, Vline2 are arranged in each column of the pixel section 4. A number indicating the column number m is added in parentheses to the reference symbols of some of the vertical output lines Vline1, Vline2 in Fig. 1. Note that, although Fig. 1 shows an example in which two vertical output lines Vline are arranged in each column, the number of vertical output lines Vline arranged in each column may be one, or three or more.

[0015] The vertical scanning unit 3 is a control circuit that operates upon receiving a signal from the control unit 2 and drives a plurality of pixels P constituting the pixel unit 4 on a row-by-row basis. The operations performed by the vertical scanning unit 3 on a plurality of pixels P constituting the pixel unit 4 include reset scanning and readout scanning. The reset scanning refers to an operation of releasing the reset state of the photoelectric conversion unit for some or all of the rows of pixels P in the pixel unit 4 sequentially on a row-by-row basis and setting the pixels P to a charge accumulation state, thereby starting exposure. The readout scanning refers to an operation of outputting a signal based on the charge accumulated in the photoelectric conversion unit from some or all of the rows of pixels P in the pixel unit 4 sequentially on a row-by-row basis. The vertical scanning unit 3 supplies a control signal to the pixels P on a row-by-row basis via a control line (not shown) arranged in each row of the pixel unit 4. The vertical scanning unit 3 may be configured using a shift register or an address decoder.

[0016] The column circuit unit 5 is a circuit block that performs predetermined processing on pixel signals output from the pixels P of the pixel unit 4, and may include, for example, an amplifier circuit, an analog-to-digital conversion (AD conversion) circuit, and a memory corresponding to each vertical output line Vline. In this case, the column circuit unit 5 performs amplification processing and AD conversion processing on the pixel signals, which are analog signals output from the pixels P of each column of the pixel unit 4 via the vertical output line Vline, and holds the pixel signals in the memory as digital data.

[0017] The horizontal scanning unit 6 is a control circuit that operates upon receiving a signal from the control unit 2 and transfers the digital data held in the memory of the column circuit unit 5 sequentially, column by column, to the signal output unit 7. The horizontal scanning unit 6 can be configured using a shift register and an address decoder.

[0018] The signal output unit 7 is an output circuit that digitally processes the signal transferred from the horizontal scanning unit 6 and outputs the signal as serial data to the outside of the photoelectric conversion device 100. The signal output unit 7 may be configured to include a digital processing unit, a parallel-serial conversion circuit, and an output circuit such as LVDS (Low Voltage Differential Signaling).

[0019] It is not essential that the column circuit section 5 has an AD conversion function, and for example, the column circuit section 5 may be configured to perform AD conversion processing outside the photoelectric conversion device 100. In this case, the configurations of the horizontal scanning section 6 and the signal output section 7 are also appropriately changed so as to be suitable for processing of analog signals.

[0020] Next, a configuration example of a pixel P in a photoelectric conversion device according to this embodiment will be described with reference to Fig. 2. Fig. 2 is a circuit diagram showing a configuration example of a pixel P in a photoelectric conversion device according to this embodiment. Fig. 2 shows only the configuration of pixel P(m,n) arranged in the mth column and nth row among the pixels P that make up the pixel section 4, but the configuration of the other pixels P is similar.

[0021] 2, each pixel P may be composed of eight photoelectric conversion units PD1 to PD8, eight transfer transistors M1 to M8, a reset transistor M9, an amplification transistor M10, and a selection transistor M11. Note that the number of photoelectric conversion units PD included in each pixel P does not necessarily have to be eight.

[0022] The photoelectric conversion units PD1 to PD8 may be composed of photoelectric conversion elements such as photodiodes and photogates. Here, it is assumed that the photoelectric conversion units PD1 to PD8 are composed of photodiodes. The photodiode constituting the photoelectric conversion unit PD1 has an anode connected to a ground node and a cathode connected to the source of the transfer transistor M1. Similarly to the photodiode constituting the photoelectric conversion unit PD1, the photodiodes constituting the photoelectric conversion units PD2 to PD8 also have an anode connected to a ground node and a cathode connected to the sources of the transfer transistors M2 to M8 corresponding thereto.

[0023] The drains of the transfer transistors M1 to M8 are connected to the source of the reset transistor M9 and the gate of the amplification transistor M10. A connection node between the drains of the transfer transistors M1 to M8, the source of the reset transistor M9, and the gate of the amplification transistor M10 is a so-called floating diffusion portion FD. The drains of the reset transistor M9 and the drain of the amplification transistor M10 are connected to a power supply voltage node (voltage VCC). The source of the amplification transistor M10 is connected to the drain of the selection transistor M11. The source of the selection transistor M11 is connected to a vertical output line Vline1(m). The vertical output line to which the pixel P is connected is different for each row. For example, the source of the selection transistor M11 of the pixel P in the odd row can be connected to the vertical output line Vline1(m), and the source of the selection transistor M11 of the pixel P in the even row can be connected to the vertical output line Vline2(m). Note that the connection to the vertical output lines Vline1 and Vline2 does not necessarily need to be changed for each row, and may be changed for each multiple rows. The same applies when three or more vertical output lines Vline are arranged in each column.

[0024] In the case of the pixel configuration shown in FIG. 2, each of the control lines arranged in each row of the pixel section 4 includes eight transfer gate signal lines corresponding to the transfer transistors M1 to M8, a reset signal line, and a selection signal line. Each of the eight transfer gate signal lines in the nth row supplies a corresponding control signal among the control signals PTX1(n) to PTX8(n) output from the vertical scanning unit 3 to the gate of the corresponding transfer transistor among the transfer transistors M1 to M8. For example, the transfer gate signal line corresponding to the transfer transistor M1 of the pixel P in the nth row supplies a control signal PTX1(n) to the gate of the transfer transistor M1 of the pixel P in the nth row. The same is true for the transfer gate signal lines corresponding to the transfer transistors M2 to M8 of the pixel P in the nth row. The reset signal line in the nth row supplies a control signal PRES(n) output from the vertical scanning unit 3 to the gate of the reset transistor M9 of the pixel P in the nth row. The selection signal line in the nth row supplies a control signal PSEL(n) output from the vertical scanning unit 3 to the gate of the selection transistor M11 of the pixel P in the nth row. A common control signal is supplied from the vertical scanning unit 3 to the pixels P in the same row.

[0025] The photoelectric conversion units PD1 to PD8 convert incident light into charges in an amount corresponding to the amount of light (photoelectric conversion) and accumulate the generated charges. When the transfer transistors M1 to M8 are turned on (conductive state), they transfer the charges held by the corresponding photoelectric conversion units PD1 to PD8 to the floating diffusion unit FD. That is, the photoelectric conversion units PD1 to PD8 share one floating diffusion unit FD. The floating diffusion unit FD has a capacitance component, and holds the charges transferred from the photoelectric conversion units PD1 to PD8, and sets the floating diffusion unit FD to a potential corresponding to the amount of the charges by charge-voltage conversion using the capacitance. The amplifier transistor M10 is configured such that a voltage VCC is supplied to its drain and a bias current is supplied to its source from a current source (not shown) via the vertical output line Vline1(m) and the selection transistor M11, forming a source follower circuit with the gate as an input. As a result, the amplifier transistor M10 outputs a signal based on the potential of the floating diffusion unit FD to the vertical output line Vline1(m) via the selection transistor M11. The reset transistor M9 resets the floating diffusion unit FD to a potential corresponding to the power supply voltage by being turned on (conductive state). In addition, by turning on (conductive state) the transfer transistors M1 to M8 simultaneously with the reset transistor M9, the photoelectric conversion units PD1 to PD8 can be reset to a potential corresponding to the voltage VCC. The selection transistor M11 switches the connection between the amplification transistor M10 and the vertical output line Vline1(m).

[0026] When the transfer transistors M1 to M8 are off (non-conductive state), the photoelectric conversion units PD1 to PD8 are in an accumulation state in which they accumulate charges generated by photoelectric conversion. When the transfer transistors M1 to M8 and the reset transistor M9 are on (conductive state), no charges are accumulated in the photoelectric conversion units PD1 to PD8, and they are in a non-accumulation state, i.e., a reset state. When the reset transistor M9 is off (non-conductive state), the transfer transistors M1 to M8 are on (conductive state), and the charges accumulated in the photoelectric conversion units PD1 to PD8 are transferred to the floating diffusion unit FD, thereby putting the pixel P in a readout state. The reset of the photoelectric conversion units PD1 to PD8 may be controlled by another transistor (not shown) that connects the cathodes of the photoelectric conversion units PD1 to PD8 to a power supply voltage.

[0027] When each transistor is an N-channel transistor, the corresponding transistor turns on when a high-level control signal is supplied from the vertical scanning unit 3, and the corresponding transistor turns off when a low-level control signal is supplied from the vertical scanning unit 3. Here, the high level corresponds to a logical value of "1" and the low level corresponds to a logical value of "0." Note that each transistor constituting a pixel P may be an N-channel transistor, but may also be a P-channel transistor.

[0028] Next, a configuration example of the control unit 2 in the photoelectric conversion device according to this embodiment will be described with reference to Fig. 3. Fig. 3 is a block diagram showing a configuration example of the control unit 2 in the photoelectric conversion device according to this embodiment.

[0029] As shown in FIG. 3, the control unit 2 has a synchronization signal generation unit 21, a read row / reset row address generation unit 22, a vertical scanning timing control unit 23, a column circuit timing control unit 24, and a horizontal scanning timing control unit 25.

[0030] The synchronization signal generation unit 21 generates a vertical synchronization signal V_RD for read processing, vertical synchronization signals V_SHA, V_SHB for reset processing, and a horizontal synchronization signal Hpd in accordance with a control signal from the processing device 1. The generation cycle of the horizontal synchronization signal Hpd is a cycle pd for switching the selection of the photoelectric conversion units PD1 to PD8. The number of vertical synchronization signals for reset processing can be appropriately changed according to the configuration of the read row / reset row address generation unit 22, and may be one or three or more.

[0031] The read row / reset row address generation unit 22 generates a read row address signal, a reset A row address signal, and a reset B row address signal in accordance with the synchronization signal from the synchronization signal generation unit 21, and outputs them to the vertical scanning unit 3. The read row address (row address signal addr_rd) indicates the position of the row in which the pixel P to be the target of the readout process is arranged. The reset A row address (row address signal addr_sha) and the reset B row address (row address signal addr_shb) indicate the position of the row in which the pixel P to be the target of the reset process is arranged. The number of reset row addresses may be one or three or more.

[0032] Furthermore, the read row / reset row address generation unit 22 generates a count signal for read processing (cnt_hpd_rd) and count signals for reset processing (cnt_hpd_sha, cnt_hpd_shb), and outputs them to the vertical scanning timing control unit 23. The number of count signals for reset processing may be one or three or more.

[0033] The vertical scanning timing control unit 23 generates a signal for controlling the drive timing of the vertical scanning unit 3 in accordance with the synchronization signal from the synchronization signal generation unit 21 and the count signal from the read row / reset row address generation unit 22, and outputs the signal to the vertical scanning unit 3.

[0034] The column circuit timing control section 24 generates a signal for controlling the drive timing of the column circuit section 5 in accordance with the synchronization signal from the synchronization signal generation section 21 , and outputs the signal to the column circuit section 5 .

[0035] The horizontal scanning timing control section 25 generates a signal for controlling the drive timing of the horizontal scanning section 6 in accordance with the synchronization signal from the synchronization signal generation section 21 , and outputs the signal to the horizontal scanning section 6 .

[0036] Next, a configuration example of the read row / reset row address generation unit 22 in the photoelectric conversion device according to the present embodiment will be described with reference to Fig. 4. Fig. 4 is a block diagram showing a configuration example of the read row / reset row address generation unit in the photoelectric conversion device according to the present embodiment.

[0037] 4, the read row / reset row address generation unit 22 has a horizontal synchronization signal generation unit 221 for read row addresses and a read row address generation unit 222. The read row / reset row address generation unit 22 further has a horizontal synchronization signal generation unit 223 for reset A row addresses, a reset A row address generation unit 224, a horizontal synchronization signal generation unit 225 for reset B row addresses, and a reset B row address generation unit 226. The number of each of the horizontal synchronization signal generation unit for reset row addresses and the reset row address generation units may be one or three or more.

[0038] The horizontal synchronization signal generator 221 for read row address receives the vertical synchronization signal V_RD and the horizontal synchronization signal Hpd supplied from the synchronization signal generator 21, and generates a horizontal synchronization signal Hfd_RD and a count signal cnt_hpd_rd. The horizontal synchronization signal Hfd_RD is a signal generated with a period fd for switching the selection of the floating diffusion unit FD, and is output to the read row address generator 222. Note that the period pd for switching the selection of the photoelectric conversion units PD1 to PD8 is shorter than the period fd for switching the selection of the floating diffusion unit FD. The count signal cnt_hpd_rd is an output signal of a read counter that counts the horizontal synchronization signal Hpd, and is output to the vertical scanning timing controller 23.

[0039] The read row address generation unit 222 receives the horizontal synchronization signal Hfd_RD supplied from the read row address horizontal synchronization signal generation unit 221, generates the address of the row to be read (row address signal addr_rd), and outputs it to the vertical scanning unit 3.

[0040] The reset A row address horizontal synchronization signal generation unit 223 receives the vertical synchronization signal V_SHA and the horizontal synchronization signal Hpd supplied from the synchronization signal generation unit 21, and generates a horizontal synchronization signal Hfd_SHA and a count signal cnt_hpd_sha. The horizontal synchronization signal Hfd_SHA is a signal generated with a period fd for switching the selection of the floating diffusion unit FD, and is output to the reset A row address generation unit 224. The count signal cnt_hpd_sha is an output signal of a reset counter that counts the horizontal synchronization signal Hpd, and is output to the vertical scanning timing control unit 23.

[0041] The reset A row address generation unit 224 receives the horizontal synchronization signal Hfd_SHA supplied from the reset A row address horizontal synchronization signal generation unit 223, generates the address of the row that is the target of the reset A process (row address signal addr_sha), and outputs it to the vertical scanning unit 3.

[0042] The horizontal synchronization signal generator 225 for reset B row address receives the vertical synchronization signal V_SHB and the horizontal synchronization signal Hpd supplied from the synchronization signal generator 21, and generates a horizontal synchronization signal Hfd_SHB and a count signal cnt_hpd_shb. The horizontal synchronization signal Hfd_SHB is a signal generated with a period fd for switching the selection of the floating diffusion unit FD, and is output to the reset B row address generator 226. The count signal cnt_hpd_shb is an output signal of a reset counter that counts the horizontal synchronization signal Hpd, and is output to the vertical scanning timing controller 23.

[0043] The reset B row address generation unit 226 receives the horizontal synchronization signal Hfd_SHB supplied from the reset B row address horizontal synchronization signal generation unit 225, generates the address of the row to be subjected to the reset B process (row address signal addr_shb), and outputs it to the vertical scanning unit 3.

[0044] Next, an example of the operation of the read row / reset row address generation unit 22 in the photoelectric conversion device according to this embodiment will be described with reference to Fig. 5. Fig. 5 is a timing chart showing an example of the operation of the read row / reset row address generation unit 22 in the photoelectric conversion device according to this embodiment.

[0045] First, the operation of generating a read row address (row address signal addr_rd) will be described with reference to FIG.

[0046] At time t100_rd, the vertical synchronization signal V_RD supplied from the synchronization signal generation unit 21 transitions from low level to high level. Then, in response to the vertical synchronization signal V_RD transitioning from low level to high level, the count value of the count signal cnt_hpd_rd is initialized to the value 0.

[0047] At the next time t101_rd, the horizontal synchronization signal Hfd_RD transitions from low level to high level in response to the count value of the count signal cnt_hpd_rd being initialized to value 0. Note that the timing at which the horizontal synchronization signal Hfd_RD transitions from low level to high level does not necessarily have to correspond to the value 0 of the count signal cnt_hpd_rd, and may be configured to be controllable by a register or the like.

[0048] Similarly, at time t101_rd, in response to the horizontal synchronization signal Hfd_RD transitioning from low level to high level, the row address signal addr_rd transitions to a value of 0. The value 0 is a preset setting value, and may be configured to be controllable by a register or the like.

[0049] At the following time t102_rd, the horizontal synchronization signal Hpd supplied from the synchronization signal generating unit 21 transitions from low level to high level. Then, in response to the transition of the horizontal synchronization signal Hpd from low level to high level, the count value of the count signal cnt_hpd_rd counts up and transitions from value 0 to value 1. Thereafter, the count value of the count signal cnt_hpd_rd counts up every time the horizontal synchronization signal Hpd transitions from low level to high level.

[0050] At the following time t103_rd, the horizontal synchronization signal Hpd transitions from low level to high level. If the count value of the count signal cnt_hpd_rd at time t103_rd is 7, then in response to the horizontal synchronization signal Hpd transitioning from low level to high level, the count value of the count signal cnt_hpd_rd is initialized to 0. Note that the timing at which the count value of the count signal cnt_hpd_rd is initialized to 0 does not necessarily have to correspond to the value 7 of the count signal cnt_hpd_rd, and may be configured to be controllable by a register or the like.

[0051] At the following time t104_rd, the count value of the count signal cnt_hpd_rd is initialized to the value 0, and the horizontal synchronization signal Hfd_RD transitions from low level to high level.

[0052] Similarly, at time t104_rd, in response to the horizontal synchronization signal Hfd_RD transitioning from low level to high level, the value of the row address signal addr_rd counts up and transitions from value 0 to value 1. The amount of count up does not necessarily have to be +1, and the signal may be configured to transition to a specific value without counting up. Alternatively, the value of the row address signal addr_rd may be configured to be controllable by a register or the like. Thereafter, the value of the row address signal addr_rd counts up every time the horizontal synchronization signal Hfd_RD transitions from low level to high level. In other words, the update cycle for the value of the row address signal addr_rd is the cycle fd.

[0053] In this driving example, the timing according to the value 7 of the count signal cnt_hpd_rd is the timing for initializing the count value of the count signal cnt_hpd_rd and is the timing for updating the row address signal addr_rd. The value 7 is a set value that specifies the update timing of the row address signal addr_rd.

[0054] Next, the operation of generating the reset A row address (row address signal addr_sha) will be described with reference to FIG.

[0055] At time t100_sha, the vertical synchronization signal V_SHA supplied from the synchronization signal generation unit 21 transitions from low level to high level. Then, in response to the vertical synchronization signal V_SHA transitioning from low level to high level, the count value of the count signal cnt_hpd_sha is initialized to the value 0.

[0056] At the next time t101_sha, the horizontal synchronization signal Hfd_SHA transitions from low level to high level in response to the count value of the count signal cnt_hpd_sha being initialized to value 0. Note that the timing at which the horizontal synchronization signal Hfd_SHA transitions from low level to high level does not necessarily have to correspond to the value 0 of the count signal cnt_hpd_sha, and may be configured to be controllable by a register or the like.

[0057] Similarly, at time t101_sha, the horizontal synchronization signal Hfd_SHA transitions from low to high, causing the row address signal addr_sha to transition to a value of 0. The value 0 is a preset value, and may be configured to be controllable by a register or the like.

[0058] At the following time t102_sha, the horizontal synchronization signal Hpd supplied from the synchronization signal generating unit 21 transitions from low level to high level. Then, in response to the transition of the horizontal synchronization signal Hpd from low level to high level, the count value of the count signal cnt_hpd_sha counts up and transitions from value 0 to value 1. Thereafter, the count value of the count signal cnt_hpd_sha counts up every time the horizontal synchronization signal Hpd transitions from low level to high level.

[0059] At the following time t103_sha, the horizontal synchronization signal Hpd transitions from low level to high level. If the count value of the count signal cnt_hpd_sha at time t103_sha is 7, then in response to the horizontal synchronization signal Hpd transitioning from low level to high level, the count value of the count signal cnt_hpd_sha is initialized to 0. Note that the timing at which the count signal cnt_hpd_sha is initialized to 0 does not necessarily have to correspond to the value 7 of the count signal cnt_hpd_sha, and may be configured to be controllable by a register or the like.

[0060] At the following time t104_sha, the count value of the count signal cnt_hpd_sha is initialized to the value 0, and the horizontal synchronization signal Hfd_SHA transitions from low level to high level.

[0061] Similarly, at time t104_sha, in response to the horizontal synchronization signal Hfd_SHA transitioning from low level to high level, the value of the row address signal addr_sha counts up, transitioning from value 0 to value 1. The amount of count up does not necessarily have to be +1, and the signal may be configured to transition to a specific value without counting up. Alternatively, the value of the row address signal addr_sha may be configured to be controllable by a register or the like. Thereafter, the value of the row address signal addr_sha counts up every time the horizontal synchronization signal Hfd_SHA transitions from low level to high level. In other words, the update cycle for the value of the row address signal addr_sha is the cycle fd.

[0062] In this driving example, the timing according to the value 7 of the count signal cnt_hpd_sha is the timing for initializing the count value of the count signal cnt_hpd_sha and is the timing for updating the row address signal addr_sha. The value 7 is a setting value that specifies the update timing of the row address signal addr_sha.

[0063] Next, the operation of generating the reset B row address (row address signal addr_shb) will be described with reference to FIG.

[0064] At time t100_shb, the vertical synchronization signal V_SHB supplied from the synchronization signal generation unit 21 transitions from low level to high level. Then, in response to the vertical synchronization signal V_SHB transitioning from low level to high level, the count value of the count signal cnt_hpd_shb is initialized to the value 0.

[0065] At the next time t101_shb, the horizontal synchronization signal Hfd_SHB transitions from low level to high level in response to the count value of the count signal cnt_hpd_shb being initialized to value 0. Note that the timing at which the horizontal synchronization signal Hfd_SHB transitions from low level to high level does not necessarily have to correspond to the value 0 of the count signal cnt_hpd_shb, and may be configured to be controllable by a register or the like.

[0066] Similarly, at time t101_shb, in response to the horizontal synchronization signal Hfd_SHB transitioning from low level to high level, the row address signal addr_shb transitions to a value of 0. The value 0 is a preset setting value, and may be configured to be controllable by a register or the like.

[0067] At the following time t102_shb, the horizontal synchronizing signal Hpd supplied from the synchronizing signal generating unit 21 transitions from low level to high level. Then, in response to the transition of the horizontal synchronizing signal Hpd from low level to high level, the count value of the count signal cnt_hpd_shb counts up and transitions from value 0 to value 1. Thereafter, the count value of the count signal cnt_hpd_shb counts up every time the horizontal synchronizing signal Hpd transitions from low level to high level.

[0068] At the following time t103_shb, the horizontal synchronization signal Hpd transitions from low level to high level. If the count value of the count signal cnt_hpd_shb at time t103_shb is 7, then in response to the horizontal synchronization signal Hpd transitioning from low level to high level, the count value of the count signal cnt_hpd_shb is initialized to 0. Note that the timing at which the count value of the count signal cnt_hpd_shb is initialized to 0 does not necessarily have to correspond to the value 7 of the count signal cnt_hpd_shb, and may be configured to be controllable by a register or the like.

[0069] At the following time t104_shb, the count value of the count signal cnt_hpd_shb is initialized to the value 0, and the horizontal synchronization signal Hfd_SHB transitions from low level to high level.

[0070] Similarly, at time t104_shb, in response to the horizontal synchronization signal Hfd_SHB transitioning from low level to high level, the value of the row address signal addr_shb counts up and transitions from value 0 to value 1. The amount of count up does not necessarily have to be +1, and it may be configured to transition to a specific value without counting up. Alternatively, the value of the row address signal addr_shb may be configured to be controllable by a register or the like. Thereafter, the value of the row address signal addr_shb counts up every time the horizontal synchronization signal Hfd_SHB transitions from low level to high level. In other words, the update cycle of the value of the row address signal addr_shb is the cycle fd.

[0071] In this driving example, the timing according to the value 7 of the count signal cnt_hpd_shb is the timing for initializing the count value of the count signal cnt_hpd_shb and is the timing for updating the row address signal addr_shb. The value 7 is a set value that specifies the update timing of the row address signal addr_shb.

[0072] Next, an example of the operation of the vertical scanning timing control section 23 in the photoelectric conversion device according to this embodiment will be described with reference to Fig. 6. Fig. 6 is a timing chart showing an example of the operation of the vertical scanning timing control section 23 in the photoelectric conversion device according to this embodiment.

[0073] The vertical scanning timing control unit 23 generates control signals psel, pres_b, ptx1_rd to ptx8_rd, ptx1_sha to ptx8_sha, and ptx1_shb to ptx8_shb, and outputs them to the vertical scanning unit 3. The vertical scanning timing control unit 23 also generates a readout row memory section control signal, a reset row memory section control signal, and a non-accumulation row memory section control signal, and outputs them to the vertical scanning unit 3. These signals are signals that control the drive timing of the vertical scanning unit 3.

[0074] The control signals psel and pres_b transition to a high level and then to a low level during a 1Hpd period from when the horizontal synchronization signal Hpd transitions to a high level until it transitions to the next high level. Here, the 1Hpd period is a cycle pd for switching the selection of the photoelectric conversion units PD1 to PD8. The timing at which the levels of the control signals psel and pres_b transition is in accordance with a predetermined set value. Note that this set value may be configured to be controllable by a register or the like.

[0075] The control signals ptx1_rd to ptx8_rd transition to a high level and then to a low level during a 1 Hpd period within an 8 Hpd period from when the count value of the count signal cnt_hpd_rd transitions to the value 0 until the next transition to the value 0. The 8 Hpd period here is a cycle fd for switching the selection of the floating diffusion unit FD. The timing at which the levels of the control signals ptx1_rd to ptx8_rd transition is in accordance with a predetermined set value. Note that this set value may be configured to be controllable by a register or the like.

[0076] When the count value of the count signal cnt_hpd_rd is 0, the control signal ptx1_rd transitions to a high level at time t200_rd and transitions to a low level at the following time t201_rd. When the count value of the count signal cnt_hpd_rd is not 0, the control signal ptx1_rd maintains a low level.

[0077] Similarly, when the count value of the count signal cnt_hpd_rd is 1, the control signal ptx2_rd transitions to a high level at time t202_rd and transitions to a low level at the following time t203_rd. When the count value of the count signal cnt_hpd_rd is not 1, the control signal ptx2_rd maintains a low level.

[0078] The same operation is performed sequentially for the control signals ptx3_rd to ptx8_rd. Note that the count value of the count signal cnt_hpd_rd when the level of the control signal ptx1_rd transitions does not need to be 0, and the timing at which the level of the control signal ptx1_rd transitions may be controlled by a register or the like. The same applies to the control signals ptx2_rd to ptx8_rd. Also, the levels of the control signals ptx1_rd to ptx8_rd do not need to transition during different 1 Hpd periods, and multiple control signals ptx#_rd (# is an integer from 1 to 8) may transition during the same 1 Hpd period.

[0079] The control signals ptx1_sha to ptx8_sha transition to a high level and then to a low level during a 1 Hpd period in an 8 Hpd period in which the count value of the count signal cnt_hpd_sha transitions to the value 0 and then transitions to the value 0 again. The operation during the 1 Hpd period is similar to the operation of the control signals ptx1_rd to ptx8_rd.

[0080] The control signals ptx1_shb to ptx8_shb transition to a high level and then to a low level during a 1 Hpd period in an 8 Hpd period in which the count value of the count signal cnt_hpd_shb transitions to the value 0 and then transitions to the value 0 again. The operation during the 1 Hpd period is similar to the operation of the control signals ptx1_rd to ptx8_rd.

[0081] Next, a configuration example of the vertical scanning unit 3 in the photoelectric conversion device according to this embodiment will be described with reference to Fig. 7. Fig. 7 is a block diagram showing a configuration example of the vertical scanning unit 3 in the photoelectric conversion device according to this embodiment.

[0082] As shown in Fig. 7, the vertical scanning unit 3 has an address decoder unit 31 and N / 2 row driving units 32. In the configuration example of Fig. 7, one row driving unit 32 drives two rows, but one row driving unit 32 may drive one row or three or more rows.

[0083] As shown in FIG. 7, the address decoder unit 31 has an RD address decoder unit 31a, an SHA address decoder unit 31b, and an SHB address decoder unit 31c.

[0084] The RD address decoder unit 31a decodes the row address signal addr_rd generated by the control unit 2 to generate decoded signals vaddr_rd(1) to vaddr_rd(N / 2), and outputs them to the corresponding row driving units 32. The row address signal addr_rd is a signal that indicates the row number to be driven in the pixel unit 4, and the decoded signals vaddr_rd(1) to vaddr_rd(N / 2) are signals for selecting the row driving unit 32 that corresponds to the row of the pixel unit 4 to be driven.

[0085] Similarly, the SHA address decoder unit 31b decodes the row address signal addr_sha to generate decoded signals vaddr_sha(1) to vaddr_sha(N / 2) and outputs them to the corresponding row driver units 32. The row address signal addr_sha is a signal that indicates the row number to be driven in the pixel unit 4, and the decoded signals vaddr_sha(1) to vaddr_sha(N / 2) are signals for selecting the row driver unit 32 that corresponds to the row to be driven in the pixel unit 4.

[0086] Moreover, the SHB address decoder unit 31c decodes the row address signal addr_shb to generate decoded signals vaddr_shb(1) to vaddr_shb(N / 2) and outputs them to the corresponding row driver units 32. The row address signal addr_shb is a signal that indicates the row number to be driven in the pixel unit 4, and the decoded signals vaddr_shb(1) to vaddr_shb(N / 2) are signals for selecting the row driver unit 32 that corresponds to the row to be driven in the pixel unit 4.

[0087] 7, each of the row driving units 32 has a readout row memory unit 321, a reset row memory unit 322, a non-accumulation row memory unit 323, and a pixel control signal generation unit 324. The vertical scanning unit 3 is supplied with the various control signals generated in the control unit 2. These control signals are common to the N / 2 row driving units 32.

[0088] In the following description, the configuration of the row driver 32 corresponding to the first and second rows will be mainly described, but the configuration of the row driver 32 corresponding to the other rows is similar.

[0089] The decoded signal vaddr_rd(1) output from the address decoder unit 31 is input to the readout row memory unit 321. The readout row memory unit 321 is controlled by a readout row memory unit control signal and stores the level of the decoded signal vaddr_rd(1). The output signal of the readout row memory unit 321 is a signal for causing the pixels P of the corresponding row to perform a charge read process.

[0090] The decoded signal vaddr_sha(1) and the decoded signal vaddr_shb(1) output from the address decoder unit 31 are input to the reset row memory unit 322. The reset row memory unit 322 is controlled by a reset row memory unit control signal, and stores the level of the decoded signal vaddr_sha(1) and the level of the decoded signal vaddr_shb(1). The output signal of the reset row memory unit 322 is a signal for causing the pixels P of the corresponding row to perform a charge reset process.

[0091] The non-accumulation row memory unit 323 is controlled by a non-accumulation row memory unit control signal, and outputs a signal to cause a pixel P that is not accumulating to perform a charge reset process in accordance with the output of the readout row memory unit 321 and the output of the reset row memory unit 322.

[0092] The pixel control signal generation unit 324 receives signals output from the readout row memory unit 321, the reset row memory unit 322, and the non-accumulation row memory unit 323, and determines whether to perform a readout process, a reset process, or a non-accumulation process for the pixels P in the target row. The pixel control signal generation unit 324 also outputs pixel control signals to the pixels P in the target row in response to the control signals psel, pres_b, ptx1_rd to ptx8_rd, ptx1_sha to ptx8_sha, and ptx1_shb to ptx8_shb. The pixel control signals output from the pixel control signal generation unit 324 are control signals PRES(1), PSEL(1), PTX1(1) to PTX8(1), PRES(2), PSEL(2), and PTX1(2) to PTX8(2).

[0093] Next, an example of the operation of the pixel control signal generation unit 324 and the pixel unit 4 in the photoelectric conversion device according to this embodiment will be described with reference to Figures 8A to 8C. Figures 8A to 8C are timing charts showing an example of the operation of the pixel control signal generation unit 324 and the pixel unit 4 in the photoelectric conversion device according to this embodiment.

[0094] First, the operation of the pixel control signal generation unit 324 and the pixel unit 4 in the readout process will be described with reference to FIG. 8B.

[0095] At time t300_rd, it is assumed that the value of row address signal addr_rd transitions from value (J-1) to value J. As a result, rows 2J and (2J-1) of pixel unit 4 become target rows for readout processing. Rows 2J and (2J-1) of pixel unit 4 perform the same operation, so only the operation in row 2J of pixel unit 4 will be described below.

[0096] The pixel control signals output to the 2Jth row of the pixel unit 4 are control signals PSEL(2J), PRES(2J), and PTX1(2J) to PTX8(2J). The control signal PSEL(2J) is generated in the pixel control signal generation unit 324 using the control signal psel as the original signal. The control signal PRES(2J) is generated in the pixel control signal generation unit 324 using the control signal pres_b as the original signal. The control signals PTX1(2J) to PTX8(2J) are generated in the pixel control signal generation unit 324 using the control signals ptx1_rd to ptx8_rd as the original signals. Since the row address signal addr_rd indicates the value J over an 8Hpd period, the 2Jth row of the pixel unit 4 is the target row for the readout process over an 8Hpd period.

[0097] At the next time t301_rd, when the value of the row address signal addr_rd transitions from value J to value (J+1), the 2Jth row of the pixel unit 4 becomes a non-accumulation row that is the target of the non-accumulation process. In the non-accumulation row, the control signals PTX1 to PTX8 and the control signal PRES are set to a high level to maintain the photoelectric conversion unit PD and the floating diffusion unit FD in a reset state.

[0098] Similarly, at time t301_rd, when the value of row address signal addr_rd transitions from value J to value (J+1), the readout process targets rows (2(J+1)) and (2(J+1)-1) of pixel unit 4. The operations of rows (2(J+1)) and (2(J+1)-1) of pixel unit 4 are similar to the operation of row 2J of pixel unit 4, and therefore will not be described.

[0099] Next, the operations of the pixel control signal generation unit 324 and the pixel unit 4 in the reset A process will be described with reference to FIG. 8A.

[0100] At time t300_sha, it is assumed that the value of row address signal addr_sha transitions from value (I-1) to value I. As a result, the 2Ith row and the (2I-1)th row of pixel unit 4 become target rows for the Reset A process. Since the 2Ith row and the (2I-1)th row of pixel unit 4 perform the same operation, only the operation in the 2Ith row of pixel unit 4 will be described below.

[0101] The pixel control signals output to the 2Ith row of the pixel unit 4 are the control signals PSEL(2I), PRES(2I), and PTX1(2I) to PTX8(2I). Of these, the control signal PSEL(2I) is fixed to a low level, and the control signal PRES(2I) is fixed to a high level. The control signals PTX1(2I) to PTX8(2I) are generated in the pixel control signal generator 324 using the control signals ptx1_sha to ptx8_sha as original signals. Since the row address signal addr_sha indicates the value I over an 8Hpd period, the 2Ith row of the pixel unit 4 is the target row of the reset A process over an 8Hpd period.

[0102] At subsequent time t301_sha, when the value of the row address signal addr_sha transitions from value I to value (I+1), the 2Ith row of the pixel unit 4 enters the accumulation state. In the rows in the accumulation state, the control signals PTX1 to PTX8 are set to low level, and charges are accumulated in the photoelectric conversion units PD.

[0103] Similarly, at time t301_sha, when the value of row address signal addr_sha transitions from value I to value (I+1), the non-accumulation process on row (2(I+1)) and row (2(I+1)-1) of pixel unit 4 is released, and they become the target rows for Reset A process. The operation of row (2(I+1)) and row (2(I+1)-1) of pixel unit 4 is similar to the operation of row 2I of pixel unit 4, so a description thereof will be omitted.

[0104] Next, the operations of the pixel control signal generation unit 324 and the pixel unit 4 in the reset B process will be described with reference to FIG. 8C.

[0105] At time t300_shb, it is assumed that the value of row address signal addr_shb transitions from value (K-1) to value K. As a result, the 2Kth row and the (2K-1)th row of the pixel unit 4 become target rows for the Reset B process. Since the 2Kth row and the (2K-1)th row of the pixel unit 4 perform the same operation, only the operation in the 2Kth row of the pixel unit 4 will be described below.

[0106] The pixel control signals output to the 2Kth row of the pixel unit 4 are the control signals PSEL(2K), PRES(2K), PTX1(2K) to PTX8(2K). Of these, the control signal PSEL(2K) is fixed to a low level, and the control signal PRES(2K) is fixed to a high level. The control signals PTX1(2K) to PTX8(2K) are generated in the pixel control signal generator 324 using the control signals ptx1_shb to ptx8_shb as original signals. Since the row address signal addr_shb indicates the value K over an 8Hpd period, the 2Kth row of the pixel unit 4 is the target row of the reset B process over an 8Hpd period.

[0107] At subsequent time t301_shb, when the value of the row address signal addr_shb transitions from value K to value (K+1), the 2Kth row of the pixel unit 4 enters the accumulation state. In the rows in the accumulation state, the control signals PTX1 to PTX8 are set to low level, and charges are accumulated in the photoelectric conversion units PD.

[0108] Similarly, at time t301_shb, when the value of row address signal addr_shb transitions from value K to value (K+1), the non-accumulation process on row (2(K+1)) and row (2(K+1)-1) of pixel unit 4 is released, and they become the target rows for reset B process. The operation of row (2(K+1)) and row (2(K+1)-1) of pixel unit 4 is similar to the operation of row 2K of pixel unit 4, so a description thereof will be omitted.

[0109] Next, the transition of row addresses during vertical scanning in the photoelectric conversion device according to this embodiment will be described with reference to Fig. 9. Fig. 9 is a timing chart illustrating the transition of row addresses during vertical scanning in the photoelectric conversion device according to this embodiment.

[0110] In the period from time P to time P+7, the FD address (2I-1) and the FD address 2I are the target rows for the reset A process. The FD address (2I-1) and the FD address 2I are the same as the (2I-1)th row and the 2Ith row of the pixel section 4.

[0111] At time P, in the FD address (2I-1) and the FD address 2I, the photoelectric conversion unit PD1 connected via the transfer transistor M1 that receives the control signal PTX1 is selected, and the reset A process is performed.

[0112] At the following time P+1, the photoelectric conversion unit PD2 connected via the transfer transistor M2 that receives the control signal PTX2 is selected in the FD address (2I-1) and the FD address 2I, and the reset A process is performed.

[0113] Thereafter, in the same manner, during the period from time P+2 to time P+7, photoelectric conversion units PD3 to PD8 are selected in sequence at FD address (2I-1) and FD address 2I, and the reset A process is performed.

[0114] When the row address transitions to (I+1) at time P+8, the photoelectric conversion unit PD1 connected via the transfer transistor M1 that receives the control signal PTX1 is selected at FD address (2(I+1)-1) and FD address (2(I+1)), and the reset A processing is performed.

[0115] Similarly, during the period from time P+9 to time P+15, photoelectric conversion units PD2 to PD8 are selected in sequence at FD address (2(I+1)-1) and FD address (2(I+1)), and the reset A process is performed.

[0116] In the period from time P+2 to time P+9, FD address (2J-1) and FD address 2J are the target rows for the read process.

[0117] At time P+2, the photoelectric conversion unit PD1 connected at the FD address (2J-1) and the FD address 2J via the transfer transistor M1 that receives the control signal PTX1 is selected, and a read process is performed.

[0118] Thereafter, in the same manner, during the period from time P+3 to time P+9, the photoelectric conversion units PD2 to PD8 are sequentially selected at the FD address (2J-1) and the FD address 2J, and the readout process is performed.

[0119] When the row address transitions to J+1 at time P+10, the photoelectric conversion unit PD1 connected via the transfer transistor M1 that receives the control signal PTX1 is selected at FD address (2(J+1)-1) and FD address (2(J+1)), and a read process is performed.

[0120] Similarly, during the period from time P+11 to time P+17, photoelectric conversion units PD2 to PD8 are sequentially selected at FD address (2(J+1)-1) and FD address (2(J+1)) and a readout process is performed.

[0121] In the period from time Q to time Q+7, FD address (2I-1) and FD address 2I are the target rows for the read process.

[0122] At time Q, in the FD address (2I-1) and the FD address 2I, the photoelectric conversion unit PD1 connected via the transfer transistor M1 that receives the control signal PTX1 is selected, and a readout process is performed. That is, in the FD address (2I-1) and the FD address 2I, the length of the exposure period of the photoelectric conversion unit PD1 is QP.

[0123] Thereafter, in the same manner, during the period from time Q+1 to time Q+7, the photoelectric conversion units PD2 to PD8 are sequentially selected at the FD address (2I-1) and the FD address 2I, and the readout process is performed.

[0124] Here, the start timing of the readout process and the start timing of the reset A process can be controlled in units of 1 Hpd as described with reference to Fig. 5, so the exposure time of the photoelectric conversion unit PD can be controlled in units of 1 Hpd. The same applies to the reset B process.

[0125] Furthermore, the timing of the level transition of the control signals ptx1_rd to ptx8_rd within a 1 Hpd period and the timing of the level transition of the control signals ptx1_sha to ptx8_sha within a 1 Hpd period can be set independently, as described with reference to Fig. 6. Therefore, the exposure time of the photoelectric conversion unit PD can be controlled in units of 1 Hpd or less. The same applies to the control signals ptx1_shb to ptx8_shb.

[0126] In this embodiment, a horizontal synchronization signal Hpd with a period pd for switching the selection of the photoelectric conversion unit PD to be processed in the readout process and the reset process, and a horizontal synchronization signal Hfd with a period fd for switching the selection of the floating diffusion unit FD to be processed are used. Furthermore, as the horizontal synchronization signal Hfd, a horizontal synchronization signal Hfd_RD, a horizontal synchronization signal Hfd_SHA, and a horizontal synchronization signal Hfd_SHB, which are independent of each other in the readout process, the reset A process, and the reset B process, are used. Since the generation timing of these horizontal synchronization signals Hfd can be controlled in units of 1 Hpd, the setting unit of the update timing of the row address signal addr_rd and the row address signals addr_sha and addr_shb is also 1 Hpd. In other words, the setting unit of the update timing of the row address signals addr_rd, addr_sha, and addr_shb is equal to the length of one period of the period pd. This makes it possible to control the length of the exposure period of the photoelectric conversion unit PD in units of 1 Hpd.

[0127] In addition, in this embodiment, there are count signals cnt_hpd_rd, cnt_hpd_sha, and cnt_hpd_shb that count the horizontal synchronization signal. This allows the control signals ptx1_rd to ptx8_rd, ptx1_sha to ptx8_sha, and ptx1_shb to ptx8_shb to be output in any order. Furthermore, by making the timing of level transitions of the control signals ptx1_rd to ptx8_rd, ptx1_sha to ptx8_sha, and ptx1_shb to ptx8_shb independent within a 1 Hpd period, it is also possible to control the exposure time in units of 1 Hpd or less.

[0128] Therefore, according to this embodiment, in a photoelectric conversion device including pixels P having a plurality of photoelectric conversion units PD sharing a floating diffusion unit FD, it is possible to improve the degree of freedom in setting the exposure time.

[0129] [Second embodiment] A photoelectric conversion device according to a second embodiment of the present invention will be described with reference to Figures 10 to 12. Components similar to those in the photoelectric conversion device according to the first embodiment are given the same reference numerals, and descriptions thereof will be omitted or simplified.

[0130] The photoelectric conversion device according to this embodiment differs from the photoelectric conversion device according to the first embodiment in the configuration of the counter that counts the horizontal synchronization signal Hpd.

[0131] First, a configuration example of the read row / reset row address generation unit 22 in the photoelectric conversion device according to the present embodiment will be described with reference to Fig. 10. Fig. 10 is a block diagram showing a configuration example of the read row / reset row address generation unit 22 in the photoelectric conversion device according to the present embodiment.

[0132] 10, the read row / reset row address generation unit 22 in the photoelectric conversion device according to this embodiment further includes a horizontal synchronization signal count generation unit 227. The horizontal synchronization signal count generation unit 227 receives the vertical synchronization signal V_ORG and the horizontal synchronization signal Hpd supplied from the synchronization signal generation unit 21, and generates a count signal cnt_hpd indicating a count value of the horizontal synchronization signal Hpd. The count signal cnt_hpd is output to the vertical scanning timing control unit 23 and is also supplied to the read row address horizontal synchronization signal generation unit 221, the reset A row address horizontal synchronization signal generation unit 223, and the reset B row address horizontal synchronization signal generation unit 225.

[0133] In this embodiment, the count signal cnt_hpd_rd is not generated in the horizontal synchronization signal generator for read row addresses 221. Similarly, the count signals cnt_hpd_sha and cnt_hpd_shb are not generated in the horizontal synchronization signal generator for reset A row addresses 223 and the horizontal synchronization signal generator for reset B row addresses 225.

[0134] The horizontal synchronization signal count generation unit 227 does not necessarily have to be a part of the read row / reset row address generation unit 22, and may be provided outside the read row / reset row address generation unit 22. For example, the horizontal synchronization signal count generation unit 227 may be included in the synchronization signal generation unit 21. Furthermore, the count signal cnt_hpd may be shared by blocks other than the read row / reset row address generation unit 22 and the vertical scanning timing control unit 23.

[0135] Next, an operation example of the read row / reset row address generation unit 22 in the photoelectric conversion device according to this embodiment will be described with reference to Fig. 11. Fig. 11 is a timing chart showing an operation example of the read row / reset row address generation unit 22 in the photoelectric conversion device according to this embodiment.

[0136] First, the operation of generating the count signal cnt_hpd will be described with reference to FIG. At time t400_cnt, the vertical synchronization signal V_ORG supplied from the synchronization signal generating unit 21 transitions from low level to high level. Then, in response to the vertical synchronization signal V_ORG transitioning from low level to high level, the count signal cnt_hpd is initialized to a value of 0. The value 0 is a preset setting value, and may be configured to be controllable by a register or the like.

[0137] At the next time t401_cnt, the horizontal synchronization signal Hpd supplied from the synchronization signal generating unit 21 transitions from low level to high level. Then, in response to the horizontal synchronization signal Hpd transitioning to high level, the value of the count signal cnt_hpd counts up and transitions from value 0 to value 1. Note that the amount of count up does not necessarily have to be +1, and the signal may be configured to transition to a specific value without counting up. Alternatively, the value of the row address signal addr_rd may be configured to be controllable by a register or the like. Thereafter, the value of the count signal cnt_hpd counts up every time the horizontal synchronization signal Hpd transitions from low level to high level.

[0138] Next, the operation of generating a read row address (row address signal addr_rd) will be described with reference to FIG.

[0139] The row address signal addr_rd is generated by referring to the lowest 3 bits of the count signal cnt_hpd. Note that the bits to be referred to do not have to be the lowest 3 bits, and may be configured to be controllable by a register or the like. Here, the timing according to the value 3 of the lowest 3 bits of the count signal cnt_hpd is assumed to be the update timing of the row address signal addr_rd. The value 3 is a set value that specifies the update timing of the row address signal addr_rd.

[0140] At time t400_rd, the vertical synchronization signal V_RD supplied from the synchronization signal generation unit 21 transitions from low level to high level.

[0141] At the following time t401_rd, the value of the lowest 3 bits of the count signal cnt_hpd transitions to value 3. Then, in response to the transition of the value of the lowest 3 bits of the count signal cnt_hpd to value 3, the horizontal synchronization signal Hfd_RD transitions from low level to high level. Note that the timing at which the horizontal synchronization signal Hfd_RD transitions from low level to high level does not necessarily have to correspond to the value 3 of the lowest 3 bits of the count signal cnt_hpd, and may be configured to be controllable by a register or the like.

[0142] Similarly, at time t401_rd, in response to the horizontal synchronization signal Hfd_RD transitioning from low to high, the row address signal addr_rd transitions to a value of 0. The value 0 is a preset setting value, and may be configured to be controllable by a register or the like.

[0143] At subsequent time t402_rd, the value of the lowest 3 bits of the count signal cnt_hpd transitions to the value 3. Then, in response to the transition of the value of the lowest 3 bits of the count signal cnt_hpd to the value 3, the horizontal synchronization signal Hfd_RD transitions from low level to high level.

[0144] Similarly, at time t402_rd, in response to the horizontal synchronization signal Hfd_RD transitioning from low level to high level, the value of the row address signal addr_rd counts up, transitioning from value 0 to value 1. The amount of count up does not necessarily have to be +1, and the signal may be configured to transition to a specific value without counting up. Alternatively, the value of the row address signal addr_rd may be configured to be controllable by a register or the like. Thereafter, the value of the row address signal addr_rd counts up every time the horizontal synchronization signal Hfd_RD transitions from low level to high level.

[0145] Next, the operation of generating the reset A row address (row address signal addr_sha) will be described with reference to FIG.

[0146] The row address signal addr_sha is generated by referring to the lowest 3 bits of the count signal cnt_hpd. Note that the bits to be referred to do not have to be the lowest 3 bits, and may be configured to be controllable by a register or the like. Here, the timing according to the value 1 of the lowest 3 bits of the count signal cnt_hpd is the update timing of the row address signal addr_sha. The value 1 is a set value that specifies the update timing of the row address signal addr_sha.

[0147] At time t400_sha, the vertical synchronization signal V_SHA supplied from the synchronization signal generation unit 21 transitions from low level to high level.

[0148] At the following time t401_sha, the value of the lowest 3 bits of the count signal cnt_hpd transitions to the value 1. Then, in response to the transition of the value of the lowest 3 bits of the count signal cnt_hpd to the value 1, the horizontal synchronization signal Hfd_SHA transitions from low level to high level. Note that the timing at which the horizontal synchronization signal Hfd_SHA transitions from low level to high level does not necessarily have to correspond to the value 1 of the lowest 3 bits of the count signal cnt_hpd, and may be configured to be controllable by a register or the like.

[0149] Similarly, at time t401_sha, in response to the horizontal synchronization signal Hfd_SHA transitioning from low to high, the row address signal addr_sha transitions to a value of 0. The value 0 is a preset setting value, and may be configured to be controllable by a register or the like.

[0150] At the following time t402_sha, the value of the lowest 3 bits of the count signal cnt_hpd transitions to the value 1. Then, in response to the value of the lowest 3 bits of the count signal cnt_hpd transitioning to the value 1, the horizontal synchronization signal Hfd_SHA transitions from low level to high level.

[0151] Similarly, at time t402_sha, in response to the horizontal synchronization signal Hfd_SHA transitioning from low level to high level, the value of the row address signal addr_sha counts up, transitioning from value 0 to value 1. The amount of count up does not necessarily have to be +1, and the signal may be configured to transition to a specific value without counting up. Alternatively, the value of the row address signal addr_sha may be configured to be controllable by a register or the like. Thereafter, the value of the row address signal addr_sha counts up every time the horizontal synchronization signal Hfd_SHA transitions from low level to high level.

[0152] Next, the operation of generating the reset B row address (row address signal addr_shb) will be described with reference to FIG.

[0153] The row address signal addr_shb is generated by referring to the lowest 3 bits of the count signal cnt_hpd. Note that the bits to be referred to do not have to be the lowest 3 bits, and may be configured to be controllable by a register or the like. Here, the timing according to the value 7 of the lowest 3 bits of the count signal cnt_hpd is the update timing of the row address signal addr_shb. The value 7 is a set value that specifies the update timing of the row address signal addr_shb.

[0154] At time t400_shb, the vertical synchronization signal V_SHB supplied from the synchronization signal generating unit 21 transitions from low level to high level.

[0155] At the following time t401_shb, the value of the lowest 3 bits of the count signal cnt_hpd transitions to the value 7. Then, in response to the transition of the value of the lowest 3 bits of the count signal cnt_hpd to the value 7, the horizontal synchronization signal Hfd_SHB transitions from low level to high level. Note that the timing at which the horizontal synchronization signal Hfd_SHB transitions from low level to high level does not necessarily have to correspond to the value 7 of the lowest 3 bits of the count signal cnt_hpd, and may be configured to be controllable by a register or the like.

[0156] Similarly, at time t401_shb, in response to the horizontal synchronization signal Hfd_SHB transitioning from low level to high level, the row address signal addr_shb transitions to a value of 0. The value 0 is a preset setting value, and may be configured to be controllable by a register or the like.

[0157] At subsequent time t402_shb, the value of the lowest 3 bits of the count signal cnt_hpd transitions to the value 7. Then, in response to the transition of the value of the lowest 3 bits of the count signal cnt_hpd to the value 7, the horizontal synchronization signal Hfd_SHB transitions from low level to high level.

[0158] Similarly, at time t402_shb, in response to the horizontal synchronization signal Hfd_SHB transitioning from low level to high level, the value of the row address signal addr_shb counts up, transitioning from value 0 to value 1. The amount of count up does not necessarily have to be +1, and the signal may be configured to transition to a specific value without counting up. Alternatively, the value of the row address signal addr_shb may be configured to be controllable by a register or the like. Thereafter, the value of the row address signal addr_shb counts up every time the horizontal synchronization signal Hfd_SHB transitions from low level to high level.

[0159] Next, an example of the operation of the vertical scanning timing control section 23 in the photoelectric conversion device according to this embodiment will be described with reference to Fig. 12. Fig. 12 is a timing chart showing an example of the operation of the vertical scanning timing control section 23 in the photoelectric conversion device according to this embodiment.

[0160] The vertical scanning timing control unit 23 generates control signals psel, pres_b, ptx1_rd to ptx8_rd, ptx1_sha to ptx8_sha, and ptx1_shb to ptx8_shb, and outputs them to the vertical scanning unit 3. The vertical scanning timing control unit 23 also generates a readout row memory section control signal, a reset row memory section control signal, and a non-accumulation row memory section control signal, and outputs them to the vertical scanning unit 3. These signals are signals that control the drive timing of the vertical scanning unit 3.

[0161] The control signals psel and pres_b transition to a high level and then to a low level during a 1Hpd period from when the horizontal synchronization signal Hpd transitions to a high level until it transitions to the next high level. Here, the 1Hpd period is a cycle pd for switching the selection of the photoelectric conversion units PD1 to PD8. The timing at which the levels of the control signals psel and pres_b transition is in accordance with a predetermined set value. Note that this set value may be configured to be controllable by a register or the like.

[0162] The control signals ptx1_rd to ptx8_rd transition to a high level and then to a low level during a 1 Hpd period within an 8 Hpd period from when the count signal cnt_hpd transitions to the value 3 until the next transition to the value 3. The 8 Hpd period here is a cycle fd for switching the selection of the floating diffusion unit FD. The timing at which the levels of the control signals ptx1_rd to ptx8_rd transition is in accordance with a predetermined set value. Note that this set value may be configured to be controllable by a register or the like.

[0163] When the count signal cnt_hpd has a value of 3, the control signal ptx1_rd transitions to a high level at time t500_rd and transitions to a low level at the following time t501_rd. When the count signal cnt_hpd does not have a value of 3, the control signal ptx1_rd maintains a low level.

[0164] Similarly, when the count signal cnt_hpd has a value of 4, the control signal ptx2_rd transitions to a high level at time t502_rd and transitions to a low level at the following time t503_rd. When the count signal cnt_hpd does not have a value of 4, the control signal ptx2_rd maintains a low level.

[0165] The same operation is performed sequentially for the control signals ptx3_rd to ptx8_rd. Note that the value of the count signal cnt_hpd when the level of the control signal ptx1_rd transitions does not need to be 3, and the timing at which the level of the control signal ptx1_rd transitions may be controlled by a register or the like. The same applies to the control signals ptx2_rd to ptx8_rd. Also, the levels of the control signals ptx1_rd to ptx8_rd do not need to transition during different 1 Hpd periods, and multiple control signals ptx#_rd (# is an integer from 1 to 8) may transition during the same 1 Hpd period.

[0166] The control signals ptx1_sha to ptx8_sha transition to a high level and then to a low level during a 1 Hpd period in an 8 Hpd period in which the count signal cnt_hpd transitions from one value to the next to the value 1. The operation during the 1 Hpd period is similar to the operation of the control signals ptx1_rd to ptx8_rd.

[0167] The control signals ptx1_shb to ptx8_shb transition to a high level and then to a low level during a 1 Hpd period in an 8 Hpd period in which the count signal cnt_hpd transitions from the value 7 to the value 7 again. The operation during the 1 Hpd period is similar to the operation of the control signals ptx1_rd to ptx8_rd.

[0168] In this manner, in this embodiment, the count signal cnt_hpd is used as the output signal of the counter that counts the horizontal synchronization signal Hpd, instead of the count signals cnt_hpd_rd, cnt_hpd_sha, and cnt_hpd_shb.

[0169] Therefore, according to this embodiment, it is not necessary to control a plurality of counters, and therefore in addition to the effect of the first embodiment, it is possible to reduce the circuit scale.

[0170] [Third embodiment] A photoelectric conversion device according to a third embodiment of the present invention will be described with reference to Figures 13 to 14. Components similar to those of the photoelectric conversion devices according to the first and second embodiments are given the same reference numerals, and descriptions thereof will be omitted or simplified.

[0171] The photoelectric conversion device according to this embodiment differs from the photoelectric conversion device according to the first embodiment in the configuration of the counter that counts the horizontal synchronization signal Hpd.

[0172] First, a configuration example of a pixel P in a photoelectric conversion device according to this embodiment will be described with reference to Fig. 13. Fig. 13 is a circuit diagram showing a configuration example of a pixel P in a photoelectric conversion device according to this embodiment. Fig. 13 shows only the configuration of pixel P(m,n) arranged in the mth column and nth row among the pixels P constituting the pixel section 4, but the configuration of the other pixels P is similar.

[0173] Each pixel P may be composed of photoelectric conversion units PD1a to PD8a, PD1b to PD8b, transfer transistors M1a to M8a, M1b to M8b, a reset transistor M9, an amplification transistor M10, and a selection transistor M11. The photoelectric conversion unit PD1a and the photoelectric conversion unit PD2b form a pair that shares one microlens, and receive light that has passed through different pupil regions. The same is true for each pair of photoelectric conversion units PD2a, PD2b to PD8a, and PD8b. The transfer transistors M1a to M8a, M1b to M8b are provided corresponding to each of the photoelectric conversion units PD1a to PD8a, PD1b to PD8b. That is, the anode of the photodiode constituting the photoelectric conversion unit PD1a is connected to the ground node, and the cathode is connected to the source of the transfer transistor M1a. The photodiode constituting the photoelectric conversion unit PD1b has an anode connected to the ground node and a cathode connected to the source of the transfer transistor M1b. The same is true for the photoelectric conversion units PD2a, PD2b to PD8a, and PD8b. The drains of the transfer transistors M1a to M8a, and M1b to M8b are connected to the floating diffusion unit FD.

[0174] In the case of the pixel configuration shown in FIG. 13, each of the control lines arranged in each row of the pixel section 4 includes 16 transfer gate signal lines corresponding to each of the transfer transistors M1a, M1b to M8a, and M8b, a reset signal line, and a selection signal line. Each of the transfer gate signal lines in the nth row supplies a corresponding control signal among the control signals PTX1a(n), PTX1b(n) to PTX8a(n), and PTX8b(n) to the gate of the corresponding transfer transistor among the transfer transistors M1a, M1b to M8a, and M8b. For example, the transfer gate signal line corresponding to the transfer transistor M1a of the pixel P in the nth row supplies a control signal PTX1a(n) output from the vertical scanning unit 3 to the gate of the transfer transistor M1a of the pixel P in the nth row. The transfer gate signal line corresponding to the transfer transistor M1b of the pixel P in the nth row supplies a control signal PTX1b(n) output from the vertical scanning unit 3 to the gate of the transfer transistor M1b of the pixel P in the nth row. The same is true for the transfer gate signal lines corresponding to the transfer transistors M2a, M2b to M8a, M8b of the pixels P in the nth row. The reset signal line of the nth row supplies a control signal PRES(n) output from the vertical scanning unit 3 to the gate of the reset transistor M9 of the pixel P in the nth row. The selection signal line of the nth row supplies a control signal PSEL(n) output from the vertical scanning unit 3 to the gate of the selection transistor M11 of the pixel P in the nth row. A common control signal is supplied from the vertical scanning unit 3 to the pixels P in the same row.

[0175] Next, an operation example of the read row / reset row address generation unit 22 in the photoelectric conversion device according to this embodiment will be described with reference to Fig. 14. Fig. 14 is a timing chart showing an operation example of the read row / reset row address generation unit 22 in the photoelectric conversion device according to this embodiment. Note that a description of the generation operation of the row address signal addr_shb will be omitted.

[0176] In this embodiment, two types of set values ​​are provided for the timing at which the value of the count signal cnt_hpd_# (# is rd or sha) is initialized to the value 0, and one of the set values ​​is selected and used for each row address. Note that there may be three or more types of set values, and a configuration may be adopted in which they can be controlled by a register or the like.

[0177] First, the operation of generating a read row address (row address signal addr_rd) will be described with reference to Fig. 14. In this embodiment, the timing at which the count signal cnt_hd_rd is initialized to the value 0 has two set values: a value of 7 and a value of 15. The timing according to these set values ​​becomes the update timing of the row address signal addr_rd. However, the timing at which the count signal cnt_hd_rd is initialized to the value 0 does not necessarily have to be the value 7 or the value 15.

[0178] At time t600_rd, when the horizontal synchronization signal Hpd transitions from low level to high level, the count value of the count signal cnt_hpd_rd is 7. In response to the horizontal synchronization signal Hpd transitioning from low level to high level, the count value of the count signal cnt_hpd_rd is initialized to 0. Then, in response to the count value of the count signal cnt_hpd_rd being initialized to 0, the horizontal synchronization signal Hfd_RD transitions from low level to high level. As a result, the row address signal addr_rd counts up and transitions to the value J.

[0179] At the next time t601_rd, when the horizontal synchronization signal Hpd transitions from low level to high level, the count value of the count signal cnt_hpd_rd counts up again to a value of 7. In response to the horizontal synchronization signal Hpd transitioning from low level to high level, the count value of the count signal cnt_hpd_rd is initialized to a value of 0. Then, in response to the count value of the count signal cnt_hpd_rd being initialized to a value of 0, the horizontal synchronization signal Hfd_RD transitions from a low level to a high level. As a result, the row address signal addr_rd counts up and transitions from a value J to a value J+1.

[0180] At the next time t602_rd, when the horizontal synchronization signal Hpd transitions from low level to high level, the count value of the count signal cnt_hpd_rd counts up to a value of 15. In response to the horizontal synchronization signal Hpd transitioning from low level to high level, the count value of the count signal cnt_hpd_rd is initialized to a value of 0. Then, in response to the count value of the count signal cnt_hpd_rd being initialized to a value of 0, the horizontal synchronization signal Hfd_RD transitions from a low level to a high level. As a result, the row address signal addr_rd counts up and transitions from a value J+1 to a value J+2.

[0181] In this manner, in the readout scan, vertical scanning is performed while switching the period fd for switching the floating diffusion portion FD between 8 Hpd and 16 Hpd for each row address.

[0182] Next, the operation of generating the reset A row address (row address signal addr_sha) will be described with reference to Fig. 14. In this embodiment, the timing at which the count signal cnt_hd_sha is initialized to the value 0 has two set values: a value of 7 and a value of 15. The timing according to these set values ​​becomes the update timing of the row address signal addr_sha. However, the timing at which the count signal cnt_hd_sha is initialized to the value 0 does not necessarily have to be the value 7 or the value 15.

[0183] At time t600_sha, when the horizontal synchronization signal Hpd transitions from low level to high level, the count value of the count signal cnt_hpd_sha is 7. In response to the horizontal synchronization signal Hpd transitioning from low level to high level, the count value of the count signal cnt_hpd_sha is initialized to 0. Then, in response to the count value of the count signal cnt_hpd_sha being initialized to 0, the horizontal synchronization signal Hfd_SHA transitions from low level to high level. As a result, the row address signal addr_sha counts up and transitions to the value I.

[0184] At the next time t601_sha, when the horizontal synchronization signal Hpd transitions from low level to high level, the count value of the count signal cnt_hpd_sha counts up again to a value of 7. In response to the horizontal synchronization signal Hpd transitioning from low level to high level, the count value of the count signal cnt_hpd_sha is initialized to a value of 0. Then, in response to the count value of the count signal cnt_hpd_sha being initialized to a value of 0, the horizontal synchronization signal Hfd_SHA transitions from a low level to a high level. As a result, the row address signal addr_sha counts up and transitions from a value I to a value I+1.

[0185] At the next time t602_sha, when the horizontal synchronization signal Hpd transitions from low level to high level, the count value of the count signal cnt_hpd_sha counts up to a value of 15. In response to the horizontal synchronization signal Hpd transitioning from low level to high level, the count value of the count signal cnt_hpd_sha is initialized to a value of 0. Then, in response to the count value of the count signal cnt_hpd_sha being initialized to a value of 0, the horizontal synchronization signal Hfd_SHA transitions from a low level to a high level. As a result, the row address signal addr_sha counts up and transitions from a value I+1 to a value I+2.

[0186] In this manner, in the reset scan, vertical scanning is performed while switching the cycle fd for switching the floating diffusion portion FD between 8 Hpd and 16 Hpd for each row address.

[0187] Next, an example of the operation of the pixel control signal generation unit 324 and the pixel unit 4 in the photoelectric conversion device according to this embodiment will be described with reference to Fig. 15A to Fig. 15C. Fig. 15A to Fig. 15C are timing charts showing an example of the operation of the pixel control signal generation unit 324 and the pixel unit 4 in the photoelectric conversion device according to this embodiment. Note that in this embodiment, each control signal PTX# (# is an integer from 1 to 8) is divided into a control signal PTX#a and a control signal PTX#b.

[0188] First, the operations of the pixel control signal generation unit 324 and the pixel unit 4 in the readout process will be described with reference to FIGS. 15A and 15C.

[0189] At time t700_rd, it is assumed that the value of the row address signal addr_rd transitions from value (J-1) to value J. As a result, the 2Jth and (2J-1)th rows of the pixel section 4 become target rows for the readout process.

[0190] The pixel control signals output to the 2Jth row of the pixel unit 4 are control signals PSEL(2J), PRES(2J), PTX1a(2J) to PTX8a(2J), and PTX1b(2J) to PTX8b(2J). The control signal PSEL(2J) is generated in the pixel control signal generation unit 324 using the control signal psel as the original signal. The control signal PRES(2J) is generated in the pixel control signal generation unit 324 using the control signal pres_b as the original signal. The control signals PTX1a(2J) to PTX8a(2J) are generated in the pixel control signal generation unit 324 using the control signals ptx1a_rd to ptx8a_rd as the original signals. The control signals PTX1b(2J) to PTX8b(2J) are generated in the pixel control signal generation unit 324 using the control signals ptx1b_rd to ptx8b_rd as the original signals. Since the row address signal addr_rd indicates the value J for an 8 Hpd period, the 2Jth row of the pixel section 4 is the target row for the readout process for an 8 Hpd period.

[0191] At the following time t701_rd, the control signals ptx1a and ptx1b transition from low to high, and at the following time t702_rd, the control signals ptx1a and ptx1b transition from high to low. Thereafter, the same operation is performed over 8 Hpd.

[0192] At the next time t703_rd, when the value of the row address signal addr_rd transitions from value J to value (J+1), the 2Jth row of the pixel unit 4 becomes a non-accumulation row that is the target of the non-accumulation process, and the 2(J+1)th row and the 2(J+1)-1th row of the pixel unit 4 become target rows for the readout process. In the non-accumulation rows, the photoelectric conversion unit PD and the floating diffusion unit FD are maintained in a reset state by setting the control signals PTX1a to PTX8a, the control signals PTX1b to PTX8b, and the control signal PRES to a high level. Since the row address signal addr_rd indicates the value J+1 for a period of 16 Hpd from time t703_rd to time t708_rd, the 2(J+1)th row of the pixel unit 4 becomes a target row for the readout process for the period of 16 Hpd.

[0193] At the following time t704_rd, the control signal ptx1a transitions from low to high, and at the following time t705_rd, the control signal ptx1a transitions from high to low. At the following time t706_rd, the control signals ptx1a and ptx1b transition from low to high, and at the following time t707_rd, the control signals ptx1a and ptx1b transition from high to low. Thereafter, the same operation is performed every 2 Hpd over 16 Hpd.

[0194] Next, the operations of the pixel control signal generation unit 324 and the pixel unit 4 in the reset A process will be described with reference to FIGS. 15A and 15B.

[0195] At time t700_sha, it is assumed that the value of the row address signal addr_sha transitions from value (I-1) to value I. As a result, the 2Ith row and the (2I-1)th row of the pixel unit 4 become target rows for the reset A process.

[0196] The pixel control signals output to the 2Jth row of the pixel unit 4 are the control signals PSEL(2I), PRES(2I), PTX1a(2I) to PTX8a(2I), and PTX1b(2I) to PTX8b(2I). Of these, the control signal PSEL(2I) is fixed to a low level, and the control signal PRES(2I) is fixed to a high level. The control signals PTX1a(2I) to PTX8a(2I) are generated in the pixel control signal generation unit 324 using the control signals ptx1a_sha to ptx8a_sha as original signals. The control signals PTX1b(2I) to PTX8b(2I) are generated in the pixel control signal generation unit 324 using the control signals ptx1b_sha to ptx8b_sha as original signals. Since the row address signal addr_sha indicates the value I over the 16 Hpd period from time t700_sha to time t705_sha, the 2Ith row of the pixel section 4 becomes a target row for the reset A process over the 16 Hpd period.

[0197] At the following time t701_sha, the control signal ptx1a transitions from low to high, and at the following time t702_sha, the control signal ptx1a transitions from high to low. At the following time t703_sha, the control signals ptx1a and ptx1b transition from low to high, and at the following time t704_sha, the control signals ptx1a and ptx1b transition from high to low. Thereafter, the same operation is performed every 2 Hpd over 16 Hpd.

[0198] At the following time t705_sha, when the value of the row address signal addr_sha transitions from value I to value (I+1), the 2Ith row of the pixel unit 4 enters the accumulation state, and the non-accumulation processing of the (2(I+1))th row and the (2(I+1)-1)th row of the pixel unit 4 is released. As a result, the (2(I+1))th row and the (2(I+1)-1)th row of the pixel unit 4 become the target rows for the Reset A processing. Because the row address signal addr_sha indicates a value (I+1) over the 8Hpd period from time t705_sha to time t708_sha, the 2(I+1)th row of the pixel unit 4 becomes the target row for the Reset A processing over the 8Hpd period.

[0199] At the following time t706_sha, the control signals ptx1a and ptx1b transition from low to high, and at the following time t707_sha, the control signals ptx1a and ptx1b transition from high to low. Thereafter, the same operation is performed over 8 Hpd.

[0200] Next, the transition of row addresses during vertical scanning in the photoelectric conversion device according to this embodiment will be described with reference to Figures 16A and 16B. Figures 16A and 16B are timing charts illustrating the transition of row addresses during vertical scanning in the photoelectric conversion device according to this embodiment.

[0201] In the period from time P to time P+15, FD address (2I-1) and FD address 2I are the target rows for the reset A process. Note that FD address (2I-1) and FD address (2I) are the same as the (2I-1)th row and the 2Ith row of the pixel unit 4.

[0202] At time P, the photoelectric conversion unit PD1a connected at the FD address (2I-1), 2I via the transfer transistor M1a receiving the control signal PTX1a is selected, and the reset A process is performed. In addition, at the following time P+1, the photoelectric conversion units PD1a and PD1b connected at the FD address (2I-1), 2I via the transfer transistors M1a and M1b receiving the control signals PTX1a and PTX1b are selected, and the reset A process is performed.

[0203] At time P+2, the photoelectric conversion unit PD2a connected at the FD address (2I-1), 2I via the transfer transistor M2a receiving the control signal PTX2a is selected, and the reset A process is performed. In the following period of time P+3, the photoelectric conversion units PD2a and PD2b connected at the FD address (2I-1), 2I via the transfer transistors M2a and M2b receiving the control signals PTX2a and PTX2b are selected, and the reset A process is performed.

[0204] Thereafter, in the same manner, during the period from time P+4 to time P+15, the photoelectric conversion units PD3a, PD3b to PD8a, PD8b are successively selected at the FD addresses (2I-1) and 2I, and the reset A process is performed.

[0205] At the next time P+16, the row address transitions to I+1. During the period from time P+16 to time P+23, FD address (2(I+1)-1) and FD address (2(I+1)) are subject to the reset A process.

[0206] At time P+16, at FD addresses (2(I+1)-1), (2(I+1)), photoelectric conversion units PD1a and PD1b connected via transfer transistors M1a and M1b receiving control signals PTX1a and PTX1b are selected, and reset A processing is performed.

[0207] Similarly, during the period from time P+17 to time P+23, photoelectric conversion units PD2a, PD2b to PD8a, PD8b are selected in sequence at FD addresses (2(I+1)-1), (2(I+1)), and the reset A process is performed.

[0208] In the period from time P+2 to time P+9, FD address (2J-1) and FD address 2J are the target rows for the read process.

[0209] At time P+2, the photoelectric conversion units PD1a and PD1b connected via the transfer transistors M1a and M1b that receive the control signals PTX1a and PTX1b at the FD address (2J-1) and the FD address 2J are selected, and a read process is performed.

[0210] Thereafter, in a similar manner, during the period from time P+3 to time P+9, the photoelectric conversion units PD2a, PD2b to PD8a, PD8b are sequentially selected at FD address (2J-1) and FD address 2J, and a readout process is performed.

[0211] At the following time P+10, the row address transitions from J to J+1. During the period from time P+10 to time P+25, FD address (2(J+1)-1) and FD address (2(J+1)) become the target rows for the read process.

[0212] At time P+10, the photoelectric conversion unit PD1a connected at FD address (2(J+1)-1), (2(J+1)) via the transfer transistor M1a receiving the control signal PTX1a is selected, and a readout process is performed. Also, at the following time P+11, the photoelectric conversion units PD1a and PD1b connected at FD address (2(J+1)-1), (2(J+1)) via the transfer transistors M1a and M1b receiving the control signals PTX1a and PTX1b are selected, and a readout process is performed.

[0213] Similarly, during the period from time P+12 to time P+25, photoelectric conversion units PD2a, PD2b to PD8a, PD8b are sequentially selected at FD address (2(J+1)-1) and FD address (2(J+1)), and a readout process is performed.

[0214] In the period from time Q to time Q+15, FD address (2I-1) and FD address 2I are the target rows for the read process.

[0215] At time Q, the photoelectric conversion unit PD1a connected at the FD address (2I-1) and the FD address 2I via the transfer transistor M1a receiving the control signal PTX1a is selected, and a readout process is performed. In addition, at the following time Q+1, the photoelectric conversion units PD1a and PD1b connected at the FD address (2I-1) and the FD address 2I via the transfer transistors M1a and M1b receiving the control signals PTX1a and PTX1b are selected, and a readout process is performed. That is, at the FD address (2I-1) and the FD address 2I, the length of the exposure period of the photoelectric conversion units PD1a and PD1b is QP.

[0216] Thereafter, in a similar manner, during the period from time Q+2 to time Q+15, the photoelectric conversion units PD2a, PD2b to PD8a, PD8b are selected in sequence at FD address (2I-1) and FD address 2I, and a readout process is performed.

[0217] As described with reference to FIG. 14, by providing two different set values ​​for the timing at which the count signal cnt_hpd_# (# is rd or sha) is initialized to the value 0, vertical scanning with a higher degree of freedom can be realized.

[0218] As described above, according to the present embodiment, by changing the operation of the counter that counts the horizontal synchronization signal Hpd, it is possible to realize vertical scanning with a higher degree of freedom, for example, by switching the drive in units of the floating diffusion unit FD.

[0219] Therefore, according to this embodiment, in a photoelectric conversion device including pixels P having a plurality of photoelectric conversion units PD sharing a floating diffusion unit FD, it is possible to improve the degree of freedom in setting the exposure time.

[0220] [Fourth embodiment] A photoelectric conversion device according to a fourth embodiment of the present invention will be described with reference to Fig. 17 to Fig. 19B. The same components as those in the photoelectric conversion device according to the first embodiment are given the same reference numerals, and the description will be omitted or simplified.

[0221] In the photoelectric conversion device according to the present embodiment, the configuration of the pixel unit 4 is the same as that of the third embodiment, but the configuration of the counter that counts the horizontal synchronization signal Hpd is different from that of the photoelectric conversion device according to the third embodiment.

[0222] First, an operation example of the read row / reset row address generation unit 22 in the photoelectric conversion device according to this embodiment will be described with reference to Fig. 17. Fig. 17 is a timing chart showing an operation example of the read row / reset row address generation unit 22 in the photoelectric conversion device according to this embodiment. Note that a description of the generation operation of the row address signals addr_sha and addr_shb will be omitted.

[0223] In this embodiment, there is one set value for the timing at which the count value of the count signal cnt_hpd_rd is initialized to the value 0. In the third embodiment, two timings, a value of 7 and a value of 15, were set for the timing at which the count signal cnt_hd_rd was initialized to the value 0, but in this embodiment, a value of 11 is set. Note that there may be two or more set values, and the configuration may be such that they can be controlled by a register or the like.

[0224] The operations of the count signal cnt_hpd_rd and the row address signal addr_rd are similar to those in the third embodiment, and therefore will not be described.

[0225] Next, an example of the operation of the pixel control signal generation unit 324 and the pixel unit 4 in the photoelectric conversion device according to this embodiment will be described with reference to Fig. 18A to Fig. 18C. Fig. 18A to Fig. 18C are timing charts showing an example of the operation of the pixel control signal generation unit 324 and the pixel unit 4 in the photoelectric conversion device according to this embodiment. Note that the operation of the pixel control signal generation unit 324 and the pixel unit 4 in the readout process will be described here, and the operation of the pixel control signal generation unit 324 and the pixel unit 4 in the reset A process and the reset B process will not be described.

[0226] At time t800_rd, it is assumed that the value of row address signal addr_rd transitions from value (J-1) to value J. As a result, the 2Jth and (2J-1)th rows of the pixel section 4 become target rows for readout processing.

[0227] During a 2 Hpd period from time t800_rd to time t801_rd, the control signal PTX1a is set to a high level to put the transfer transistor M1a into a conductive state, and then the control signals PTX1a and PTX1b are set to a high level to put the transfer transistors M1a and M1b into a conductive state.

[0228] During the subsequent 1 Hpd period from time t801_rd to time t802_rd, the control signals PTX2a and PTX2b are set to a high level to bring the transfer transistors M2a and M2b into a conductive state.

[0229] During the subsequent 1 Hpd period from time t802_rd to time t803_rd, the control signals PTX3a and PTX3b are set to a high level to put the transfer transistors M3a and M3b into a conductive state.

[0230] During the subsequent 2 Hpd period from time t803_rd to time t804_rd, the control signal PTX4a is set to a high level to put the transfer transistor M4a into a conductive state, and then the control signals PTX4a and PTX4b are set to a high level to put the transfer transistors M4a and M4b into a conductive state.

[0231] During the subsequent 4 Hpd period from time t804_rd to time t805_rd, the transfer transistors M5a, M5b to M8a, M8b are driven in the same manner as in the 4 Hpd period from time t800_rd to time t803_rd.

[0232] In this manner, in this embodiment, the driving is switched in a staggered manner in units of photoelectric conversion units PD. Note that it is not necessarily required to switch the driving in a staggered manner in units of photoelectric conversion units PD, and for example, the driving may be switched in alternating rows in units of photoelectric conversion units PD, in units of photoelectric conversion units PD, or in alternating rows and columns in units of photoelectric conversion units PD.

[0233] Furthermore, at time t805_rd, when the value of row address signal addr_rd transitions to value J+1, the (2(J+1))th and (2(J+1)-1)th rows of the pixel section 4 become target rows for readout processing. Thereafter, vertical scanning is performed while driving the pixels in the same manner.

[0234] Next, the transition of row addresses during vertical scanning of the photoelectric conversion device according to this embodiment will be described with reference to Figures 19A and 19B. Figures 19A and 19B are timing diagrams for explaining the transition of row addresses during vertical scanning of the photoelectric conversion device according to this embodiment. In this embodiment, as described with reference to Figures 18A to 18C, vertical scanning is performed while switching the drive in a staggered pattern in units of PD. The transition of row addresses during vertical scanning is the same as in the third embodiment, so a description thereof will be omitted.

[0235] As described above, according to the present embodiment, by changing the operation of the counter that counts the horizontal synchronization signal Hpd, it is possible to realize vertical scanning with a higher degree of freedom, such as switching the drive in units of photoelectric conversion units PD.

[0236] Therefore, according to this embodiment, in a photoelectric conversion device including pixels P having a plurality of photoelectric conversion units PD sharing a floating diffusion unit FD, it is possible to improve the degree of freedom in setting the exposure time.

[0237] [Fifth embodiment] An imaging system according to a fifth embodiment of the present invention will be described with reference to Fig. 20. Fig. 20 is a block diagram showing a schematic configuration of the imaging system according to this embodiment.

[0238] The photoelectric conversion device 100 described in the first to fourth embodiments can be applied to various imaging systems. Examples of the applicable imaging systems include digital still cameras, digital camcorders, security cameras, copiers, fax machines, mobile phones, car-mounted cameras, and observation satellites. Camera modules equipped with an optical system such as a lens and an imaging device are also included in the imaging system. FIG. 20 illustrates a block diagram of a digital still camera as an example of these.

[0239] 20 includes an imaging device 201, a lens 202 that forms an optical image of a subject on the imaging device 201, an aperture 204 that varies the amount of light passing through the lens 202, and a barrier 206 that protects the lens 202. The lens 202 and the aperture 204 form an optical system that focuses light on the imaging device 201. The imaging device 201 is the photoelectric conversion device 100 described in any one of the first to fourth embodiments, and converts the optical image formed by the lens 202 into image data.

[0240] The imaging system 200 also includes a signal processing unit 208 that processes an output signal output from the imaging device 201. The signal processing unit 208 generates image data from a digital signal output from the imaging device 201. The signal processing unit 208 also performs various corrections and compression as necessary to output image data. The imaging device 201 may include an AD conversion unit that generates a digital signal to be processed by the signal processing unit 208. The AD conversion unit may be formed in a semiconductor layer (semiconductor substrate) in which a photoelectric conversion unit of the imaging device 201 is formed, or may be formed in a semiconductor substrate different from the semiconductor layer in which the photoelectric conversion unit of the imaging device 201 is formed. The signal processing unit 208 may also be formed in the same semiconductor substrate as the imaging device 201.

[0241] The imaging system 200 further includes a memory unit 210 for temporarily storing image data, and an external interface unit (external I / F unit) 212 for communicating with an external computer or the like. The imaging system 200 further includes a recording medium 214 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 216 for recording or reading out on the recording medium 214. The recording medium 214 may be built into the imaging system 200, or may be removable.

[0242] Furthermore, the imaging system 200 has an overall control / calculation unit 218 that performs various calculations and controls the entire digital still camera, and a timing generation unit 220 that outputs various timing signals to the imaging device 201 and the signal processing unit 208. Here, the timing signals and the like may be input from outside, and the imaging system 200 only needs to have at least the imaging device 201 and the signal processing unit 208 that processes the output signal output from the imaging device 201.

[0243] The imaging device 201 outputs an imaging signal to the signal processing unit 208. The signal processing unit 208 performs predetermined signal processing on the imaging signal output from the imaging device 201, and outputs image data. The signal processing unit 208 generates an image using the imaging signal.

[0244] In this way, according to this embodiment, it is possible to realize an imaging system to which the photoelectric conversion device 100 according to the first to fifth embodiments is applied.

[0245] [Sixth embodiment] An imaging system and a moving object according to a sixth embodiment of the present invention will be described with reference to Fig. 21. Fig. 21 is a diagram showing the configuration of an imaging system and a moving object according to this embodiment.

[0246] FIG. 21(a) shows an example of an imaging system related to an on-vehicle camera. The imaging system 300 has an imaging device 310. The imaging device 310 is the photoelectric conversion device 100 described in any one of the first to fourth embodiments. The imaging system 300 has an image processing unit 312 that performs image processing on a plurality of image data acquired by the imaging device 310, and a parallax acquisition unit 314 that calculates parallax (phase difference of parallax images) from the plurality of image data acquired by the imaging system 300. The imaging system 300 also has a distance acquisition unit 316 that calculates a distance to an object based on the calculated parallax, and a collision determination unit 318 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are examples of distance information acquisition means that acquire distance information to the object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 318 may determine the possibility of a collision using any of these distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination of these.

[0247] The imaging system 300 is connected to a vehicle information acquisition device 320, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The imaging system 300 is also connected to a control ECU 330, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the judgment result of the collision judgment unit 318. The imaging system 300 is also connected to an alarm device 340 that issues an alarm to the driver based on the judgment result of the collision judgment unit 318. For example, when the judgment result of the collision judgment unit 318 indicates that there is a high possibility of a collision, the control ECU 330 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 340 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., and vibrating the seat belt or steering wheel.

[0248] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the imaging system 300. Fig. 21(b) shows an imaging system for imaging the area in front of the vehicle (imaging range 350). The vehicle information acquisition device 320 sends instructions to the imaging system 300 or the imaging device 310. This configuration can further improve the accuracy of distance measurement.

[0249] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from lanes, etc. Furthermore, the imaging system is not limited to vehicles such as the vehicle itself, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to moving bodies, but also to devices that use object recognition widely, such as intelligent transport systems (ITS).

[0250] [Seventh embodiment] A device according to a seventh embodiment of the present invention will be described with reference to Fig. 22. Fig. 22 is a block diagram showing a schematic configuration of the device according to this embodiment.

[0251] FIG. 22 is a schematic diagram showing an apparatus EQP including a photoelectric conversion device APR. The photoelectric conversion device APR has the functions of the photoelectric conversion device 100 according to any one of the first to fourth embodiments. All or a part of the photoelectric conversion device APR is a semiconductor device IC. The photoelectric conversion device APR of this example can be used as, for example, an image sensor, an AF (Auto Focus) sensor, a photometry sensor, or a distance measurement sensor. The semiconductor device IC has a pixel area PX in which pixel circuits PXC including photoelectric conversion units are arranged in a matrix. The semiconductor device IC can have a peripheral area PR around the pixel area PX. Circuits other than pixel circuits can be arranged in the peripheral area PR.

[0252] The photoelectric conversion device APR may have a structure (a chip stacking structure) in which a first semiconductor chip provided with a plurality of photoelectric conversion units and a second semiconductor chip provided with peripheral circuits are stacked. The peripheral circuits in the second semiconductor chip may be column circuits corresponding to the pixel columns of the first semiconductor chip. The peripheral circuits in the second semiconductor chip may be matrix circuits corresponding to the pixels or pixel blocks of the first semiconductor chip. The first and second semiconductor chips may be connected to each other by through-hole vias (TSVs), inter-chip wiring by direct bonding of a conductor such as copper, connection by microbumps between chips, connection by wire bonding, or the like.

[0253] The photoelectric conversion device APR may include a package PKG that houses the semiconductor device IC in addition to the semiconductor device IC. The package PKG may include a base to which the semiconductor device IC is fixed, a cover such as glass that faces the semiconductor device IC, and connection members such as bonding wires and bumps that connect terminals provided on the base and terminals provided on the semiconductor device IC.

[0254] The equipment EQP may further include at least one of an optical device OPT, a control device CTRL, a processing device PRCS, a display device DSPL, a memory device MMRY, and a mechanical device MCHN. The optical device OPT corresponds to the photoelectric conversion device APR as a photoelectric conversion device, and is, for example, a lens, a shutter, or a mirror. The control device CTRL controls the photoelectric conversion device APR, and is, for example, a semiconductor device such as an ASIC. The processing device PRCS processes a signal output from the photoelectric conversion device APR, and constitutes an AFE (analog front end) or a DFE (digital front end). The processing device PRCS is a semiconductor device such as a CPU (central processing unit) or an ASIC (application specific integrated circuit). The display device DSPL is an EL display device or a liquid crystal display device that displays information (images) obtained by the photoelectric conversion device APR. The memory device MMRY is a magnetic device or a semiconductor device that stores information (images) obtained by the photoelectric conversion device APR. The memory device MMRY is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive. The mechanical device MCHN has a moving part or a propulsion part such as a motor or an engine. In the device EQP, the signal output from the photoelectric conversion device APR is displayed on the display device DSPL, and is transmitted to the outside by a communication device (not shown) provided in the device EQP. For this purpose, the device EQP preferably further includes a memory device MMRY and a processing device PRCS in addition to the memory circuit unit and the arithmetic circuit unit provided in the photoelectric conversion device APR.

[0255] The device EQP shown in FIG. 14 may be an electronic device such as an information terminal having a photographing function (e.g., a smartphone or a wearable device) or a camera (e.g., an interchangeable lens camera, a compact camera, a video camera, or a surveillance camera). The mechanical device MCHN in the camera can drive components of the optical device OPT for zooming, focusing, and shutter operation. The device EQP may also be a transportation device (moving object) such as a vehicle, a ship, or an aircraft. The device EQP may also be a medical device such as an endoscope or a CT scanner. The device EQP may also be a medical device such as an endoscope or a CT scanner.

[0256] The mechanical device MCHN in the transportation equipment can be used as a moving device. The device EQP as a transportation equipment is suitable for transporting the photoelectric conversion device APR and for assisting and / or automating driving (operation) by using a photographing function. The processing device PRCS for assisting and / or automating driving (operation) can perform processing for operating the mechanical device MCHN as a moving device based on information obtained by the photoelectric conversion device APR.

[0257] The photoelectric conversion device APR according to this embodiment can provide high value to its designer, manufacturer, seller, purchaser and / or user. Therefore, if the photoelectric conversion device APR is installed in equipment EQP, the value of the equipment EQP can also be increased. Therefore, when manufacturing and selling equipment EQP, deciding to install the photoelectric conversion device APR of this embodiment in the equipment EQP is advantageous in increasing the value of the equipment EQP.

[0258] [Modified embodiment] The present invention is not limited to the above-described embodiment, and various modifications are possible. For example, an example in which part of the configuration of any one of the embodiments is added to another embodiment, or an example in which part of the configuration of another embodiment is substituted therefor, is also an embodiment of the present invention.

[0259] 2 and 3 are merely examples and are not limited thereto. For example, the number of photoelectric conversion units PD sharing one floating diffusion unit FD is not limited to 8 or 16, and can be changed as appropriate. In addition, among the multiple photoelectric conversion units PD sharing one floating diffusion unit FD, two or more may be configured to share a microlens. The present invention is particularly useful in a photoelectric conversion device having a pixel P in which the number of photoelectric conversion units PD sharing one floating diffusion unit FD is three or more.

[0260] Furthermore, the imaging systems shown in the fifth and sixth embodiments are examples of imaging systems to which the photoelectric conversion device of the present invention can be applied, and imaging systems to which the photoelectric conversion device of the present invention can be applied are not limited to the configurations shown in Figures 20 and 21(a).

[0261] The present invention can also be realized by a process in which a program for implementing one or more of the functions of the above-described embodiments is supplied to a system or device via a network or a storage medium, and one or more processors in a computer of the system or device read and execute the program. The present invention can also be realized by a circuit (e.g., ASIC) that implements one or more of the functions.

[0262] It should be noted that the above-mentioned embodiments are merely examples of the implementation of the present invention, and the technical scope of the present invention should not be interpreted as being limited by these embodiments. In other words, the present invention can be implemented in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0263] FD: Floating diffusion section P…pixel PD, PD1 to PD8, PD1a to PD8a, PD1b to PD8b...Photoelectric conversion section 1... Processing equipment 2...Control section 21...Synchronization signal generator 22...Read row / reset row address generation unit 221...Horizontal sync signal generator for read row address 222...Read row address generation unit 223...Reset A row address horizontal sync signal generator 224…Reset A row address generation unit 225...Reset B row address horizontal sync signal generator 226…Reset B row address generation unit 227...Horizontal sync signal count generation unit 23...Vertical scanning timing control section 24...Column circuit timing control unit 25...Horizontal scanning timing control section 3. Vertical scanning section 31...Address decoder section 31a...RD address decoder section 31b…SHA address decoder section 31c…SHB address decoder section 32... Row driver 4. Pixel section 100...Photoelectric conversion unit 200,300...imaging system

Claims

1. a pixel section in which a plurality of pixels each having three or more photoelectric conversion units, a floating diffusion unit to which charges of the plurality of photoelectric conversion units are transferred, and an output unit that outputs a signal according to a voltage of the floating diffusion unit are arranged in a plurality of rows and a plurality of columns; a vertical scanning unit that performs a read process of reading out signals from the pixels and a reset process of resetting the pixels, while switching between a photoelectric conversion unit that is a processing target and a floating diffusion unit that is a processing target, for the plurality of pixels arranged in the pixel unit; A control unit that controls the vertical scanning unit, the control unit includes a read row address generation unit that generates row addresses of pixels from which signals are read during the read process and outputs the row addresses to the vertical scanning unit; and a reset row address generation unit that generates row addresses of pixels to be reset during the reset process and outputs the row addresses to the vertical scanning unit; a first period, which is a period for switching the photoelectric conversion unit to be processed during the readout process and the reset process, is shorter than a second period, which is a period for switching the floating diffusion unit to be processed during the readout process and the reset process; an update period of the row addresses in the read row address generation unit and the reset row address generation unit is equal to the second period; The setting unit of the update timing of the row addresses in the read row address generation unit and the reset row address generation unit is equal to the length of one period of the first period. A photoelectric conversion device comprising:

2. the control unit further includes a read counter and a reset counter whose count value transitions in the first period, an update timing of the row address in the read row address generation unit is controlled according to a count value of the read counter; The timing of updating the row address in the reset row address generating unit is controlled according to the count value of the reset counter.

2. The photoelectric conversion device according to claim 1.

3. the control unit further includes a counter whose count value transitions in the first period, an update timing of the row address in the read row address generation unit is controlled in response to a count value of the counter and a first setting value; The update timing of the row address in the reset row address generating unit is controlled in accordance with the count value of the counter and a second set value.

2. The photoelectric conversion device according to claim 1.

4. The read row address generation unit and the reset row address generation unit have a plurality of setting values ​​that define update timings of the row addresses.

4. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

5. the plurality of rows include a first row and a second row that are targets of the readout process and the reset process; The second period in the first row is different from the second period in the second row.

5. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

6. the plurality of photoelectric conversion units include a first set having a first photoelectric conversion unit and a second photoelectric conversion unit, and a second set having a third photoelectric conversion unit and a fourth photoelectric conversion unit; the signals output from the first row include a signal based on charges generated in the first photoelectric conversion unit, a signal based on charges generated in the first photoelectric conversion unit and the second photoelectric conversion unit, a signal based on charges generated in the third photoelectric conversion unit, and a signal based on charges generated in the third photoelectric conversion unit and the fourth photoelectric conversion unit; The signal output from the second row includes a signal based on charges generated in the first photoelectric conversion unit and the second photoelectric conversion unit, and a signal based on charges generated in the third photoelectric conversion unit and the fourth photoelectric conversion unit.

6. The photoelectric conversion device according to claim 5.

7. the plurality of photoelectric conversion units include a first set having a first photoelectric conversion unit and a second photoelectric conversion unit, and a second set having a third photoelectric conversion unit and a fourth photoelectric conversion unit; The number of signals based on the first set output during one period of the second period is greater than the number of signals based on the second set.

5. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

8. the signal output from the first set includes a signal based on the charge generated in the first photoelectric conversion unit and a signal based on the charge generated in the first photoelectric conversion unit and the second photoelectric conversion unit; The signal output from the second set includes a signal based on the charges generated in the third photoelectric conversion unit and the fourth photoelectric conversion unit.

8. The photoelectric conversion device according to claim 7.

9. Each of the first set and the second set shares one microlens.

9. The photoelectric conversion device according to claim 6, wherein the first and second electrodes are arranged in a first direction.

10. the reset row address generation unit includes a first reset row address generation unit and a second reset row address generation unit; The update timing of the row address in the first reset row address generation unit is different from the update timing of the row address in the second reset row address generation unit.

10. The photoelectric conversion device according to claim 1,

11. A plurality of output lines are provided for each of the plurality of columns, The plurality of output lines include a first output line through which signals of pixels arranged in a first row are output, and a second output line through which signals of pixels arranged in a second row are output.

11. The photoelectric conversion device according to claim 1,

12. The photoelectric conversion device according to any one of claims 1 to 11, a signal processing unit that processes a signal output from the photoelectric conversion device; An imaging system comprising:

13. A mobile object, The photoelectric conversion device according to any one of claims 1 to 11, a distance information acquiring means for acquiring distance information to an object from a parallax image based on a signal from the photoelectric conversion device; a control means for controlling the moving object based on the distance information; A moving object comprising:

14. The photoelectric conversion device according to any one of claims 1 to 11, an optical device corresponding to the photoelectric conversion device; A control device for controlling the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a mechanical device controlled based on information obtained by the photoelectric conversion device; A display device that displays information obtained by the photoelectric conversion device; and a storage device for storing information obtained by the photoelectric conversion device; An apparatus comprising:

Images