Imaging devices, electronic devices

Abstract

Provided is an image capture apparatus of low power consumption. A first circuit and a second circuit are provided in a pixel. The first circuit can generate image capture data and can hold differential data relative to data acquired in an initial frame. A circuit for comparing the differential data with a voltage range that is arbitrarily specified is provided in the second circuit. The second circuit supplies a read signal depending on the comparison result to the first circuit. Employment of this configuration makes it possible to effect no reading from the pixel when it is determined that the differential data is within the specified voltage range and to effect reading from the pixel only when it is determined that the differential data is not within the voltage range.

Description

[Technical field]

[0001] One aspect of the present invention relates to an imaging device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification etc. relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a memory device, an imaging device, an operation method thereof, or a manufacturing method thereof.

[0003] Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. Further, a memory device, a display device, an imaging device, and an electronic device may include a semiconductor device. [Background technology]

[0004] A technology for forming a transistor using an oxide semiconductor thin film formed over a substrate has attracted attention. For example, Patent Document 1 discloses an imaging device in which a transistor that includes an oxide semiconductor and has an extremely low off-state current is used in a pixel circuit. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2011-119711 A Summary of the Invention [Problem to be solved by the invention]

[0006] When capturing moving images using a CMOS image sensor, etc., an operation is performed to read out data acquired from all pixels for each frame. In this operation, data that can be regarded as identical may be acquired from the same pixel in multiple consecutive frames.

[0007] For example, a still subject outdoors is subject to changes in the brightness of natural light over time, but there are almost no changes that can be discerned by humans at short intervals of 1 / 10 seconds or less, which corresponds to the frame rate of moving images. In other words, it can be said that data that can be considered to be the same is acquired across multiple frames.

[0008] The data is read out for each frame, consuming power. If the data can be considered to be the same, power consumption can be reduced by eliminating the read operation.

[0009] Therefore, an object of one embodiment of the present invention is to provide an imaging device with low power consumption. Another object is to provide an imaging device that can detect a change in a subject. Another object is to provide an imaging device with high reliability. Another object is to provide a novel imaging device or the like. Another object is to provide a method for operating the imaging device. Another object is to provide a novel semiconductor device or the like.

[0010] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract problems other than these from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0011] One aspect of the present invention relates to an imaging device having a circuit for comparing data between adjacent frames and determining which pixels to read out.

[0012] One embodiment of the present invention is an imaging device having a pixel including a first circuit and a second circuit, the first circuit having a first node, a second node, and a first switch, the first node having a function of holding first image data generated in a first frame period, the first node having a function of holding second image data generated in an nth frame period (n is a natural number equal to or greater than 2), the second node having a function of holding differential data that is a difference between the first image data and the second image data, the first switch having a function of controlling output of the first image data and the second image data, the second circuit having a comparison circuit and an output circuit, the comparison circuit having a function of determining whether the differential data is within an arbitrarily set voltage range, and the output circuit having a function of outputting a voltage that turns off the first switch when the differential data is within the voltage range, and outputting a voltage that turns on the first switch when the differential data is not within the voltage range.

[0013] The first circuit may have a photoelectric conversion device, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, and a second capacitor, and one electrode of the photoelectric conversion device is electrically connected to one of the source or drain of the first transistor, the other of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor, the gate of the third transistor, one electrode of the first capacitor, and one electrode of the second capacitor, one of the source or drain of the third transistor is electrically connected to one of the source or drain of the fourth transistor, the other of the source or drain of the third transistor is electrically connected to one of the source or drain of the fifth transistor, and the other electrode of the second capacitor is electrically connected to one of the source or drain of the sixth transistor. The fifth transistor may operate as a first switch.

[0014] The first circuit may further include a seventh transistor, one of the source or drain of the seventh transistor being electrically connected to the other of the source or drain of the first transistor and one of the source or drain of the second transistor, and the other of the source or drain of the seventh transistor being electrically connected to the gate of the third transistor, one electrode of the first capacitor, and one electrode of the second capacitor.

[0015] The first to seventh transistors preferably have a metal oxide in a channel formation region. The metal oxide can include In, Zn, and M (M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, and Hf).

[0016] The comparison circuit may have a first sense amplifier and a second sense amplifier, the first sense amplifier having a third node, the second sense amplifier having a fourth node, the output circuit having a fifth node, the first sense amplifier having a first input portion for inputting a voltage at the lower end of a voltage range, the second sense amplifier having a second input portion for inputting a voltage at the upper end of the voltage range, the first sense amplifier and the second sense amplifier each having a third input portion to which the second node is electrically connected, the third node and the fourth node being electrically connected to the output circuit, and the fifth node being electrically connected to the first switch.

[0017] The third input section may be electrically connected to the second node of one pixel, and the fifth node may be electrically connected to first switches of a plurality of pixels.

[0018] The second circuit further includes an inverter circuit, and the transistors included in the inverter circuit, the first sense amplifier, the second sense amplifier, and the output circuit can have silicon in a channel formation region.

[0019] Alternatively, the first sense amplifier and the second sense amplifier may each have a first power switch and a second power switch, the first power switch having a p-channel transistor, and the second power switch having an n-channel transistor, the n-channel transistor having a metal oxide in a channel formation region. The metal oxide preferably has In, Zn, and M (M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, and Hf).

[0020] The first circuit and the second circuit may have an overlapping area, or a plurality of first circuits and one second circuit may have an overlapping area.

[0021] Another embodiment of the present invention is a method of operating an imaging device, which sets a first voltage and a second voltage (first voltage<second voltage) in a pixel, acquires first image data in a first frame period, acquires second image data in an nth frame period (n is a natural number greater than or equal to 2), calculates a third voltage which is the difference between the first image data and the second image data, compares the first voltage, the second voltage, and the third voltage, and does not read out the second data from the pixel when the third voltage is greater than the first voltage and less than the second voltage, and reads out the second data from the pixel when the third voltage is less than the first voltage or greater than the second voltage. Effect of the Invention

[0022] By using one embodiment of the present invention, an imaging device with low power consumption can be provided. Alternatively, an imaging device capable of detecting a change in a subject can be provided. Alternatively, an imaging device with high reliability can be provided. Alternatively, a novel imaging device or the like can be provided. Alternatively, a method for operating the imaging device can be provided. Alternatively, a novel semiconductor device or the like can be provided. [Brief description of the drawings]

[0023] FIG. 1 is a diagram illustrating a pixel. 2A and 2B are circuit diagrams illustrating the circuit 10. FIG. FIG. 3 is a circuit diagram illustrating the circuit 11. As shown in FIG. FIG. 4 is a timing chart illustrating the operation of the pixel. FIG. 5 is a diagram for explaining the operation of the circuit 11. In FIG. FIG. 6 is a timing chart illustrating the operation of the pixel. FIG. 7 is a diagram for explaining the operation of the circuit 11. In FIG. FIG. 8 is a diagram for explaining the operation of the circuit 11. In FIG. FIG. 9 is a timing chart illustrating the operation of the pixel. FIG. 10 is a diagram for explaining the operation of the circuit 11. In FIG. FIG. 11 is a timing chart illustrating the operation of the pixel. FIG. 12 is a diagram for explaining the operation of the circuit 11. In FIG. FIG. 13 is a timing chart illustrating the operation of the pixel. FIG. 14 is a block diagram illustrating an imaging device. 15A to 15D are diagrams for explaining the configuration of a pixel. FIG. 16 is a block diagram illustrating the configuration of a pixel. FIG. 17 is a block diagram illustrating the configuration of a pixel. 18A and 18B are circuit diagrams illustrating the circuit 10. FIG. 19A to 19E are circuit diagrams illustrating a portion of circuit 10. FIG. 20A and 20B are circuit diagrams illustrating the circuit 10. FIG. 21A to 21D are diagrams illustrating the configuration of a pixel of an imaging device. 22A to 22C are diagrams illustrating the configuration of a photoelectric conversion device. FIG. 23 is a cross-sectional view illustrating a pixel. 24A to 24C are diagrams illustrating a Si transistor. FIG. 25 is a cross-sectional view illustrating a pixel. FIG. 26 is a cross-sectional view illustrating a pixel. 27A to 27D illustrate OS transistors. FIG. 28 is a cross-sectional view illustrating a pixel. FIG. 29 is a cross-sectional view illustrating a pixel. FIG. 30 is a cross-sectional view illustrating a pixel. 31A to 31C are perspective views (cross-sectional views) illustrating a pixel. 32A1 to 32A3 and 32B1 to 32B3 are perspective views of a package and a module that house an imaging device. 33A to 33F are diagrams illustrating an electronic device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention is not interpreted as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. In addition, hatching of the same elements constituting the drawings may be omitted or changed as appropriate between different drawings.

[0025] In addition, even if a circuit diagram shows a single element, the element may be configured as a plurality of elements as long as there is no functional problem. For example, a plurality of transistors operating as a switch may be connected in series or parallel. A capacitor may also be divided and placed in multiple positions.

[0026] In addition, one conductor may have multiple functions such as wiring, an electrode, and a terminal, and in this specification, multiple names may be used for the same element. Even if elements are shown as being directly connected to each other on a circuit diagram, the elements may actually be connected to each other via one or more conductors, and in this specification, such a configuration is also included in the category of direct connection.

[0027] (Embodiment 1) In this embodiment, an imaging device which is one embodiment of the present invention will be described with reference to drawings.

[0028] One embodiment of the present invention has a function of comparing data between frames and determining whether or not to perform readout based on the result of the comparison. Whether or not to perform readout can be controlled on a pixel-by-pixel basis.

[0029] The pixel is provided with a first circuit and a second circuit. The first circuit can generate imaging data and can hold differential data, which is the difference between the first and initial frame data. The second circuit is provided with a circuit that compares the differential data with an arbitrarily set voltage range. The second circuit supplies a readout signal to the first circuit according to the comparison result.

[0030] By using this configuration, for example, if it is determined that the differential data is within a set voltage range, no reading is performed from the pixel, and if it is determined that the differential data is not within the voltage range, reading is performed from the pixel.

[0031] Therefore, when data that can be regarded as the same as the data of the initial frame is acquired, the read operation can be omitted, and power consumption can be reduced. When performing this operation, it is sufficient to generate frame data by rewriting only the data of the pixels that have been read based on the data of the initial frame.

[0032] <Pixel circuit> 1 is a circuit diagram of a pixel included in an imaging device of one embodiment of the present invention. The pixel includes a circuit 10 and a circuit 11. The circuit 10 has a function of generating and holding imaging data. The circuit 10 can also hold differential data that is the difference between data acquired during a first frame (initial frame) period and data acquired during an nth frame (target frame) period (n is a natural number of 2 or more). The circuit 11 is a determination circuit that can determine whether the differential data is large or small and determine whether or not to read the data from the circuit 10.

[0033] <Circuit 10> The circuit 10 includes a photoelectric conversion device 101, a transistor 102, a transistor 103, a transistor 104, a transistor 105, a transistor 106, a transistor 107, a capacitor 108, and a capacitor 109. Note that the capacitor 108 may be omitted.

[0034] One electrode of the photoelectric conversion device 101 is electrically connected to one of the source or drain of the transistor 102. The other of the source or drain of the transistor 102 is electrically connected to one of the source or drain of the transistor 103, the gate of the transistor 104, one electrode of the capacitor 108, and one electrode of the capacitor 109. One of the source or drain of the transistor 104 is electrically connected to one of the source or drain of the transistor 105. The other of the source or drain of the transistor 104 is electrically connected to one of the source or drain of the transistor 106. The other electrode of the capacitor 109 is electrically connected to one of the source or drain of the transistor 107.

[0035] The gate of the transistor 106 is electrically connected to the circuit 11 through a wiring 242. The other electrode of the capacitor 109 is electrically connected to the circuit 11 through a wiring 241.

[0036] Here, a point (wiring) where the other of the source or drain of transistor 102, one of the source or drain of transistor 103, the gate of transistor 104, one electrode of capacitor 108, and one electrode of capacitor 109 are connected is referred to as node FD1. Also, a point (wiring) where the other electrode of capacitor 109, one of the source or drain of transistor 107, and wiring 241 are connected is referred to as node FD2. Node FD1 can hold data acquired in each frame period. Node FD2 can hold data of an initial frame or differential data that is the difference between data of the initial frame and data of a target frame.

[0037] The other electrode of the photoelectric conversion device 101 is electrically connected to a wiring 121. The other of the source and drain of the transistor 103 is electrically connected to a wiring 122. The other of the source and drain of the transistor 105 is electrically connected to a wiring 125. The other of the source and drain of the transistor 106 is electrically connected to a wiring 123. The other of the source and drain of the transistor 107 is electrically connected to a wiring 124.

[0038] A gate of the transistor 102 is electrically connected to a wiring 231. A gate of the transistor 103 is electrically connected to a wiring 232. A gate of the transistor 105 is electrically connected to a wiring 234. A gate of the transistor 107 is electrically connected to a wiring 233. Note that the wiring 234 is also electrically connected to the circuit 11.

[0039] The wirings 121 to 124 can function as power supply lines. For example, the wiring 121 can be a low-potential power supply line, and the wirings 122, 123, and 124 can be high-potential power supply lines. Note that in the configuration shown in FIG. 1, the cathode side of the photoelectric conversion device 101 is electrically connected to the transistor 102, and therefore the power supply lines are as described above. On the other hand, as shown in FIG. 2A, the anode side of the photoelectric conversion device 101 may be electrically connected to the transistor 102. In this case, the wiring 122 may be a low-potential power supply line, and the wirings 121, 123, and 124 may be high-potential power supply lines.

[0040] The wirings 231 to 234 can function as signal lines for controlling the conduction of each transistor. The wiring 125 can function as an output line and is electrically connected to, for example, an interlayer double sampling circuit (CDS circuit) or a readout circuit including an A / D conversion circuit.

[0041] The transistor 102 has a function of controlling the potential of the node FD1. The transistor 103 has a function of resetting the potential of the node FD1. The transistor 104 functions as an element of a source follower circuit. The transistors 105 and 106 have a function of selecting an output of a pixel. The transistor 107 has a function of resetting the potential of the node FD2.

[0042] The transistors included in the circuit 10 are preferably transistors having a metal oxide in a channel formation region (hereinafter, referred to as OS transistors). OS transistors have characteristics of extremely low off-state current. In particular, it is preferable to use transistors with low off-state current for the transistors 102, 103, and 107. By using these transistors as OS transistors, the period during which charge can be held at the nodes FD1 and FD2 can be made extremely long, and image data with little degradation can be read out.

[0043] Alternatively, transistors having silicon in a channel formation region (hereinafter, Si transistors) can be used as the transistors 102 to 107. Examples of Si transistors include transistors having amorphous silicon and transistors having crystalline silicon (microcrystalline silicon, low-temperature polysilicon, and single crystal silicon). Si transistors have high mobility and are suitable for high-speed operation.

[0044] Note that when the transistors 102 and 103 are Si transistors, a transistor 111 is preferably further provided as shown in Fig. 2B. Here, the transistor 111 is an OS transistor.

[0045] One of the source and the drain of the transistor 111 is electrically connected to the other of the source and the drain of the transistor 102 and one of the source and the drain of the transistor 103. The other of the source and the drain of the transistor 111 is electrically connected to the gate of the transistor 104, one electrode of the capacitor 108, and one electrode of the capacitor 109.

[0046] A gate of the transistor 111 is electrically connected to a wiring 235. The wiring 235 can function as a signal line that controls conduction of the transistor 111.

[0047] In the configuration of FIG. 2B, a point (wiring) where the other of the source or drain of the transistor 111, the gate of the transistor 104, one electrode of the capacitor 108, and one electrode of the capacitor 109 are connected is the node FD1.

[0048] Since the transistor 111 is an OS transistor with low off-state current, the charge retention function of the nodes FD1 and FD2 can be improved. Furthermore, since the photoelectric conversion device 101 can be a buried photodiode formed on a silicon substrate, a pixel circuit with low noise can be formed.

[0049] <Circuit 11> 3 shows a circuit diagram of the circuit 11. The circuit 11 has sense amplifiers 11A and 11B as comparison circuits. It also has an output circuit 11C. In addition, inverters 171 and 172 are connected to a part of the signal line connecting the sense amplifiers 11A and 11B and the output circuit 11C. Note that the connection relationship of each element constituting the circuit 11 is referred to in FIG. 3, and a detailed description thereof will be omitted.

[0050] The sense amplifier 11A has a configuration in which an inverter latch circuit (transistors 141, 142, 143, 144) is electrically connected to a power switch (transistors 131, 133) connected to a high potential power line (wiring 127), and the inverter latch circuit is electrically connected to a power switch (transistors 135, 137) connected to a low potential power line (wiring 128) via transistors 145 and 146.

[0051] A gate of the transistor 145 is electrically connected to a node FD2 of the circuit 10 through a wiring 241. A gate of the transistor 146 is electrically connected to a wiring 238. The wiring 238 is a wiring to which a constant potential determined for a specific purpose is supplied.

[0052] A transistor 147 is electrically connected to a node LATNB of the inverter latch circuit, and a transistor 148 is electrically connected to the node LATN. The transistor 147 has a function of precharging the node LATNB to the potential of the wiring 129. The transistor 148 has a function of precharging the node LATN to the potential of the wiring 129. The potential of the wiring 129 can be set to approximately an intermediate potential between the potential of the wiring 127 and the potential of the wiring 128, for example.

[0053] The sense amplifier 11B has a configuration in which an inverter latch circuit (transistors 151, 152, 153, 154) is electrically connected to a power switch (transistors 132, 134) connected to a high potential power line (wiring 127), and the inverter latch circuit is electrically connected to a power switch (transistors 136, 138) connected to a low potential power line (wiring 128) via transistors 155 and 156.

[0054] A gate of the transistor 155 is electrically connected to a node FD2 of the circuit 10 through a wiring 241. A gate of the transistor 156 is electrically connected to a wiring 239. The wiring 239 is a wiring to which a constant potential determined for a specific purpose is supplied.

[0055] A transistor 157 is electrically connected to a node LATPB of the inverter latch circuit, and a transistor 158 is electrically connected to the node LATP. The transistor 157 has a function of precharging the node LATPB to the potential of the wiring 129. The transistor 158 has a function of precharging the node LATP to the potential of the wiring 129.

[0056] The output circuit 11C has a power switch (transistors 161 and 162) connected to a high potential power line (wiring 127), a power switch (transistors 167 and 168) connected to a low potential power line (wiring 128), and transistors 163, 164, 165, 166, and 169. Each transistor is electrically connected to an output node PCTR.

[0057] The gates of the transistors 164 and 165 are electrically connected to a node LATN. The gates of the transistors 163 and 166 are electrically connected to a node LATPB. The gate of the transistor 169 is electrically connected to a wiring 236 via an inverter 172. The output node PCTR is electrically connected to the gate of the transistor 106 included in the circuit 10 via a wiring 242.

[0058] Wirings 236, 234, and 237 are electrically connected to the circuit 11. The wirings 236, 234, and 237 are signal lines for controlling the conduction of the transistors.

[0059] When a high potential ("H") is supplied to the wiring 236, the potential of the node PCTR is forcibly set to a high potential ("H"), and the transistor 106 in the circuit 10 is turned on. That is, the transistor 106, which is one of the two selection transistors included in the circuit 10, can be forcibly turned on.

[0060] The wiring 236 can be electrically connected to the gates of the transistors 131, 132, and 161. The wiring 236 can be electrically connected to the gates of the transistors 135, 136, 167, and 169 via the inverter 172.

[0061] The wiring 234 can be electrically connected to the gates of the transistors 133, 134, and 162 through the inverter 171. The wiring 234 can also be electrically connected to the gates of the transistors 137, 138, and 168. When a low potential ("L") is supplied to the wiring 236 and a high potential ("H") is supplied to the wiring 234, each power switch can be turned on.

[0062] The wiring 237 can be electrically connected to the gates of the transistors 147, 148, 157, and 158. When a high potential ("H") is supplied to the wiring 237, the transistors 147, 148, 157, and 158 are turned on, and the nodes LATNB, LATN, LATPB, and LATP can be precharged.

[0063] The circuit 11 includes p-channel transistors (transistors 131, 132, 133, 134, 141, 143, 151, 153, 161, 162, 164, and 169) and n-channel transistors (transistors 135, 136, 137, 138, 142, 144, 145, 146, 147, 148, 152, 154, 155, 156, 157, 158, 165, 166, 167, and 168).

[0064] It is preferable to use Si transistors as these transistors. Alternatively, OS transistors may be used as n-channel transistors. In particular, by using OS transistors as the transistors 135, 136, 137, and 138 that configure the power switches, unnecessary leakage current between power lines that occurs when the power switches are not in operation can be suppressed, and power consumption can be reduced.

[0065] <Operations of Circuit 10 and Circuit 11> Next, the operations of the circuits 10 and 11 will be described. The operations include imaging and readout of the initial frame, normal imaging, difference calculation, and judgment, which will be described in order. In the following description, a high potential signal that makes an n-channel transistor conductive and a high potential signal that makes a p-channel transistor non-conductive are represented by "H", and a low potential signal that makes an n-channel transistor non-conductive and a low potential signal that makes a p-channel transistor conductive are represented by "L".

[0066] In the circuit 11, a potential VN is supplied to the wiring 238, and a potential VP is supplied to the wiring 239. The potential VN is the lower end voltage of a voltage range used for the determination, and the potential VP is the upper end voltage. This voltage range corresponds to a range in which the data of the initial frame and the data of the target frame are considered to be the same.

[0067] <Initial frame capture operation> 4 is a timing chart for explaining the imaging operation (period T1) and the readout operation (period T2) of the initial frame. In the figure, [0] to [n] (n is a natural number) represent row numbers. In the following explanation, only row number [0] will be explained.

[0068] In a period T1, when the potential of the wiring 231 is set to "H", the potential of the wiring 232 is set to "H", the potential of the wiring 233 is set to "H", the potential of the wiring 236 is set to "L", the potential of the wiring 237 is set to "L", and the potential of the wiring 234[0:n] is set to "L", in the circuit 10, the transistors 102, 103, and 107 are turned on, and the potentials of the cathode of the photoelectric conversion device 101 and the node FD1 are reset to the potential "VRES1" of the wiring 122. In addition, the potential of the node FD2 is reset to the potential "VRES2" of the wiring 124.

[0069] Next, when the potential of the wiring 231 is set to "L", charges are accumulated in the cathode in response to the operation of the photoelectric conversion device 101. In addition, the potential of the wiring 232 is set to "L", the transistor 103 is turned off, and the potential of the node FD1 is held at "VRES1".

[0070] Next, when the potential of the wiring 231 is set to "H" after a predetermined exposure time has elapsed, the charge accumulated in the cathode of the photoelectric conversion device 101 is transferred to the node FD1. At this time, the potential of the node FD1 drops by an amount of potential ("Vref") corresponding to the amount of transferred charge, and becomes "VRES1-Vref." At this time, "VRES2" is supplied to the node FD2.

[0071] Next, the potential of the wiring 231 is set to "L", the potential of the wiring 233 is set to "L", the transistors 102 and 107 are turned off, and the potential of the node FD1 is held at "VRES1-Vref". The potential of the node FD2 is held at "VRES2". Here, "VRES2" can also be said to be a value that replaces the data of the initial frame. This concludes the description of the imaging operation of the initial frame.

[0072] <Initial frame read operation>

[0073] In the period T2, when the potential of the wiring 231 is set to "L", the potential of the wiring 232 is set to "L", the potential of the wiring 233 is set to "L", the potential of the wiring 236 is set to "H", the potential of the wiring 237 is set to "L", and the potential of the wiring 234[0:n] is set to "L", as shown in FIG. 5, in the circuit 11, all the power switches are turned off and the transistor 169 is turned on. Therefore, the potential of the output node PCTR becomes "H", and in the circuit 10, the transistor 106 is turned on, and the potential of the wiring 123 (power supply potential) is supplied to the other of the source and drain of the transistor 104. Note that in the figure, ◯ indicates that a transistor is on, and × indicates that a transistor is not on.

[0074] Next, when the potential of the wiring 234[0] is set to "H", the transistor 105 is turned on and data corresponding to the potential of the node FD1 is output to the wiring 125. This completes the description of the read operation of the initial frame. The data read here can be stored in a frame memory, for example.

[0075] <Normal imaging operation and difference calculation operation> FIG. 6 is a timing chart for explaining the normal imaging operation and difference calculation operation (period T3) and the difference determination operation and readout operation (period T4) following the initial frame readout operation (period T2 in FIG. 4).

[0076] In period T3, when the potential of wiring 231 is set to "H", the potential of wiring 232 is set to "H", the potential of wiring 233 is set to "L", the potential of wiring 236 is set to "L", the potential of wiring 237 is set to "L", and the potential of wiring 234[0:n] is set to "L", the transistors 102 and 103 become conductive, and the potentials of the cathode of the photoelectric conversion device 101 and the node FD1 are reset to the potential of wiring 122, "VRES1".

[0077] At this time, since the node FD2 is in a floating state, the change in the potential of the node FD1 is added to the potential of the node FD2 due to the capacitive coupling of the capacitor 109. Since the change in the potential of the node FD1 is "+Vref", the potential of the node FD2 becomes "VRES2+Vref".

[0078] Next, when the potential of the wiring 231 is set to "L", charges are accumulated in the cathode in response to the operation of the photoelectric conversion device 101. In addition, the potential of the wiring 232 is set to "L", the transistor 103 is turned off, and the potential of the node FD1 is held at "VRES1".

[0079] Next, when the potential of the wiring 231 is set to "H" after a predetermined exposure time has elapsed, the charge accumulated in the cathode of the photoelectric conversion device 101 is transferred to the node FD1. At this time, the potential of the node FD1 drops by an amount ("Vtar1") corresponding to the amount of charge transferred, and becomes "VRES1-Vtar1". Furthermore, due to the capacitive coupling of the capacitor 109, the change in the potential of the node FD1 is added to the potential of the node FD2. Since the change in the potential of the node FD1 is "-Vtar1", the potential of the node FD2 becomes "VRES2+Vref-Vtar1".

[0080] Next, the potential of the wiring 231 is set to "L" to turn off the transistor 102, and the potential of the node FD1 is held at "VRES1-Vtar1." In addition, the potential of the node FD2 is held at "VRES2+Vref-Vtar1."

[0081] The above is the normal imaging operation and the difference calculation operation. As a result of the normal imaging operation, "VRES1-Vtar1" is held in node FD1. Also, as a result of the difference calculation operation, "VRES2+Vref-Vtar1" is held in node FD2. "VRES2" is a reset potential, but can be considered to be 0. Therefore, "+Vref-Vtar1" is the difference between the data of the initial frame and the data acquired in the normal imaging operation.

[0082] <Difference judgment operation, read operation (no excess difference)>

[0083] In period T4, when the potential of wiring 231 is set to "L", the potential of wiring 232 is set to "L", the potential of wiring 233 is set to "L", the potential of wiring 236 is set to "L", the potential of wiring 237 is set to "H", and the potential of wiring 234[0:n] is set to "L", as shown in FIG. 7, in circuit 11, transistors 147, 148, 157, and 158 are turned on, and nodes LATNB, LATN, LATPB, and LATP are precharged to the potential of wiring 129.

[0084] Next, when the potential of the wiring 237 is set to "L" and the potential of the wiring 234[0] is set to "H", all the power switches are turned on and current starts to flow to the sense amplifier, as shown in Fig. 8. Here, the potential of the node FD2, "VRES2+Vref-Vtar1", is supplied to the gate of the transistor 145 and the gate of the transistor 155, the potential of the wiring 238 is supplied with "VN", and the potential of the wiring 239 is supplied with "VP".

[0085] 6, if "VN"<"VRES2+Vref-Vtar1"<"VP", the channel resistance of transistor 145 is lower than the channel resistance of transistor 146, and therefore the precharge potential of node LATNB is lowered preferentially than the precharge potential of node LATN. Therefore, transistors 142 and 143 are rendered conductive, power supply voltages are supplied from wirings 127 and 128, and the potentials of nodes LATNB and LATN are determined.

[0086] In addition, since the channel resistance of the transistor 156 is lower than the channel resistance of the transistor 155, the precharge potential of the node LATP is lowered preferentially than that of the node LATPB. Therefore, the transistors 151 and 154 are turned on, and the power supply voltage is supplied from the wirings 127 and 128 to determine the potentials of the nodes LATP and LATPB.

[0087] At this time, the potential of node LATN is "H", and the potential of node LATPB is "H", so that transistors 165 and 166 are turned on and transistors 163 and 164 are turned off, and the potential of the output node PCTR is "L". Therefore, in the circuit 10, the transistor 106 is not turned on and power is not supplied to the transistor 104, so that even if the transistor 105 is turned on, the data of the node FD1 is not output to the wiring 125. In other words, if "VN"<"VRES2+Vref-Vtar1"<"VP", no data is output from the circuit 10.

[0088] Here, since a source follower bias transistor (not shown) is connected to the wiring 125, the potential of the wiring 125 becomes 0 V unless the transistor 104 outputs data. When reading data, a steady current flows through the bias transistor. Therefore, if a read operation is not performed, power consumption equivalent to the steady current can be reduced.

[0089] <Difference judgment operation, read operation (positive difference exceeded)> A case where the difference exceeds the set voltage range will be described using the timing chart in Fig. 9. Note that the period T5 is a normal imaging operation and difference calculation operation similar to the period T3, so the description will be omitted. However, the potential of the node FD1 due to the normal imaging operation is "VRES1-Vtar2" (Vtar1>Vtar2), the potential of the node FD2 is "VRES1+Vref-Vtar2", and "VP"<"VRES1+Vref-Vtar2".

[0090] In period T6, when the potential of wiring 231 is set to "L", the potential of wiring 232 is set to "L", the potential of wiring 233 is set to "L", the potential of wiring 236 is set to "L", the potential of wiring 237 is set to "H", and the potential of wiring 234[0:n] is set to "L", as shown in FIG. 7, in circuit 11, transistors 147, 148, 157, and 158 are turned on, and nodes LATNB, LATN, LATPB, and LATP are precharged to the potential of wiring 129.

[0091] Next, when the potential of the wiring 237 is set to "L" and the potential of the wiring 234[0] is set to "H", all the power switches are turned on and current starts to flow to the sense amplifier, as shown in Fig. 10. Here, the potential of the node FD2, "VRES2+Vref-Vtar2", is supplied to the gate of the transistor 145 and the gate of the transistor 155, the potential of the wiring 238 is supplied to "VN", and the potential of the wiring 239 is supplied to "VP".

[0092] 9, if "VN"<"VP"<"VRES2+Vref-Vtar2", the channel resistance of the transistor 145 is lower than the channel resistance of the transistor 146, and therefore the precharge potential of the node LATNB is lowered preferentially than the precharge potential of the node LATN. Therefore, the transistors 142 and 143 are rendered conductive, and the power supply voltage is supplied from the wirings 127 and 128, so that the potentials of the nodes LATNB and LATN are determined.

[0093] In addition, the precharge potential of the node LATPB is lowered preferentially than the precharge potential of the node LATP because the channel resistance of the transistor 155 is lower than the channel resistance of the transistor 156. Therefore, the transistors 152 and 153 are turned on, and the power supply voltage is supplied from the wirings 127 and 128 to determine the potentials of the nodes LATPB and LATP.

[0094] At this time, the potential of node LATN becomes "H" and the potential of node LATPB becomes "L", so that transistors 163 and 165 are turned on and transistors 164 and 166 are turned off, and the potential of the output node PCTR becomes "H". Therefore, in the circuit 10, the transistor 106 is turned on and power is supplied to the transistor 104, so that the data of the node FD1 is output to the wiring 125 due to the conduction of the transistor 105. In other words, if "VN"<"VP"<"VRES2+Vref-Vtar2", data is output from the circuit 10.

[0095] The data output from the circuit 10 is stored in the frame memory where the image data of the initial frame is stored, at an address corresponding to that circuit 10. In other words, data is rewritten only at the address of the circuit 10 from which it was read. This operation makes it possible to reduce the write power compared to the case where the data of all the circuits 10 is rewritten.

[0096] Even if the read operation is not performed, the A / D conversion circuit generates digital data corresponding to the analog data of 0 V. When the digital data is generated, control is performed so that the write operation to the frame memory is not performed.

[0097] <Difference judgment operation, read operation (negative difference exceeded)> A case where the difference exceeds the lower side of the set voltage range will be described using the timing chart in Fig. 11. Note that the period T7 is a normal imaging operation and difference calculation operation similar to the period T3, so the description will be omitted. However, the potential of the node FD1 due to the normal imaging operation is "VRES1-Vtar3" ("Vtar3" > "Vtar1"), and the potential of the node FD2 is "VRES1+Vref-Vtar3", where "VRES1+Vref-Vtar3" < "VN" < "VP".

[0098] In period T8, when the potential of wiring 231 is set to "L", the potential of wiring 232 is set to "L", the potential of wiring 233 is set to "L", the potential of wiring 236 is set to "L", the potential of wiring 237 is set to "H", and the potential of wiring 234[0:n] is set to "L", as shown in FIG. 7, in circuit 11, transistors 147, 148, 157, and 158 are turned on, and nodes LATNB, LATN, LATPB, and LATP are precharged to the potential of wiring 129.

[0099] Next, when the potential of the wiring 237 is set to "L" and the potential of the wiring 234[0] is set to "H", all the power switches are turned on and current starts to flow to the sense amplifier, as shown in Fig. 12. Here, the potential of the node FD2, "VRES2+Vref-Vtar3", is supplied to the gate of the transistor 145 and the gate of the transistor 155, the potential of the wiring 238 is supplied with "VN", and the potential of the wiring 239 is supplied with "VP".

[0100] 11, if "VRES2+Vref-Vtar3"<"VN"<"VP", the channel resistance of transistor 146 is lower than the channel resistance of transistor 145, and therefore the precharge potential of node LATN is lowered preferentially than the precharge potential of node LATNB. Therefore, transistors 141 and 144 are rendered conductive, power supply voltages are supplied from wirings 127 and 128, and the potentials of nodes LATN and LATNB are determined.

[0101] In addition, since the channel resistance of the transistor 154 is lower than the channel resistance of the transistor 155, the precharge potential of the node LATP is lowered preferentially than that of the node LATPB. Therefore, the transistors 151 and 154 are turned on, and the power supply voltage is supplied from the wirings 127 and 128 to determine the potentials of the nodes LATP and LATPB.

[0102] At this time, the potential of node LATN becomes "L" and the potential of node LATPB becomes "H", so that transistor 164 is turned on, transistors 163 and 165 are turned off, and the potential of the output node PCTR becomes "H". Therefore, in the circuit 10, transistor 106 is turned on and power is supplied to transistor 104, so that data of node FD1 is output to wiring 125 due to the conduction of transistor 105. In other words, if "VRES2+Vref-Vtar3"<"VN"<"VP", data is output from the circuit 10.

[0103] As described above, the output of the circuit 10 can be controlled by the operation of the circuit 11. Since the data of the initial frame and the data of the target frame become more widely separated as time passes, it is preferable to update the data of the initial frame at regular intervals or for a certain number of frames. The data of the initial frame may be updated every other frame.

[0104] 4, 6, 9, and 11 show the operation of the circuit 10 shown in Fig. 1, but in the case of the configuration of Fig. 2B, a potential supply operation to the wiring 235 may be added as shown in Fig. 13. Note that Fig. 13 shows the imaging operation of the initial frame (period T1), but the normal imaging operation (period T3, etc.) is similar.

[0105] <Configuration of imaging device> 14 is a block diagram illustrating an imaging device according to one embodiment of the present invention. The imaging device includes a pixel array 21 having pixels (circuits 10 and circuits 11) arranged in a matrix, a circuit 22 (row driver) having a function of selecting a row of the pixel array 21, a circuit 23 having a function of reading data from the circuit 10, and a circuit 28 that supplies a power supply potential. Note that the number of wirings connecting the respective elements is simplified in FIG. 14. Also, the circuits 22, 23, and 28 may be multiple.

[0106] The circuit 23 may include a circuit 24 (CDS circuit) for performing correlated double sampling processing on the output data of the circuit 10, a circuit 25 (A / D conversion circuit or the like) having a function of converting analog data output from the circuit 24 into digital data, a circuit 26 (column driver) having a function of selecting a column to output data, etc. The circuit 10 and the circuit 23 are electrically connected via wiring 125.

[0107] 14, the circuit 10 and the circuit 11 are illustrated as having an overlapping region. Although details will be described later, by forming the circuit 10 and the circuit 11 into a stacked structure, the pixel area can be easily reduced and the resolution can be improved. In addition, by forming the circuit 11 with a Si transistor and forming the circuit 10 thereon with an OS transistor, a stacked structure can be formed without performing a process such as bonding.

[0108] Note that the configuration is not limited to one circuit 10 overlapping one circuit 11. For example, as shown in FIG. 15A, two circuits 10 arranged in the horizontal direction (the direction in which the gate lines extend) may overlap one circuit 11. Alternatively, as shown in FIG. 15B, two circuits 10 arranged in the vertical direction (the direction in which the source lines extend) may overlap one circuit 11. Alternatively, as shown in FIG. 15C, 2×2 circuits 10 arranged in the horizontal and vertical directions may overlap one circuit 11. Alternatively, as shown in FIG. 15D, 3×3 circuits 10 arranged in the horizontal and vertical directions may overlap one circuit 11. Alternatively, the number of circuits 10 overlapping one circuit 11 may be more than 3×3.

[0109] In this way, in a configuration in which multiple circuits 10 are connected to one circuit 11, the difference data of any one of the circuits 10 is acquired, and the other circuits 10 perform the same operation according to the judgment. An example of this is described below.

[0110] 16 is a diagram for explaining the connection form of 3×3 circuits 10 (circuits 10[0,0] to [2,2]) and one circuit 11. Since the three signal lines (wirings 231, 232, 233) in each row are electrically connected to each other, operations other than the read operation are performed simultaneously in the 3×3 circuits 10. The selection signal line (wirings 234[0:2]) of each row is electrically connected to the circuit 11 via the OR circuit 112. Therefore, the circuit 11 can be operated according to the selection operation of each row.

[0111] Here, the node FD2 of any one of the circuits 10 is electrically connected to the circuit 11. Although FIG. 16 shows an example in which the node FD2 of the circuit 10[0,1] is connected to the circuit 11, the circuit 11 may be connected to the node FD2 of the other circuits 10. In addition, the output node PCTR of the circuit 11 is electrically connected to all the circuits 10. Therefore, whether or not to read from all the circuits 10 is determined according to the value of the node FD2 of one of the circuits 10. In such a configuration, the number of the circuits 11 can be reduced, and therefore the power required for precharging the sense amplifiers of the circuits 11 can be reduced.

[0112] 17 shows a configuration in which a transistor 113 is added to the configuration in FIG. 16 and the OR circuit 112 is omitted. The transistor 113 is provided between an output node PCTR of the circuit 11 and a wiring 242. In the configuration in FIG. 17, the node FD2 of the circuit 10 in the row to be read out first is connected to the circuit 11. The gate of the transistor 113 is connected to a wiring 234 that is connected to the circuit 10 in that row.

[0113] In the read operation of the first row, the potential of the output node PCTR is determined in the circuit 11, the transistor 113 is turned on, and the potential is output to each circuit 10. When the next row is read, the transistor 113 is turned off, and the potential of the wiring 242 is maintained. Therefore, the same operation (read or not read) can be performed in all the circuits 10.

[0114] In such a configuration, the potential generated at the output node PCTR of the circuit 11 in the selection operation of the first row can be held. Therefore, since it is not necessary to generate a potential at the output node PCTR in the selection operation of other rows, the number of operations of the circuit 11 can be reduced, and power consumption can be reduced.

[0115] In one embodiment of the present invention, as illustrated in FIG. 18A, a transistor may have a back gate. FIG. 18A illustrates a structure in which the back gate is electrically connected to the front gate, which has an effect of increasing the on-state current. Alternatively, as illustrated in FIG. 18B, a constant potential may be supplied to the back gate. In this structure, the threshold voltage of the transistor can be controlled. Moreover, the structures illustrated in FIG. 18A and FIG. 18B may be mixed in one circuit. Moreover, a transistor without a back gate may be provided.

[0116] In the circuit 10, the arrangement order of the transistors 104, 105, and 106 connected in series to the wiring 123 and the wiring 125 may be the arrangement shown in FIGS. 19A to 19E instead of the arrangement shown in FIG.

[0117] 2B, one of the source and the drain of the transistor 103 may be electrically connected to the other of the source and the drain of the transistor 111, one electrode of the capacitor 108, and the gate of the transistor 104 as shown in Fig. 20A. As shown in Fig. 20B, the gate of the transistor 102 and the gate of the transistor 111 may be electrically connected to a wiring 231, and the wiring 235 may be omitted.

[0118] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes.

[0119] (Embodiment 2) In this embodiment, a structural example of an imaging device according to one embodiment of the present invention will be described.

[0120] <Structure example> FIG. 21A is a diagram showing an example of the structure of a pixel of an imaging device, which can have a stacked structure of a layer 561 and a layer 563.

[0121] The layer 561 includes the photoelectric conversion device 101. The photoelectric conversion device 101 can include a layer 565a and a layer 565b as shown in Fig. 22A. Note that the layer may be referred to as a region in some cases.

[0122] 22A is a pn junction photodiode, and may use, for example, a p-type semiconductor for the layer 565a and an n-type semiconductor for the layer 565b. Alternatively, the layer 565a may be an n-type semiconductor, and the layer 565b may be a p-type semiconductor.

[0123] The pn junction photodiode can be typically formed using single crystal silicon.

[0124] Furthermore, the photoelectric conversion device 101 included in the layer 561 may be a laminate of layers 566a, 566b, 566c, and 566d, as shown in Fig. 22B. The photoelectric conversion device 101 shown in Fig. 22B is an example of an avalanche photodiode, in which the layers 566a and 566d correspond to electrodes, and the layers 566b and 566c correspond to a photoelectric conversion unit.

[0125] Layer 566a is preferably a low resistance metal layer, such as aluminum, titanium, tungsten, tantalum, silver, or a laminate of these.

[0126] The layer 566d is preferably a conductive layer having a high light-transmitting property to visible light. For example, indium oxide, tin oxide, zinc oxide, indium-tin oxide, gallium-zinc oxide, indium-gallium-zinc oxide, graphene, or the like can be used. Note that the layer 566d may be omitted.

[0127] The layers 566b and 566c of the photoelectric conversion unit can be configured as a pn junction photodiode with a photoelectric conversion layer made of, for example, a selenium-based material. It is preferable that the layer 566b is made of a selenium-based material that is a p-type semiconductor, and the layer 566c is made of gallium oxide or the like that is an n-type semiconductor.

[0128] Photoelectric conversion devices using selenium-based materials have the characteristic of high external quantum efficiency for visible light. In such photoelectric conversion devices, avalanche multiplication can be used to increase the amplification of electrons relative to the amount of incident light. In addition, selenium-based materials have a high optical absorption coefficient, which offers the advantage of production in that the photoelectric conversion layer can be made as a thin film. Thin films of selenium-based materials can be formed using vacuum deposition or sputtering methods.

[0129] As the selenium-based material, crystalline selenium such as single crystal selenium and polycrystalline selenium, amorphous selenium, a compound of copper, indium, and selenium (CIS), or a compound of copper, indium, gallium, and selenium (CIGS) can be used.

[0130] The n-type semiconductor is preferably made of a material that has a wide band gap and is transparent to visible light. For example, zinc oxide, gallium oxide, indium oxide, tin oxide, or a mixture of these oxides can be used. These materials also function as a hole injection blocking layer, and can reduce dark current.

[0131] Furthermore, the photoelectric conversion device 101 included in the layer 561 may be a laminate of layers 567a, 567b, 567c, 567d, and 567e, as shown in Fig. 22C. The photoelectric conversion device 101 shown in Fig. 22C is an example of an organic photoconductive film, in which the layer 567a is a lower electrode, the layer 567e is a light-transmitting upper electrode, and the layers 567b, 567c, and 567d correspond to photoelectric conversion units.

[0132] One of the layers 567b and 567d of the photoelectric conversion portion can be a hole transport layer, and the other can be an electron transport layer. The layer 567c can be a photoelectric conversion layer.

[0133] For the hole transport layer, for example, molybdenum oxide can be used. For the electron transport layer, for example, C 60 , C 70or derivatives thereof can be used.

[0134] As the photoelectric conversion layer, a mixed layer (bulk heterojunction structure) of an n-type organic semiconductor and a p-type organic semiconductor can be used.

[0135] For example, a silicon substrate can be used as the layer 563 shown in FIG. 21A. The silicon substrate has Si transistors and the like. A pixel circuit can be formed using the Si transistors. In addition, a circuit for driving the pixel circuit, a readout circuit for the pixel circuit, an image processing circuit, a neural network, a communication circuit, and the like can be formed.

[0136] In addition, a memory circuit such as a dynamic random access memory (DRAM), a central processing unit (CPU), a micro controller unit (MCU), etc. may be formed. In this embodiment, the circuit 10 and the circuit 11 described in the first embodiment are called pixel circuits, and the other circuits are called functional circuits.

[0137] For example, some or all of the transistors included in the circuit 10, the circuit 11, and the functional circuits (circuits 22, 23, 28, etc.) can be provided in the layer 563.

[0138] Also, the layer 563 may be a laminate of multiple layers as shown in FIG. 21B. Although three layers, 563a, 563b, and 563c, are illustrated in FIG. 21B, two layers may be used. Alternatively, the layer 563 may be a laminate of four or more layers. These layers can be laminated using, for example, a bonding process. With this configuration, the pixel circuits and the functional circuits can be distributed among multiple layers and the pixel circuits and the functional circuits can be stacked, so that a small-sized, highly functional imaging device can be manufactured.

[0139] Alternatively, the pixel may have a stacked structure of a layer 561, a layer 562, and a layer 563 as shown in FIG. 21C.

[0140] The layer 562 can have OS transistors. For example, the circuit 10 can be formed in the layer 562, and the circuit 11 can be formed in the layer 563. One or more of the functional circuits described above may be formed using OS transistors. Alternatively, one or more of the functional circuits may be formed using Si transistors included in the layer 563 and OS transistors included in the layer 562. Alternatively, the layer 563 may be used as a supporting substrate such as a glass substrate, and a pixel circuit and a functional circuit may be formed using OS transistors included in the layer 562.

[0141] For example, a normally-off CPU (also referred to as an Noff-CPU) can be realized by using OS transistors and Si transistors. Note that an Noff-CPU is an integrated circuit including normally-off transistors that are in a non-conducting state (also referred to as an off state) even when the gate voltage is 0 V.

[0142] The Noff-CPU can stop the power supply to circuits in the Noff-CPU that are not required to operate, and put the circuits into a standby state. When the power supply is stopped and the circuits are in a standby state, no power is consumed. Thus, the Noff-CPU can minimize power consumption. The Noff-CPU can also retain information necessary for operation, such as setting conditions, for a long period of time even if the power supply is stopped. To return from the standby state, it is only necessary to resume the power supply to the circuit, and there is no need to rewrite the setting conditions, etc. In other words, high-speed return from the standby state is possible. In this way, the Noff-CPU can reduce power consumption without significantly reducing the operating speed.

[0143] Furthermore, layer 562 may be a laminate of multiple layers as shown in Fig. 21D. Although two layers, layer 562a and layer 562b, are illustrated in Fig. 21D, layer 562 may be a laminate of three or more layers. These layers may be formed by stacking them on layer 563, for example. Alternatively, layer 562 may be formed by bonding a layer formed on layer 563 and a layer formed on layer 561.

[0144] As a semiconductor material used for an OS transistor, a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used. A typical example is an oxide semiconductor containing indium, for example, CAAC-OS or CAC-OS described later can be used. CAAC-OS has stable atoms constituting the crystal, and is suitable for transistors that emphasize reliability. In addition, CAC-OS has high mobility characteristics, and is suitable for transistors that operate at high speed.

[0145] OS transistors have a large energy gap in the semiconductor layer, and therefore exhibit extremely low off-current characteristics of a few yA / μm (current value per 1 μm of channel width). OS transistors also have characteristics different from Si transistors, such as the absence of impact ionization, avalanche breakdown, and short channel effects, and can form highly reliable circuits with high voltage resistance. OS transistors are also less susceptible to variations in electrical characteristics caused by non-uniformity in crystallinity, which is a problem with Si transistors.

[0146] A semiconductor layer included in an OS transistor can be, for example, a film represented by an In-M-Zn-based oxide containing indium, zinc, and M (one or more selected from metals such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, and hafnium). The In-M-Zn-based oxide can be formed by, for example, a sputtering method, an atomic layer deposition (ALD) method, or a metal organic chemical vapor deposition (MOCVD) method.

[0147] When forming a film of an In-M-Zn oxide by a sputtering method, it is preferable that the atomic ratio of the metal elements of the sputtering target satisfies In≧M and Zn≧M. As the atomic ratio of the metal elements of such a sputtering target, In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=10:1:3, etc. are preferable. Note that the atomic ratio of the semiconductor layer to be formed includes a variation of ±40% of the atomic ratio of the metal elements contained in the above sputtering target.

[0148] The semiconductor layer is made of an oxide semiconductor with a low carrier density. For example, the semiconductor layer has a carrier density of 1×10 17 / cm 3 Less than or equal to 1×10 15 / cm 3 Less than 1×10, more preferably 13 / cm 3 Less than or equal to 1×10 11 / cm 3 Less than 1×10, more preferably 10 / cm 3 Less than 1 x 10 -9 / cm 3 The above oxide semiconductors can be used. Such an oxide semiconductor is called a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. The oxide semiconductor has a low density of defect states and has stable characteristics.

[0149] Note that the composition is not limited to these, and an appropriate composition may be used depending on the required semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the transistor. In order to obtain the required semiconductor characteristics of the transistor, it is preferable to appropriately set the carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, and the like of the semiconductor layer.

[0150] When silicon or carbon, which is one of the group 14 elements, is contained in the oxide semiconductor constituting the semiconductor layer, oxygen vacancies increase and the semiconductor layer becomes n-type. For this reason, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 2×10 18 atoms / cm 3 Less than or equal to 2×10 17 atoms / cm 3 The following applies.

[0151] In addition, when an alkali metal or an alkaline earth metal is bonded to an oxide semiconductor, carriers may be generated, which may increase the off-state current of a transistor. For this reason, the concentration of an alkali metal or an alkaline earth metal in a semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 1×10 18 atoms / cm 3 Less than or equal to 2×10 16 atoms / cm 3 To the following:

[0152] In addition, when nitrogen is contained in the oxide semiconductor constituting the semiconductor layer, electrons that act as carriers are generated, which increases the carrier density and makes the semiconductor layer more likely to be n-type. As a result, a transistor using an oxide semiconductor that contains nitrogen is likely to have normally-on characteristics. For this reason, the nitrogen concentration in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 5×10 18 atoms / cm 3 It is preferable to do the following:

[0153] Furthermore, when hydrogen is contained in an oxide semiconductor constituting a semiconductor layer, it reacts with oxygen bonded to a metal atom to form water, which may form oxygen vacancies in the oxide semiconductor. When oxygen vacancies are present in a channel formation region in an oxide semiconductor, the transistor may have normally-on characteristics. Furthermore, defects in which hydrogen has entered the oxygen vacancies may function as donors and generate electrons that serve as carriers. In addition, some of the hydrogen may bond with oxygen that is bonded to a metal atom to generate electrons that serve as carriers. Therefore, a transistor using an oxide semiconductor that contains a large amount of hydrogen is likely to have normally-on characteristics.

[0154] A defect in which hydrogen has entered an oxygen vacancy can function as a donor for an oxide semiconductor. However, it is difficult to quantitatively evaluate the defect. Thus, an oxide semiconductor may be evaluated by its carrier concentration instead of its donor concentration. Thus, in this specification and the like, a carrier concentration assuming a state in which no electric field is applied may be used as a parameter of an oxide semiconductor instead of the donor concentration. In other words, the "carrier concentration" described in this specification and the like may be rephrased as the "donor concentration".

[0155] Therefore, it is preferable that hydrogen in the oxide semiconductor be reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor measured by secondary ion mass spectrometry (SIMS) is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 When an oxide semiconductor in which impurities such as hydrogen are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0156] The semiconductor layer may have a non-single crystal structure. The non-single crystal structure includes, for example, a C-Axis Aligned Crystalline Oxide Semiconductor (CAAC-OS) having crystals oriented along the c-axis, a polycrystalline structure, a microcrystalline structure, or an amorphous structure. Among the non-single crystal structures, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density of defect states.

[0157] An oxide semiconductor film having an amorphous structure has, for example, a disordered atomic arrangement and does not include a crystalline component, or an oxide film having an amorphous structure has, for example, a completely amorphous structure and does not include a crystalline portion.

[0158] The semiconductor layer may be a mixed film having two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. The mixed film may have a single layer structure or a multilayer structure including two or more of the above-mentioned regions.

[0159] The following describes the structure of a cloud-aligned composite (CAC)-OS, which is one type of non-single crystal semiconductor layer.

[0160] CAC-OS is, for example, a material in which elements constituting an oxide semiconductor are unevenly distributed with a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or thereabouts. Note that, hereinafter, a state in which one or more metal elements are unevenly distributed in an oxide semiconductor and regions containing the metal elements are mixed with a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or thereabouts, is also referred to as a mosaic or patch shape.

[0161] The oxide semiconductor preferably contains at least indium, particularly indium and zinc, and may further contain one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.

[0162] For example, the CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide among CAC-OS may be specifically referred to as CAC-IGZO) is an indium oxide (hereinafter, InO X1 (X1 is a real number greater than 0).) or indium zinc oxide (hereinafter, In X2 Zinc Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0.) and gallium oxide (GaO X3 (X3 is a real number greater than 0). ) or gallium zinc oxide (Ga X4 Zinc Y4 O Z4 (X4, Y4, and Z4 are real numbers greater than 0).) The material is separated into a mosaic shape, and the mosaic shape of InO X1 , or In X2 Zinc Y2 O Z2 However, the structure is such that the particles are uniformly distributed in the film (hereinafter, also referred to as a cloud-like structure).

[0163] In other words, CAC-OS is X3 The region where In is the main component and X2 Zinc Y2 O Z2 , or InO X1 In this specification, for example, when the atomic ratio of In to element M in the first region is greater than the atomic ratio of In to element M in the second region, the first region is said to have a higher In concentration than the second region.

[0164] IGZO is a common name and may refer to a compound made of In, Ga, Zn, and O. A typical example is InGaO 3 (ZnO) m1 (m1 is a natural number), or In (1+x0) Ga (1-x0) O 3 (ZnO) m0 (-1≦x0≦1, m0 is an arbitrary number).

[0165] The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure, where multiple IGZO nanocrystals have a c-axis orientation and are connected without being oriented in the ab plane.

[0166] On the other hand, CAC-OS is a material composition of oxide semiconductor. CAC-OS is a material composition containing In, Ga, Zn, and O, in which some regions observed as nanoparticles mainly composed of Ga and some regions observed as nanoparticles mainly composed of In are randomly distributed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary element.

[0167] Note that the CAC-OS does not include a laminated structure of two or more films with different compositions, such as a two-layer structure consisting of a film mainly containing In and a film mainly containing Ga.

[0168] In addition, GaO X3 The region where In is the main component and X2 Zinc Y2 O Z2 , or InO X1 In some cases, it may be difficult to observe a clear boundary between the region in which the main component is the

[0169] In addition, when one or more elements selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. are contained instead of gallium, the CAC-OS has a configuration in which some regions observed to be in the form of nanoparticles mainly composed of the metal element and some regions observed to be in the form of nanoparticles mainly composed of In are randomly dispersed in a mosaic pattern.

[0170] CAC-OS can be formed, for example, by a sputtering method under conditions where the substrate is not intentionally heated. When CAC-OS is formed by a sputtering method, any one or more selected from an inert gas (typically argon), oxygen gas, and nitrogen gas may be used as a deposition gas. The lower the flow rate ratio of oxygen gas to the total flow rate of deposition gas during deposition, the more preferable it is, for example, 0% or more and less than 30%, preferably 0% or more and 10% or less.

[0171] CAC-OS has the characteristic that no clear peaks are observed when it is measured using the θ / 2θ scan by the out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. In other words, the X-ray diffraction measurement shows that there is no orientation in the ab plane direction or the c axis direction in the measurement area.

[0172] In addition, in the electron beam diffraction pattern obtained by irradiating CAC-OS with an electron beam (also called nano-beam electron beam) with a probe diameter of 1 nm, a ring-shaped region of high brightness (ring region) and multiple bright spots are observed in the ring region. Therefore, the electron beam diffraction pattern shows that the crystal structure of CAC-OS has an nc (nano-crystal) structure that does not have orientation in the planar direction and cross-sectional direction.

[0173] For example, in the case of CAC-OS of In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) revealed that GaO X3 The region where In is the main component and X2 Zinc Y2 O Z2 , or InO X1 It can be seen that the region in which the main component is the crystalline silicon is unevenly distributed and mixed.

[0174] CAC-OS has a different structure from IGZO compounds in which metal elements are uniformly distributed, and has different properties from IGZO compounds. X3 The main components are In X2 Zinc Y2 O Z2 , or InO X1 The structure is such that the regions having each element as the main component are separated from each other in a mosaic pattern.

[0175] Here, In X2 Zinc Y2 O Z2 , or InO X1 The area where GaO is the main component X3 This region has a higher electrical conductivity than the region where In is the main component. X2 Zinc Y2 O Z2 , or InO X1 When carriers flow through the region where In is the main component, the conductivity of the oxide semiconductor is expressed. X2 Zinc Y2 O Z2 , or InO X1 When the region mainly composed of is distributed in a cloud shape in the oxide semiconductor, high field-effect mobility (μ) can be achieved.

[0176] On the other hand, GaO X3 The region where the main components are In X2 Zinc Y2 O Z2 , or InOX1 This region has higher insulating properties than the region where GaO is the main component. X3 When a region containing these as main components is distributed in an oxide semiconductor, leakage current can be suppressed and favorable switching operation can be achieved.

[0177] Therefore, when CAC-OS is used in a semiconductor device, GaO X3 Insulation caused by X2 Zinc Y2 O Z2 , or InO X1 The conductivity caused by the MOSFET and the MOSFET's resistance to the MOSFET's resistance act in a complementary manner, resulting in a high on-state current (I on ), and high field-effect mobility (μ).

[0178] In addition, semiconductor elements using CAC-OS have high reliability, making CAC-OS suitable as a constituent material for various semiconductor devices.

[0179] <Laminated structure 1> Next, the laminated structure of the imaging device will be described using a cross-sectional view. Note that the elements such as the insulating layer and the conductive layer shown below are examples, and other elements may be further included. Alternatively, some of the elements shown below may be omitted. Also, the laminated structure shown below can be formed using a bonding process, a polishing process, etc., as necessary.

[0180] FIG. 23 is an example of a cross-sectional view of a laminate having layers 560, 561, and a layer 563, with a bonding surface between layers 563a and 563b that constitute layer 563.

[0181] <layer 563b> The layer 563b includes elements of the circuit 11 provided on the silicon substrate 610. Here, the transistors 203 and 204 included in the inverter 172, and the transistor 169 are shown as some of the elements of the circuit 11.

[0182] The layer 563b includes a silicon substrate 610 and insulating layers 611, 612, 613, 614, 615, 616, 617, and 618. A conductive layer 619 is also provided. The insulating layer 611 functions as a protective film. The insulating layers 612, 613, 614, 615, 616, and 617 function as an interlayer insulating film and a planarizing film. The insulating layer 618 and the conductive layer 619 function as a bonding layer. The conductive layer 619 is electrically connected to the transistor 169.

[0183] The protective film may be, for example, a silicon nitride film, a silicon oxide film, or an aluminum oxide film. The interlayer insulating film and the planarizing film may be, for example, an inorganic insulating film such as a silicon oxide film, or an organic insulating film such as an acrylic resin or a polyimide resin. The dielectric layer of the capacitor may be, for example, a silicon nitride film, a silicon oxide film, or an aluminum oxide film. The lamination layer will be described later.

[0184] The conductor that can be used as wiring, electrodes, and plugs for electrical connection between devices may be a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as components, or an alloy combining the above-mentioned metal elements, etc. The conductor is not limited to a single layer, and may be multiple layers composed of different materials.

[0185] <Layer 563a> The layer 563a includes elements of the circuit 10. Here, the transistor 102 and the transistor 106 are shown as some of the elements of the circuit 10. In the cross-sectional view shown in FIG. 23, electrical connection between the two is not shown.

[0186] The layer 563a is provided with a silicon substrate 632, insulating layers 631, 633, 634, 635, 637, and 638, and conductive layers 636 and 639.

[0187] The insulating layer 631 and the conductive layer 639 function as bonding layers. The insulating layers 634, 635, and 637 function as an interlayer insulating film and a planarizing film. The insulating layer 633 functions as a protective film. The insulating layer 638 functions to insulate the silicon substrate 632 and the conductive layer 639. The insulating layer 638 can be formed of the same material as the other insulating layers. The insulating layer 638 may be formed of the same material as the insulating layer 631.

[0188] The conductive layer 639 is electrically connected to the gate of the transistor 106 and the conductive layer 619. The conductive layer 636 is electrically connected to the wiring 121 (see FIG. 1).

[0189] The Si transistor shown in Fig. 23 is a fin type having a channel formation region in a silicon substrate (silicon substrates 610 and 632). A cross section in the channel width direction (a cross section of A1-A2 shown in layer 563a in Fig. 23) is shown in Fig. 24A. The Si transistor may be a planar type as shown in Fig. 24B.

[0190] 24C, it may be a transistor having a silicon thin-film semiconductor layer 545. The semiconductor layer 545 may be, for example, single crystal silicon (SOI (Silicon on Insulator)) formed on an insulating layer 546 on a silicon substrate 632.

[0191] <layer 561> The layer 561 has a photoelectric conversion device 101. The photoelectric conversion device 101 can be formed on the layer 563a. Fig. 23 shows a configuration in which the organic photoconductive film shown in Fig. 22C is used as the photoelectric conversion layer for the photoelectric conversion device 101. Here, the layer 567a is a cathode, and the layer 567e is an anode.

[0192] Layer 561 is provided with insulating layers 651, 652, 653, 654 and a conductive layer 655.

[0193] The insulating layers 651, 653, and 654 function as an interlayer insulating film and a planarizing film. The insulating layer 654 is provided to cover the end of the photoelectric conversion device 101, and also functions to prevent a short circuit between the layer 567e and the layer 567a. The insulating layer 652 functions as an element isolation layer. It is preferable to use an organic insulating film or the like as the element isolation layer.

[0194] The layer 567a corresponding to the cathode of the photoelectric conversion device 101 is electrically connected to one of the source and drain of the transistor 102 included in the layer 563a. The layer 567e corresponding to the anode of the photoelectric conversion device 101 is electrically connected to the conductive layer 636 included in the layer 563a through the conductive layer 655.

[0195] <layer 560> The layer 560 is formed on the layer 561. The layer 560 includes a light-shielding layer 671, an optical conversion layer 672, and a microlens array 673.

[0196] The light-shielding layer 671 can suppress the inflow of light into adjacent pixels. A metal layer such as aluminum or tungsten can be used for the light-shielding layer 671. In addition, the metal layer and a dielectric film having a function as an anti-reflection film may be laminated.

[0197] A color filter can be used for the optical conversion layer 672. A color image can be obtained by assigning colors such as red (red), green (G), blue (B), yellow (Y), cyan (C), and magenta (M) to the color filters for each pixel. For example, as shown in the perspective view (including the cross section) of FIG. 31A, a color filter 672R (red), a color filter 672G (green), and a color filter 672B (blue) can be assigned to different pixels.

[0198] Furthermore, if a wavelength cut filter is used in the optical conversion layer 672, an imaging device capable of obtaining images in various wavelength regions can be obtained.

[0199] For example, an infrared imaging device can be formed by using an infrared filter that blocks light with wavelengths equal to or shorter than visible light in the optical conversion layer 672. A far-infrared imaging device can be formed by using a filter that blocks light with wavelengths equal to or shorter than near-infrared light in the optical conversion layer 672. An ultraviolet imaging device can be formed by using an ultraviolet filter that blocks light with wavelengths equal to or longer than visible light in the optical conversion layer 672.

[0200] In addition, a plurality of different optical conversion layers may be arranged in one imaging device. For example, as shown in FIG. 31B, a color filter 672R (red), a color filter 672G (green), a color filter 672B (blue), and an infrared filter 672IR can be assigned to different pixels. In this configuration, a visible light image and an infrared light image can be acquired simultaneously.

[0201] 31C, color filter 672R (red), color filter 672G (green), color filter 672B (blue), and ultraviolet filter 672UV can be assigned to different pixels. In this configuration, a visible light image and an ultraviolet light image can be acquired simultaneously.

[0202] Furthermore, if a scintillator is used for the optical conversion layer 672, it can be used as an imaging device for obtaining an image that visualizes the intensity of radiation to be used in an X-ray imaging device or the like. When radiation such as X-rays that has passed through a subject is incident on the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by the photoluminescence phenomenon. Then, image data is obtained by detecting the light with the photoelectric conversion device 101. Also, an imaging device having such a configuration may be used as a radiation detector or the like.

[0203] Scintillators contain materials that absorb the energy of radiation, such as X-rays or gamma rays, and emit visible or ultraviolet light when irradiated with the radiation. For example, Gd 2 O2 S: Tb, Gd 2 O 2 S: Pr, Gd 2 O 2 S:Eu, BaFCl:Eu, NaI, CsI, CaF 2 , BaF 2 , CeF 3 , LiF, LiI, ZnO, etc. dispersed in resin or ceramics can be used.

[0204] A microlens array 673 is provided on the optical conversion layer 672. Light passing through each lens of the microlens array 673 passes through the optical conversion layer 672 directly below, and is irradiated onto the photoelectric conversion device 101. By providing the microlens array 673, concentrated light can be incident on the photoelectric conversion device 101, so that photoelectric conversion can be performed efficiently. The microlens array 673 is preferably formed of a resin or glass that is highly translucent to light of the wavelength of the object of imaging.

[0205] <Lamination> Next, the bonding of the layer 563b and the layer 563a will be described.

[0206] The layer 563b is provided with an insulating layer 618 and a conductive layer 619. The conductive layer 619 has a region buried in the insulating layer 618. The surfaces of the insulating layer 618 and the conductive layer 619 are flattened so that they are at the same height.

[0207] The layer 563a is provided with an insulating layer 631 and a conductive layer 639. The conductive layer 639 has a region buried in the insulating layer 631. The surfaces of the insulating layer 631 and the conductive layer 639 are flattened so that they are at the same height.

[0208] Here, the conductive layer 619 and the conductive layer 639 preferably contain the same metal element as a main component. The insulating layer 618 and the insulating layer 631 preferably contain the same component.

[0209] For example, Cu, Al, Sn, Zn, W, Ag, Pt, or Au can be used for the conductive layers 619 and 639. Cu, Al, W, or Au is preferably used because of ease of bonding. Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, titanium nitride, or the like can be used for the insulating layers 618 and 631.

[0210] That is, the same metal material as described above is preferably used for the conductive layer 619 and the conductive layer 639. The same insulating material as described above is preferably used for the insulating layer 618 and the insulating layer 631. With this structure, the layer 563b and the layer 563a can be bonded to each other at a boundary between them.

[0211] The conductive layers 619 and 639 may have a multi-layer structure with multiple layers, in which case the surface layers (joint surfaces) may be made of the same metal material. The insulating layers 618 and 631 may also have a multi-layer structure with multiple layers, in which case the surface layers (joint surfaces) may be made of the same insulating material.

[0212] This bonding makes it possible to obtain electrical connection between the conductive layer 619 and the conductive layer 639. Also, it makes it possible to obtain a connection between the insulating layer 618 and the insulating layer 631 that has sufficient mechanical strength.

[0213] To bond metal layers together, a surface activation bonding method can be used, in which oxide films and adsorbed layers of impurities on the surfaces are removed by sputtering or other methods, and cleaned and activated surfaces are brought into contact with each other to bond them. Alternatively, a diffusion bonding method can be used, in which surfaces are bonded together using a combination of temperature and pressure. Both methods involve bonding at the atomic level, resulting in excellent bonding not only electrically but also mechanically.

[0214] In addition, for bonding insulating layers, a hydrophilic bonding method can be used in which high flatness is achieved by polishing, etc., and then the surfaces that have been hydrophilically treated with oxygen plasma or the like are brought into contact with each other to form a temporary bond, and then the final bond is achieved by dehydrating them through heat treatment. Hydrophilic bonding also produces bonds at the atomic level, and therefore can provide mechanically excellent bonds.

[0215] When bonding the layer 563b and the layer 563a, an insulating layer and a metal layer are mixed on each bonding surface, so that, for example, a surface activated bonding method and a hydrophilic bonding method may be combined.

[0216] For example, a method of cleaning the surface after polishing, subjecting the surface of the metal layer to an anti-oxidation treatment, and then subjecting it to a hydrophilic treatment and bonding can be used. The surface of the metal layer may be made of a resistant metal such as Au and then subjected to a hydrophilic treatment. Note that bonding methods other than the above-mentioned methods may also be used.

[0217] By the above-mentioned bonding, the elements included in the layer 563b can be electrically connected to the elements included in the layer 563a.

[0218] <Modification of Laminate Structure 1> FIG. 25 shows a modified example of the stacked structure shown in FIG. 23, in which the configuration of the photoelectric conversion device 101 in the layer 561 and a portion of the configuration of the layer 563a are different, and a bonding surface is also provided between the layer 561 and the layer 563a.

[0219] Layer 561 includes photovoltaic device 101, insulating layers 661, 662, 664, 665 and conductive layers 685,686.

[0220] The photoelectric conversion device 101 is a pn junction type photodiode formed on a silicon substrate, and has a layer 565b corresponding to a p-type region and a layer 565a corresponding to an n-type region. The photoelectric conversion device 101 is a buried type photodiode, and a thin p-type region (part of the layer 565b) provided on the front side (current extraction side) of the layer 565a can suppress dark current and reduce noise.

[0221] The insulating layer 661 and the conductive layers 685 and 686 function as bonding layers. The insulating layer 662 functions as an interlayer insulating film and a planarizing film. The insulating layer 664 functions as an element isolation layer. The insulating layer 665 functions to suppress the outflow of carriers.

[0222] The silicon substrate is provided with grooves for separating pixels, and the insulating layer 665 is provided on the upper surface of the silicon substrate and in the grooves. By providing the insulating layer 665, it is possible to prevent carriers generated in the photoelectric conversion device 101 from flowing out to adjacent pixels. The insulating layer 665 also has a function of preventing the intrusion of stray light. Therefore, the insulating layer 665 can prevent color mixing. An anti-reflection film may be provided between the upper surface of the silicon substrate and the insulating layer 665.

[0223] The element isolation layer can be formed by using a LOCOS (LOCal Oxidation of Silicon) method. Alternatively, it may be formed by using a STI (Shallow Trench Isolation) method or the like. For example, an inorganic insulating film such as silicon oxide or silicon nitride, or an organic insulating film such as polyimide or acrylic can be used as the insulating layer 665. The insulating layer 665 may have a multi-layer structure. It is also possible to adopt a structure in which no element isolation layer is provided.

[0224] A layer 565a (n-type region, corresponding to a cathode) of the photoelectric conversion device 101 is electrically connected to a conductive layer 685. A layer 565b (p-type region, corresponding to an anode) is electrically connected to a conductive layer 686. The conductive layers 685 and 686 have regions embedded in an insulating layer 661. The surfaces of the insulating layer 661 and the conductive layers 685 and 686 are flattened so that they are at the same height.

[0225] In the layer 563a, an insulating layer 638 is formed over the insulating layer 637. In addition, a conductive layer 683 electrically connected to one of the source and the drain of the transistor 102, and a conductive layer 684 electrically connected to the conductive layer 636 are formed.

[0226] The insulating layer 638 and the conductive layers 683 and 684 function as bonding layers. The conductive layers 683 and 684 have a region buried in the insulating layer 638. The surfaces of the insulating layer 638 and the conductive layers 683 and 684 are flattened so that they are at the same height.

[0227] Here, the conductive layers 683, 684, 685, and 686 are lamination layers similar to the above-described conductive layers 619 and 639. The insulating layers 638 and 661 are lamination layers similar to the above-described insulating layers 618 and 631.

[0228] Therefore, by bonding the conductive layer 683 and the conductive layer 685 together, it is possible to electrically connect the layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device to one of the source or drain of the transistor 102. Also, by bonding the conductive layer 684 and the conductive layer 686 together, it is possible to electrically connect the layer 565b (p-type region, corresponding to the anode) of the photoelectric conversion device to the wiring 121 (see FIG. 1). Also, by bonding the insulating layer 638 and the insulating layer 661 together, it is possible to electrically and mechanically bond the layer 561 to the layer 563a.

[0229] <Laminated structure 2> 26 is an example of a cross-sectional view of a stack having layers 560, 561, 562, and 563 and no bonding surface. A Si transistor is provided in the layer 563. An OS transistor is provided in the layer 562. Note that the structures of the layers 563, 561, and 560 are the same as those shown in FIG. 23, and therefore description thereof will be omitted here.

[0230] <layer 562> A layer 562 is formed on the layer 563. The layer 562 includes OS transistors. Here, the transistors 102 and 106 are shown as part of the components of the circuit 10. In the cross-sectional view shown in FIG. 26, the electrical connection between the two is not shown.

[0231] Insulating layers 621, 622, 623, 624, 625, 626, and 628 are provided in the layer 562. In addition, a conductive layer 627 is provided. The conductive layer 627 can be electrically connected to the wiring 121 (see FIG. 1).

[0232] The insulating layer 621 functions as a blocking layer. The insulating layers 622, 623, 625, 626, and 628 function as an interlayer insulating film and a planarizing film. The insulating layer 624 functions as a protective film.

[0233] The blocking layer is preferably a film having a function of preventing hydrogen diffusion. In a Si device, hydrogen is required to terminate dangling bonds, but hydrogen near an OS transistor is one of the factors that generate carriers in an oxide semiconductor layer, thereby reducing reliability. Therefore, a hydrogen blocking film is preferably provided between a layer in which a Si device is formed and a layer in which an OS transistor is formed.

[0234] As the blocking film, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria stabilized zirconia (YSZ), or the like can be used.

[0235] The gate of the transistor 106 is electrically connected to the transistor 169 via a plug.

[0236] One of the source and the drain of the transistor 102 is electrically connected to a layer 567a of the photoelectric conversion device 101 included in the layer 561. The conductive layer 627 is electrically connected to a layer 567e of the photoelectric conversion device 101 included in the layer 561.

[0237] Fig. 27A shows details of an OS transistor. The OS transistor shown in Fig. 27A has a self-aligned structure in which an insulating layer is provided over a stack of an oxide semiconductor layer and a conductive layer, and a source electrode 705 and a drain electrode 706 are formed by providing openings that reach the oxide semiconductor layer.

[0238] The OS transistor can have a channel formation region, a source region 703, and a drain region 704 formed in the oxide semiconductor layer, as well as a gate electrode 701 and a gate insulating film 702. At least the gate insulating film 702 and the gate electrode 701 are provided in the opening. An oxide semiconductor layer 707 may be further provided in the opening.

[0239] As shown in FIG. 27B, the OS transistor may have a self-aligned structure in which a source region 703 and a drain region 704 are formed in a semiconductor layer using a gate electrode 701 as a mask.

[0240] Alternatively, as shown in FIG. 27C, it may be a non-self-aligned top-gate transistor having a region where the source electrode 705 or the drain electrode 706 overlaps with the gate electrode 701.

[0241] Although the OS transistor has a structure having a back gate 535, it may have a structure without a back gate. The back gate 535 may be electrically connected to the front gate of the transistor provided opposite to it, as shown in the cross-sectional view of the transistor in the channel width direction shown in Fig. 27D. Note that Fig. 27D shows the cross section of the transistor taken along B1-B2 in Fig. 27A as an example, but the same applies to transistors of other structures. In addition, a fixed potential different from that of the front gate may be supplied to the back gate 535.

[0242] <Modification 1 of laminate structure 2> FIG. 28 shows a modified example of the stacked structure shown in FIG. 26, in which the configuration of the photoelectric conversion device 101 included in the layer 561 and a portion of the configuration of the layer 562 are different, and a bonding surface is provided between the layers 561 and 562.

[0243] The photoelectric conversion device 101 included in the layer 561 is a pn junction type photodiode formed on a silicon substrate, and has the same configuration as that shown in FIG.

[0244] In the layer 562, an insulating layer 648 is formed over the insulating layer 626. In addition, a conductive layer 688 electrically connected to one of the source and the drain of the transistor 102, and a conductive layer 689 electrically connected to the conductive layer 627 are formed.

[0245] The insulating layer 648 and the conductive layers 688 and 689 function as bonding layers. The conductive layers 688 and 689 have a region buried in the insulating layer 648. The surfaces of the insulating layer 648 and the conductive layers 688 and 689 are flattened so that they are at the same height.

[0246] Here, the conductive layers 688 and 689 are lamination layers similar to the above-described conductive layers 619 and 639. The insulating layer 648 is a lamination layer similar to the above-described insulating layers 618 and 631.

[0247] Therefore, by bonding the conductive layer 688 and the conductive layer 685 together, it is possible to electrically connect the layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device to one of the source or drain of the transistor 102. Also, by bonding the conductive layer 689 and the conductive layer 686 together, it is possible to electrically connect the layer 565b (p-type region, corresponding to the anode) of the photoelectric conversion device to the wiring 121 (see FIG. 1). Also, by bonding the insulating layer 648 and the insulating layer 661 together, it is possible to electrically and mechanically bond the layer 561 to the layer 562a.

[0248] When stacking multiple Si devices, the polishing and bonding processes are required multiple times. This poses issues such as a large number of steps, the need for dedicated equipment, low yields, and high manufacturing costs. OS transistors can be formed by stacking on a silicon substrate on which devices are already formed, eliminating the need for the bonding process.

[0249] <Modification 2 of laminated structure 2> FIG. 29 shows a modified example of the laminated structure shown in FIG. 28, in which the configuration of layer 561 and part of the configuration of layer 562 are different, and a bonding surface is provided between layer 561 and layer 562.

[0250] In this modified example, the transistor 102 included in the circuit 10 is provided in a layer 561. In the layer 561, the transistor 102 is formed of a Si transistor. One of the source and the drain of the transistor 102 is directly connected to the photoelectric conversion device 101, and the other of the source and the drain acts as a node FD1.

[0251] In this case, the layer 562 includes all the transistors included in the circuit 10 except for at least the transistor 102. FIG. 29 illustrates an example in which the transistor 104 and the transistor 106 are provided.

[0252] <Laminated structure 3> 25 to 29 show an example of a stacked structure for the circuit 10 shown in FIG. 1, but the circuit 10 shown in FIG. 2B may have a structure shown in FIG. 30. FIG. 30 shows an example of a structure in which Si transistors 102, 103, 104, 105, and 106 (transistor 105 is not shown) are provided in a layer 561, and a transistor 111 that is an OS transistor is provided in the layer 561. Note that FIG. 30 shows an example of a structure in which the layer 562 and the layer 563 are bonded to each other, but the layer 561 and the layer 562 may be bonded to each other as in FIG. 29.

[0253] <Package, module> Fig. 32A1 is a perspective view showing the appearance of the upper surface of a package containing an image sensor chip. The package includes a package substrate 410 for fixing an image sensor chip 450 (see Fig. 32A3), a cover glass 420, and an adhesive 430 for bonding the two together.

[0254] 32A2 is an external perspective view of the bottom surface of the package. The bottom surface of the package has a BGA (Ball grid array) with solder balls as bumps 440. Note that the package is not limited to a BGA, and may have an LGA (Land grid array) or a PGA (Pin Grid Array), etc.

[0255] 32A3 is a perspective view of the package with a portion of the cover glass 420 and the adhesive 430 omitted. Electrode pads 460 are formed on the package substrate 410, and the electrode pads 460 and the bumps 440 are electrically connected via through holes. The electrode pads 460 are electrically connected to the image sensor chip 450 by wires 470.

[0256] Fig. 32B1 is a perspective view showing the appearance of the upper surface of a camera module in which an image sensor chip is housed in a lens-integrated package. The camera module includes a package substrate 411 for fixing an image sensor chip 451 (see Fig. 32B3), a lens cover 421, and a lens 435. An IC chip 490 (see Fig. 32B3) having functions such as a drive circuit for an imaging device and a signal conversion circuit is also provided between the package substrate 411 and the image sensor chip 451, and the camera module is configured as a SiP (System in Package).

[0257] 32B2 is a perspective view of the appearance of the bottom surface side of the camera module. The bottom surface and side surfaces of the package substrate 411 have a QFN (Quad flat no-lead package) configuration with mounting lands 441 provided thereon. Note that this configuration is one example, and a QFP (Quad flat package) or the above-mentioned BGA may also be provided.

[0258] 32B3 is a perspective view of the module in which a portion of lens cover 421 and lens 435 is omitted. Land 441 is electrically connected to electrode pad 461, and electrode pad 461 is electrically connected to image sensor chip 451 or IC chip 490 by wire 471.

[0259] By housing the image sensor chip in a package of the above-mentioned type, mounting on a printed circuit board or the like becomes easy, and the image sensor chip can be incorporated into various semiconductor devices and electronic devices.

[0260] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes.

[0261] (Embodiment 3) Examples of electronic devices that can use the imaging device according to one embodiment of the present invention include display devices, personal computers, image storage devices or image playback devices equipped with a recording medium, mobile phones, game machines including portable types, portable data terminals, electronic book terminals, cameras such as video cameras and digital still cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer-combined machines, automated teller machines (ATMs), vending machines, etc. Specific examples of these electronic devices are shown in Figures 33A to 33F.

[0262] 33A shows an example of a mobile phone, which includes a housing 981, a display portion 982, operation buttons 983, an external connection port 984, a speaker 985, a microphone 986, a camera 987, and the like. The mobile phone includes a touch sensor in the display portion 982. Any operation, such as making a call or inputting characters, can be performed by touching the display portion 982 with a finger or a stylus. The imaging device of one embodiment of the present invention and the operating method thereof can be applied to the mobile phone, thereby reducing power consumption.

[0263] 33B shows a portable data terminal, which includes a housing 911, a display portion 912, a speaker 913, a camera 919, and the like. Information can be input and output using a touch panel function of the display portion 912. Characters and the like can be recognized from an image acquired by the camera 919, and the characters can be output as voice through the speaker 913. The imaging device of one embodiment of the present invention and an operating method thereof can be applied to the portable data terminal, thereby reducing power consumption.

[0264] FIG. 33C shows a surveillance camera, which includes a support base 951, a camera unit 952, a protective cover 953, and the like. The camera unit 952 is provided with a rotation mechanism and the like, and can capture images of the entire surroundings by being installed on a ceiling. The imaging device and the operation method thereof according to one embodiment of the present invention can be applied to an element for acquiring an image in the camera unit, and power consumption can be reduced. Note that the term "surveillance camera" is a common name and is not intended to limit the use. For example, a device having a function as a surveillance camera is also called a camera or a video camera.

[0265] 33D shows a video camera having a first housing 971, a second housing 972, a display unit 973, operation keys 974, a lens 975, a connection unit 976, a speaker 977, a microphone 978, and the like. The operation keys 974 and the lens 975 are provided in the first housing 971, and the display unit 973 is provided in the second housing 972. The imaging device and the operating method thereof according to one embodiment of the present invention can be applied to the video camera, and power consumption can be reduced.

[0266] 33E shows a digital camera including a housing 961, a shutter button 962, a microphone 963, a light-emitting portion 967, a lens 965, and the like. The imaging device and the operating method thereof according to one embodiment of the present invention can be applied to the digital camera, and power consumption can be reduced.

[0267] 33F shows a wristwatch-type information terminal, which includes a display portion 932, a housing / wristband 933, a camera 939, and the like. The display portion 932 includes a touch panel for operating the information terminal. The display portion 932 and the housing / wristband 933 are flexible and have excellent wearability on the body. The imaging device and the operating method thereof according to one embodiment of the present invention can be applied to this information terminal, thereby reducing power consumption.

[0268] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes. [Explanation of symbols]

[0269] 10: circuit, 11: circuit, 11A: sense amplifier, 11B: sense amplifier, 11C: output circuit, 21: pixel array, 22: circuit, 23: circuit, 24: circuit, 25: circuit, 26: circuit, 28: circuit, 101: photoelectric conversion device, 102: transistor, 103: transistor, 104: transistor, 105: transistor, 106: transistor, 107: transistor, 108: capacitor, 109: capacitor, 111: transistor, 112: OR circuit, 113: transistor, 121: wiring, 122: wiring, 123: wiring, 124: wiring, 125 : Wiring, 127: Wiring, 128: Wiring, 129: Wiring, 131: Transistor, 132: Transistor, 133: Transistor, 134: Transistor, 135: Transistor, 136: Transistor, 137: Transistor, 138: Transistor, 141: Transistor, 142: Transistor, 143: Transistor, 144: Transistor, 145: Transistor, 146: Transistor, 147: Transistor, 148: Transistor, 151: Transistor, 152: Transistor, 153: Transistor, 154: Transistor, 155: Transistor, 156: transistor, 157: transistor, 158: transistor, 161: transistor, 162: transistor, 163: transistor, 164: transistor, 165: transistor, 166: transistor, 167: transistor, 168: transistor, 169: transistor, 171: inverter, 172: inverter, 203: transistor, 204: transistor, 231: wiring, 232: wiring, 233: wiring, 234: wiring, 235: wiring, 236: wiring, 237: wiring, 238: wiring, 239: wiring, 241: wiring Line, 242: wiring, 410: package substrate, 411: package substrate, 420: cover glass, 421: lens cover, 430: adhesive, 435: lens, 440: bump, 441: land, 450: image sensor chip, 451: image sensor chip, 460: electrode pad, 461: electrode pad, 470: wire, 471: wire, 490: IC chip, 535: back gate, 545: semiconductor layer, 546: insulating layer, 560: layer, 561: layer, 562: layer, 562a: layer, 562b: layer, 563: layer, 563a: layer, 563b: layer, 563c: layer,565a: layer, 565b: layer, 566a: layer, 566b: layer, 566c: layer, 566d: layer, 567a: layer, 567b: layer, 567c: layer, 567d: layer, 567e: layer, 610: silicon substrate, 611: insulating layer, 612: insulating layer, 613: insulating layer, 614: insulating layer, 615: insulating layer, 616: insulating layer, 617: insulating layer, 618: insulating layer, 619: conductive layer, 621: insulating layer, 622: insulating layer, 623: insulating layer, 624: insulating layer, 625: insulating layer , 626: insulating layer, 627: conductive layer, 628: insulating layer, 631: insulating layer, 632: silicon substrate, 633: insulating layer, 634: insulating layer, 635: insulating layer, 636: conductive layer, 637: insulating layer, 638: insulating layer, 639: conductive layer, 648: insulating layer, 651: insulating layer, 652: insulating layer, 653: insulating layer, 654: insulating layer, 655: conductive layer, 661: insulating layer, 662: insulating layer, 664: insulating layer, 665: insulating layer, 671: light shielding layer, 672: optical conversion layer, 6 73: microlens array, 683: conductive layer, 684: conductive layer, 685: conductive layer, 686: conductive layer, 688: conductive layer, 689: conductive layer, 701: gate electrode, 702: gate insulating film, 703: source region, 704: drain region, 705: source electrode, 706: drain electrode, 707: oxide semiconductor layer, 911: housing, 912: display unit, 913: speaker, 919: camera, 932: display unit, 933: housing / wristband, 939: camera, 951: support stand, 952: camera unit, 953: protective cover, 961: housing, 962: shutter button, 963: microphone, 965: lens, 967: light emitting section, 971: housing, 972: housing, 973: display section, 974: operation keys, 975: lens, 976: connection section, 977: speaker, 978: microphone, 981: housing, 982: display section, 983: operation button, 984: external connection port, 985: speaker, 986: microphone, 987: camera,

Claims

1. An imaging device including a pixel having a first circuit and a second circuit, the first circuit includes a first switch; the first circuit has a function of holding first image data generated in a first frame period at a first node of the first circuit; the first circuit has a function of holding second image data generated in an n-th frame period (n is a natural number equal to or greater than 2) at the first node; the first circuit has a function of holding, at a second node of the first circuit, difference data that is a difference between the first image data and the second image data; the first switch has a function of controlling an output of the first image data and the second image data; the second circuit includes a comparison circuit and an output circuit; the comparison circuit has a function of determining whether the difference data is within an arbitrarily set voltage range, The output circuit has a function of outputting a voltage that turns off the first switch when the difference data is within the voltage range, and outputting a voltage that turns on the first switch when the difference data is not within the voltage range.

2. In claim 1, the first circuit includes a photoelectric conversion device, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, and a second capacitor; one electrode of the photoelectric conversion device is electrically connected to one of the source and drain of the first transistor; the other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor, a gate of the third transistor, one electrode of the first capacitor, and one electrode of the second capacitor; one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor; the other of the source and the drain of the third transistor is electrically connected to one of the source and the drain of the fifth transistor; the other electrode of the second capacitor is electrically connected to one of the source and the drain of the sixth transistor; The fifth transistor has a function as the first switch.

3. In claim 2, The imaging device includes the first to sixth transistors each having a channel formation region formed of a metal oxide.

4. In claim 2 or 3, the first circuit further comprises a seventh transistor; one of the source and the drain of the seventh transistor is electrically connected to the other of the source and the drain of the first transistor and to one of the source and the drain of the second transistor; the other of the source and the drain of the seventh transistor is electrically connected to the gate of the third transistor, one electrode of the first capacitor, and one electrode of the second capacitor; The seventh transistor has a metal oxide in a channel formation region.

5. In claim 3 or claim 4, The metal oxide comprises In, Zn, and M (M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, and Hf).

6. In any one of claims 1 to 5, the comparison circuit includes a first sense amplifier and a second sense amplifier; the first sense amplifier has a first input section for inputting a voltage at the lower end of the voltage range; the second sense amplifier has a second input section for inputting a voltage at the upper end of the voltage range; the first sense amplifier and the second sense amplifier each have a third input section to which the second node is electrically connected; a third node of the first sense amplifier and a fourth node of the second sense amplifier are electrically connected to the output circuit; The imaging device, wherein a fifth node of the output circuit is electrically connected to the first switch.

7. In claim 6, the second node of one pixel is electrically connected to the third input section; an imaging device, the fifth node being electrically connected to the first switches of a plurality of pixels;

8. In claim 6 or 7, the second circuit further includes an inverter circuit; an inverter circuit, a first sense amplifier, a second sense amplifier, and an output circuit each having a transistor, the transistor having silicon in a channel formation region;

9. In claim 6 or 7, the first sense amplifier and the second sense amplifier each have a first power switch and a second power switch; the first power switch has a p-channel transistor; the second power switch has an n-channel transistor; the n-channel transistor has a metal oxide in a channel formation region, The metal oxide comprises In, Zn, and M (M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, and Hf).

10. In any one of claims 1 to 9, An imaging device, wherein the first circuit and the second circuit have an overlapping area.

11. In any one of claims 1 to 9, An imaging device, wherein a plurality of the first circuits and one of the second circuits have an overlapping area.

12. 12. An electronic device comprising: the imaging device according to claim 1; and a display device.

Images