Solid-state imaging device, imaging apparatus, and method for controlling solid-state imaging device

Abstract

A solid-state imaging element for comparing a reference signal with a pixel signal, wherein a frame rate is improved.　A differential amplification circuit amplifies a difference in potential between each of a pair of input nodes and outputs the difference from an output node. A transfer transistor transfers electric charges from a photoelectric conversion element to a floating diffusion layer. The gate of a source follower transistor is connected to the floating diffusion layer, and a source is connected to one of the pair of input nodes. A measurement unit measures the gate-to-source voltage of the source follower transistor and supplies a measured value. A correction-computing unit computes a correction value that corrects the potential of the other of the pair of input nodes on the basis of the measured value.

Description

[Technical field]

[0001] The present technology relates to a solid-state imaging element and an imaging device, and more particularly to a solid-state imaging element in which an ADC (Analog to Digital Converter) is provided for each pixel, an imaging device, and a method for controlling the solid-state imaging element. [Background technology]

[0002] Conventionally, solid-state imaging devices with an ADC for each pixel have been used for the purpose of capturing image data at high speed. For example, a solid-state imaging device has been proposed in which a circuit with an ADC for each pixel is distributed and arranged on two stacked chips (see, for example, Non-Patent Document 1). In this solid-state imaging device, a floating diffusion layer in a pixel is connected to one of two input terminals of a differential amplifier circuit in the ADC, and a reference signal is input to the other of the input terminals. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Masaki Sakakibara, et al., A 6.9-μm Pixel-Pitch Back-Illuminated Global Shutter CMOS Image Sensor With Pixel-Parallel 14-Bit Subthreshold ADC, IEEE Journal of Solid-State Circuits 2018. Summary of the Invention [Problem to be solved by the invention]

[0004] In the above-mentioned conventional technology, circuits are distributed across two stacked chips to achieve high functionality and finer pixel size. However, in the above-mentioned conventional technology, a change in the reference signal is transmitted to a node in the floating diffusion layer via the parasitic capacitance in the differential amplifier circuit, which can cause the potential of the node to fluctuate. This potential fluctuation can delay the timing at which the output of the differential amplifier circuit is inverted, and this delay can cause a decrease in frame rate.

[0005] The present technology has been developed in view of these circumstances, and aims to improve the frame rate in a solid-state imaging device that compares a reference signal with a pixel signal. [Means for solving the problem]

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect of the present technology is a solid-state imaging device including a differential amplifier circuit that amplifies the difference between the potentials of a pair of input nodes and outputs the amplified difference from an output node, a transfer transistor that transfers charges from a photoelectric conversion element to a floating diffusion layer, a source follower transistor having a gate connected to the floating diffusion layer and a source connected to one of the pair of input nodes, a measurement unit that measures the gate-source voltage of the source follower transistor and supplies the measured value, and a correction calculation unit that calculates a correction value that corrects the potential of the other of the pair of input nodes based on the measured value. This suppresses the potential fluctuation of the floating diffusion layer, thereby improving the frame rate. In addition, the correction value corrects the variation in the gate-source voltage.

[0007] In addition, in the first aspect, the pixel may further include a short-circuiting transistor that shorts the source and gate of the source follower transistor in accordance with a predetermined control signal, the differential amplifier circuit, the transfer transistor and the source follower transistor are disposed in the effective pixel and the measurement pixel, respectively, the short-circuiting transistor is disposed in the measurement pixel, and the measurement unit measures the gate-source voltage of the measurement pixel. This provides the effect of correcting variations in the gate-source voltage of the measurement pixel.

[0008] In the first aspect, the measurement section may measure the gate-source voltage every time a frame is captured, thereby improving the accuracy of correction.

[0009] In the first aspect, the measurement unit may measure the gate-source voltage at startup, thereby providing an effect that variations due to temperature fluctuations after chip testing are corrected.

[0010] In addition, in the first aspect, the measurement unit may measure the gate-source voltage when testing a chip, thereby providing an effect of reducing the amount of calculation.

[0011] In addition, in the first aspect, the pixel may further include a short-circuiting transistor that shorts the source and gate of the source follower transistor in accordance with a predetermined control signal, the differential amplifier circuit, the transfer transistor, the source follower transistor and the short-circuiting transistor being disposed in an effective pixel, and the measurement unit may measure the gate-source voltage of the effective pixel, thereby providing an effect of correcting variations in the gate-source voltage of the effective pixel.

[0012] In the first aspect, the measurement unit may measure the gate-source voltage at startup, thereby providing an effect that variations due to temperature fluctuations after chip testing are corrected.

[0013] In addition, in the first aspect, the measurement unit may measure the gate-source voltage when testing a chip, thereby providing an effect of reducing the amount of calculation.

[0014] In addition, in the first aspect, the measurement unit may measure, as the measurement value, a difference between a digital signal corresponding to a signal output from the differential amplifier circuit when the source and the gate are shorted and a digital signal corresponding to a signal output from the differential amplifier circuit when the source and the gate are not shorted, and the correction calculation unit may calculate a statistic of the measurement value as the correction value, thereby improving the correction accuracy.

[0015] In addition, in the first aspect, the digital signal processing device may further include a delay time integration processing unit that performs a time delay integration process on a digital signal corresponding to the signal output from the differential amplifier circuit.

[0016] In addition, in the first aspect, a part of the differential amplifier circuit, the transfer transistor, and the source follower transistor may be provided on a predetermined light receiving chip, and the remainder of the differential amplifier circuit, the measurement unit, and the correction calculation unit may be provided on a predetermined circuit chip, thereby providing an effect that the circuit is distributed and arranged on a plurality of chips.

[0017] In the first aspect, the photosensor chip and the circuit chip may be connected by Cu-Cu bonding, thereby providing an effect of electrically connecting the chips.

[0018] A second aspect of the present technology is an imaging device including a differential amplifier circuit that amplifies a difference between the potentials of a pair of input nodes and outputs the amplified potential from an output node, a transfer transistor that transfers charges from a photoelectric conversion element to a floating diffusion layer, a source follower transistor having a gate connected to the floating diffusion layer and a source connected to one of the pair of input nodes, a measurement unit that measures a gate-source voltage of the source follower transistor and supplies a measurement value, a correction calculation unit that calculates a correction value for correcting the potential of the other of the pair of input nodes based on the measurement value, and a storage unit that stores a frame in which a digital signal corresponding to a signal output from the differential amplifier circuit is arranged. This brings about an effect that a frame rate with improved image quality is stored. [Brief description of the drawings]

[0019] [Figure 1] 1 is a block diagram showing an example of a configuration of an imaging device according to a first embodiment of the present technology. [Diagram 2] 1 is a diagram for explaining a usage example of an imaging system according to a first embodiment of the present technology. [Diagram 3] 1 is a diagram showing an example of a layered structure of a solid-state imaging element according to a first embodiment of the present technology. [Figure 4] 1 is a block diagram showing a configuration example of a photosensor chip according to a first embodiment of the present technology; [Diagram 5] 1 is an example of a plan view of a pixel array unit according to a first embodiment of the present technology. [Figure 6] 1 is a block diagram showing a configuration example of a circuit chip according to a first embodiment of the present technology; [Figure 7] 2 is a diagram illustrating an example of a configuration of a pixel AD (Analog to Digital) conversion unit according to the first embodiment of the present technology. FIG. [Figure 8] 1 is a block diagram showing a configuration example of effective pixels and an ADC according to a first embodiment of the present technology. [Figure 9] 1 is a circuit diagram showing a configuration example of a differential amplifier and a positive feedback circuit according to a first embodiment of the present technology. [Figure 10] 1 is a circuit diagram showing a configuration example of a source follower circuit and a pixel circuit in an effective pixel according to a first embodiment of the present technology. [Figure 11] 4A to 4C are diagrams for explaining a method of controlling a transistor in an effective pixel in the first embodiment of the present technology. [Figure 12] 4 is a timing chart showing an example of a potential fluctuation in the first embodiment of the present technology. [Figure 13] 4 is a diagram illustrating an example of inversion timing of an output of a differential amplifier circuit according to a first embodiment of the present technology and a first comparative example. FIG. [Figure 14] 1 is a block diagram showing a configuration example of a measurement pixel and an ADC according to a first embodiment of the present technology. FIG. [Figure 15] 1 is a circuit diagram showing a configuration example of a source follower circuit and a pixel circuit according to a first embodiment of the present technology. [Figure 16] 1 is a block diagram showing a configuration example of a signal processing circuit according to a first embodiment of the present technology. [Figure 17] 10 is a block diagram showing another example of a signal processing circuit according to the first embodiment of the present technology. FIG. [Figure 18] 4A to 4C are diagrams for explaining a correction method according to the first embodiment of the present technology. [Figure 19] 4 is a flowchart showing an example of a measurement process in the first embodiment of the present technology. [Figure 20] 13 is a circuit diagram showing a configuration example of a differential amplifier, a source follower circuit, and a pixel circuit in an effective pixel according to a second embodiment of the present technology. [Figure 21] 1 is a block diagram showing a schematic configuration example of a vehicle control system; [Figure 22] FIG. 4 is an explanatory diagram showing an example of an installation position of an imaging unit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] Hereinafter, modes for carrying out the present technology (hereinafter, referred to as embodiments) will be described. The description will be made in the following order. 1. First embodiment (example of correction based on measured value of gate-source voltage) 2. Second embodiment (an example in which a short-circuit transistor is added within an effective pixel and correction is performed based on the measured value of the gate-source voltage) 3. Application examples for mobile objects

[0021] <1. First embodiment> [Example of imaging device configuration] 1 is a block diagram showing an example of a configuration of an imaging device 100 according to a first embodiment of the present technology. The imaging device 100 is a device that captures image data, and includes an optical unit 110, a solid-state imaging element 200, a storage unit 120, a control unit 130, and a communication unit 140.

[0022] The optical unit 110 collects incident light and guides it to the solid-state imaging element 200. The solid-state imaging element 200 captures image data. The solid-state imaging element 200 supplies the image data to the storage unit 120 via a signal line 209.

[0023] The storage unit 120 stores image data. The control unit 130 controls the solid-state imaging element 200 to capture the image data. The control unit 130 supplies a vertical synchronization signal VSYNC indicating imaging timing to the solid-state imaging element 200 via a signal line 208, for example.

[0024] The communication unit 140 reads out image data from the storage unit 120 and transmits it to the outside.

[0025] 2 is a diagram for explaining an example of use of the imaging device 100 according to the first embodiment of the present technology. As illustrated in the figure, the imaging device 100 is used in a factory or the like where a belt conveyor 510 is installed.

[0026] Belt conveyor 510 moves subject 511 in a predetermined direction at a constant speed. Imaging device 100 is fixed near belt conveyor 510 and captures an image of subject 511 to generate image data. The image data is used, for example, to inspect for the presence or absence of defects. This realizes FA (Factory Automation).

[0027] Although imaging device 100 captures an image of subject 511 moving at a constant speed, the present invention is not limited to this configuration. It may be configured such that imaging device 100 moves at a constant speed relative to the subject and captures the image, such as aerial photography.

[0028] [Example of the configuration of a solid-state imaging element] 3 is a diagram showing an example of a stacked structure of a solid-state imaging element 200 according to the first embodiment of the present technology. The solid-state imaging element 200 includes a circuit chip 202 and a light receiving chip 201 stacked on the circuit chip 202. These chips are electrically connected through a connection portion such as a via. Note that, other than the via, the connection can also be made by Cu-Cu bonding or bumps.

[0029] 4 is a block diagram showing an example of a configuration of the light receiving chip 201 according to the first embodiment of the present technology. The light receiving chip 201 includes a pixel array unit 210 and a peripheral circuit 212.

[0030] In the pixel array section 210, a plurality of pixel circuits 220 are arranged in a two-dimensional lattice. The pixel array section 210 is divided into a plurality of pixel blocks 211. In each of these pixel blocks 211, for example, pixel circuits 220 are arranged in 4 rows and 2 columns. In addition, a plurality of transistors are further arranged outside each pixel circuit 220, but these transistors are omitted in the figure for convenience of description.

[0031] In the peripheral circuit 212, for example, a circuit for supplying a DC (Direct Current) voltage and the like are arranged.

[0032] 5 is an example of a plan view of a pixel array section 210 according to the first embodiment of the present technology. The pixel array section 210 is divided into an unshielded effective pixel area 214 and light-shielded OPB (OPB) areas 213 and 215.

[0033] In the effective pixel region 214, a plurality of effective pixels are arranged in a two-dimensional lattice. These effective pixels photoelectrically convert incident light to generate pixel signals. A predetermined number of light-shielded pixels are arranged in each of the OPB regions 213 and 215. Some of these light-shielded pixels are also used to measure a gate-source voltage, which will be described later. Among the light-shielded pixels, pixels used to measure a gate-source voltage are hereinafter referred to as "measurement pixels." For example, the OPB region 213 is arranged on the left side of the effective pixel region 214, and the OPB region 215 is arranged on the right side of the effective pixel region 214. At least one measurement pixel is arranged for each row. It is desirable to provide a measurement pixel on each of the left and right sides of each row of effective pixels.

[0034] Although the OPB regions 213 and 215 are arranged on the left and right of the effective pixel region 214, the OPB regions may be arranged above and below the effective pixel region 214. Furthermore, the OPB regions may be arranged above, below, left and right of the effective pixel region 214.

[0035] 6 is a block diagram showing an example of a configuration of the circuit chip 202 according to the first embodiment of the present technology. The circuit chip 202 is provided with a DAC (Digital to Analog Converter) 251, a pixel driving circuit 252, a time code generating unit 253, a pixel AD conversion unit 254, and a vertical scanning circuit 255. The circuit chip 202 further includes a control circuit 256, a signal processing circuit 400, an image processing circuit 260, and an output circuit 257.

[0036] The DAC 251 generates a reference signal by DA (Digital to Analog) conversion over a predetermined AD conversion period. For example, a sawtooth ramp signal is used as the reference signal. The DAC 251 supplies the reference signal to the pixel AD conversion unit 254.

[0037] The time code generation unit 253 generates a time code indicating a time within an AD conversion period. The time code generation unit 253 is realized by, for example, a counter. As the counter, for example, a Gray code counter is used. The time code generation unit 253 supplies the time code to the pixel AD conversion unit 254.

[0038] The pixel drive circuit 252 drives each of the pixel circuits 220 to generate an analog pixel signal.

[0039] The pixel AD conversion unit 254 performs AD conversion to convert the analog signals (i.e., pixel signals) of the pixel circuits 220 into digital signals. The pixel AD conversion unit 254 is divided into a plurality of clusters 300. The clusters 300 are provided for each pixel block 211, and convert the analog signals in the corresponding pixel blocks 211 into digital signals.

[0040] The pixel AD conversion unit 254 generates image data in the form of a frame by arranging digital signals through AD conversion, and supplies the image data to the signal processing circuit 400 .

[0041] The vertical scanning circuit 255 drives the pixel AD conversion unit 254 to perform AD conversion.

[0042] The signal processing circuit 400 performs a predetermined signal processing on the frame. As the signal processing, various types of processing including CDS (Correlated Double Sampling) processing are executed. The signal processing circuit 400 supplies the processed frame to the image processing circuit 260.

[0043] The image processing circuit 260 executes a predetermined image processing on the frame from the signal processing circuit 400. The image processing includes image recognition processing, black level correction processing, image correction processing, demosaic processing, etc. The image processing circuit 260 supplies the processed frame to the output circuit 257.

[0044] The output circuit 257 outputs the processed frame to the outside.

[0045] The control circuit 256 controls the operation timing of each of the DAC 251, the pixel drive circuit 252, the vertical scanning circuit 255, the signal processing circuit 400, the image processing circuit 260, and the output circuit 257 in synchronization with the vertical synchronization signal VSYNC.

[0046] [Example of pixel AD conversion section configuration] 7 is a diagram showing an example configuration of the pixel AD conversion unit 254 in the first embodiment of the present technology. In this pixel AD conversion unit 254, a plurality of ADCs 310 are arranged in a two-dimensional lattice. An ADC 310 is arranged for each pixel circuit 220. When the number of rows and the number of columns of the pixel circuits 220 are N rows (N is an integer) and M columns (M is an integer), N×M ADCs 310 are arranged.

[0047] Each cluster 300 has the same number of ADCs 310 as the number of pixel circuits 220 in the pixel block 211. When 4 rows and 2 columns of pixel circuits 220 are arranged in the pixel block 211, 4 rows and 2 columns of ADCs 310 are also arranged in the cluster 300.

[0048] The ADC 310 performs AD conversion on the analog pixel signal generated by the corresponding pixel circuit 220. In the AD conversion, the ADC 310 compares the pixel signal with a reference signal and holds the time code when the comparison result is inverted. The ADC 310 then outputs the held time code as a digital signal after AD conversion.

[0049] Furthermore, a repeater unit 370 is arranged for each column of the cluster 300. When the number of columns of the cluster 300 is M / 2, M / 2 repeater units 370 are arranged. The repeater unit 370 transfers a time code. The repeater unit 370 transfers the time code from the time code generation unit 253 to the ADC 310. The repeater unit 370 also transfers a digital signal from the ADC 310 to the signal processing circuit 400. This transfer of the digital signal is also called "reading" the digital signal.

[0050] In addition, in the figure, the numbers in parentheses indicate an example of the read order of the digital signals of the ADC 310. For example, the digital signal of the odd-numbered column of the first row is read out first, and the digital signal of the even-numbered column of the first row is read out second. The digital signal of the odd-numbered column of the second row is read out third, and the digital signal of the even-numbered column of the second row is read out third. Similarly, the digital signals of the odd-numbered columns and even-numbered columns of each row are read out in order.

[0051] Although the ADC 310 is provided for each pixel circuit 220, the present invention is not limited to this configuration. A configuration in which a plurality of pixel circuits 220 share one ADC 310 is also possible.

[0052] [ADC configuration example] 8 is a block diagram showing an example of a configuration of an effective pixel and an ADC 310 according to the first embodiment of the present technology. The ADC 310 includes a differential amplifier 320, a positive feedback circuit 340, a latch control circuit 350, and a plurality of latch circuits 360.

[0053] In addition, a source follower circuit 230 is disposed between the pixel circuit 220 and the ADC 310. The source follower circuit 230 receives the potential V SIN Depending on the potential V SOUT This signal is supplied to the ADC 310. A circuit made up of the pixel circuit 220 and the source follower circuit 230 functions as one effective pixel.

[0054] Furthermore, the pixel circuit 220 , the source follower circuit 230 and part of the differential amplifier 320 are disposed on the light receiving chip 201 , and the remainder of the differential amplifier 320 and the circuit at the subsequent stage are disposed on the circuit chip 202 .

[0055] The differential amplifier 320 compares the pixel signal from the source follower circuit 230 with the reference signal from the DAC 251. The differential amplifier 320 supplies a comparison result signal indicating the comparison result to a positive feedback circuit 340.

[0056] The positive feedback circuit 340 adds a part of the output to the input (comparison result signal) and supplies the result to the latch control circuit 350 as an output signal VCO.

[0057] The latch control circuit 350 causes a plurality of latch circuits 360 to hold the time code when the output signal VCO is inverted, in accordance with the control signal xWORD from the vertical scanning circuit 255 .

[0058] The latch circuit 360 holds the time code from the repeater unit 370 under the control of the latch control circuit 350. The number of latch circuits 360 is equal to the number of bits of the time code. For example, if the time code is 15 bits, 15 latch circuits 360 are arranged in the ADC 310. The held time code is read by the repeater unit 370 as a digital signal after AD conversion.

[0059] According to the configuration illustrated in the figure, the ADC 310 converts the pixel signal from the source follower circuit 230 into a digital signal.

[0060] [Example of differential amplifier and positive feedback circuit configuration] FIG. 9 is a circuit diagram showing an example configuration of the pixel circuit 220, the differential amplifier 320, and the positive feedback circuit 340 according to the first embodiment of the present technology.

[0061] The differential amplifier 320 includes p-channel Metal Oxide Semiconductor (pMOS) transistors 331, 334, and 321. The differential amplifier 320 also includes n-channel MOS (nMOS) transistor 322, auto-zero transistor 323, differential transistors 332 and 335, and current source transistor 333. Of these, the auto-zero transistor 323, the differential transistors 332 and 335, and the current source transistor 333 are disposed on the light receiving chip 201, and the remaining are disposed on the circuit chip 202. For example, nMOS transistors are used as the differential transistors 332 and 335. For example, nMOS transistors are used as the auto-zero transistor 323 and the current source transistor 333.

[0062] The differential transistors 332 and 335 form a differential pair, and the sources of these transistors are commonly connected to the drain of the current source transistor 333. The drain of the differential transistor 332 is connected to the drain of the pMOS transistor 331 and the gates of the pMOS transistors 331 and 334. The drain of the differential transistor 335 is connected to the drain of the pMOS transistor 334 and the gate of the pMOS transistor 321. A reference signal from the DAC 251 is input to the gate of the differential transistor 332. The potential of this reference signal is V REF Let us assume that.

[0063] A predetermined bias voltage BIAS1 is applied to the gate of the current source transistor 333, and a predetermined ground voltage is applied to the source of the current source transistor 333. This current source transistor 333 supplies a current according to the bias voltage BIAS1.

[0064] The pixel signal from the source follower circuit 230 is input to the gate of the differential transistor 335. SOUT Let us assume that.

[0065] The pMOS transistors 331, 334, and 321 configure a current mirror circuit. The sources of the pMOS transistors 331, 334, and 321 are applied with the power supply voltage VDD.

[0066] The drain of the nMOS transistor 322 is connected to the drain of the pMOS transistor 321 , and the source is connected to the positive feedback circuit 340 .

[0067] The auto-zero transistor 323 shorts the drain of the differential transistor 335 and the input node of the source follower circuit 230 in accordance with an auto-zero signal AZ from the pixel drive circuit 252 .

[0068] The positive feedback circuit 340 includes pMOS transistors 341, 342, 344, and 345, and nMOS transistors 343, 346, and 347. The pMOS transistors 341 and 342 and the nMOS transistor 343 are connected in series to the gate of the nMOS transistor 322. The gate of the pMOS transistor 341 receives the drive signal INI2 from the vertical scanning circuit 255. The connection point of the pMOS transistor 342 and the nMOS transistor 343 is connected to the source of the nMOS transistor 322.

[0069] A ground voltage is applied to the source of the nMOS transistor 343, and the drive signal INI1 from the vertical scanning circuit 255 is input to the gate.

[0070] The pMOS transistors 344 and 345 are connected in series to the gate of the nMOS transistor 322. The drain of the pMOS transistor 345 is connected to the gate of the pMOS transistor 342 and the drains of the nMOS transistors 346 and 347. A control signal TESTVCO from the vertical scanning circuit 255 is input to the gates of the pMOS transistor 345 and the nMOS transistor 347. The gates of the pMOS transistor 344 and the nMOS transistor 346 are connected to the connection point of the pMOS transistor 342 and the nMOS transistor 343.

[0071] An output signal VCO is output from the connection point of the pMOS transistor 345 and the nMOS transistor 347. In addition, the sources of the nMOS transistors 346 and 347 are applied with the ground voltage.

[0072] It should be noted that the differential amplifier 320 and the positive feedback circuit 340 are not limited to the circuit illustrated in FIG. 8 as long as they have the functions described in FIG.

[0073] 10 is a circuit diagram showing a configuration example of a source follower circuit 230 and a pixel circuit 220 in an effective pixel in the first embodiment of the present technology. The pixel circuit 220 includes a drain transistor 221, a photoelectric conversion element 222, a transfer transistor 223, and a floating diffusion layer 224. The source follower circuit 230 includes a source follower transistor 231 and a current source transistor 232. For example, nMOS transistors are used as the drain transistor 221, the transfer transistor 223, the source follower transistor 231, and the current source transistor 232.

[0074] The discharge transistor 221 discharges the electric charge accumulated in the photoelectric conversion element 222 in accordance with a drive signal OFG from the pixel drive circuit 252. The photoelectric conversion element 222 generates electric charge by photoelectric conversion.

[0075] The transfer transistor 223 transfers electric charges from the photoelectric conversion element 222 to the floating diffusion layer 224 in accordance with a transfer signal TRG from the pixel drive circuit 252 .

[0076] The floating diffusion layer 224 accumulates the transferred charge and generates a voltage according to the amount of charge. The node of the floating diffusion layer 224 on the transfer transistor 223 side is set as a floating diffusion layer node 225, and its potential is set to V SIN Let us assume that.

[0077] A gate of the source follower transistor 231 is connected to a floating diffusion layer node 225 of the floating diffusion layer 224. In addition, a source of the source follower transistor 231 is connected to a drain of the current source transistor 232.

[0078] A predetermined bias voltage BIAS2 is applied to the gate of the current source transistor 232, and a predetermined ground voltage is applied to the source of the current source transistor 232. The current source transistor 232 supplies a current according to the bias voltage BIAS2.

[0079] In addition, the connection node between the source follower transistor 231 and the current source transistor 232 (ie, the source of the source follower transistor 231 ) is connected to the gate of the differential transistor 335 .

[0080] The gate-source voltage of the source follower transistor 231 is V GS Then, the potential V of the gate of the source follower transistor 231 is SIN and the source potential V SOUT The following formula holds between V SIN =V SOUT +V GS ...Formula 1

[0081] From equation 1, the source potential V of the source follower transistor 231 SOUT is the gate potential V SIN It fluctuates according to.

[0082] Moreover, a circuit consisting of the pMOS transistors 331 and 334 , the differential transistors 332 and 335 , and the current source transistor 333 in the differential amplifier 320 functions as a differential amplifier circuit 330 .

[0083] Potential V REF The gate of the differential transistor 332 corresponds to the input node 337 of the differential amplifier circuit 330. SOUTThe gate of the differential transistor 335 corresponds to an input node 338 of the differential amplifier circuit 330. The drain of the differential transistor 335 corresponds to an output node 339 of the differential amplifier circuit 330. The potential of this output node is V COUT It is also assumed that a parasitic capacitance 336 occurs between the gate and source of the differential transistor 335.

[0084] The differential amplifier circuit 330 detects the potential V REF and the potential V of the input node 338 SOUT The difference between these is amplified and output from the output node 339.

[0085] The auto-zero transistor 323 shorts the output node 339 of the differential amplifier circuit 330 and the floating diffusion layer node 225 (in other words, the input node of the source follower circuit 230) in accordance with the auto-zero signal AZ.

[0086] Here, a first comparative example is considered in which the source follower circuit 230 is not provided and the floating diffusion node 225 is directly connected to the gate of the differential transistor 335 (i.e., the input node 338). In this first comparative example, the high-impedance floating diffusion node 225 is directly connected to the input node 338 of the differential amplifier circuit 330, so that a change in the reference signal is propagated to the floating diffusion node 225 via the parasitic capacitance 336 of the differential transistor 335. For example, when the reference signal decreases in a slope-like manner, the potential V SIN Therefore, the potential V SIN When it coincides with REF An error occurs in the value of V and the propagation delay time of the differential amplifier circuit 330 increases significantly. SIN The voltage V SIN and potential V REF The timing when the two coincide is delayed from the original timing, and the potential V SIN and potential V REF The reason is that the rate at which the difference between the input nodes of the differential amplifier circuit 330 increases becomes slower even after the inputs match.

[0087] Of the two problems, the error in the potential and the increase in the propagation delay time, the error can be removed by CDS processing, but the increase in the propagation delay time cannot be eliminated by CDS processing. If the propagation delay time increases, the AD conversion time of the ADC 310 becomes longer, and the frame rate decreases.

[0088] If the capacitance of the floating diffusion layer 224 is increased, the potential V SIN However, if the capacitance of the floating diffusion layer 224 is increased, the charge-voltage conversion efficiency of the floating diffusion layer 224 decreases, which is not preferable.

[0089] In this way, if the floating diffusion layer node 225 is directly connected to the gate of the differential transistor 335, there is a risk that the frame rate will decrease.

[0090] In contrast, in the circuit shown in FIG. 1, which includes the source follower circuit 230, the potential V SOUT is the potential V SIN When the auto-zero transistor 323 is in the off state, the source follower circuit 230 changes the potential V SIN Since the impedance of the reference signal is low, the potential V SIN does not change. Therefore, the potential V REF The potential V due to the change SIN This can prevent fluctuations in the AD conversion time and improve the frame rate. In particular, when performing TDI (Time Delayed Integration) processing, a very high frame rate (for example, 200 to 300 kHz) is required, and adding the source follower circuit 230 makes it easy to meet such a requirement.

[0091] Furthermore, in a configuration in which the source follower circuit 230 is provided, the propagation delay time does not increase even if the impedance increases by reducing the capacitance of the floating diffusion layer 224. Therefore, it is possible to reduce the capacitance of the floating diffusion layer 224 and increase the charge-voltage conversion efficiency while maintaining the frame rate.

[0092] Next, a second comparative example will be considered in which a source follower circuit 230 is provided, an auto-zero capacitance is inserted between the source follower circuit 230 and the gate of the differential transistor 335, and the auto-zero transistor shorts the gate and drain of the differential transistor 335. This second comparative example is described in, for example, Japanese Patent Application No. 2016-545441. In this second comparative example, the potential V SIN However, the gain from the connection node (output of the source follower) of the source follower transistor 231 and the current source transistor 232 to the gate of the differential transistor 335 is determined by the auto-zero capacitance and the parasitic capacitance 336, and is expressed by the following equation. C AZ / (C AZ +C gs ) In the above formula, C AZ indicates the capacitance value of the auto-zero capacitance, and C gs indicates the capacitance value of the parasitic capacitance 336.

[0093] C AZ and C gs If is a constant value, the gain will be constant just by attenuation, but C gs is not a constant value but has bias dependency, so when the voltage at the gate of the differential transistor 335 changes, the gain also changes, and linearity deteriorates.

[0094] C AZ But, C gs If the capacitance is very large compared to C, the degradation of linearity can be suppressed. However, since the auto-zero capacitance needs to be placed inside the pixel, only a small capacitance value (about a few femtofarads) can be placed. This is because gsOn the other hand, the value is only a few to 10 times that of C gs Since has a bias dependency of several percent, the gain also fluctuates by several percent. This fluctuation is an unacceptable value.

[0095] Also, C AZ and C. gs Since the ratio of is small, the absolute value of the gain is also small, and the noise converted into the input of the floating diffusion layer 224 becomes worse.

[0096] Thus, the second comparative example can solve the problem of the first comparative example, but has drawbacks such as deterioration of linearity and increase in noise.

[0097] On the other hand, the auto-zero capacitance is not required in a configuration in which the auto-zero transistor 323 shorts the drain of the differential transistor 335 and the input node of the source follower circuit 230. This makes it possible to suppress deterioration of linearity and noise.

[0098] 11 is a diagram for explaining a method for controlling a transistor in an effective pixel in the first embodiment of the present technology, in which a in the figure shows a method for controlling a transistor during auto-zero, and b in the figure shows a method for controlling a transistor after auto-zero.

[0099] In the figure, the differential amplifier circuit 330 is represented by a comparator symbol, and the source follower circuit 230 is represented by a voltage buffer symbol. The auto-zero transistor 323 and the transfer transistor 223 are represented by switch symbols.

[0100] As shown in FIG. 1A, prior to the comparison operation of the comparator (differential amplifier circuit 330), the pixel drive circuit 252 turns on the auto-zero transistor 323 and turns off the transfer transistor 223. This shorts the output node of the comparator (differential amplifier circuit 330) and the input node of the source follower circuit 230, and feedback is applied to match the zero of the reference signal with the zero of the pixel signal (i.e., auto-zero). The potential V SIN is set as zero of the pixel signal. Also, according to Equation 1, the source follower circuit 230 outputs a potential V SIN The potential V according to SOUT will be output.

[0101] As shown in FIG. 1B, after auto-zero, the pixel driving circuit 252 turns off the auto-zero transistor 323. The DAC 251 changes the reference signal to a slope, and the ADC 310 converts the analog pixel signal into a digital signal according to the initialized potential of the floating diffusion layer 224. The level of the pixel signal at this time is called the P phase or reset level.

[0102] After the conversion of the P phase, the pixel drive circuit 252 turns on the transfer transistor 223 to transfer the charge from the photoelectric conversion element 222 to the floating diffusion layer 224. The DAC 251 changes the reference signal into a slope, and the ADC 310 converts the analog pixel signal according to the potential of the floating diffusion layer 224 after the transfer into a digital signal. The level of the pixel signal at this time is called the D phase or signal level.

[0103] At b in the figure, the source follower circuit 230 generates a potential V SOUT Since the impedance of the MOSFET is low, even if the reference signal drops in a slope during the conversion of the P phase and the D phase, the potential V SIN does not change.

[0104] 12 is a timing chart showing an example of a potential fluctuation in the first embodiment of the present technology. In the figure, a indicates the potential V SINand the potential of the output node V SOUT 1 is a timing chart showing an example of the fluctuation of the potential V REF and the potential V SOUT 10 is a timing chart showing an example of the fluctuations of the respective

[0105] As illustrated in FIG. 1A, during the auto-zero period from timing T0 to T1, the source follower circuit 230 operates to detect the potential V SIN The potential V according to SOUT is output from the output node. The relationship between these potentials is expressed by Equation 1. Then, when the charge is transferred at timing T5, the potential V SIN decreases with the amount of charge.

[0106] Also, as illustrated in FIG. 1B, during the auto-zero period from timing T0 to T1, the potential V SOUT is the potential of the reference signal V REF During the period from timing T2 to T4 after this auto-zero, the DAC 251 changes the potential of the reference signal V REF The ADC310 changes the potential V REF is the potential V SOUT The time code is held at timing T3 that coincides with the time code, and the time code is output as a digital signal obtained by converting the P phase.

[0107] Then, when the charge is transferred at timing T5 after the P phase change, the potential V SIN During the period from timing T6 to T8 after the transfer, the DAC 251 reduces the potential V REF The ADC310 changes the potential V REF is the potential V SOUT The time code is held at timing T7 that coincides with the time code, and the time code is output as a digital signal obtained by converting the D phase.

[0108] 13 is a diagram showing an example of the inversion timing of the output of the differential amplifier circuit 330 in the first embodiment of the present technology and the first comparative example. In the figure, "a" is a diagram showing an example of the inversion timing of the output of the differential amplifier circuit 330 in the first embodiment. In the figure, "b" is a diagram showing an example of the inversion timing of the output of the differential amplifier circuit 330 in the first comparative example.

[0109] As shown in FIG. 1A, in the first embodiment in which the source follower circuit 230 is added, the potential V REF is the potential V of the output of the source follower circuit 230. SOUT At a timing T3 that coincides with the potential V COUT is inverted.

[0110] On the other hand, as illustrated in FIG. 1B, in the first comparative example without the source follower circuit 230, the potential V COUT This is because, as mentioned above, the potential V SIN When it coincides with REF This is because an error occurs in the value of and the propagation delay time of the differential amplifier circuit 330 increases significantly. In the first comparative example, the period from timing T3 to T4 when the reference signal is changed to a slope (i.e., the AD conversion period) needs to be set longer in consideration of this delay, and the longer AD conversion period may result in a decrease in the frame rate.

[0111] In contrast to this, in a configuration in which the source follower circuit 230 is added, no delay occurs, so that the AD conversion period can be made shorter than in the first comparative example, and the frame rate can be improved.

[0112] As described above with reference to FIG. 10, in the effective pixel, the potential V SIN is expressed by Equation 1. SOUT and the potential of the reference signal is V REFand are approximately equal, then formula 1 can be replaced with the following formula: V SIN =V REF +V GS ...Formula 2

[0113] The potential V of the floating diffusion layer 224 during auto-zero SIN must be designed to be as high as possible in order to increase the charge transfer efficiency from the photoelectric conversion element 222 to the floating diffusion layer 224 and to increase the amount of saturated charge. On the other hand, in order to prevent the feedback loop including the comparator and the source follower circuit 280 from being saturated during auto-zero, the potential V SIN is a certain upper limit V MAX Must be less than or equal to:

[0114] However, the gate-source voltage V GS In reality, there is variation due to process and temperature fluctuations for each chip. If this variation due to process and temperature is ±ΔV, the potential V during auto-zero is SIN is expressed by the following formula: V SIN =V REF +V GS ±ΔV...Equation 3

[0115] From equation 3, the gate-source voltage V GS Even when the potential V SIN The upper limit value V MAX To achieve this, the following formula must be satisfied: V SIN =V REF +V GS +ΔV≦V MAX ...Formula 4

[0116] By transforming equation 4, we obtain the following equation. V REF ≦V MAX -(V GS +ΔV)...Equation 5

[0117] The maximum V that satisfies Equation 5 REFSet the gate-source voltage V GS In reality, if the variation in is minimum, i.e., −ΔV, the potential V of the floating diffusion layer 224 during auto-zero is SIN is expressed by the following formula: V SIN =V REF +V GS -ΔV =V MAX -(V GS +ΔV)-ΔV =V MAX -V GS -2ΔV...Equation 6

[0118] From Equation 6, the gate-source voltage V GS When compared with the case where the variation of the potential V SIN would be lower by 2ΔV. If the charge transfer from the photoelectric conversion element 222 to the floating diffusion layer 224 is designed based on Equation 6, the amount of saturation charge would be small, which would be disadvantageous in terms of charge transfer.

[0119] In order to prevent the above-mentioned decrease in charge transfer efficiency, the gate-source voltage V GS The signal processing circuit 400 measures the potential of the reference signal V REF It was decided to correct the above.

[0120] 14 is a block diagram showing a configuration example of a measurement pixel and an ADC 610 according to the first embodiment of the present technology. The ADC 610 includes a differential amplifier 620, a positive feedback circuit 640, a latch control circuit 650, and a plurality of latch circuits 660. The function of each circuit in the ADC 610 is similar to that of the circuit of the same name in the ADC 310 corresponding to the effective pixel.

[0121] Furthermore, a source follower circuit 280 is disposed between the pixel circuit 270 and the ADC 610. A circuit consisting of the pixel circuit 270 and the source follower circuit 280 functions as one measurement pixel.

[0122] 15 is a circuit diagram showing a configuration example of a source follower circuit 280 and a pixel circuit 270 in a measurement pixel in the first embodiment of the present technology. The pixel circuit 270 includes a discharge transistor 271, a photoelectric conversion element 272, a transfer transistor 273, and a floating diffusion layer 274. The source follower circuit 280 includes a source follower transistor 281 and a current source transistor 282.

[0123] In addition, a differential amplifier circuit 630 and a short-circuit transistor 623 are arranged in the differential amplifier 620. The differential amplifier circuit 630 includes pMOS transistors 631 and 634, differential transistors 632 and 635, and a current source transistor 633.

[0124] In the figure, the connection configuration of elements other than the short-circuit transistor 623 is the same as that of the elements of the same name on the effective pixel side illustrated in Figure 10. Comparing Figures 10 and 15, the auto-zero transistor 323 on the effective pixel side is not arranged on the measurement pixel side, and a short-circuit transistor 623 is arranged instead. In addition, the discharge transistor 271 is used to apply a predetermined external voltage (such as 2 volts) to the photoelectric conversion element 272. For this reason, the discharge transistor 271 is represented by the diagram symbol of an amplifier.

[0125] The short-circuit transistor 623 shorts the gate and source of the source follower transistor 281 in accordance with a control signal SH from the pixel drive circuit 252 .

[0126] The variation in the gate-source voltage of the transistors in the chip is small, so that by providing a measurement pixel with almost the same layout as the effective pixel and turning on and off its short-circuit transistor 623, it is possible to measure a voltage that is almost the same as the gate-source voltage in the effective pixel, as shown in the example of FIG.

[0127] Here, the gate-source voltage varies from pixel to pixel within a chip, although this variation is smaller than the variation between chips. Taking this variation into account, it is desirable to arrange multiple measurement pixels and obtain statistics (such as the average) of their measurement values.

[0128] 16 is a block diagram showing an example of a configuration of a signal processing circuit 400 according to the first embodiment of the present technology. The signal processing circuit 400 includes a measurement unit 430 and a correction calculation unit 440. Furthermore, the signal processing circuit 400 includes a plurality of selectors 405, a plurality of CDS processing units 410, and a plurality of TDI processing units 420.

[0129] The measurement unit 430 measures the gate-source voltage of the source follower transistor 281 in the measurement pixel. During measurement, the pixel drive circuit 252 applies an external voltage to the discharge transistor 271 while turning on the short-circuit transistor 623, and the ADC 610 performs only D-phase conversion. The measurement unit 430 stores the D-phase value of each measurement pixel as V1 in a memory or the like.

[0130] Then, the pixel driving circuit 252 turns off the short-circuit transistor 623 while keeping the external voltage applied, and the ADC 610 performs only D-phase conversion. The measurement unit 430 stores the D-phase value of each measurement pixel as V2 in a memory or the like. The measurement unit 430 calculates the difference between V1 and V2 for each measurement pixel. This difference indicates the measurement value of the gate-source voltage of the source follower transistor 281 in the measurement pixel. The measurement unit 430 supplies the difference (i.e., the measurement value) for each measurement pixel to the correction calculation unit 440.

[0131] The correction calculation unit 440 calculates the potential V of the reference signal based on the measured value. REF The correction calculation unit 440 calculates the statistics of the measurement values ​​of the multiple measurement pixels. For example, if the average value of the measurement values ​​is V GS_ave The correction calculation unit 440 calculates the average value V GS_ave is supplied to the control circuit 256 as a correction value.

[0132] The control circuit 256 determines the correction value (V GS_ave ) is set as a reference signal to the DAC 251. For example, the potential of the reference signal V REF is set to a value that satisfies the following formula: V REF =V MAX -V GS_ave ...Formula 7

[0133] In reality, the gate-source voltage varies between pixels on a chip, so the potential of the reference signal V REF It is desirable to set it to a value that satisfies the following formula: V REF =V MAX -V GS_ave -V margin In the above formula, V margin is the margin voltage that takes into account the variation within a chip. However, since the variation within a chip is smaller than the variation between chips, the margin voltage V margin will be a small value.

[0134] A selector 405 is arranged for each column of clusters 300 in the effective pixel area, in other words, for each repeater unit 370. When two columns of ADCs 310 are arranged in a cluster 300, a selector 405 is arranged for every two columns. Also, a CDS processing unit 410 and a TDI processing unit 420 are arranged for each column of ADCs 310. When the ADCs 310 have M columns, M / 2 selectors 405, M CDS processing units 410, and M TDI processing units 420 are arranged.

[0135] As described above, the repeater unit 370 outputs the odd-numbered digital signals and the even-numbered digital signals in sequence.

[0136] The selector 405 selects the output destination of the digital signal of the effective pixel in accordance with the control of the control circuit 256. When an odd-numbered column is output by the repeater unit 370, the selector 405 outputs the digital signal to the CDS processing unit 410 corresponding to the odd-numbered column. On the other hand, when an even-numbered column is output, the selector 405 outputs the digital signal to the CDS processing unit 410 corresponding to the even-numbered column.

[0137] The CDS processing unit 410 performs CDS processing to obtain a difference between the P phase and the D phase on the digital signal from the selector 405. The CDS processing unit 410 supplies a digital signal of the difference to the TDI processing unit 420.

[0138] The TDI processing unit 420 performs TDI processing on the digital signal after the TDI processing, integrating the digital signal while shifting the time in accordance with the moving speed of the subject. The TDI processing unit 420 supplies the digital signal after the TDI processing to the image processing circuit 260.

[0139] Although the TDI processing unit 420 is provided in the signal processing circuit 400, it is also possible to configure the circuit 400 without the TDI processing unit 420, as shown in Fig. 17. Such a solid-state imaging element 200 is used in devices that do not require TDI processing, such as digital cameras and smartphones.

[0140] 18 is a diagram for explaining a correction method in the first embodiment of the present technology. The measurement unit 430 holds, for each measurement pixel, a D-phase value V1 when the short-circuiting transistor 623 is in an on-state and a D-phase value V2 when the short-circuiting transistor 623 is in an off-state. Then, the measurement unit 430 calculates the difference between V1 and V2 for each measurement pixel, and supplies the difference to the correction calculation unit 440 as a measurement value of the gate-source voltage.

[0141] The correction calculation unit 440 calculates the average value V GS_aveis calculated as a correction value. The DAC 251 supplies a reference signal of a potential corrected based on this correction value to one of the input nodes of each differential amplifier circuit 630 in the effective pixel area 215. Note that an uncorrected reference signal of a fixed amplitude is input to the differential amplifier circuits in the OPB area 215.

[0142] 19 is a flowchart showing an example of a measurement process according to the first embodiment of the present technology. This measurement process is executed, for example, at any one of the following times: when a frame is captured, at the time of startup after chip inspection, and at the time of chip inspection.

[0143] The pixel driving circuit 252 turns on the shorting transistor 623 and applies an external voltage to the discharge transistor 271 (step S901). The ADC 310 converts only the D phase of the measurement pixel, as with the effective pixel, and the measurement section 430 holds the conversion result in memory as V1 (step S902).

[0144] The pixel driving circuit 252 turns off the shorting transistor 623 while keeping the external voltage applied (step S903). The ADC 310 converts only the D phase of the measurement pixel, and the measurement unit 430 stores the conversion result in memory as V2 (step S904). The measurement unit 430 calculates the difference between V1 and V2 for each measurement pixel as a measurement value (step S905).

[0145] The correction calculation unit 440 calculates the average value V GS_ave is calculated as a correction value (step S906). The control circuit 256 sets a reference signal that satisfies Equation 5 or Equation 7 based on the correction value in the DAC 251 (step S907). After step S907, the solid-state imaging device 200 ends the measurement process.

[0146] When the above-mentioned measurement process is performed for each frame, the measurement value measured when capturing an image of a certain frame is reflected in the reference signal when capturing the next frame. In this way, when the measurement process is performed during the image capturing operation, although the amount of calculation increases, the variation due to temperature fluctuation can be corrected, and therefore the correction accuracy is high.

[0147] In contrast, when the measurement process is performed at startup, the reference signal value set at startup is always used after startup. In this way, when the measurement process is performed only at startup, the amount of calculation is small, but it becomes impossible to correct the variation due to temperature fluctuation during the imaging operation.

[0148] Furthermore, when performing measurement processing during chip inspection, the reference signal value set during chip inspection is always used during chip inspection. In this way, when performing measurement processing only during chip inspection, calculation of correction values ​​after chip inspection (at startup or during imaging operation) is not required, but it becomes impossible to correct variations due to temperature fluctuations.

[0149] As described above, according to the first embodiment of the present technology, the source follower circuit 230 supplies a potential corresponding to the potential of the floating diffusion layer to the input node 338 of the differential amplifier circuit 330, so that it is possible to suppress the potential fluctuation of the input node 338 caused by the fluctuation of the reference signal. This makes it possible to suppress the lengthening of the AD conversion period caused by the potential fluctuation of the input node 338, and improve the frame rate.

[0150] Furthermore, the measurement unit 430 measures the gate-source voltage of the source follower transistor 281, and the correction calculation unit 440 calculates a correction value of the reference signal based on the measurement value, so that the reference signal can be corrected to improve the charge transfer efficiency.

[0151] <2. Second embodiment> In the first embodiment described above, measurement pixels are arranged in the OPB regions 213 and 215, and the gate-source voltages in the measurement pixels are measured. However, the number of pixels in the OPB region is generally smaller than the number of pixels in the effective pixel region, and there is a risk of an insufficient number of measured values. The solid-state imaging device 200 of the second embodiment differs from the first embodiment in that the gate-source voltages in the effective pixels are measured.

[0152] 20 is a circuit diagram showing a configuration example of a differential amplifier 320, a source follower circuit 230, and a pixel circuit 220 in an effective pixel according to the second embodiment of the present technology. A short-circuit transistor 324 is further arranged in the differential amplifier 320 on the effective pixel side according to the second embodiment.

[0153] The short-circuit transistor 324 shorts the gate and source of the source follower transistor 231 of the effective pixel in accordance with a control signal SH from the pixel drive circuit 252 .

[0154] Moreover, no measurement pixels are arranged in the OPB regions 213 and 215 in the second embodiment.

[0155] The measurement process of the second embodiment is the same as that of the first embodiment, except that the D phase in the effective pixels is read out. However, in the second embodiment, the measurement process cannot be performed for each frame, and is performed at the time of startup or chip inspection.

[0156] Since the number of pixels in the effective pixel area 214 is generally greater than the number of pixels in the OPB areas 213 and 215, the second embodiment can measure more measurement values ​​than the first embodiment. This can improve the correction accuracy.

[0157] In this way, according to the second embodiment of the present technology, the measurement unit 430 measures the gate-source voltage of the effective pixel, and therefore obtains more measurement values ​​than the number of pixels in the OPB region, thereby improving the correction accuracy.

[0158] <3. Application examples for mobile objects> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, etc.

[0159] FIG. 21 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a moving object control system to which the technology according to the present disclosure can be applied.

[0160] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 21, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also, as functional configurations of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053 are illustrated.

[0161] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0162] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as head lamps, back lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves or signals of various switches transmitted from a portable device that replaces a key may be input to the body system control unit 12020. The body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, and the like of the vehicle.

[0163] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for a person, a car, an obstacle, a sign, or characters on a road surface, based on the received image.

[0164] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0165] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing.

[0166] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the outside-of-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0167] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on the driver's operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0168] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0169] The audio / video output unit 12052 transmits at least one output signal of audio and video to an output device capable of visually or audibly notifying information to passengers in the vehicle or the outside of the vehicle. In the example of Fig. 21, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as the output device. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.

[0170] FIG. 22 is a diagram showing an example of the installation position of the imaging unit 12031.

[0171] In FIG. 22, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0172] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin is mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

[0173] 22 shows an example of the imaging ranges of the imaging units 12101 to 12104. An imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and an imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.

[0174] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of a plurality of imaging elements, or may be an imaging element having pixels for detecting a phase difference.

[0175] For example, the microcomputer 12051 can extract, as a preceding vehicle, a three-dimensional object that is the closest three-dimensional object on the travel path of the vehicle 12100 and travels at a predetermined speed (for example, 0 km / h or more) in approximately the same direction as the vehicle 12100, by calculating the distance to each three-dimensional object in the imaging ranges 12111 to 12114 and the change over time of this distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. Furthermore, the microcomputer 12051 can set a vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving that travels autonomously without relying on the driver's operation.

[0176] For example, the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0177] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured images of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

[0178] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 among the configurations described above. Specifically, for example, the imaging device 100 in FIG. 1 can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to improve the frame rate and generate a video with higher image quality.

[0179] The above-mentioned embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specified in the claims correspond to each other. Similarly, the matters specified in the claims and the matters in the embodiment of the present technology having the same name correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist of the technology.

[0180] It should be noted that the effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0181] The present technology can also be configured as follows. (1) a differential amplifier circuit that amplifies a difference between potentials of a pair of input nodes and outputs the amplified difference from an output node; a transfer transistor that transfers charges from the photoelectric conversion element to the floating diffusion layer; a source follower transistor having a gate connected to the floating diffusion layer and a source connected to one of the pair of input nodes; a measurement unit that measures a gate-source voltage of the source follower transistor and supplies the measured value; a correction calculation unit that calculates a correction value for correcting the potential of the other of the pair of input nodes based on the measurement value; A solid-state imaging device comprising: (2) further comprising a short-circuit transistor for shorting the source and the gate of the source follower transistor in accordance with a predetermined control signal; the differential amplifier circuit, the transfer transistor, and the source follower transistor are disposed in each of an effective pixel and a measurement pixel; the shorting transistor is disposed at the measurement pixel; The measurement unit measures the gate-source voltage of the measurement pixel. The solid-state imaging device according to (1) above. (3) The measurement unit measures the gate-source voltage every time a frame is captured. The solid-state imaging device according to (2) above. (4) The measurement unit measures the gate-source voltage at startup. The solid-state imaging device according to (2) above. (5) The measurement unit measures the gate-source voltage during chip testing. The solid-state imaging device according to (2) above. (6) further comprising a short-circuit transistor for short-circuiting the source and the gate of the source follower transistor in accordance with a predetermined control signal; the differential amplifier circuit, the transfer transistor, the source follower transistor, and the short-circuit transistor are disposed in an effective pixel; The measurement unit measures the gate-source voltage of the effective pixel. The solid-state imaging device according to (1) above. (7) The measurement unit measures the gate-source voltage at startup. The solid-state imaging device according to (6) above. (8) The measurement unit measures the gate-source voltage during chip testing. The solid-state imaging device according to (6) above. (9) The measurement unit measures, as the measurement value, a difference between a digital signal corresponding to a signal output from the differential amplifier circuit when the source and the gate are shorted and a digital signal corresponding to a signal output from the differential amplifier circuit when the source and the gate are not shorted; The correction calculation unit calculates a statistical quantity of the measurement values ​​as the correction value. The solid-state imaging device according to any one of (1) to (8). (10) A delay time integration processing unit that performs a time delay integration process on a digital signal corresponding to the signal output from the differential amplifier circuit. The solid-state imaging device according to any one of (1) to (9). (11) A part of the differential amplifier circuit, the transfer transistor, and the source follower transistor are provided on a predetermined photosensor chip; The remainder of the differential amplifier circuit, the measurement unit, and the correction calculation unit are provided on a predetermined circuit chip. The solid-state imaging device according to any one of (1) to (10). (12) The light-receiving chip and the circuit chip are connected by Cu-Cu bonding. The solid-state imaging device according to (11) above. (13) A differential amplifier circuit that amplifies a difference between potentials of a pair of input nodes and outputs the amplified difference from an output node; a transfer transistor that transfers charges from the photoelectric conversion element to the floating diffusion layer; a source follower transistor having a gate connected to the floating diffusion layer and a source connected to one of the pair of input nodes; a measurement unit that measures a gate-source voltage of the source follower transistor and supplies the measured value; a correction calculation unit that calculates a correction value for correcting the potential of the other of the pair of input nodes based on the measurement value; a storage unit that stores a frame in which digital signals corresponding to the signal output from the differential amplifier circuit are arranged; An imaging device comprising: (14) A transfer step of transferring charges from the photoelectric conversion element to the floating diffusion layer; a measurement step of measuring a gate-source voltage of a source follower transistor having a gate connected to the floating diffusion layer and a source connected to one of a pair of input nodes of a differential amplifier circuit, and supplying a measurement value; a correction calculation step of calculating a correction value for correcting the potential of the other of the pair of input nodes based on the measurement value; A method for controlling a solid-state imaging device comprising the steps of: [Explanation of symbols]

[0182] 100 Imaging device 110 Optics Department 120 Storage section 130 Control section 140 Communications Department 200 Solid-state image sensor 201 Photodetector chip 202 Circuit Chip 210 Pixel array section 211 pixel block 212 Peripheral Circuits 213, 215 OPB area 214 Effective pixel area 220, 270 pixel circuit 221, 271 Emission transistor 222, 272 Photoelectric conversion element 223, 273 Transfer transistor 224, 274 Floating diffusion layer 230, 280 Source follower circuit 231, 281 Source follower transistor 232, 282, 333, 633 Current source transistor 251 DAC 252 Pixel driving circuit 253 Time Code Generator 254 pixel AD conversion section 255 vertical scanning circuit 256 Control Circuit 257 Output circuit 260 Image Processing Circuit 300 Clusters 310, 610 ADCs 320, 620 Differential Amplifier 321, 331, 334, 341, 342, 344, 345, 631, 634 pMOS transistors 322, 343, 346, 347 nMOS transistors 323 Auto-zero transistor 324, 623 Shorted transistor 330, 630 Differential amplifier circuit 332, 335, 632, 635 Differential Transistors 340, 640 Positive feedback circuit 350, 650 Latch control circuit 360, 660 Latch circuit 370 Repeater section 400 Signal Processing Circuit 405 Selector 410 CDS Processing Unit 420 TDI Processing Section 430 Measuring section 440 Correction Calculation Unit 510 Conveyor Belt 511 Subject 12031 Imaging unit

Claims

1. a differential amplifier circuit that amplifies a difference between potentials of a pair of input nodes and outputs the amplified difference from an output node; a transfer transistor that transfers charges from the photoelectric conversion element to the floating diffusion layer; a source follower transistor having a gate connected to the floating diffusion layer and a source connected to one of the pair of input nodes; a measurement unit that measures a gate-source voltage of the source follower transistor and supplies the measured value; a correction calculation unit that calculates a correction value for correcting the potential of the other of the pair of input nodes based on the measurement value; A solid-state imaging device comprising:

2. a short-circuit transistor for short-circuiting the source and the gate of the source follower transistor in accordance with a predetermined control signal; the differential amplifier circuit, the transfer transistor, the source follower transistor, and the short-circuit transistor are disposed in a pixel array section, the pixel array section includes an effective pixel region in which a predetermined number of non-light-shielded effective pixels are arranged, and an OPB (OPT) region in which a predetermined number of light-shielded pixels are arranged, At least one of the pixels in the OPB region is a measurement pixel for measuring the gate-source voltage; the differential amplifier circuit, the transfer transistor, and the source follower transistor are disposed in each of the effective pixels and the measurement pixels; the shorting transistor is disposed at the measurement pixel; The measurement unit measures the gate-source voltage of the measurement pixel.

2. The solid-state imaging device according to claim 1.

3. The measurement unit measures the gate-source voltage every time a frame is captured.

3. The solid-state imaging device according to claim 2.

4. The measurement unit measures the gate-source voltage at the time of start-up.

3. The solid-state imaging device according to claim 2.

5. The measurement unit measures the gate-source voltage during chip inspection.

3. The solid-state imaging device according to claim 2.

6. a short-circuit transistor for short-circuiting the source and the gate of the source follower transistor in accordance with a predetermined control signal; the differential amplifier circuit, the transfer transistor, the source follower transistor, and the short-circuit transistor are disposed in an effective pixel; The measurement unit measures the gate-source voltage of the effective pixel.

2. The solid-state imaging device according to claim 1.

7. The measurement unit measures the gate-source voltage at the time of start-up.

7. The solid-state imaging device according to claim 6.

8. The measurement unit measures the gate-source voltage during chip inspection.

7. The solid-state imaging device according to claim 6.

9. the measurement unit measures, as the measurement value, a difference between a digital signal corresponding to a signal output from the differential amplifier circuit when the source and the gate are shorted and a digital signal corresponding to a signal output from the differential amplifier circuit when the source and the gate are not shorted; The correction calculation unit calculates a statistical quantity of the measurement values ​​as the correction value.

2. The solid-state imaging device according to claim 1.

10. The differential amplifier further includes a delay time integration processing unit that performs a time delay integration process on a digital signal corresponding to the signal output from the differential amplifier circuit.

2. The solid-state imaging device according to claim 1.

11. a part of the differential amplifier circuit, the transfer transistor, and the source follower transistor are provided on a predetermined photosensor chip; The remainder of the differential amplifier circuit, the measurement unit, and the correction calculation unit are provided on a predetermined circuit chip.

2. The solid-state imaging device according to claim 1.

12. The light receiving chip and the circuit chip are connected by Cu-Cu bonding. The solid-state imaging device according to claim 11.

13. a differential amplifier circuit that amplifies a difference between potentials of a pair of input nodes and outputs the amplified difference from an output node; a transfer transistor that transfers charges from the photoelectric conversion element to the floating diffusion layer; a source follower transistor having a gate connected to the floating diffusion layer and a source connected to one of the pair of input nodes; a measurement unit that measures a gate-source voltage of the source follower transistor and supplies the measured value; a correction calculation unit that calculates a correction value for correcting the potential of the other of the pair of input nodes based on the measurement value; a storage unit that stores a frame in which digital signals corresponding to the signal output from the differential amplifier circuit are arranged; An imaging device comprising:

14. A transfer step of transferring charges from the photoelectric conversion element to the floating diffusion layer; a measurement step of measuring a gate-source voltage of a source follower transistor having a gate connected to the floating diffusion layer and a source connected to one of a pair of input nodes of a differential amplifier circuit, and supplying a measured value; a correction calculation step of calculating a correction value for correcting the potential of the other of the pair of input nodes based on the measurement value; A method for controlling a solid-state imaging device comprising the steps of:

Images