Semiconductor Device

Abstract

The present invention provides a semiconductor device with little variation in transistor characteristics. This semiconductor device comprises: a first insulating body; a first oxide upon the first insulating body; a first conductor and a second conductor upon the first oxide; a first layer and a second layer in contact with the side surface of the first oxide; a second insulating body upon the first insulating body, upon the first layer, upon the second layer, upon the first conductor, and upon the second conductor; a third insulating body upon the second insulating body; a second oxide interposed between the first conductor and the second conductor, and disposed upon the first oxide; a fourth insulating body upon the second oxide; and a third conductor upon the fourth insulating body. The first layer and the second layer respectively have metals contained in the first conductor and the second conductor. The first insulating body in a region in contact with the second insulating body has a region where the metal concentration is lower than that of the first layer or the second layer.

Description

[Technical field]

[0001] 1. Field of the Invention An embodiment of the present invention relates to a transistor, a semiconductor device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device. Another embodiment of the present invention relates to a semiconductor wafer and a module.

[0002] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0003] Note that one aspect of the present invention is not limited to the above technical field. One aspect of the invention disclosed in the present specification etc. relates to an object, a method, or a manufacturing method. Another aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. [Background technology]

[0004] Technology that constructs transistors using semiconductor thin films formed on substrates with insulating surfaces is attracting attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, but oxide semiconductors are also attracting attention as other materials.

[0005] In oxide semiconductors, c-axis aligned crystalline (CAAC) structures and nanocrystalline (nc) structures, which are neither single crystal nor amorphous, have been found (see Non-Patent Documents 1 and 2).

[0006] Non-Patent Documents 1 and 2 disclose techniques for manufacturing a transistor using an oxide semiconductor having a CAAC structure. [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186 [Non-Patent Document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 Summary of the Invention [Problem to be solved by the invention]

[0008] An object of one embodiment of the present invention is to provide a semiconductor device with little variation in transistor characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high reliability. Another object of one embodiment of the present invention is to provide a semiconductor device having good electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with large on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract problems other than these from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0010] One embodiment of the present invention is a semiconductor device having a first insulator, a first oxide on the first insulator, a first conductor and a second conductor on the first oxide, a first layer and a second layer in contact with side surfaces of the first oxide, a second insulator on the first insulator, on the first layer, on the second layer, on the first conductor, and on the second conductor, a third insulator on the second insulator, a second oxide disposed between the first conductor and the second conductor and disposed on the first oxide, a fourth insulator on the second oxide, and a third conductor on the fourth insulator, wherein each of the first layer and the second layer contains metal contained in the first conductor and the second conductor, and the first insulator in a region in contact with the second insulator has a region having a lower concentration of metal than the first layer or the second layer.

[0011] In the above semiconductor device, it is preferable that the thickness of each of the first layer and the second layer has a range of 0.5 nm or more and 1.5 nm or less.

[0012] In the above semiconductor device, the metal is preferably tantalum.

[0013] In the above semiconductor device, the first oxide preferably contains indium, an element M (M is gallium, aluminum, yttrium, or tin), and zinc.

[0014] Another embodiment of the present invention is a method for forming a first insulator, forming a first oxide film on the first insulator, forming a first conductive film on the first oxide film, forming a resist mask on the first conductive film, hardening the resist mask, processing the first oxide film and the first conductive film using the resist mask to form an island-shaped first oxide and conductive layer, removing a layer formed on the first insulator by processing by performing dry etching treatment, and forming a second insulator on the first insulator, the first oxide, and the conductive layer. a third insulator on the second insulator; forming openings in the third insulator, the second insulator, and the conductive layer that expose the first oxide to form a first conductor and a second conductor; forming a second oxide film on the first insulator, the first oxide, and the third insulator; forming an insulating film on the second oxide film; forming a second conductive film on the insulating film; and removing part of the second oxide film, part of the insulating film, and part of the second conductive film until the third insulator is exposed.

[0015] In the above-mentioned method for manufacturing a semiconductor device, it is preferable that the steps of hardening the resist mask, processing the first oxide film and the first conductive film using the resist mask to form an island-shaped first oxide and conductive layer, and removing the layer formed on the first insulator by processing through a dry etching process are performed consecutively using one dry etching apparatus.

[0016] Another aspect of the invention is a semiconductor memory device having a first layer having a first memory device, a second layer having a second memory device, and a first insulator, the second layer being disposed above the first layer, the first memory device having a first transistor and a first capacitance device, the second memory device having a second transistor and a second capacitance device, the first transistor having a second insulator, a first oxide on the second insulator, a first conductor and a second conductor on the first oxide, a third insulator on the first insulator, on the first conductor and on the second conductor, a fourth insulator on the third insulator, a second oxide disposed between the first conductor and the second conductor and disposed on the first oxide, and a fifth insulator on the second oxide. and a third conductor on the fifth insulator, the second transistor having a sixth insulator, a third oxide on the sixth insulator, a fourth conductor and a fifth conductor on the third oxide, a seventh insulator on the sixth insulator, on the fourth conductor and on the fifth conductor, an eighth insulator on the seventh insulator, a fourth oxide disposed between the fourth conductor and the fifth conductor and disposed on the third oxide, a ninth insulator on the fourth oxide, and a sixth conductor on the ninth insulator, the first insulator having an area contacting each of a side surface of the second insulator, a side surface of the third insulator, a side surface of the fourth insulator, a side surface of the sixth insulator, a side surface of the seventh insulator, and a side surface of the eighth insulator, each of the first oxide and the third oxide having a hydrogen concentration of 1×10 20 atoms / cm 3 The semiconductor device has an area of ​​less than 100 nm. Effect of the Invention

[0017] According to one embodiment of the present invention, a semiconductor device with little variation in transistor characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0018] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not need to have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract effects other than these from the description in the specification, drawings, claims, etc. [Brief description of the drawings]

[0019] Fig. 1A is a top view of a semiconductor device according to one embodiment of the present invention, and Figs. 1B to 1D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. FIG. 2 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. Figure 3A is a diagram for explaining the classification of IGZO crystal structures, Figure 3B is a diagram for explaining the XRD spectrum of a CAAC-IGZO film, and Figure 3C is a diagram for explaining the ultrafine electron beam diffraction pattern of a CAAC-IGZO film. 4A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 4B to 4D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. 5A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 5B to 5D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 6A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 6B to 6D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 7B to 7D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 8A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 8B to 8D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 9A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 9B to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 10A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 10B to 10D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 11A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 11B to 11D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 12A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 12B to 12D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 13A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 13B to 13D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 14A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 14B to 14D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 15A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 15B to 15D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 16A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 16B to 16D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 17A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 17B to 17D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 18A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 18B to 18D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 19A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 19B to 19D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 20A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 20B to 20D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 21A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 21B to 21D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 22A and 22B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. FIG. 23 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. FIG. 24 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. 25A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 25B to 25D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. FIG. 26 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 27 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 28A and 28B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 29 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 30 is a top view illustrating an apparatus for manufacturing a semiconductor device of one embodiment of the present invention. 31A and 31B are block diagrams illustrating a configuration example of a storage device according to one embodiment of the present invention. 32A to 32H are circuit diagrams illustrating configuration examples of a memory device according to one embodiment of the present invention. FIG. 33 is a diagram showing various storage devices by hierarchy. 34A and 34B are block diagrams and schematic diagrams of a semiconductor device according to one embodiment of the present invention. 35A and 35B are diagrams illustrating an example of an electronic component. 36A to 36E are schematic diagrams of a memory device according to one embodiment of the present invention. 37A to 37H are diagrams illustrating electronic devices according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] Hereinafter, the embodiments will be described with reference to the drawings. However, it will be easily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that the modes and details can be changed in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0021] In addition, in the drawings, the size, thickness of layers, or areas may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, in an actual manufacturing process, layers, resist masks, etc. may be unintentionally thinned by etching or other processes, but this may not be reflected in the drawings to facilitate understanding. In addition, in the drawings, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. In addition, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be attached.

[0022] In order to facilitate understanding of the invention, particularly in top views (also called "plan views") and perspective views, some components may be omitted from the drawings. Also, some hidden lines may be omitted from the drawings.

[0023] In addition, in this specification, ordinal numbers such as first, second, etc. are used for convenience and do not indicate the order of steps or stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third" for explanation. In addition, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one embodiment of the present invention.

[0024] In addition, in this specification, the terms "above" and "below" indicating the arrangement are used for convenience in order to explain the positional relationship between the components with reference to the drawings. In addition, the positional relationship between the components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0025] For example, when it is explicitly stated in this specification that X and Y are connected, the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are directly connected are considered to be disclosed in this specification. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and a connection relationship other than that shown in a figure or text is also considered to be disclosed in the figure or text. Here, X and Y are objects (for example, a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0026] In this specification, a transistor is an element having at least three terminals including a gate, a drain, and a source. A region where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode) (hereinafter, also referred to as a channel formation region) is provided, and a current can flow between the source and the drain through the channel formation region. In this specification, a channel formation region refers to a region through which a current mainly flows.

[0027] Furthermore, the functions of the source and drain may be interchanged when transistors of different polarities are used, when the direction of current changes during circuit operation, etc. For this reason, in this specification and the like, the terms source and drain may be used interchangeably.

[0028] The channel length refers to, for example, a region where the semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap in a top view of a transistor, or a distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in a channel formation region. Note that the channel length of one transistor does not necessarily have the same value in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0029] The channel width refers to, for example, the length of a channel formation region in a vertical direction based on the channel length direction in a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate electrode overlap in a top view of a transistor, or in a channel formation region. Note that the channel width does not necessarily have the same value in all regions in one transistor. In other words, the channel width of one transistor may not be determined to a single value. Therefore, in this specification, the channel width is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0030] In this specification and the like, depending on the structure of a transistor, the channel width in a region where a channel is actually formed (hereinafter also referred to as an "effective channel width") may differ from the channel width shown in a top view of the transistor (hereinafter also referred to as an "apparent channel width"). For example, when a gate electrode covers a side surface of a semiconductor, the effective channel width may be larger than the apparent channel width, and the influence of this may not be negligible. For example, in a fine transistor in which a gate electrode covers a side surface of a semiconductor, the proportion of a channel formation region formed on the side surface of the semiconductor may be large. In that case, the effective channel width is larger than the apparent channel width.

[0031] In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not precisely known, it is difficult to accurately measure the effective channel width.

[0032] In this specification, when simply described as a channel width, it may refer to an apparent channel width. Alternatively, when simply described as a channel width, it may refer to an effective channel width. Note that the values ​​of the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image, etc.

[0033] Note that impurities in a semiconductor refer to, for example, anything other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The inclusion of impurities can, for example, increase the density of defect states in the semiconductor or reduce the crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. For example, the inclusion of impurities can cause oxygen deficiencies (V O Sometimes it is written as ". ) may be formed.

[0034] In this specification and the like, silicon oxynitride refers to a material having a composition that contains more oxygen than nitrogen, and silicon nitride oxide refers to a material having a composition that contains more nitrogen than oxygen.

[0035] In this specification and the like, the term "insulator" can be replaced with an insulating film or an insulating layer, the term "conductor" can be replaced with a conductive film or a conductive layer, and the term "semiconductor" can be replaced with a semiconductor film or a semiconductor layer.

[0036] In addition, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes the case of -5 degrees or more and 5 degrees or less. "Approximately parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. "Perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes the case of 85 degrees or more and 95 degrees or less. "Approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0037] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like. For example, when a metal oxide is used for a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor having a metal oxide or an oxide semiconductor.

[0038] In this specification and the like, normally off means that when no potential is applied to the gate or when a ground potential is applied to the gate, the drain current flowing through the transistor per 1 μm of channel width is 1×10 -20 A or less, 1×10 at 85℃ -18 A or less, or 1×10 at 125°C -16 This means that it is A or lower.

[0039] (Embodiment 1) In this embodiment, an example of a semiconductor device including a transistor 200 according to one embodiment of the present invention and a manufacturing method thereof will be described with reference to FIGS.

[0040] <Example of semiconductor device configuration> A configuration of a semiconductor device having a transistor 200 will be described with reference to FIGS. 1A to 1D. FIGS. 1A to 1D are a top view and a cross-sectional view of a semiconductor device having a transistor 200. FIG. 1A is a top view of the semiconductor device. FIGS. 1B to 1D are cross-sectional views of the semiconductor device. FIG. 1B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 1C is a cross-sectional view of a portion indicated by a dashed line A3-A4 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 1D is a cross-sectional view of a portion indicated by a dashed line A5-A6 in FIG. 1A. Note that some elements are omitted in the top view of FIG. 1A for clarity.

[0041] The semiconductor device of one embodiment of the present invention includes an insulator 211 on a substrate (not shown), an insulator 212 on the insulator 211, an insulator 214 on the insulator 212, a transistor 200 on the insulator 214, an insulator 280 on the transistor 200, an insulator 282 on the insulator 280, an insulator 283 on the insulator 282, and an insulator 284 on the insulator 283. The insulators 211, 212, 214, 280, 282, 283, and 284 function as interlayer films. The semiconductor device also includes a conductor 240a and a conductor 240b which are electrically connected to the transistor 200 and function as plugs. Note that an insulator 241a is provided in contact with a side surface of the conductor 240a which functions as a plug, and an insulator 241b is provided in contact with a side surface of the conductor 240b which functions as a plug. Moreover, a conductor 246a electrically connected to the conductor 240a and functioning as a wiring is provided on the insulator 284, the conductor 240a, and the conductor 240b, and a conductor 246b electrically connected to the conductor 240b and functioning as a wiring is provided. Furthermore, an insulator 286 is provided on the conductor 246a, the conductor 246b, and the insulator 284.

[0042] Insulator 241a is provided in contact with the inner wall of the opening of insulator 280, insulator 282, insulator 283, insulator 284, etc., a first conductor of conductor 240a is provided in contact with the side surface of insulator 241a, and a second conductor of conductor 240a is provided further inside. Insulator 241b is provided in contact with the inner wall of the opening of insulator 280, insulator 282, insulator 283, insulator 284, etc., a first conductor of conductor 240b is provided in contact with the side surface of insulator 241b, and a second conductor of conductor 240b is provided further inside. Here, the height of the upper surface of conductor 240a and the height of the upper surface of insulator 284 in the area overlapping with conductor 246a can be made approximately the same. In addition, the height of the upper surface of conductor 240b and the height of the upper surface of insulator 284 in the area overlapping with conductor 246b can be made approximately the same. In the transistor 200, the first conductor and the second conductor of the conductor 240a are stacked, and the first conductor and the second conductor of the conductor 240b are stacked, but the present invention is not limited to this. For example, the conductor 240a and the conductor 240b may each be provided as a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, ordinal numbers may be assigned to indicate the order of formation to distinguish them from one another.

[0043] [Transistor 200] As shown in FIGS. 1A to 1D , the transistor 200 includes an insulator 216 on an insulator 214, a conductor 205 (conductor 205a and conductor 205b) disposed so as to be embedded in the insulator 214 or the insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, an oxide 243a, an oxide 243b, and an oxide 230c on the oxide 230b, a conductor 242a on the oxide 243a, a conductor 242b on the oxide 243b, and an oxide 230c on the oxide 230c. oxide 230c, an insulator 250 on oxide 230d, a conductor 260 (conductor 260a and conductor 260b) located on insulator 250 and overlapping a portion of oxide 230c, a layer 244a in contact with the side surfaces of oxide 230a, oxide 230b, oxide 243a, and conductor 242a, a layer 244b in contact with the side surfaces of oxide 230a, oxide 230b, oxide 243b, and conductor 242b, and an insulator 254 in contact with the upper surface of insulator 224, the side surfaces of layer 244a, the side surfaces of layer 244b, the upper surface of conductor 242a, and the upper surface of conductor 242b. The oxide 230c contacts the side surfaces of the oxide 243a, the oxide 243b, the conductor 242a, and the conductor 242b. The insulator 282 contacts the top surfaces of the conductor 260, the insulator 250, the oxide 230d, the oxide 230c, and the insulator 280.

[0044] An opening reaching the oxide 230b is provided in the insulator 280. The oxide 230c, the oxide 230d, the insulator 250, and the conductor 260 are disposed in the opening. In addition, the conductor 260, the insulator 250, the oxide 230d, and the oxide 230c are provided between the conductor 242a and the oxide 243a and the conductor 242b and the oxide 243b in the channel length direction of the transistor 200. The insulator 250 has a region in contact with the side surface of the conductor 260 and a region in contact with the bottom surface of the conductor 260. The oxide 230c has a region in contact with the oxide 230b, a region overlapping with the side surface of the conductor 260 via the oxide 230d and the insulator 250, and a region overlapping with the bottom surface of the conductor 260 via the oxide 230d and the insulator 250.

[0045] Oxide 230 preferably includes oxide 230a disposed on insulator 224, oxide 230b disposed on oxide 230a, oxide 230c disposed on oxide 230b and at least partially in contact with oxide 230b, and oxide 230d disposed on oxide 230c.

[0046] In the transistor 200, the oxide 230 has a four-layer structure of the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d, but the present invention is not limited to this. For example, the oxide 230 may have a single layer of the oxide 230b, a two-layer structure of the oxide 230a and the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230c, a three-layer structure of the oxide 230a, the oxide 230b, and the oxide 230c, a three-layer structure of the oxide 230a, the oxide 230b, and the oxide 230d, or a stacked structure of five or more layers. Each of the oxides 230a, 230b, 230c, and 230d may have a stacked structure.

[0047] The conductor 260 functions as a first gate (also referred to as a top gate) electrode, and the conductor 205 functions as a second gate (also referred to as a back gate) electrode. The insulator 250 functions as a first gate insulator, and the insulators 224 and 222 function as second gate insulators. The conductor 242a functions as one of a source or a drain, and the conductor 242b functions as the other of a source or a drain. The oxide 230 functions as a channel formation region.

[0048] Here, an enlarged view of the vicinity of the channel formation region in FIG. 1B is shown in FIG. 2. As shown in FIG. 2, the oxide 230 has a region 234 that functions as a channel formation region of the transistor 200, and regions 236a and 236b that are provided on either side of the region 234 and function as a source region or a drain region. At least a portion of the region 234 overlaps with the conductor 260. A conductor 242a and a conductor 242b are provided on the oxide 230b, and regions with lower resistance are formed near the conductor 242a in the region 236a and near the conductor 242b in the region 236b.

[0049] The regions 236a and 236b functioning as source and drain regions are regions with a low oxygen concentration, an increased carrier concentration due to the inclusion of impurities such as hydrogen, nitrogen, and metal elements, and the like, and thus have a low resistance. That is, the regions 236a and 236b are regions with a high carrier concentration and a low resistance compared to the region 234. The region 234 functioning as a channel formation region is a region with a low carrier concentration and a high resistance due to a higher oxygen concentration and a lower impurity concentration than the regions 236a and 236b. A region with an oxygen concentration equal to or higher than that of the region 236a (region 236b) and equal to or lower than that of the region 234 may be formed between the region 234 and the region 236a (region 236b).

[0050] 2, the width of the region 234 in the channel length direction is equal to the width of the conductor 260; however, this is not limited to this embodiment of the present invention. The width of the region 234 may be shorter than the width of the conductor 260, or the width of the region 234 may be longer than the width of the conductor 260.

[0051] In addition, it may be difficult to clearly detect the boundaries between the regions in the oxide 230. The concentration of impurities such as hydrogen, nitrogen, and metal elements detected in each region may not only vary stepwise from region to region, but may also vary continuously within each region. In other words, it is sufficient that the concentration of impurities such as hydrogen, nitrogen, and metal elements decreases in the region closer to the channel formation region.

[0052] In the transistor 200, it is preferable to use a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor) for the oxide 230 (the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d) including a channel formation region.

[0053] In addition, the metal oxide functioning as a semiconductor preferably has a band gap of 2 eV or more, and more preferably has a band gap of 2.5 eV or more. By using a metal oxide having such a large band gap, the off-state current of a transistor can be reduced.

[0054] As the oxide 230, for example, a metal oxide such as an In-M-Zn oxide having indium, an element M, and zinc (the element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.) may be used. Alternatively, as the oxide 230, an In-Ga oxide, an In-Zn oxide, or an indium oxide may be used.

[0055] The oxide 230 preferably has a stacked structure of multiple oxide layers with different chemical compositions. Also, the oxide 230 preferably has a stacked structure of multiple oxide layers that have a common element (main component) other than oxygen.

[0056] Specifically, the atomic ratio of element M to In in the metal oxide used for oxide 230a or oxide 230d is preferably greater than the atomic ratio of element M to In in the metal oxide used for oxide 230b or oxide 230c. The greater the atomic ratio of element M to In, the easier it is to suppress the diffusion of impurities or oxygen. Thus, by having oxide 230a below oxide 230b, it is possible to suppress the diffusion of impurities from structures formed below oxide 230a to oxide 230b. Also, by having oxide 230d on oxide 230c, it is possible to suppress the diffusion of impurities from structures formed above oxide 230d to oxide 230c.

[0057] In other words, the atomic ratio of In to element M in the metal oxide used for the oxide 230b or the oxide 230c is preferably greater than the atomic ratio of In to element M in the metal oxide used for the oxide 230a or the oxide 230d. In this case, the main carrier path is the oxide 230b, the oxide 230c or its vicinity, for example, the interface between the oxide 230b and the oxide 230c. In addition, the oxide 230b and the oxide 230c have a common element other than oxygen (as a main component), so that the defect level density at the interface between the oxide 230b and the oxide 230c can be reduced, and therefore the effect of interface scattering on carrier conduction is small, and a high on-current can be obtained.

[0058] In order to make the oxide 230c the main path of carriers, the atomic ratio of indium to the main metal element in the oxide 230c is preferably larger than the atomic ratio of indium to the main metal element in the oxide 230b. By using a metal oxide with a high indium content in the channel formation region, the on-current of the transistor can be increased. Therefore, with this structure, the oxide 230c can be the main path of carriers.

[0059] In order to make the oxide 230c the main carrier path, the conduction band minimum of the oxide 230c is preferably farther from the vacuum level than the conduction band minimums of the oxides 230a, 230b, and 230d. In other words, the electron affinity of the oxide 230c is preferably greater than the electron affinity of the oxides 230a, 230b, and 230d.

[0060] It is preferable that the oxide 230b and the oxide 230c each have crystallinity. In particular, it is preferable to use a c-axis aligned crystalline oxide semiconductor (CAAC-OS) described later as the oxide 230b and the oxide 230c. In addition, the oxide 230d may have crystallinity.

[0061] By using the CAAC-OS for the oxide 230b and the oxide 230c, impurities and oxygen vacancies can be reduced in a region in the oxide semiconductor where a channel is formed, thereby making it possible to provide a transistor with reduced fluctuation in electrical characteristics, stable electrical characteristics, and improved reliability.

[0062] In addition, the extraction of oxygen from the oxide 230b by the source electrode or the drain electrode can be suppressed. As a result, even if a heat treatment is performed, the extraction of oxygen from the oxide 230b can be reduced, so that the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0063] In addition, the CAAC-OS has a property of easily transferring oxygen in a direction perpendicular to the c-axis of the crystal of the CAAC structure, so that oxygen in the oxide 230c can be efficiently supplied to the oxide 230b.

[0064] CAAC-OS is a metal oxide having a highly crystalline and dense structure and few impurities and defects (such as oxygen vacancies). In particular, by performing heat treatment at a temperature (e.g., 400° C. or higher and 600° C. or lower) at which the metal oxide does not polycrystallize after formation of the metal oxide, the CAAC-OS can have a more crystalline and dense structure. In this way, the density of the CAAC-OS can be increased, and the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0065] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in a channel formation region of the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may be reduced. In addition, hydrogen near the oxygen vacancies is called a defect in which hydrogen enters the oxygen vacancy (hereinafter referred to as V O H) and generate electrons that serve as carriers. For this reason, when oxygen vacancies are contained in the channel formation region in the oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists even when no voltage is applied to the gate electrode, and a current flows through the transistor). Therefore, impurities and oxygen vacancies are preferably reduced as much as possible in the channel formation region in the oxide semiconductor. In other words, it is preferable that the carrier concentration in the channel formation region in the oxide semiconductor is reduced and the channel formation region in the oxide semiconductor is made i-type (intrinsic) or substantially i-type.

[0066] In response to this problem, an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) may be provided near the oxide semiconductor, and oxygen may be supplied from the insulator to the oxide semiconductor by performing heat treatment. This allows oxygen vacancies in a channel formation region in the oxide semiconductor to be repaired by the supplied oxygen. Furthermore, part of the supplied oxygen reacts with hydrogen remaining in the oxide semiconductor, and the hydrogen can be removed as HO (dehydrated). This allows the oxide semiconductor to have V O The formation of H can be suppressed.

[0067] However, if an excessive amount of oxygen is supplied to the source region or drain region, the carrier concentration in the source region or drain region may decrease, which may cause a decrease in the on-current or the field effect mobility of the transistor 200. Furthermore, the oxygen supplied to the source region or drain region may vary within the substrate surface, which may cause variations in the characteristics of a semiconductor device having a transistor.

[0068] Therefore, in the oxide semiconductor, the region 234 functioning as a channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, while the regions 236a and 236b functioning as source and drain regions preferably have a high carrier concentration and are n-type. In other words, it is preferable to supply oxygen to the oxide semiconductor region 234 and prevent an excessive amount of oxygen from being supplied to the regions 236a and 236b.

[0069] For example, oxygen can be injected into the insulator 224 by forming the insulator 254 by a sputtering method. Then, the oxygen injected into the insulator 224 is supplied to the oxide 230b via the oxide 230c. This allows oxygen to be selectively supplied to the oxide 230c that occupies most of the region 234 and to the region of the oxide 230b that is in contact with the oxide 230c.

[0070] In addition, by using the CAAC-OS having the above-mentioned dense structure as the oxide 230b, the diffusion of impurities and oxygen in the oxide 230b can be reduced, and thus the diffusion of oxygen supplied to the region 234 of the oxide 230b to the regions 236a and 236b of the oxide 230b can be reduced.

[0071] In addition, a part of the excess oxygen diffused into the oxide 230c also diffuses into the oxide 230d. Since oxygen is less likely to diffuse into the oxide 230d than into the oxide 230c, the diffusion of oxygen into the insulator 250 is relatively suppressed. This makes it possible to suppress the oxidation of the conductor 260 via the insulator 250.

[0072] Although the details will be described later, when the oxide 230a and the oxide 230b are etched, a layer 244A may be formed on the insulator 224, etc. (see FIGS. 6B to 6D). When the layer 244A is formed on the insulator 224, the amount of oxygen injected into the insulator 224 by forming the insulator 254 by a sputtering method is reduced. In addition, if the layer 244A has a function of suppressing oxygen diffusion, the diffusion of excess oxygen contained in the insulator 280, etc., into the insulator 224 is suppressed. This raises a concern that the amount of oxygen supplied to the channel formation region of the oxide 230 may be reduced.

[0073] The thickness of the layer 244A on the insulator 224 tends to be thicker closer to the conductive layer 242B and thinner farther away from the conductive layer 242B. For example, if the integration density of the transistors is different, the distribution of the thickness of the layer 244A may be different. This causes a variation in the amount of oxygen supplied to the channel formation region of the oxide 230.

[0074] Therefore, in the transistor 200 according to one embodiment of the present invention, it is preferable to remove the layer 244A over the insulator 224. Furthermore, in the transistor 200 according to one embodiment of the present invention, it is preferable to suppress formation of the layer 244A and remove the layer 244A over the insulator 224.

[0075] The layer 244A may be removed by dry etching or wet etching, with dry etching being particularly preferred, as described in detail below.

[0076] By removing the layer 244A on the insulator 224, a part of the layer 244A remains, and the layer 244B may be formed to cover the side surfaces of the oxide 230a, the oxide 230b, etc. (see FIGS. 7A to 7D). When the layer 244B has a function of suppressing oxygen diffusion, the layer 244B formed on the side surfaces of the oxide 230a and the oxide 230b can suppress the intrusion of oxygen into the regions 236a and 236b. Therefore, the regions 236a and 236b can maintain low resistance regions.

[0077] In the subsequent process, the layer 244a is disposed in contact with the side surface of the oxide 230a, the side surface of the oxide 230b, the oxide 243a, and the side surface of the conductor 242a (see FIG. 1A, FIG. 1B, and FIG. 1D). That is, the oxide 230a and the oxide 230b are separated from the insulator 280 by the insulator 254 and the layer 244a that does not easily diffuse oxygen. This makes it possible to suppress the direct diffusion of excess oxygen contained in the insulator 280 into the oxide 230a and the oxide 230b. Although only the conductor 242a side (region 236a side) is mentioned in the above, the diffusion of excess oxygen can also be suppressed on the conductor 242b side (region 236b side) in the same manner.

[0078] In this manner, oxygen is selectively supplied to the oxide semiconductor region 234, making the region 234 i-type or substantially i-type, and oxygen diffusion to the regions 236a and 236b functioning as source and drain regions is suppressed, thereby maintaining the regions 236a and 236b as n-type. This can suppress fluctuations in the electrical characteristics of the transistor 200 and variations in the electrical characteristics of the transistor 200 within the substrate surface.

[0079] By adopting the above-mentioned configuration, it is possible to provide a semiconductor device with less variation in transistor characteristics, a highly reliable semiconductor device, and a semiconductor device having good electrical characteristics.

[0080] An example of a parameter for evaluating the reliability of a transistor is the shift voltage (Vsh) measured in a +GBT (Gate Bias Temperature) stress test of a transistor. Vsh is defined as the Vg at which the tangent to the maximum slope of the drain current (Id)-gate voltage (Vg) curve of the transistor intersects with the line of Id=1pA. The amount of change in Vsh is expressed as ΔVsh.

[0081] In a +GBT stress test of a transistor, ΔVsh may shift in the negative direction over time. Also, ΔVsh may not fluctuate in the negative direction (e.g., in the negative direction), but may exhibit behavior in which it fluctuates in both the negative and positive directions. Note that in this specification and the like, the above behavior may be referred to as the jagged behavior of ΔVsh in a +GBT stress test.

[0082] By using a metal oxide that does not contain element M as a main component or a metal oxide with a low ratio of element M for oxide 230c, for example, it is possible to reduce ΔVsh, suppress the jagged behavior of ΔVsh, and improve the reliability of the transistor.

[0083] Moreover, the oxide 230d preferably contains at least one of the metal elements constituting the metal oxide used in the oxide 230c, and more preferably contains all of the metal elements. For example, the oxide 230c may be In-M-Zn oxide, In-Zn oxide, or indium oxide, and the oxide 230d may be In-M-Zn oxide, M-Zn oxide, or an oxide of element M. This can reduce the defect state density at the interface between the oxide 230c and the oxide 230d.

[0084] Moreover, the oxide 230d is preferably a metal oxide that suppresses the diffusion or permeation of oxygen more than the oxide 230c. By providing the oxide 230d between the insulator 250 and the oxide 230c, it is possible to suppress the diffusion of oxygen contained in the insulator 280 into the insulator 250. Therefore, the oxygen can be efficiently supplied to the oxide 230b via the oxide 230c.

[0085] In addition, by making the atomic ratio of In to the main component metal element in the metal oxide used for the oxide 230d smaller than the atomic ratio of In to the main component metal element in the metal oxide used for the oxide 230c, it is possible to suppress the diffusion of In to the insulator 250 side. Since the insulator 250 functions as a gate insulator, if In gets mixed into the insulator 250, the transistor characteristics will be poor. Therefore, by providing the oxide 230d between the oxide 230c and the insulator 250, it is possible to provide a highly reliable semiconductor device.

[0086] Here, the conduction band minimum changes gradually at the junctions of the oxides 230a, 230b, 230c, and 230d. In other words, the conduction band minimum at the junctions of the oxides 230a, 230b, 230c, and 230d can be said to change continuously or to be a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layers formed at the interface between the oxides 230a and 230b, the interface between the oxides 230b and 230c, and the interface between the oxides 230c and 230d.

[0087] Specifically, the oxide 230a and the oxide 230b, the oxide 230b and the oxide 230c, and the oxide 230c and the oxide 230d have a common element other than oxygen as a main component, thereby forming a mixed layer with a low density of defect states. For example, when the oxide 230b is an In-M-Zn oxide, the oxide 230a, the oxide 230c, and the oxide 230d may be an In-M-Zn oxide, an M-Zn oxide, an oxide of element M, an In-Zn oxide, indium oxide, or the like.

[0088] Specifically, the oxide 230a may be a metal oxide having a composition of In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto, or In:M:Zn=1:1:0.5 [atomic ratio] or a composition close thereto. The oxide 230b may be a metal oxide having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, or In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto. The oxide 230c may be a metal oxide having a composition of In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto, In:M:Zn=5:1:3 [atomic ratio] or a composition close thereto, or In:M:Zn=10:1:3 [atomic ratio] or a composition close thereto, or indium oxide. Also, as the oxide 230d, a metal oxide having a composition of In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto, M:Zn=2:1 [atomic ratio] or a composition close thereto, or M:Zn=2:5 [atomic ratio] or a composition close thereto, or an oxide of element M may be used. Note that a composition close thereto includes a range of ±30% of the desired atomic ratio. Also, it is preferable to use gallium as element M.

[0089] By configuring the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d as described above, it is possible to reduce the defect state density at the interface between the oxide 230a and the oxide 230b, the interface between the oxide 230b and the oxide 230c, and the interface between the oxide 230c and the oxide 230d. As a result, the effect of interface scattering on carrier conduction is reduced, and the transistor 200 can obtain a large on-current and high frequency characteristics.

[0090] In addition, in a cross-sectional view of the transistor in the channel length direction, a groove is preferably provided in the oxide 230b, and the oxide 230c having the CAAC-OS is preferably filled in the groove. In this case, the oxide 230c is disposed so as to cover the inner wall (side wall and bottom surface) of the groove.

[0091] Moreover, it is preferable that the depth of the groove of the oxide 230b is approximately equal to the film thickness of the oxide 230c. In other words, it is preferable that the upper surface of the oxide 230c in the region overlapping with the oxide 230b is disposed approximately equal to the interface between the oxide 230b and the oxide 243a or the oxide 243b. For example, when the bottom surface of the insulator 222 is used as a reference, the difference between the height of the interface between the oxide 230b and the oxide 243a or the oxide 243b and the height of the interface between the oxide 230c and the oxide 230d is preferably equal to or less than the film thickness of the oxide 230c, and more preferably equal to or less than half the film thickness of the oxide 230c.

[0092] By using the above configuration, the transistor V O The influence of defects and impurities such as H can be reduced, and a channel can be formed in the oxide 230c. This allows the transistor to have good electrical characteristics. Furthermore, a semiconductor device with little variation in transistor characteristics and good reliability can be provided.

[0093] Also, it is preferable that impurities at the interface between the oxide 230b and the oxide 230c and in the vicinity thereof are reduced or removed. In particular, impurities such as aluminum and silicon are preferable to be reduced or removed because they hinder the improvement of the crystallinity or c-axis orientation of the oxide 230c and the oxide 230b. For example, the concentration of aluminum atoms at the interface between the oxide 230b and the oxide 230c and in the vicinity thereof is preferably 2.0 atomic % or less, more preferably 1.5 atomic % or less, and even more preferably 1.0 atomic % or less.

[0094] In addition, the region of the metal oxide in which the improvement of the crystallinity or c-axis orientation is hindered by impurities such as aluminum and silicon and which becomes a quasi-amorphous-like oxide semiconductor (a-like OS) is sometimes called a non-CAAC region. OTherefore, when the non-CAAC region is formed in the channel formation region, the transistor may be easily normally-on. For these reasons, it is preferable that the non-CAAC region is reduced or removed in the channel formation region.

[0095] In contrast, in the oxide 230b and the oxide 230c having the CAAC structure, a dense crystal structure is formed, so that V O Furthermore, in the oxygen addition process described later, excess oxygen is supplied to the oxide 230b and the oxide 230c, so that V O H→V O +H, V O +O→null reaction can proceed. This allows the V in oxide 230b and oxide 230c to O Reduce H and V O In this manner, the oxide 230b and the oxide 230c have a CAAC structure, which can suppress the transistor from becoming normally on.

[0096] 2 shows a configuration in which the side surface of the opening in which the conductor 260 and the like are embedded, including the groove of the oxide 230b, is substantially perpendicular to the surface on which the oxide 230b is formed, but this is not a limitation of one embodiment of the present invention. The bottom of the opening may be U-shaped with a gentle curve.

[0097] Here, in the oxide 230c, the c-axis of the crystal of the CAAC structure is preferably oriented in a direction substantially perpendicular to the surface on which the oxide 230c is formed or the top surface. Therefore, the crystal layer has a region that extends so as to be substantially parallel to the bottom and side surfaces of the opening. It is more preferable that the oxide 230d has the same crystal structure as the oxide 230c.

[0098] Moreover, the angle between the ab plane of the crystal of the CAAC structure of the oxide 230c in the groove and the ab plane of the crystal of the CAAC structure of the oxide 230b is preferably 60 degrees or less, more preferably 45 degrees or less, and even more preferably 30 degrees or less. In this way, by reducing the angle between the ab plane of the crystal of the CAAC structure of the oxide 230c in the groove and the ab plane of the crystal of the CAAC structure of the oxide 230b, the crystallinity of the oxide 230c in the groove can be increased.

[0099] In addition, the oxide consisting of the non-CAAC region is not limited to being formed so as to be surrounded by oxide 230b, oxide 243a, oxide 230c, and oxide 230d, but may also be formed so as to be sandwiched between oxide 230b and oxide 230c.

[0100] 1C, in a cross-sectional view in the channel width direction of the transistor 200, a curved surface may be formed between the side surface of the oxide 230b and the top surface of the oxide 230b. In other words, the end of the side surface and the end of the top surface may be curved (hereinafter also referred to as rounded).

[0101] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 230b in the region overlapping with the conductor 242a or conductor 242b, or smaller than half the length of the region of the upper surface of the oxide 230b that does not have the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and less than 20 nm, preferably greater than 1 nm and less than 15 nm, and more preferably greater than 2 nm and less than 10 nm. By forming the shape in this way, the coverage of the groove portion by the insulator 250 and the conductor 260 formed in a later process can be improved. In addition, the length of the region of the upper surface of the oxide 230b that does not have the curved surface can be prevented from decreasing, and the on-current and mobility of the transistor 200 can be suppressed from decreasing. Therefore, a semiconductor device having good electrical characteristics can be provided.

[0102] Note that the oxide 230c may be provided for each transistor 200. That is, the oxide 230c of one transistor 200 and the oxide 230c of another transistor 200 adjacent to the transistor 200 may not be in contact with each other. Furthermore, the oxide 230c of one transistor 200 and the oxide 230c of another transistor 200 adjacent to the transistor 200 may be separated from each other. In other words, a configuration in which the oxide 230c is not provided between the transistor 200 and the transistor 200 adjacent to the transistor 200 may be used.

[0103] In a semiconductor device in which a plurality of transistors 200 are arranged in the channel width direction, the above configuration allows the oxide 230c to be provided independently in each of the transistors 200. This makes it possible to suppress the generation of a parasitic transistor between a transistor 200 and a transistor 200 adjacent to the transistor 200, and to suppress the generation of a leakage path along the conductor 260. As a result, a semiconductor device having favorable electrical characteristics and capable of being miniaturized or highly integrated can be provided.

[0104] For example, when the distance between the side end of the oxide 230c of the transistor 200 and the side end of the oxide 230c of the transistor 200 adjacent to the transistor 200, which face each other in the channel width direction of the transistor 200, is expressed as L1, L1 is set to be larger than 0 nm. Also, when the distance between the side end of the oxide 230a of the transistor 200 and the side end of the oxide 230a of the transistor 200 adjacent to the transistor 200, which face each other in the channel width direction of the transistor 200, is expressed as L2, the value of the ratio of L1 to L2 (L1 / L2) is preferably larger than 0 and smaller than 1, more preferably 0.1 or more and 0.9 or less, and even more preferably 0.2 or more and 0.8 or less. Note that L2 may be the distance between the side end of the oxide 230b of the transistor 200 and the side end of the oxide 230b of the transistor 200 adjacent to the transistor 200, which face each other.

[0105] By reducing the ratio of L1 to L2 (L1 / L2) described above, even if a misalignment occurs in a region where oxide 230c is not located between transistor 200 and a transistor 200 adjacent to said transistor 200, oxide 230c of transistor 200 can be separated from oxide 230c of a transistor 200 adjacent to said transistor 200.

[0106] Furthermore, by increasing the ratio of L1 to L2 (L1 / L2), even if the distance between transistor 200 and the adjacent transistor 200 is narrowed, the minimum processing dimension width can be secured, thereby enabling further miniaturization or high integration of the semiconductor device.

[0107] Note that the conductor 260 and the insulator 250 may be shared between adjacent transistors 200. That is, the conductor 260 of one transistor 200 has a region provided contiguous with the conductor 260 of another transistor 200 adjacent to the transistor 200. The insulator 250 of one transistor 200 has a region provided contiguous with the insulator 250 of another transistor 200 adjacent to the transistor 200.

[0108] With the above structure, the oxide 230d has a region in contact with the insulator 224 between the transistor 200 and another transistor 200 adjacent to the transistor 200. Note that the oxide 230d of the transistor 200 may be separated from the oxide 230d of the transistor 200 adjacent to the transistor 200. In this case, the insulator 250 has a region in contact with the insulator 224 between the transistor 200 and another transistor 200 adjacent to the transistor 200.

[0109] The insulators 211, 212, 214, 254, 282, 283, 284, and 286 preferably function as barrier insulating films that suppress the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200 to the transistor 200. Therefore, the insulators 211, 212, 214, 254, 282, 283, 284, and 286 are preferably made of an insulating material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), and copper atoms (through which the above impurities are unlikely to permeate). Alternatively, it is preferable to use an insulating material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (through which the above oxygen is unlikely to permeate).

[0110] In this specification, a barrier insulating film refers to an insulating film having a barrier property. In this specification, the barrier property means a function of suppressing the diffusion of a corresponding substance (also called low permeability) or a function of capturing and fixing a corresponding substance (also called gettering).

[0111] For example, it is preferable to use silicon nitride or the like as the insulators 211, 212, 283, and 284, and aluminum oxide or the like as the insulators 214, 254, and 282. This can suppress impurities such as water and hydrogen from diffusing from the substrate side to the transistor 200 side through the insulators 211, 212, and 214. Alternatively, it is possible to suppress oxygen contained in the insulator 224 or the like from diffusing to the substrate side through the insulators 211, 212, and 214. In this manner, it is preferable to have a structure in which the transistor 200 is surrounded by the insulators 211, 212, 214, 254, 282, 283, and 284, which have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0112] In addition, it may be preferable to reduce the resistivity of the insulators 211, 284, and 286. For example, it is preferable to reduce the resistivity of the insulators 211, 284, and 286 to approximately 1×10 13 By setting the resistivity at Ωcm, the insulator 211, the insulator 284, and the insulator 286 may be able to reduce charge-up of the conductor 205, the conductor 242a, the conductor 242b, the conductor 260, the conductor 246a, or the conductor 246b in a process using plasma or the like in a semiconductor device manufacturing process. 10 Ωcm or more 1×10 15 Ωcm or less.

[0113] Note that the insulator 211 or the insulator 212 is not necessarily provided, and the insulator 283 or the insulator 284 is not necessarily provided. For example, the insulator 212 and the insulator 284 may be formed by a CVD method using a compound gas that does not contain hydrogen atoms or has a small amount of hydrogen atoms.

[0114] The insulator 216 and the insulator 280 preferably have a lower dielectric constant than the insulator 214. By using a material with a low dielectric constant as an interlayer film, the parasitic capacitance generated between wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like may be used as the insulator 216 and the insulator 280 as appropriate.

[0115] The conductor 205 may function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 and reduce the off-current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V, compared to not applying a negative potential.

[0116] The conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260. In addition, the conductor 205 is preferably embedded in the insulator 214 or the insulator 216.

[0117] As shown in FIG. 1A, the conductor 205 is preferably provided larger than the size of the region of the oxide 230 that does not overlap with the conductor 242a and the conductor 242b. In particular, as shown in FIG. 1C, the conductor 205 preferably extends in a region outside the end of the oxide 230a and the oxide 230b that intersects with the channel width direction. In other words, outside the side surface of the oxide 230 in the channel width direction, the conductor 205 and the conductor 260 preferably overlap with each other via an insulator. With this configuration, the channel formation region of the oxide 230 can be electrically surrounded by the electric field of the conductor 260 that functions as the first gate electrode and the electric field of the conductor 205 that functions as the second gate electrode. In this specification, a structure of a transistor in which the channel formation region is electrically surrounded by the electric fields of the first gate and the second gate is called a surrounded channel (S-channel) structure.

[0118] In this specification and the like, a transistor with an S-channel structure refers to a transistor structure in which a channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. The S-channel structure disclosed in this specification and the like is different from a fin type structure and a planar type structure. By adopting the S-channel structure, it is possible to improve resistance to the short channel effect, in other words, to make a transistor in which the short channel effect is unlikely to occur.

[0119] 1C, the conductor 205 is extended to function as wiring. However, the present invention is not limited to this, and a conductor functioning as wiring may be provided below the conductor 205. Also, it is not necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by multiple transistors.

[0120] Note that, in the transistor 200, the conductor 205 has a structure in which the conductor 205a and the conductor 205b are stacked, but the present invention is not limited to this. For example, the conductor 205 may have a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, the structures may be distinguished by giving ordinal numbers to the order of formation.

[0121] Here, the conductor 205a is preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferably made of a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0122] By using a conductive material having a function of suppressing the diffusion of oxygen for the conductor 205a, it is possible to suppress the conductor 205b from being oxidized and its conductivity from decreasing. As the conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. are preferably used. Therefore, the conductor 205a may be a single layer or a multilayer of the above conductive material. For example, the conductor 205a may be a multilayer of tantalum, tantalum nitride, ruthenium, or ruthenium oxide, and titanium or titanium nitride.

[0123] The conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Although the conductor 205b is illustrated as a single layer, it may have a multilayer structure, for example, a multilayer structure of titanium or titanium nitride and the conductive material.

[0124] The insulator 222 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). The insulator 222 preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.

[0125] The insulator 222 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. As the insulator, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the oxide 230 to the substrate side and the diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Thus, by providing the insulator 222, it is possible to suppress the diffusion of impurities such as hydrogen into the inside of the transistor 200 and the generation of oxygen vacancies in the oxide 230. In addition, it is possible to suppress the reaction of the conductor 205 with the insulator 224 and the oxygen contained in the oxide 230.

[0126] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. Alternatively, these insulators may be nitrided. The insulator 222 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0127] The insulator 222 may be a single layer or a multilayer of insulators containing so-called high-k materials, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), (Ba,Sr)TiO3 (BST), etc. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0128] It is preferable that the insulator 224 in contact with the oxide 230 release oxygen by heating. For example, the insulator 224 may be made of silicon oxide, silicon oxynitride, or the like as appropriate. By providing an insulator containing oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced and the reliability of the transistor 200 can be improved.

[0129] Specifically, it is preferable to use an oxide material from which some oxygen is released by heating, in other words, an insulator material having an excess oxygen region, as the insulator 224. An oxide film from which oxygen is released by heating is an oxide film from which the amount of released oxygen molecules is 1.0×10 18 molecules / cm 3 More than 1.0×10 19 molecules / cm 3 More preferably, 2.0×10 19 molecules / cm 3 or more, or 3.0×10 20 molecules / cm 3 The oxide film is one having the above-mentioned properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100° C. or more and 700° C. or less, or 100° C. or more and 400° C. or less.

[0130] In addition, the oxide 230 may be brought into contact with an insulator having the excess oxygen region and subjected to one or more of heat treatment, microwave treatment, and RF treatment. By carrying out such treatment, water or hydrogen in the oxide 230 can be removed. For example, in the oxide 230, defects in which hydrogen has entered an oxygen vacancy (V O A reaction occurs in which the bond of V O H→V O A reaction of "H + H" occurs, resulting in dehydrogenation. Some of the hydrogen generated at this time may combine with oxygen to form HO, and be removed from the oxide 230 or an insulator in the vicinity of the oxide 230. Some of the hydrogen may also be diffused or captured (also called gettering) in the conductor 242a or the conductor 242b.

[0131] The microwave treatment is preferably performed using, for example, a device having a power source for generating high-density plasma or a device having a power source for applying RF to the substrate side. For example, high-density oxygen radicals can be generated by using a gas containing oxygen and high-density plasma, and the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 230 or an insulator near the oxide 230 by applying RF to the substrate side. The microwave treatment may be performed under a pressure of 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more. For example, oxygen and argon are used as gases to be introduced into the microwave treatment device, and the oxygen flow rate ratio (O2 / (O2+Ar)) is 50% or less, preferably 10% or more and 30% or less.

[0132] In addition, in a manufacturing process of the transistor 200, it is preferable to perform heat treatment in a state where the surface of the oxide 230 is exposed. The heat treatment may be performed, for example, at a temperature of 100° C. or higher and 450° C. or lower, more preferably 350° C. or higher and 400° C. or lower. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. For example, the heat treatment is preferably performed in an oxygen atmosphere. This makes it possible to supply oxygen to the oxide 230 and reduce oxygen vacancies. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher in order to compensate for desorbed oxygen after the heat treatment in a nitrogen gas or inert gas atmosphere. Alternatively, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher, and then the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0133] In addition, by subjecting the oxide 230 to an oxygen addition treatment, the oxygen vacancies in the oxide 230 are repaired by the supplied oxygen. In other words, OIn addition, the reaction of the hydrogen remaining in the oxide 230 with the oxygen supplied can be promoted, and the hydrogen can be removed as H2O (dehydrated). As a result, the hydrogen remaining in the oxide 230 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0134] The insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In this case, the laminated structure is not limited to being made of the same material, and may be made of different materials.

[0135] Oxide 243a and oxide 243b may be provided on oxide 230b.

[0136] The oxide 243a and the oxide 243b preferably have a function of suppressing oxygen permeation. By disposing the oxide 243a (oxide 243b) having a function of suppressing oxygen permeation between the conductor 242a (conductor 242b) functioning as a source electrode or a drain electrode and the oxide 230b, the electrical resistance between the conductor 242a (conductor 242b) and the oxide 230b is reduced, which is preferable. With such a configuration, the electrical characteristics and reliability of the transistor 200 can be improved. Note that if the electrical resistance between the conductor 242a (conductor 242b) and the oxide 230b can be sufficiently reduced, the oxide 243a (oxide 243b) may not be provided.

[0137] Metal oxides having element M may be used as the oxide 243a and the oxide 243b. In particular, the element M may be aluminum, gallium, yttrium, or tin. The oxide 243a and the oxide 243b preferably have a higher concentration of element M than the oxide 230b. Gallium oxide may be used as the oxide 243a and the oxide 243b. Metal oxides such as In-M-Zn oxide may be used as the oxide 243a and the oxide 243b. Specifically, in the metal oxide used for the oxide 243a and the oxide 243b, the atomic ratio of element M to In is preferably greater than the atomic ratio of element M to In in the metal oxide used for the oxide 230b. The film thickness of the oxide 243a and the oxide 243b is preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and 3 nm or less, and even more preferably 1 nm or more and 2 nm or less. The oxide 243a and the oxide 243b preferably have crystallinity. When the oxide 243a and the oxide 243b have crystallinity, it is possible to suitably suppress the release of oxygen from the oxide 230. For example, when the oxide 243a and the oxide 243b have a crystal structure such as a hexagonal crystal structure, it is possible to suppress the release of oxygen from the oxide 230.

[0138] The conductor 242a is provided over the oxide 243a, and the conductor 242b is provided over the oxide 243b. The conductor 242a and the conductor 242b function as a source electrode and a drain electrode of the transistor 200, respectively.

[0139] As the conductor 242a and the conductor 242b, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, a nitride containing titanium and aluminum, or the like is preferably used. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Also, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like may be used. These materials are preferable because they are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when they absorb oxygen.

[0140] There may be curved surfaces between the side surface of the conductor 242a and the top surface of the conductor 242a, and between the side surface of the conductor 242b and the top surface of the conductor 242b. That is, the ends of the side surfaces and the ends of the top surface may be curved. The curved surfaces have a radius of curvature of, for example, 3 nm to 10 nm, preferably 5 nm to 6 nm, at the ends of the conductor 242a and the conductor 242b. The lack of corners at the ends improves the coverage of the film in the subsequent film formation process.

[0141] In addition, if the oxide 243a (oxide 243b) is not provided, the conductor 242a (conductor 242b) comes into contact with the oxide 230b or the oxide 230c, and oxygen in the oxide 230b or the oxide 230c diffuses into the conductor 242a (conductor 242b), which may cause the conductor 242a (conductor 242b) to oxidize. The oxidation of the conductor 242a and the conductor 242b is likely to reduce the conductivity of the conductor 242a and the conductor 242b. The diffusion of oxygen in the oxide 230b or the oxide 230c into the conductor 242a and the conductor 242b can be rephrased as the conductor 242a and the conductor 242b absorbing the oxygen in the oxide 230b or the oxide 230c.

[0142] In addition, oxygen in the oxide 230b or the oxide 230c may diffuse into the conductor 242a and the conductor 242b, forming layers between the conductor 242a and the oxide 230b, between the conductor 242b and the oxide 230b, or between the conductor 242a and the oxide 230c, and between the conductor 242b and the oxide 230c. Since the layer contains more oxygen than the conductor 242a or the conductor 242b, the layer is presumed to have insulating properties. In this case, the three-layer structure of the conductor 242a or the conductor 242b, the layer, and the oxide 230b or the oxide 230c can be regarded as a three-layer structure made of a metal-insulator-semiconductor, and can be regarded as a MIS (Metal-Insulator-Semiconductor) structure or a diode junction structure mainly based on the MIS structure.

[0143] Note that hydrogen contained in the oxide 230b, the oxide 230c, etc. may diffuse into the conductor 242a or the conductor 242b. In particular, by using a nitride containing tantalum for the conductor 242a and the conductor 242b, hydrogen contained in the oxide 230b, the oxide 230c, etc. may easily diffuse into the conductor 242a or the conductor 242b, and the diffused hydrogen may combine with nitrogen contained in the conductor 242a or the conductor 242b. In other words, hydrogen contained in the oxide 230b, the oxide 230c, etc. may be absorbed by the conductor 242a or the conductor 242b.

[0144] Layer 244a (layer 244b) contacts the side of oxide 230a, the side of oxide 230b, the side of oxide 243a (oxide 243b), and the side of conductor 242a (conductor 242b).

[0145] The layers 244a and 244b may have a function of suppressing the diffusion of oxygen. With the above configuration, it is possible to suppress the oxygen contained in the insulator 280 from being mixed in through the side surfaces of the oxide 230b and the oxide 230a in the region overlapping with the conductor 242a or the conductor 242b. This makes it possible to maintain the n-type of the side surfaces of the oxide 230b and their vicinity, and the side surfaces of the oxide 230a and their vicinity in the region overlapping with the conductor 242a or the conductor 242b.

[0146] In this manner, by making the side surfaces of the oxide 230a and the oxide 230b overlapping with the conductor 242a or the conductor 242b functioning as a source electrode and a drain electrode n-type, the on-state current of the transistor 200 can be increased.

[0147] The layer 244a and the layer 244b contain oxygen and one or more elements that are main components of a film (such as the conductive layer 242B) that is partially removed when the oxide 230a and the oxide 230b are etched. For example, when a nitride containing tantalum is used as the conductive layer 242B, the layer 244a and the layer 244b may contain tantalum and oxygen. Also, for example, when a nitride containing titanium is used as the conductive layer 242B, the layer 244a and the layer 244b may contain titanium and oxygen. Oxides containing metal elements, such as oxides containing tantalum and oxides containing titanium, are preferable because they have a function of suppressing the diffusion of oxygen.

[0148] The thickness of the layer 244a and the layer 244b is 0.1 nm or more and 3.0 nm or less, preferably 0.2 nm or more and 2.0 nm or less, and more preferably 0.5 nm or more and 1.5 nm or less.

[0149] The insulator 254 is provided to cover the side surfaces of the oxide 230a, the side surfaces of the oxide 230b, the side surfaces of the oxide 243a (oxide 243b), the side surfaces of the conductor 242a (conductor 242b), and the top surface of the conductor 242a (conductor 242b) via the layer 244a (layer 244b).

[0150] The insulator 254 preferably has a function of suppressing oxygen diffusion. For example, the insulator 254 preferably has a function of suppressing oxygen diffusion more than the insulator 280. As the insulator 254, for example, an insulator containing an oxide of one or both of aluminum and hafnium may be formed.

[0151] Moreover, the insulator 254 is preferably formed by forming a film of aluminum oxide or hafnium oxide in an atmosphere containing oxygen by bias sputtering. Bias sputtering is a method of sputtering while applying RF power to a substrate. By applying RF power to the substrate, the potential of the substrate becomes negative with respect to the plasma potential (called bias potential), and positive ions in the plasma are accelerated to this bias potential and injected into the substrate. The bias potential can be controlled by the magnitude of the RF power applied to the substrate. Therefore, oxygen can be injected into the insulator 224 by forming a film of aluminum oxide or hafnium oxide in an atmosphere containing oxygen by bias sputtering.

[0152] In the bias sputtering method, the amount of oxygen implanted into the insulator 224, which is the base of the insulator 254, can be controlled by the magnitude of the RF power applied to the substrate. For example, the RF power is set to 0.31 W / cm 2 More than 0.62 W / cm 2 More preferably, 1.86 W / cm 2 The above bias may be applied to the substrate. In other words, the amount of oxygen suitable for the characteristics of the transistor can be changed and injected by adjusting the RF power when forming the insulator 254. Also, the amount of oxygen suitable for improving the reliability of the transistor can be injected. Also, the RF frequency is preferably 10 MHz or more. Typically, it is 13.56 MHz. The higher the RF frequency, the less damage can be caused to the substrate. Therefore, by adjusting the RF power applied to the substrate, the amount of oxygen injected into the insulator 224 can be controlled, and therefore the amount of oxygen injected into the insulator 224 can be optimized.

[0153] As described above, the insulator 254 has a function of injecting oxygen into the underlying film, but the insulator 254 itself has a function of suppressing oxygen permeation. Therefore, when the insulator 280 is formed on the insulator 254 in a later process and oxygen is diffused from the insulator 280, it is possible to prevent oxygen from diffusing directly from the insulator 280 to the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B.

[0154] By providing the insulator 254 and the layer 244a (layer 244b) as described above, the oxide 230a, the oxide 230b, the oxide 243a (oxide 243b), and the conductor 242a (conductor 242b) can be separated from the insulator 280. Therefore, it is possible to suppress the direct diffusion of oxygen from the insulator 280 to the oxide 230a, the oxide 230b, the oxide 243a, the oxide 243b, the conductor 242a, and the conductor 242b. This makes it possible to prevent the carrier concentration of the source region and the drain region from being reduced by excessive oxygen being supplied to the source region and the drain region of the oxide 230. In addition, it is possible to suppress the conductor 242a and the conductor 242b from being excessively oxidized, which increases the resistivity and reduces the on-current.

[0155] The insulator 250 is preferably disposed in contact with at least a portion of the oxide 230d. The insulator 250 may be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, or the like. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat.

[0156] The insulator 250 is preferably formed using an insulator that releases oxygen when heated, similar to the insulator 224. By providing the insulator that releases oxygen when heated as the insulator 250 in contact with at least a part of the oxide 230d, oxygen can be effectively supplied to the channel formation region of the oxide 230, and oxygen vacancies in the channel formation region of the oxide 230 can be reduced. Therefore, a transistor with suppressed fluctuations in electrical characteristics, stable electrical characteristics, and improved reliability can be provided. Also, similar to the insulator 224, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 250 is reduced. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0157] In addition, although the insulator 250 is illustrated as a single layer in FIG. 1B and FIG. 1C, it may be a laminated structure of two or more layers. When the insulator 250 is a laminated structure of two layers, it is preferable that the lower layer of the insulator 250 is formed using an insulator that releases oxygen when heated, and the upper layer of the insulator 250 is formed using an insulator that has a function of suppressing the diffusion of oxygen. By adopting such a configuration, it is possible to suppress the diffusion of oxygen contained in the lower layer of the insulator 250 to the conductor 260. In other words, it is possible to suppress the decrease in the amount of oxygen supplied to the oxide 230. In addition, it is possible to suppress the oxidation of the conductor 260 due to the oxygen contained in the lower layer of the insulator 250. For example, the lower layer of the insulator 250 can be provided using a material that can be used for the insulator 250 described above, and the upper layer of the insulator 250 can be provided using a material similar to that of the insulator 222.

[0158] When silicon oxide or silicon oxynitride is used for the lower layer of the insulator 250, the upper layer of the insulator 250 may be made of an insulating material that is a high-k material with a high dielectric constant. By forming the gate insulator into a laminated structure of the lower layer of the insulator 250 and the upper layer of the insulator 250, it is possible to obtain a laminated structure that is stable against heat and has a high dielectric constant. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

[0159] Specifically, the upper layer of the insulator 250 may be a metal oxide containing one or more of hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc., or a metal oxide that can be used as the oxide 230. In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium.

[0160] By forming the insulator 250 into a two-layer laminated structure, the physical thickness of the insulator 250 can maintain a distance between the conductor 260 and the oxide 230, thereby suppressing leakage current between the conductor 260 and the oxide 230. In addition, the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230 can be easily and appropriately adjusted.

[0161] Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. In other words, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Furthermore, oxidation of the conductor 260 due to oxygen from the insulator 250 can be suppressed.

[0162] It is preferable that the metal oxide has a function as a part of the first gate electrode. For example, the metal oxide that can be used as the oxide 230 can be used as the metal oxide. In this case, the electric resistance value of the metal oxide can be reduced to make it a conductor by forming the conductor 260a by a sputtering method. This can be called an OC (Oxide Conductor) electrode.

[0163] By including the metal oxide, the on-state current of the transistor 200 can be improved without weakening the influence of the electric field from the conductor 260.

[0164] The conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed so as to wrap the bottom and side surfaces of the conductor 260b. As shown in FIG. 1B and FIG. 1C, the upper surface of the conductor 260 is disposed so as to substantially coincide with the upper surface of the insulator 250, the upper surface of the oxide 230d, and the upper surface of the oxide 230c. Note that, although the conductor 260 is shown in FIG. 1B and FIG. 1C as having a two-layer structure of the conductor 260a and the conductor 260b, it may be a single-layer structure or a laminated structure of three or more layers.

[0165] The conductor 260a is preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0166] Furthermore, since the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 250. As a conductive material having a function of suppressing the diffusion of oxygen, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0167] In addition, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 260b can be a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 260b may also have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above-mentioned conductive material.

[0168] Moreover, in the transistor 200, the conductor 260 is formed in a self-aligned manner so as to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be reliably disposed in the region between the conductor 242a and the conductor 242b without alignment.

[0169] As shown in FIG. 1C, in the channel width direction of the transistor 200, the bottom surface of the conductor 260 in the region where the conductor 260 and the oxide 230b do not overlap is preferably lower than the bottom surface of the oxide 230b. The conductor 260, which functions as a gate electrode, is configured to cover the side and top surfaces of the channel formation region of the oxide 230b via the insulator 250 or the like, so that the electric field of the conductor 260 can be easily applied to the entire channel formation region of the oxide 230b. This makes it possible to increase the on-current of the transistor 200 and improve the frequency characteristics. When the bottom surface of the insulator 222 is used as a reference, the difference between the height of the bottom surface of the conductor 260 in the region where the oxide 230a and the oxide 230b do not overlap with the conductor 260 and the height of the bottom surface of the oxide 230b is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0170] The insulator 280 is provided on the insulator 254. In addition, the upper surface of the insulator 280 may be flattened.

[0171] The insulator 280 that functions as an interlayer film preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced. The insulator 280 is preferably formed using, for example, the same material as the insulator 216. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferable because they can easily form a region containing oxygen that is desorbed by heating.

[0172] The concentration of impurities such as water and hydrogen in the insulator 280 is preferably reduced. The insulator 280 preferably has a low hydrogen concentration and an excess oxygen region or excess oxygen, and may be formed using, for example, a material similar to that of the insulator 216. The insulator 280 may have a structure in which the above materials are stacked, for example, a stacked structure of silicon oxide formed by a sputtering method and silicon oxynitride formed by a chemical vapor deposition (CVD) method. Silicon nitride may also be stacked on top of that.

[0173] The insulator 282 or the insulator 283 preferably functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from above into the insulator 280. The insulator 282 or the insulator 283 preferably functions as a barrier insulating film that suppresses oxygen transmission. The insulator 282 and the insulator 283 may be, for example, an insulator such as aluminum oxide, silicon nitride, or silicon nitride oxide. For example, the insulator 282 may be made of aluminum oxide, which has a high blocking property against oxygen, and the insulator 283 may be made of silicon nitride, which has a high blocking property against hydrogen.

[0174] Conductor 240a and conductor 240b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component.

[0175] Moreover, each of the conductor 240a and the conductor 240b may have a laminated structure. When each of the conductor 240a and the conductor 240b has a laminated structure, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen for the conductor in contact with the insulator 284, the insulator 283, the insulator 282, the insulator 280, and the insulator 254. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. Also, the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a laminated layer. Also, it is possible to suppress impurities such as water and hydrogen contained in layers above the insulator 284 from being mixed into the oxide 230 through the conductor 240a and the conductor 240b.

[0176] As the insulator 241a and the insulator 241b, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide may be used. Since the insulator 241a and the insulator 241b are provided in contact with the insulator 254, impurities such as water and hydrogen contained in the insulator 280 can be prevented from being mixed into the oxide 230 through the conductor 240a and the conductor 240b. In particular, silicon nitride is preferable because it has a high blocking property against hydrogen. In addition, it can prevent the oxygen contained in the insulator 280 from being absorbed by the conductor 240a and the conductor 240b.

[0177] Also, a conductor 246a that functions as wiring in contact with the upper surface of the conductor 240a, and a conductor 246b that functions as wiring in contact with the upper surface of the conductor 240b may be disposed. The conductor 246a and the conductor 246b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor may have a laminated structure, for example, a laminate of titanium or titanium nitride and the above-mentioned conductive material. The conductor may be formed so as to be embedded in an opening provided in an insulator.

[0178] The insulator 286 is provided on the conductor 246a, the conductor 246b, and the insulator 284. As a result, the upper surface of the conductor 246a, the side surface of the conductor 246a, the upper surface of the conductor 246b, and the side surface of the conductor 246b are in contact with the insulator 286, and the lower surface of the conductor 246a and the lower surface of the conductor 246b are in contact with the insulator 284. In other words, the conductor 246a and the conductor 246b can be configured to be wrapped in the insulator 284 and the insulator 286. With such a configuration, it is possible to suppress the permeation of oxygen from the outside and to prevent the conductor 246a and the conductor 246b from being oxidized. In addition, it is preferable because it is possible to prevent impurities such as water and hydrogen from conductor 246a and conductor 246b from diffusing to the outside.

[0179] <Materials for semiconductor devices> The following describes constituent materials that can be used in the semiconductor device.

[0180] <<Substrate>> The substrate on which the transistor 200 is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria stabilized zirconia substrate), and a resin substrate. Examples of semiconductor substrates include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include a semiconductor substrate having an insulating region inside the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Examples of conductive substrates include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Examples of substrates include a substrate having a metal nitride, a substrate having a metal oxide, and the like. Examples of substrates include a substrate having a conductor or semiconductor provided on an insulating substrate, a substrate having a conductor or insulator provided on a semiconductor substrate, and a substrate having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0181] <<Insulators>> Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, each of which has insulating properties.

[0182] For example, as transistors become smaller and more highly integrated, problems such as leakage current can occur due to thinner gate insulators. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the voltage required for transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, it is possible to reduce the parasitic capacitance that occurs between wiring. Therefore, it is best to select materials according to the function of the insulator.

[0183] Further, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0184] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, or resin.

[0185] In addition, the transistor using metal oxide can have stable electrical characteristics by being surrounded by an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. As the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer. Specifically, as the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.

[0186] The insulator that functions as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated for.

[0187] <<Conductors>> As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. In addition, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxygen is absorbed, so they are preferable. Furthermore, a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0188] A plurality of conductive layers formed of the above-mentioned materials may be stacked. For example, a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0189] In addition, when an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing a metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0190] In particular, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed as a conductor functioning as a gate electrode. The conductive material containing the metal element and nitrogen described above may also be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may also be used. Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon is added may also be used. Indium gallium zinc oxide containing nitrogen may also be used. By using such a material, hydrogen contained in the metal oxide in which the channel is formed may be captured. Alternatively, hydrogen mixed in from an external insulator may be captured.

[0191] <<Metal oxides>> It is preferable to use a metal oxide that functions as a semiconductor (oxide semiconductor) as the oxide 230. Hereinafter, metal oxides that can be applied to the oxide 230 according to the present invention will be described.

[0192] The metal oxide preferably contains at least indium or zinc. In particular, it is preferable that the metal oxide contains indium and zinc. In addition to these, it is preferable that the metal oxide contains aluminum, gallium, yttrium, tin, etc. In addition, it may contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0193] In this specification and the like, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, metal oxides containing nitrogen may also be referred to as metal oxynitrides.

[0194] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 3A. Fig. 3A is a diagram for explaining classification of crystal structures of oxide semiconductors, typically IGZO (metal oxide containing In, Ga, and Zn).

[0195] As shown in FIG. 3A, oxide semiconductors are broadly classified into "Amorphous", "Crystalline", and "Crystal". "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC) (excluding single crystal and poly crystal). "Crystalline" excludes single crystal, poly crystal, and completely amorphous. "Crystal" includes single crystal and poly crystal.

[0196] The structure in the bold frame shown in Fig. 3A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure is completely different from the energetically unstable "Amorphous" and "Crystal".

[0197] The crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. Figure 3B shows an XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of the CAAC-IGZO film classified as "Crystalline". The GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in Figure 3B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 3B is approximately In:Ga:Zn=4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 3B is 500 nm.

[0198] As shown in Figure 3B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ=31° in the XRD spectrum of the CAAC-IGZO film. Note that, as shown in Figure 3B, the peak near 2θ=31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0199] The crystal structure of the film or substrate can be evaluated from the diffraction pattern (also called the nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in Figure 3C. Figure 3C shows a diffraction pattern observed by NBED, which causes an electron beam to be incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 3C is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0200] As shown in Figure 3C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0201] <<Structure of oxide semiconductor>> In addition, when focusing on the crystal structure, oxide semiconductors may be classified differently from that shown in FIG. 3A. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. In addition, non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous-like oxide semiconductors (a-like OS), amorphous oxide semiconductors, and the like.

[0202] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0203] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystalline regions, each of which has a c-axis aligned in a specific direction. The specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. The crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, the crystalline region is also a region with a uniform lattice arrangement. CAAC-OS has a region in which a plurality of crystalline regions are connected in the ab-plane direction, and the region may have distortion. The distortion refers to a portion in which the direction of the lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in the region in which the plurality of crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor having a c-axis aligned and no clear orientation in the ab-plane direction.

[0204] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be about several tens of nm.

[0205] In addition, in an In-M-Zn oxide (wherein element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter, (M, Zn) layer) are stacked. Note that indium and element M are mutually substituted. Thus, the (M, Zn) layer may contain indium. Also, the In layer may contain element M. Note that the In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0206] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD device, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0207] For example, a plurality of bright points (spots) are observed in the electron diffraction pattern of the CAAC-OS film, and the two spots are observed at positions symmetrical to each other with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0208] When the crystal region is observed from the specific direction, the lattice arrangement in the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. The above distortion may have a pentagonal or heptagonal lattice arrangement. In addition, no clear grain boundary can be confirmed in the CAAC-OS even in the vicinity of the distortion. That is, it is found that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is considered to be because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab-plane direction and the bond distance between atoms changes due to the substitution of metal atoms.

[0209] A crystal structure in which clear grain boundaries are observed is called a polycrystal. The grain boundaries are likely to become recombination centers and capture carriers, causing a decrease in the on-current of a transistor and a decrease in field effect mobility. Therefore, CAAC-OS in which clear grain boundaries are not observed is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. In order to form a CAAC-OS, a structure containing Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the occurrence of grain boundaries more than indium oxide.

[0210] The CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. In addition, since the crystallinity of an oxide semiconductor can be decreased by the inclusion of impurities or the generation of defects, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of an oxide semiconductor having the CAAC-OS are stable. Therefore, an oxide semiconductor having the CAAC-OS is resistant to heat and has high reliability. In addition, the CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, the use of the CAAC-OS in an OS transistor can increase the degree of freedom in the manufacturing process.

[0211] [nc-OS] The nc-OS has periodic atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has minute crystals. Note that the size of the minute crystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the minute crystals are also called nanocrystals. In addition, the nc-OS does not show regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is seen in the entire film. Therefore, depending on the analysis method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structure analysis is performed on an nc-OS film using an XRD device, no peak indicating crystallinity is detected in out-of-plane XRD measurement using θ / 2θ scan. In addition, when an nc-OS film is subjected to electron diffraction (also called selected area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystals (for example, 50 nm or more), a diffraction pattern like a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter (e.g., 1 nm to 30 nm) that is close to the size of a nanocrystal or smaller than the nanocrystal, an electron diffraction pattern in which multiple spots are observed within a ring-shaped region centered on the direct spot may be obtained.

[0212] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Moreover, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0213] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, with reference to its material composition.

[0214] [CAC-OS] CAC-OS is, for example, a material configuration in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide and the regions having the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0215] Furthermore, CAC-OS is a composite metal oxide in which the material is separated into a first region and a second region, forming a mosaic structure, and the first region is distributed throughout the film (hereinafter, also referred to as a cloud structure). In other words, CAC-OS is a composite metal oxide in which the first region and the second region are mixed together.

[0216] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are represented as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. Also, the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. Also, the second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0217] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0218] In addition, there are cases where a clear boundary between the first region and the second region cannot be observed.

[0219] For example, in the case of a CAC-OS of an In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) has confirmed that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0220] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, giving the CAC-OS a switching function (On / Off function). In other words, CAC-OS has a conductive function in part of the material and an insulating function in other parts of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, it is possible to maximize both functions. Therefore, by using CAC-OS in a transistor, it is possible to achieve a high on-current (I on ), high field effect mobility (μ), and good switching behavior can be achieved.

[0221] Oxide semiconductors have a variety of structures and each structure has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0222] <Transistor Having Oxide Semiconductor> Next, the case where the oxide semiconductor is used for a transistor will be described.

[0223] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0224] For the transistor, an oxide semiconductor having a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 Less than or equal to 1×10 15 cm -3 Less than 1×10, more preferably 13 cm -3 Less than or equal to 1×10 11 cm -3 Less than 1×10, more preferably 10 cm -3 Less than 1 x 10 -9 cm-3 The above is the case. Note that in order to reduce the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, an oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. Note that in this specification and the like, when the carrier concentration of a metal oxide in a channel formation region is 1×10 16 cm -3 The following cases are defined as substantially high purity and authentic:

[0225] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states might also be low.

[0226] In addition, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave as if they are fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0227] In addition, when impurities and oxygen vacancies are present in a channel formation region of a transistor including an oxide semiconductor, the resistance of the oxide semiconductor may be reduced and the electrical characteristics may be easily changed, resulting in reduced reliability.

[0228] In a transistor using an oxide semiconductor for a channel formation region, when a low-resistance region is formed in the channel formation region, a leakage current (parasitic channel) between the source electrode and the drain electrode of the transistor is likely to occur in the low-resistance region. In addition, the parasitic channel is likely to cause defects in the transistor characteristics, such as a normally-on transistor, an increase in leakage current, and a shift in threshold voltage due to application of stress. In addition, if the processing precision of the transistor is low, the parasitic channel varies from transistor to transistor, causing variation in the transistor characteristics.

[0229] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a film adjacent to the oxide semiconductor.

[0230] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0231] When impurities are mixed into an oxide semiconductor, defect states or oxygen vacancies may be formed. Thus, when impurities are mixed into a channel formation region of an oxide semiconductor, the electrical characteristics of a transistor using the oxide semiconductor are likely to fluctuate, and the reliability may be reduced. Furthermore, when oxygen vacancies are included in the channel formation region, the transistor is likely to have normally-on characteristics (characteristics in which a channel exists and a current flows through the transistor even when no voltage is applied to the gate electrode).

[0232] A transistor using a metal oxide is likely to have normally-on characteristics due to impurities and oxygen vacancies in the metal oxide, and when the transistor is operated in a state where the metal oxide contains excess oxygen that exceeds an appropriate amount, the valence of the excess oxygen atom changes, causing the electrical characteristics of the transistor to change, which may result in poor reliability.

[0233] Furthermore, when impurities are present in a channel formation region of an oxide semiconductor, the crystallinity of the channel formation region may be reduced, or the crystallinity of an oxide provided in contact with the channel formation region may be reduced. When the crystallinity of the channel formation region is low, the stability or reliability of the transistor tends to be degraded. When the crystallinity of an oxide provided in contact with the channel formation region is low, an interface state may be formed, which may degrade the stability or reliability of the transistor.

[0234] Impurities in the metal oxide include, for example, hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0235] When an oxide semiconductor contains silicon or carbon, which is one of the group 14 elements, defect levels are formed in the oxide semiconductor. For this reason, the concentrations of silicon or carbon in the oxide semiconductor and those near the interface with the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are calculated as 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0236] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect states may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of an alkali metal or an alkaline earth metal in an oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 To the following:

[0237] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor tends to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen for a semiconductor layer tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in an oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17atoms / cm 3 To the following:

[0238] Furthermore, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. In addition, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce hydrogen in the oxide semiconductor as much as possible. Specifically, when the hydrogen concentration in an oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0239] A defect in which hydrogen has entered an oxygen vacancy (V O H) can function as a donor for the metal oxide. However, it is difficult to quantitatively evaluate the defect. Therefore, in the case of metal oxides, the carrier concentration may be used instead of the donor concentration. Therefore, in this specification, the carrier concentration assuming a state in which no electric field is applied may be used as a parameter of the metal oxide instead of the donor concentration. In other words, the "carrier concentration" described in this specification may be rephrased as the "donor concentration". In addition, the "carrier concentration" described in this specification may be rephrased as the "carrier density".

[0240] When an oxide semiconductor in which impurities are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0241] <<Other semiconductor materials>> The semiconductor material that can be used for the oxide 230 is not limited to the above-mentioned metal oxides. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used for the oxide 230. For example, a semiconductor of a single element such as silicon, a compound semiconductor such as gallium arsenide, or a layered material (also called an atomic layer material, a two-dimensional material, etc.) that functions as a semiconductor is preferably used for the semiconductor material. In particular, it is preferable to use a layered material that functions as a semiconductor for the semiconductor material.

[0242] Here, in this specification and the like, the layered material is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces. The layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0243] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds that contain chalcogen. Chalcogen is a general term for elements in group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides include transition metal chalcogenides and group 13 chalcogenides.

[0244] It is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor as the oxide 230. Specific examples of transition metal chalcogenides that can be used as the oxide 230 include molybdenum sulfide (representatively MoS2), molybdenum selenide (representatively MoSe2), molybdenum tellurium (representatively MoTe2), tungsten sulfide (representatively WS2), tungsten selenide (representatively WSe2), tungsten tellurium (representatively WTe2), hafnium sulfide (representatively HfS2), hafnium selenide (representatively HfSe2), zirconium sulfide (representatively ZrS2), and zirconium selenide (representatively ZrSe2).

[0245] <Modifications of the semiconductor device> An example of a semiconductor device which is one embodiment of the present invention will be described below with reference to FIGS. 4A to 4D.

[0246] Fig. 4A shows a top view of the semiconductor device. Fig. 4B is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in Fig. 4A. Fig. 4C is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in Fig. 4A. Fig. 4D is a cross-sectional view corresponding to the portion indicated by the dashed line A5-A6 in Fig. 4A. Some elements are omitted from the top view of Fig. 4A for clarity.

[0247] 4A to 4D, structures having the same functions as those of the structures constituting the semiconductor device shown in <Configuration example of semiconductor device> are denoted by the same reference numerals. Note that, in this section, the materials described in detail in <Configuration example of semiconductor device> can be used as the materials constituting the semiconductor device.

[0248] <<Modification 1 of the semiconductor device>> The semiconductor device shown in Figures 4A to 4D is a modified example of the semiconductor device shown in Figures 1A to 1D. The semiconductor device shown in Figures 4A to 4D is different from the semiconductor device shown in Figures 1A to 1D in the shapes of the insulator 283 and the insulator 284. Also, the semiconductor device shown in Figures 4A to 4D is different in that it has the insulator 274 and the insulator 287.

[0249] 4A to 4D, the insulator 212, the insulator 214, the insulator 216, the insulator 222, the insulator 224, the insulator 254, the insulator 280, and the insulator 282 are patterned, and the insulator 287 is provided in contact with the side surfaces of the insulator 212, the insulator 214, the insulator 216, the insulator 222, the insulator 224, the insulator 254, the insulator 280, and the insulator 282. The insulators 283 and 284 are structured to cover the insulator 212, the insulator 214, the insulator 216, the insulator 222, the insulator 224, the insulator 254, the insulator 280, the insulator 282, and the insulator 287. That is, the insulator 283 contacts the upper surface of the insulator 282, the upper surface and side surface of the insulator 287, and the upper surface of the insulator 211, and the insulator 284 contacts the upper surface and side surface of the insulator 283. As a result, the insulators 214, 216, 222, 224, 254, 280, 282, and 287, including the oxide 230 and the like, are isolated from the outside by the insulators 283 and 284 and the insulator 211. In other words, the transistor 200 is disposed in a region sealed by the insulators 283, 284, and the insulator 211.

[0250] For example, it is preferable to form the insulators 212, 214, 287, and 282 using a material having a function of capturing and fixing hydrogen, and to form the insulators 211, 283, and 284 using a material having a function of suppressing the diffusion of hydrogen and oxygen. Typically, the insulators 212, 214, 287, and 282 can be made of aluminum oxide. Typically, the insulators 211, 283, and 284 can be made of silicon nitride.

[0251] With this configuration, it is possible to prevent hydrogen contained outside the sealed region from entering the sealed region.

[0252] 4A to 4D, the insulator 211, the insulator 283, and the insulator 284 are each provided as a single layer, but the present invention is not limited to this. For example, each of the insulator 211, the insulator 283, and the insulator 284 may be provided as a stacked structure of two or more layers.

[0253] The insulator 274 functions as an interlayer film. The insulator 274 preferably has a lower dielectric constant than the insulator 214. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance generated between wirings can be reduced. The insulator 274 can be provided using, for example, a material similar to that of the insulator 280.

[0254] <Method for manufacturing semiconductor device> Next, a manufacturing method of the semiconductor device illustrated in FIGS. 4A to 4D which is one embodiment of the present invention will be described with reference to FIGS.

[0255] Figures 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, and 21A show top views. In addition, Figures 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, 15B, 16B, 17B, 18B, 19B, 20B, and 21B are cross-sectional views corresponding to the portions indicated by the dashed dotted line A1-A2 in Figures 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, and 21A, respectively, and are also cross-sectional views in the channel length direction of transistor 200. In addition, Figures 5C, 6C, 7C, 8C, 9C, 10C, 11C, 12C, 13C, 14C, 15C, 16C, 17C, 18C, 19C, 20C, and 21C are cross-sectional views corresponding to the portions indicated by the dotted line A3-A4 in Figures 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, and 21A, respectively, and are also cross-sectional views in the channel width direction of transistor 200. In addition, Figures 5D, 6D, 7D, 8D, 9D, 10D, 11D, 12D, 13D, 14D, 15D, 16D, 17D, 18D, 19D, 20D, and 21D are cross-sectional views of the areas indicated by the dotted line A5-A6 in Figures 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, and 21A, respectively. Note that in the top views of Figures 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, and 21A, some elements have been omitted to clarify the figures.

[0256] First, a substrate (not shown) is prepared, and a film of the insulator 211 is formed on the substrate. The film of the insulator 211 can be formed by using a sputtering method, a CVD method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0257] CVD methods can be classified into plasma enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, photo CVD (Photo CVD), etc. They can also be further divided into metal CVD (MCVD) and metal organic CVD (MOCVD), depending on the source gas used.

[0258] The plasma CVD method can obtain a high-quality film at a relatively low temperature. Moreover, the thermal CVD method is a film formation method that can reduce plasma damage to the object to be processed because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitive elements, etc.) included in a semiconductor device may be charged up by receiving electric charge from plasma. At this time, the wiring, electrodes, elements, etc. included in the semiconductor device may be destroyed by the accumulated electric charge. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so the yield of the semiconductor device can be increased. Furthermore, in the thermal CVD method, plasma damage does not occur during film formation, so a film with few defects can be obtained.

[0259] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a plasma enhanced ALD method in which a plasma excited reactant is used, or the like can be used.

[0260] In addition, the ALD method utilizes the self-regulating nature of atoms and can deposit atoms one layer at a time, which has the following advantages: extremely thin films can be formed; films can be formed on structures with high aspect ratios; films can be formed with fewer defects such as pinholes; films can be formed with excellent coverage; and films can be formed at low temperatures. In the PEALD (Plasma Enhanced ALD) method, the use of plasma can enable film formation at lower temperatures, which may be preferable. Note that some precursors used in the ALD method contain impurities such as carbon. For this reason, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. Note that the amount of impurities can be quantified using X-ray photoelectron spectroscopy (XPS).

[0261] The CVD method and the ALD method are different from the film formation method in which particles emitted from a target or the like are deposited, and are film formation methods in which a film is formed by a reaction on the surface of a workpiece. Therefore, they are film formation methods that are not easily affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, so it is suitable for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation speed.

[0262] In the CVD method and the ALD method, the composition of the film obtained can be controlled by the flow rate ratio of the raw material gases. For example, in the CVD method and the ALD method, a film of any composition can be formed by changing the flow rate ratio of the raw material gases. In addition, for example, in the CVD method and the ALD method, a film whose composition changes continuously can be formed by changing the flow rate ratio of the raw material gases while forming the film. When forming a film while changing the flow rate ratio of the raw material gases, the time required for film formation can be shortened compared to the case of forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.

[0263] In this embodiment, the insulator 211 is formed by depositing silicon nitride by a CVD method.

[0264] Next, the insulator 212 is formed over the insulator 211. The insulator 212 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, the insulator 212 is formed by forming a silicon nitride film by a sputtering method.

[0265] In this way, by using an insulator such as silicon nitride through which copper does not easily permeate as insulator 211 and insulator 212, even if a metal that easily diffuses, such as copper, is used for a conductor in a layer below insulator 211 (not shown), it is possible to suppress the metal from diffusing upward through insulator 211 and insulator 212. Furthermore, by using an insulator such as silicon nitride through which impurities such as water and hydrogen do not easily permeate, it is possible to suppress the diffusion of impurities such as water and hydrogen contained in the layer below insulator 211.

[0266] Next, the insulator 214 is deposited over the insulator 212. The insulator 214 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, aluminum oxide is used as the insulator 214.

[0267] It is preferable that the hydrogen concentration of the insulator 212 is lower than that of the insulator 211, and the hydrogen concentration of the insulator 214 is lower than that of the insulator 212. By forming a silicon nitride film as the insulator 212 by a sputtering method, it is possible to form silicon nitride having a lower hydrogen concentration than the insulator 211 formed by forming a silicon nitride film by a CVD method. Furthermore, by using aluminum oxide as the insulator 214, it is possible to form a hydrogen concentration lower than that of the insulator 212.

[0268] In a subsequent process, the transistor 200 is formed on the insulator 214, and it is preferable that the film close to the transistor 200 has a relatively low hydrogen concentration, and it is preferable that the film with a relatively high hydrogen concentration is placed away from the transistor 200.

[0269] Next, the insulator 216 is deposited over the insulator 214. The insulator 216 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide or silicon oxynitride is used as the insulator 216. The insulator 216 is preferably deposited by a deposition method using a gas in which hydrogen atoms are reduced or removed. This allows the hydrogen concentration in the insulator 216 to be reduced.

[0270] Next, an opening is formed in the insulator 216, reaching the insulator 214. The opening may be, for example, a groove or a slit. The opening may be an area where an opening is formed. The opening may be formed by wet etching, but dry etching is preferable for fine processing. For the insulator 214, it is preferable to select an insulator that functions as an etching stopper film when etching the insulator 216 to form a groove. For example, when silicon oxide or silicon oxynitride is used for the insulator 216 that forms the groove, the insulator 214 may be silicon nitride, aluminum oxide, or hafnium oxide.

[0271] As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can be configured to apply a high frequency voltage to one of the parallel plate electrodes. Alternatively, it can be configured to apply a plurality of different high frequency voltages to one of the parallel plate electrodes. Alternatively, it can be configured to apply a high frequency voltage of the same frequency to each of the parallel plate electrodes. Alternatively, it can be configured to apply high frequency voltages of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high density plasma source can be used. As the dry etching apparatus having a high density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus or the like can be used.

[0272] After the opening is formed, a conductive film that becomes the conductor 205a is formed. The conductive film preferably contains a conductor that has a function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, the conductive film may be a stacked film of a conductor that has a function of suppressing oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0273] In this embodiment, the conductive film that becomes the conductor 205a has a multi-layer structure. First, a tantalum nitride film is formed by sputtering, and titanium nitride is laminated on the tantalum nitride. By using such a metal nitride as the lower layer of the conductor 205b, even if a metal that easily diffuses, such as copper, is used for the conductive film that becomes the conductor 205b described later, the metal can be prevented from diffusing out of the conductor 205a.

[0274] Next, a conductive film that becomes the conductor 205b is formed. The conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a low-resistance conductive material such as copper is formed as the conductive film.

[0275] Next, a CMP process is performed to remove the conductive film that will become the conductor 205a and a portion of the conductive film that will become the conductor 205b, thereby exposing the insulator 216. As a result, the conductor 205a and the conductor 205b remain only in the openings. This makes it possible to form a conductor 205 with a flat upper surface (see FIGS. 5A to 5D). Note that the CMP process may remove a portion of the insulator 216.

[0276] Note that in the above description, the conductor 205 is formed to be embedded in the opening of the insulator 216; however, one embodiment of the present invention is not limited to this. For example, the conductor 205 may be formed over the insulator 214, the insulator 216 may be formed over the conductor 205, and a part of the insulator 216 may be removed by performing CMP treatment on the insulator 216 to expose the surface of the conductor 205.

[0277] Next, the insulator 222 is formed over the insulator 216 and the conductor 205. As the insulator 222, an insulator containing an oxide of one or both of aluminum and hafnium may be formed. The insulator containing an oxide of one or both of aluminum and hafnium has a barrier property against oxygen, hydrogen, and water. When the insulator 222 has a barrier property against hydrogen and water, the hydrogen and water contained in the structure provided around the transistor 200 are prevented from diffusing into the inside of the transistor 200 through the insulator 222, and the generation of oxygen vacancies in the oxide 230 can be suppressed.

[0278] The insulator 222 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0279] It is preferable to carry out a heat treatment subsequently. The heat treatment may be carried out at 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. The heat treatment may be carried out in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. For example, when the heat treatment is carried out in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas may be about 20%. The heat treatment may be carried out under reduced pressure. Alternatively, the heat treatment may be carried out in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas to compensate for the desorbed oxygen.

[0280] In addition, it is preferable that the gas used in the heat treatment is highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being taken into the insulator 222 as much as possible.

[0281] In this embodiment, after the insulator 222 is formed, heat treatment is performed at a temperature of 400° C. for 1 hour with a nitrogen gas flow rate of 4 slm and an oxygen gas flow rate of 1 slm. The heat treatment can remove impurities such as water and hydrogen contained in the insulator 222. When an oxide containing hafnium is used as the insulator 222, the heat treatment can improve the crystallinity of the insulator 222. The heat treatment can also be performed at a timing such as after the insulator 224 is formed.

[0282] Next, the insulator 224 is formed on the insulator 222. The insulator 224 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, the insulator 224 is formed by forming a silicon oxide or silicon oxynitride film by a CVD method. The insulator 224 is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. This allows the hydrogen concentration of the insulator 224 to be reduced. Since the insulator 224 will become the insulator 224 in contact with the oxide 230a in a later process, it is preferable that the hydrogen concentration be reduced in this manner.

[0283] Here, in order to form an excess oxygen region in the insulator 224, a plasma treatment including oxygen may be performed under reduced pressure. For the plasma treatment including oxygen, it is preferable to use an apparatus having a power source that generates high density plasma using, for example, microwaves. Alternatively, the apparatus may have a power source that applies RF (Radio Frequency) to the substrate side. By using high density plasma, high density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high density plasma can be efficiently guided into the insulator 224. Alternatively, after performing a plasma treatment including an inert gas using this apparatus, a plasma treatment including oxygen may be performed to compensate for the desorbed oxygen. Note that impurities such as water and hydrogen contained in the insulator 224 can be removed by appropriately selecting the conditions for the plasma treatment. In that case, heat treatment does not need to be performed.

[0284] Here, after forming an aluminum oxide film on the insulator 224 by, for example, a sputtering method, a CMP process may be performed until the insulator 224 is reached. The CMP process can planarize and smooth the surface of the insulator 224. By disposing the aluminum oxide on the insulator 224 and performing the CMP process, it becomes easy to detect the end point of the CMP process. In addition, the CMP process may polish a part of the insulator 224, and the thickness of the insulator 224 may become thin, but the thickness may be adjusted when the insulator 224 is formed. By planarizing and smoothing the surface of the insulator 224, it may be possible to prevent a deterioration in the coverage rate of the oxide to be formed later and to prevent a decrease in the yield of the semiconductor device. In addition, it is preferable to form an aluminum oxide film on the insulator 224 by a sputtering method, since oxygen can be added to the insulator 224.

[0285] Next, oxide film 230A and oxide film 230B are sequentially formed on insulator 224 (see FIGS. 5A to 5D). Note that oxide film 230A and oxide film 230B are preferably formed successively without exposure to the air environment. By forming the films without exposure to the air, it is possible to prevent impurities or moisture from the air environment from adhering to oxide film 230A and oxide film 230B, and it is possible to keep the vicinity of the interface between oxide film 230A and oxide film 230B clean.

[0286] The oxide film 230A and the oxide film 230B can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0287] For example, when the oxide film 230A and the oxide film 230B are formed by sputtering, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the ratio of oxygen contained in the sputtering gas, the excess oxygen in the oxide film to be formed can be increased. In addition, when the oxide film is formed by sputtering, the above-mentioned In-M-Zn oxide target can be used.

[0288] In particular, during the formation of the oxide film 230A, a portion of the oxygen contained in the sputtering gas may be supplied to the insulator 224. Therefore, the ratio of oxygen contained in the sputtering gas may be set to 70% or more, preferably 80% or more, and more preferably 100%.

[0289] When the oxide film 230B is formed by a sputtering method, an oxygen-excessive oxide semiconductor is formed when the ratio of oxygen contained in the sputtering gas is more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excessive oxide semiconductor for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. When the oxide film 230B is formed by a sputtering method, an oxygen-deficient oxide semiconductor is formed when the ratio of oxygen contained in the sputtering gas is more than or equal to 1% and less than or equal to 30%, preferably 5% to 20%,. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have relatively high field-effect mobility. When the oxide film is formed while the substrate is heated, the crystallinity of the oxide film can be improved.

[0290] In this embodiment, the oxide film 230A is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4. The oxide film 230B is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1. Each oxide film may be formed according to the characteristics required for the oxide 230a and the oxide 230b by appropriately selecting the film formation conditions and atomic ratio.

[0291] Next, the oxide film 243A is formed on the oxide film 230B (see FIGS. 5A to 5D). The oxide film 243A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The atomic ratio of Ga to In in the oxide film 243A is preferably greater than the atomic ratio of Ga to In in the oxide film 230B. In this embodiment, the oxide film 243A is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4.

[0292] It is preferable to form the insulator 222, the insulator 224, the oxide film 230A, the oxide film 230B, and the oxide film 243A without exposing them to the atmosphere, for example, by using a multi-chamber type film forming apparatus.

[0293] Next, it is preferable to perform a heat treatment. The heat treatment may be performed in a temperature range in which the oxide film 230A, the oxide film 230B, and the oxide film 243A are not polycrystallized, and may be performed at 250°C to 650°C, preferably 400°C to 600°C. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas may be about 20%. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.

[0294] In addition, the gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment may be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By using a highly purified gas to perform the heat treatment, it is possible to prevent moisture and the like from being taken into the oxide film 230A, the oxide film 230B, the oxide film 243A, and the like as much as possible.

[0295] In this embodiment, the heat treatment is performed in a nitrogen atmosphere at 550° C. for 1 hour, followed by another heat treatment in an oxygen atmosphere at 550° C. for 1 hour. This heat treatment can remove impurities such as water and hydrogen from the oxide film 230A, the oxide film 230B, and the oxide film 243A. Furthermore, this heat treatment can improve the crystallinity of the oxide film 230B, resulting in a denser and more compact structure. This can suppress the diffusion of oxygen or impurities in the oxide film 230B.

[0296] Next, the conductive film 242A is formed on the oxide film 243A (see FIGS. 5A to 5D). The conductive film 242A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. Note that a heat treatment may be performed before the conductive film 242A is formed. The heat treatment may be performed under reduced pressure, and the conductive film 242A may be formed continuously without exposure to the air. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 243A can be removed, and the moisture concentration and hydrogen concentration in the oxide film 230A, the oxide film 230B, and the oxide film 243A can be reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the temperature of the heat treatment is set to 200° C.

[0297] Next, the oxide film 230A, the oxide film 230B, the oxide film 243A, and the conductive film 242A are processed into an island shape by using a lithography method.

[0298] First, a resist is formed over the conductive film 242A and exposed to light through a mask. Next, the exposed region is removed or left using a developer to form a resist mask 277 (see FIGS. 5A to 5D).

[0299] For example, the resist may be exposed to KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like to form the resist mask 277. Alternatively, a liquid immersion technique may be used in which exposure is performed by filling a space between the substrate and the projection lens with liquid (e.g., water). Alternatively, an electron beam or an ion beam may be used instead of the light described above. Note that when an electron beam or an ion beam is used, no mask is required.

[0300] Here, the heat resistance or dry etching resistance of the resist mask 277 may be improved. In this specification, improving the heat resistance or dry etching resistance of the resist mask may be referred to as hardening the resist mask.

[0301] For example, by irradiating a resist mask with ultraviolet light, resist molecules are crosslinked, and the heat resistance and dry etching resistance of the resist mask can be improved. As the ultraviolet light, it is preferable to use near ultraviolet light (ultraviolet light having a wavelength of 200 nm to 380 nm) or far ultraviolet light (ultraviolet light having a wavelength of 10 nm to 200 nm, also called vacuum ultraviolet light), and it is more preferable to use ultraviolet light having a wavelength of 250 nm to 300 nm. After the irradiation with ultraviolet light, a high-temperature heat treatment may be performed.

[0302] Also, for example, the heat resistance and dry etching resistance of the resist mask can be improved by exposing the resist mask to plasma to modify the film quality on the resist surface side. For the plasma, H2 gas, a mixed gas of H2 and Ar, a mixed gas of CF4 and O2, a mixed gas of C2HCl3 and O2, etc. can be used.

[0303] Next, the oxide film 230A, the oxide film 230B, the oxide film 243A, and the conductive film 242A are processed into islands by etching through a resist mask 277, to form the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B (see FIGS. 6A to 6D). This processing can be performed by a dry etching method or a wet etching method. Processing by the dry etching method is suitable for fine processing. The oxide film 230A, the oxide film 230B, the oxide film 243A, and the conductive film 242A may be processed under different conditions. In this process, the thickness of the region of the insulator 224 that does not overlap with the oxide 230a may be thin.

[0304] Here, the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B are formed so that at least a part of them overlaps with the conductor 205. In addition, it is preferable that the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B are approximately perpendicular to the upper surface of the insulator 222. When the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B are approximately perpendicular to the upper surface of the insulator 222, it is possible to reduce the area and increase the density when providing a plurality of transistors 200. Alternatively, a configuration may be used in which the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B form a small angle with the upper surface of the insulator 222. By forming such a shape, the coverage of the insulator 254 and the like is improved in the subsequent steps, and defects such as voids can be reduced.

[0305] Furthermore, there is a curved surface between the side surface of the conductive layer 242B and the top surface of the conductive layer 242B. In other words, it is preferable that the end of the side surface and the end of the top surface are curved. For example, the curved surface has a radius of curvature of 3 nm or more and 10 nm or less, preferably 5 nm or more and 6 nm or less, at the end of the conductive layer 242B. By not having corners at the end, the coverage of the film in the subsequent film formation process is improved.

[0306] In the above process, a layer 244A is formed on the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B (see FIGS. 6B to 6D). The layer 244A is formed when a part of the conductive layer 242B is etched, floats up in the chamber, and is deposited again. Thus, the layer 244A is an oxide containing the main component of the conductive layer 242B. For example, when tantalum nitride is used for the conductive layer 242B, the layer 244A is an oxide containing tantalum.

[0307] Next, the layer 244A is anisotropically etched to remove the layer 244A on the insulator 224 and the conductive layer 242B. At this time, a part of the layer 244A may remain, and a layer 244B may be formed (see FIGS. 7A to 7D).

[0308] The layer 244A on the insulator 224 is removed by the anisotropic etching. Therefore, the concentration of the metal contained in the layer 244B becomes below the detection limit at the interface between the insulator 224 and the insulator 254 to be formed later and in the vicinity thereof. Depending on the method of the anisotropic etching, the metal contained in the layer 244B may be detected at the interface and in the vicinity thereof. In either case, the concentration of the metal contained in the layer 244B at the interface and in the vicinity thereof is lower than the concentration of the metal in the layer 244B. Alternatively, the insulator 224 in the region in contact with the insulator 254 has a region with a lower concentration of the metal than the layer 244a or layer 244b formed from the layer 244B.

[0309] After the anisotropic etching, the resist mask 277 may remain. The remaining resist mask 277 can be removed by performing a dry etching process such as ashing, a wet etching process, a wet etching process after the dry etching process, or a dry etching process after the wet etching process.

[0310] It is preferable to perform the hardening of the resist mask 277, the island-shaped processing of the oxide film 230A, the oxide film 230B, the oxide film 243A, and the conductive film 242A, and the anisotropic etching of the layer 244A in succession using one dry etching apparatus. In addition, if the resist mask 277 remains after the anisotropic etching, it is preferable to perform the hardening of the resist mask 277, the island-shaped processing of the oxide film 230A, the oxide film 230B, the oxide film 243A, and the conductive film 242A, the anisotropic etching of the layer 244A, and the removal of the resist mask 277 (also called resist peeling) in succession using one dry etching apparatus. By performing these steps in succession, the process can be simplified. It is preferable to perform a step of removing deposits on the inner wall of the processing chamber of the dry etching apparatus (so-called chamber cleaning step) between the anisotropic etching and the resist peeling.

[0311] Next, the insulator 254 is formed on the insulator 224, the layer 244B, and the conductive layer 242B (see FIGS. 8B to 8D). The insulator 254 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, the insulator 254 is formed by forming an aluminum oxide film by a sputtering method.

[0312] Next, an insulating film to be the insulator 280 is formed on the insulator 254. The insulating film can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. For example, a silicon oxide film can be formed as the insulating film by sputtering, and a silicon oxide film can be formed thereon by PEALD or thermal ALD. The insulating film is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. This can reduce the hydrogen concentration in the insulator 280. Before the insulating film is formed, a heat treatment can be performed. The heat treatment can be performed under reduced pressure, and the insulating film can be formed continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulator 254 can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a, the oxide 230b, the oxide layer 243B, and the insulator 224 can be reduced. The heat treatment can be performed under the above-mentioned heat treatment conditions.

[0313] Next, the insulating film is subjected to CMP processing to form an insulator 280 with a flat upper surface (see FIGS. 8B to 8D). Note that, similarly to the insulator 224, a film of aluminum oxide may be formed on the insulator 280 by, for example, a sputtering method, and CMP may be performed until the aluminum oxide reaches the insulator 280.

[0314] Here, a microwave treatment may be performed. The microwave treatment is preferably performed in an oxygen-containing atmosphere under reduced pressure. By performing the microwave treatment, an electric field due to microwaves is applied to the insulator 280, the oxide 230b, the oxide 230a, etc., and the V in the oxide 230b and the oxide 230a is increased. O H can be split into oxygen vacancies and hydrogen. At this time, some of the split hydrogen may be combined with oxygen contained in the insulator 280 and removed as water molecules. Also, some of the hydrogen may be gettered to the conductor 242a or the conductor 242b via the insulator 254.

[0315] After the microwave treatment, a heat treatment may be performed while maintaining the reduced pressure. By performing such a treatment, hydrogen in the insulator 280, the oxide 230b, and the oxide 230a can be efficiently removed. Note that the heat treatment temperature is preferably 300° C. or more and 500° C. or less.

[0316] Furthermore, by performing microwave treatment, the film quality of the insulator 280 can be modified, thereby suppressing the diffusion of hydrogen, water, impurities, etc. Therefore, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. into the oxide 230 through the insulator 280 in a post-process after the formation of the insulator 280, or by heat treatment, etc.

[0317] Next, a part of the insulator 280, a part of the insulator 254, a part of the conductive layer 242B, a part of the oxide layer 243B, and a part of the layer 244B are processed to form an opening that reaches the oxide 230b. The opening is preferably formed so as to overlap the conductor 205. By forming the opening, the conductor 242a, the conductor 242b, the oxide 243a, the oxide 243b, the layer 244a, and the layer 244b are formed (see FIGS. 9A to 9D).

[0318] When forming the opening, the upper part of the oxide 230b is removed. By removing a part of the oxide 230b, a groove is formed in the oxide 230b. Depending on the depth of the groove, the groove may be formed in the process of forming the opening, or may be formed in a process different from the process of forming the opening.

[0319] In addition, a part of the insulator 280, a part of the insulator 254, a part of the conductive layer 242B, a part of the oxide layer 243B, a part of the layer 244B, and a part of the oxide 230b can be processed by dry etching or wet etching. Processing by the dry etching method is suitable for fine processing. In addition, the processing may be performed under different conditions. For example, a part of the insulator 280 may be processed by dry etching, a part of the insulator 254 may be processed by wet etching, and a part of the oxide layer 243B, a part of the conductive layer 242B, and a part of the oxide 230b may be processed by dry etching. In addition, processing of a part of the oxide layer 243B and a part of the conductive layer 242B and processing of a part of the oxide 230b may be performed under different conditions. In addition, a part of the layer 244B may be processed when processing a part of the insulator 254, or when processing a part of the oxide layer 243B and a part of the conductive layer 242B.

[0320] Here, when a part of the oxide 230b is removed by dry etching to form a groove, it is preferable to perform the process by increasing the bias power. For example, the power density of the bias power is set to 0.03 W / cm 2 It is preferable to set it to 0.06 W / cm or more. 2 It is more preferable that the dry etching time is set to be equal to or longer than that. The dry etching time may be appropriately set according to the depth of the groove.

[0321] When the above opening is formed, the surface of the oxide 230b at the bottom of the opening may be damaged. In the damaged area of ​​the oxide 230b, crystal defects such as oxygen vacancies are formed, and impurities (metal elements such as hydrogen, nitrogen, silicon, and aluminum) may be present. In the damaged area, oxygen vacancies and impurities such as hydrogen are likely to exist, so that V O +H→V O In this way, the reaction V H occurs in the damaged area. OA large amount of H is formed. Therefore, even if the oxide 230c is formed on the oxide 230b while leaving the damaged region, the transistor is likely to have normally-on characteristics. Furthermore, the damaged region varies within the substrate surface, which causes variations in the characteristics of the semiconductor device having the transistor.

[0322] Here, it is preferable to remove impurities attached to the surfaces of the oxide 230a, the oxide 230b, etc. or diffused therein. It is also preferable to remove damaged areas formed on the surface of the oxide 230b by the dry etching. The impurities include those originating from components contained in the insulator 280, the insulator 254, the layer 244B, and the conductive layer 242B, components contained in the members used in the device used to form the opening, and components contained in the gas or liquid used in the etching. The impurities include, for example, aluminum, silicon, tantalum, fluorine, and chlorine.

[0323] A cleaning process is performed to remove the damaged area, the impurities, etc. The cleaning method includes wet cleaning using a cleaning solution, plasma processing using plasma, cleaning by heat treatment, etc., and the above cleaning methods may be combined appropriately. Note that the cleaning process may deepen the grooves.

[0324] For wet cleaning, a cleaning process may be performed using an aqueous solution of ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, or the like diluted with carbonated water or pure water, pure water, carbonated water, or the like. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0325] In this specification, an aqueous solution obtained by diluting commercially available hydrofluoric acid with pure water may be called diluted hydrofluoric acid, and an aqueous solution obtained by diluting commercially available ammonia water with pure water may be called diluted ammonia water. The concentration and temperature of the aqueous solution may be appropriately adjusted depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water may be 0.01% or more and 5% or less, preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid may be 0.01 ppm or more and 100 ppm or less, preferably 0.1 ppm or more and 10 ppm or less.

[0326] In addition, the ultrasonic cleaning uses a frequency of 200 kHz or more, preferably 900 kHz or more. By using such a frequency, damage to the oxide 230b and the like can be reduced.

[0327] The above cleaning process may be performed multiple times, and the cleaning solution may be changed for each cleaning process. For example, a first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and a second cleaning process may be performed using pure water or carbonated water.

[0328] In the present embodiment, as the cleaning process, wet cleaning is performed using diluted hydrofluoric acid, followed by wet cleaning using pure water or carbonated water. By performing this cleaning process, impurities attached to the surfaces of the oxide 230a, the oxide 230b, etc. or diffused inside can be removed. Furthermore, the crystallinity of the oxide 230c formed on the oxide 230b can be improved.

[0329] In the past, processing such as dry etching or the above-mentioned cleaning process may result in the thickness of insulator 224 in the area that overlaps with the opening but does not overlap with oxide 230b being thinner than the thickness of insulator 224 in the area that overlaps with oxide 230b.

[0330] A heat treatment may be performed after the etching or cleaning. The heat treatment may be performed at 100° C. to 450° C., preferably 350° C. to 400° C. The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. This allows oxygen to be supplied to the oxide 230a and the oxide 230b, thereby reducing oxygen deficiency. In addition, by performing such a heat treatment, the crystallinity of the oxide 230b can be improved, and the crystallinity of the oxide 230c formed in the groove portion of the oxide 230b can also be improved. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the oxygen atmosphere, the heat treatment may be performed in a nitrogen atmosphere without exposure to the air.

[0331] By removing the damaged region, the oxide 230c having the CAAC-OS can be formed in the groove of the oxide 230b from which the damaged region has been removed. The damaged region may be removed by forming a groove on the oxide 230b in a cross-sectional view in the channel length direction of the transistor.

[0332] Next, the oxide film 230C is formed (see FIGS. 10A to 10D). A heat treatment may be performed before the formation of the oxide film 230C, and the heat treatment is preferably performed under reduced pressure, and the oxide film 230C is formed continuously without exposure to the atmosphere. The heat treatment is preferably performed in an atmosphere containing oxygen. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide 230b can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a and the oxide 230b can be further reduced. The temperature of the heat treatment is preferably 100° C. or more and 400° C. or less. In this embodiment, the temperature of the heat treatment is 200° C.

[0333] Here, the oxide film 230C is preferably provided so as to contact at least the inner wall of the groove formed in the oxide 230b, a part of the side surface of the oxide 243a, a part of the side surface of the oxide 243b, a part of the side surface of the conductor 242a, a part of the side surface of the conductor 242b, a part of the side surface of the insulator 254, and a part of the side surface of the insulator 280. By being surrounded by the oxide 243a (oxide 243b), the insulator 254, the layer 244a (layer 244b), and the oxide film 230C, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 242a (conductor 242b) in the subsequent steps.

[0334] The oxide film 230C can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The oxide film 230C may be formed by the same film formation method as the oxide film 230A or the oxide film 230B according to the characteristics required for the oxide film 230C. In this embodiment, the oxide film 230C is formed by sputtering using an oxide target with In:Ga:Zn=4:2:3 [atomic ratio], an oxide target with In:Ga:Zn=5:1:3 [atomic ratio], an oxide target with In:Ga:Zn=10:1:3 [atomic ratio], or an indium oxide target.

[0335] When the oxide film 230C is formed, some of the oxygen contained in the sputtering gas may be supplied to the oxide 230a and the oxide 230b. Alternatively, when the oxide film 230C is formed, some of the oxygen contained in the sputtering gas may be supplied to the insulator 280. Therefore, the proportion of oxygen contained in the sputtering gas for the oxide film 230C may be 70% or more, preferably 80% or more, and more preferably 100%. Furthermore, by forming the oxide film 230C in an atmosphere containing a large amount of oxygen in this manner, the oxide film 230C is more likely to become a CAAC-OS.

[0336] The oxide film 230C is preferably formed while heating the substrate. At this time, by setting the substrate temperature to 200° C. or higher, oxygen vacancies in the oxide film 230C and the oxide 230b can be reduced. By forming the oxide film 230C while heating the substrate, the crystallinity of the oxide film 230C and the oxide 230b can be improved.

[0337] Next, a mask is formed on the oxide film 230C by lithography. Note that a hard mask or a resist mask may be used as the mask.

[0338] Next, the above mask is used to selectively remove a portion of the oxide film 230C. The portion of the oxide film 230C may be removed by using a wet etching method or the like. This process can remove a portion of the oxide film 230C located between the transistors 200 adjacent to each other in the channel width direction.

[0339] In the above process, in the region where part of oxide film 230C has been removed, the surfaces of insulator 224 and insulator 280 are exposed. At this time, the film thickness of insulator 224 and the film thickness of insulator 280 in the region may become thin. Also, insulator 224 in the region may be removed, exposing the surface of insulator 222. The process of forming the mask may also serve as a process of removing part of oxide film 230C.

[0340] Next, the mask is removed (see FIGS. 11A, 11C, and 11D). The mask may be removed by etching or the like.

[0341] Next, the oxide film 230D is formed (see FIGS. 12A to 12D). The oxide film 230D can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The oxide film 230D may be formed by the same film formation method as the oxide film 230A or the oxide film 230B according to the characteristics required for the oxide film 230D. In this embodiment, the oxide film 230D is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4.

[0342] When the oxide film 230D is formed, some of the oxygen contained in the sputtering gas may be supplied to the oxide film 230C. Alternatively, when the oxide film 230D is formed, some of the oxygen contained in the sputtering gas may be supplied to the insulator 280. Therefore, the ratio of oxygen contained in the sputtering gas for the oxide film 230D may be 70% or more, preferably 80% or more, and more preferably 100%.

[0343] Next, the insulating film 250A is formed (see FIGS. 12A to 12D). A heat treatment may be performed before the formation of the insulating film 250A, and the heat treatment may be performed under reduced pressure, and the insulating film 250A may be formed continuously without exposure to the atmosphere. The heat treatment is preferably performed in an atmosphere containing oxygen. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 230D can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a, the oxide 230b, the oxide film 230C, and the oxide film 230D can be reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower.

[0344] The insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 250A is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. This allows the hydrogen concentration of the insulating film 250A to be reduced. Since the insulating film 250A becomes the insulator 250 that contacts the oxide 230d in a later process, it is preferable that the hydrogen concentration is reduced in this manner.

[0345] When the insulator 250 has a two-layer laminated structure, it is preferable to continuously deposit the insulating film that will be the lower layer of the insulator 250 and the insulating film that will be the upper layer of the insulator 250 without exposing them to the atmospheric environment. By depositing the films without exposing them to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the insulating film that will be the lower layer of the insulator 250 and the insulating film that will be the upper layer of the insulator 250, and it is possible to keep the vicinity of the interface between the insulating film that will be the lower layer of the insulator 250 and the insulating film that will be the upper layer of the insulator 250 clean.

[0346] Here, after the insulating film 250A is formed, a microwave treatment may be performed under an oxygen-containing atmosphere and reduced pressure. By performing the microwave treatment, an electric field due to microwaves is applied to the insulating film 250A, the oxide film 230D, the oxide film 230C, the oxide 230b, the oxide 230a, etc., and V in the oxide film 230D, the oxide film 230C, the oxide 230b, and the oxide 230a is increased. O H to V O and hydrogen. At this time, some of the hydrogen separated may combine with oxygen to become H2O, which may be removed from the insulating film 250A, the oxide film 230D, the oxide film 230C, the oxide 230b, and the oxide 230a. Also, some of the hydrogen may be gettered to the conductor 242a and the conductor 242b. In this way, by performing microwave processing, the hydrogen concentrations in the insulating film 250A, the oxide film 230D, the oxide film 230C, the oxide 230b, and the oxide 230a can be reduced. Also, the V in the oxide 230a, the oxide 230b, the oxide film 230C, and the oxide film 230D can be reduced. O H to V O V that can exist after splitting into and hydrogen O Oxygen is supplied to V O can be repaired or compensated for.

[0347] Also, a heat treatment may be performed while maintaining the reduced pressure state after the microwave treatment. By performing such a treatment, hydrogen in the insulating film 250A, the oxide film 230D, the oxide film 230C, the oxide 230b, and the oxide 230a can be efficiently removed. Also, some of the hydrogen may be gettered to the conductor 242a and the conductor 242b. Alternatively, a step of performing a heat treatment may be repeated multiple times while maintaining the reduced pressure state after the microwave treatment. By repeatedly performing the heat treatment, hydrogen in the insulating film 250A, the oxide film 230D, the oxide film 230C, the oxide 230b, and the oxide 230a can be more efficiently removed. Note that the heat treatment temperature is preferably 300° C. or more and 500° C. or less.

[0348] Furthermore, by performing microwave processing to modify the film quality of the insulating film 250A, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. Therefore, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. into the oxide 230b, the oxide 230a, etc. through the insulator 250 by a post-process such as film formation of a conductive film that becomes the conductor 260, or a post-treatment such as heat treatment.

[0349] Next, the conductive film 260A and the conductive film 260B are formed in this order (see FIGS. 13A to 13D). The conductive film 260A and the conductive film 260B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, the conductive film 260A is formed by an ALD method, and the conductive film 260B is formed by a CVD method.

[0350] Next, the oxide film 230C, the oxide film 230D, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished by CMP until the insulator 280 is exposed, thereby forming the oxide 230c, the oxide 230d, the insulator 250, and the conductor 260 (the conductor 260a and the conductor 260b) (see FIGS. 14A to 14D). As a result, the oxide 230c is arranged so as to cover the opening that reaches the oxide 230b and a part of the inner wall (side wall and bottom surface) of the groove of the oxide 230b. The oxide 230d is arranged so as to cover the opening and the inner wall of the groove through the oxide 230c. The insulator 250 is arranged so as to cover the opening and the inner wall of the groove through the oxide 230c and the oxide 230d. Moreover, the conductor 260 is arranged so as to fill the opening and the groove via the oxide 230c, the oxide 230d, and the insulator 250.

[0351] Next, heat treatment may be performed. In this embodiment, the treatment is performed in a nitrogen atmosphere at a temperature of 400° C. for 1 hour. The heat treatment can reduce the moisture and hydrogen concentrations in the insulators 250 and 280. Note that after the heat treatment, the insulator 282 may be formed without exposure to the air.

[0352] Next, the insulator 282 is formed over the oxide 230c, the oxide 230d, the insulator 250, the conductor 260, and the insulator 280 (see FIGS. 15B to 15D). The insulator 282 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulator 282, for example, it is preferable to form a film of aluminum oxide by a sputtering method. By forming the insulator 282 in an atmosphere containing oxygen by a sputtering method, oxygen can be added to the insulator 280 while forming the film. At this time, it is preferable to form the insulator 282 while heating the substrate. Moreover, it is preferable to form the insulator 282 in contact with the upper surface of the conductor 260, because this can suppress the oxygen contained in the insulator 280 from being absorbed by the conductor 260 in a subsequent heat treatment.

[0353] Next, a part of the insulator 282, a part of the insulator 280, a part of the insulator 254, a part of the insulator 224, a part of the insulator 222, a part of the insulator 216, a part of the insulator 214, and a part of the insulator 212 are processed to form an opening that reaches the insulator 211 (see FIGS. 16A to 16D). The opening may be formed so as to surround the transistor 200. Alternatively, the opening may be formed so as to surround a plurality of transistors 200. Thus, in the opening, a part of the side surface of the insulator 282, a part of the side surface of the insulator 280, a part of the side surface of the insulator 254, a part of the side surface of the insulator 224, a part of the side surface of the insulator 222, a part of the side surface of the insulator 216, a part of the side surface of the insulator 214, and a part of the side surface of the insulator 212 are exposed.

[0354] A dry etching method or a wet etching method can be used for processing a part of the insulator 282, a part of the insulator 280, a part of the insulator 254, a part of the insulator 224, a part of the insulator 222, a part of the insulator 216, a part of the insulator 214, and a part of the insulator 212. Processing by the dry etching method is suitable for fine processing. Moreover, the processing may be performed under different conditions. In this process, the film thickness of the region of the insulator 211 that overlaps with the opening may become thin.

[0355] Next, an insulating film 287A is formed to cover the insulators 282, 280, 254, 224, 222, 216, 214, and 212 (see FIGS. 17B to 17D). The insulating film 287A is preferably formed under the same conditions as those for the insulator 282. For example, the insulating film 287A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0356] Specifically, the insulating film 287A is preferably an aluminum oxide film formed by, for example, a sputtering method. By forming the insulating film 287A in an oxygen-containing atmosphere using a sputtering method, oxygen can be added to the insulator 280 while the insulating film 287A is being formed. At this time, it is preferable to form the insulating film 287A while heating the substrate. In addition, since the insulator 282 is formed in contact with the upper surface of the conductor 260, it is possible to suppress the oxygen contained in the insulator 280 from being absorbed by the conductor 260 during the film formation process of the insulating film 287A.

[0357] Next, an anisotropic etching process is performed on insulating film 287A to form insulator 287 on the sides of insulator 282, insulator 280, insulator 254, insulator 224, insulator 222, insulator 216, insulator 214 and insulator 212 (see Figures 18B to 18D).

[0358] Here, a side end of insulator 282 contacts the upper end of insulator 287, and a side end of insulator 212 contacts the lower end of insulator 287, thereby forming a structure that seals transistor 200 and insulator 280.

[0359] The anisotropic etching is preferably a dry etching process, which can remove the insulating film formed on a surface approximately parallel to the substrate surface and form the insulator 287 in a self-aligned manner.

[0360] Next, the insulator 283 is formed to cover the insulator 282, the insulator 287, and the insulator 211 (see FIGS. 19B to 19D). The insulator 283 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 283 may be multi-layered. For example, a silicon nitride film may be formed by a sputtering method, and a silicon nitride film may be formed on the silicon nitride by a CVD method. As shown in FIGS. 19B to 19D, the insulator 283 contacts the insulator 211 at the bottom surface of the opening. That is, the upper surface and side surface of the transistor 200 are wrapped by the insulator 283, and the lower surface is wrapped by the insulator 211. In this way, by wrapping the transistor 200 with the insulator 283 and the insulator 211, which have high barrier properties, it is possible to prevent moisture and hydrogen from entering from the outside.

[0361] Next, the insulator 284 may be formed on the insulator 283 (see FIGS. 19B to 19D). Note that the insulator 284 is preferably formed using a film formation method with high film-forming properties. For example, the insulator 284 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Note that the insulator 284 is preferably formed using the same material as the insulators 212 and 283.

[0362] Specifically, a silicon nitride film may be formed by a CVD method. In particular, the insulator 284 may be formed by a CVD method using a compound gas that does not contain hydrogen atoms or that contains a small amount of hydrogen atoms.

[0363] Next, an insulating film to be the insulator 274 is formed on the insulator 284. The insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, a silicon oxide film can be formed by a CVD method. In addition, the insulating film is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed as described above. This allows the hydrogen concentration of the insulating film to be reduced.

[0364] Next, the insulating film that will become the insulator 274 is subjected to CMP processing to form the insulator 274 with a flat upper surface (see FIGS. 19B to 19D).

[0365] Next, heat treatment may be performed. In this embodiment, the treatment is performed in a nitrogen atmosphere at a temperature of 400° C. for one hour. This heat treatment allows oxygen added by the formation of the insulator 282 to diffuse into the insulator 280 and to be further supplied to the oxide 230a and the oxide 230b via the oxide 230c. Note that this heat treatment may be performed not only after the formation of the insulator 274 but also after the formation of the insulator 282 or the insulator 284.

[0366] Next, an opening reaching the conductor 242a and an opening reaching the conductor 242b are formed in the insulators 254, 280, 282, 283, and 284 (see FIGS. 20A and 20B). The openings may be formed by using a lithography method. Note that, although the shape of the opening is circular in top view in FIG. 20A, the shape is not limited to this. For example, the opening may be substantially circular such as an ellipse, polygonal such as a rectangle, or polygonal such as a rectangle with rounded corners in top view.

[0367] Next, an insulating film that will become the insulators 241a and 241b is formed, and the insulating film is anisotropically etched to form the insulators 241a and 241b (see FIGS. 20A and 20B). The insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. It is preferable to use an insulating film that has a function of suppressing oxygen permeation as the insulating film. For example, it is preferable to form an aluminum oxide film by the ALD method. Alternatively, it is preferable to form a silicon nitride film by the PEALD method. Silicon nitride is preferable because it has a high blocking property against hydrogen.

[0368] Moreover, the anisotropic etching of the insulating film that becomes the insulators 241a and 241b may be performed by, for example, dry etching. By providing the insulators 241a and 241b on the side walls of the opening, it is possible to suppress the permeation of oxygen from the outside and prevent the oxidation of the conductors 240a and 240b that will be formed next. It is also possible to prevent impurities such as water and hydrogen from diffusing to the outside from the conductors 240a and 240b.

[0369] Next, a conductive film that becomes the conductor 240a and the conductor 240b is formed. The conductive film is preferably a laminated structure including a conductor that has a function of suppressing the permeation of impurities such as water and hydrogen. For example, it can be a laminated structure of tantalum nitride, titanium nitride, or the like, and tungsten, molybdenum, copper, or the like. The conductive film can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0370] Next, a CMP process is performed to remove parts of the conductive film that will become conductor 240a and conductor 240b, exposing the upper surfaces of insulator 284 and insulator 274. As a result, the conductive film remains only in the openings, forming conductors 240a and 240b with flat upper surfaces (see FIGS. 20A and 20B). Note that the CMP process may remove parts of the upper surfaces of insulator 284 and insulator 274.

[0371] Next, a conductive film that will become the conductor 246a and the conductor 246b is formed. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0372] Next, the conductive film that will become the conductor 246a and the conductor 246b is processed by lithography to form the conductor 246a that contacts the upper surface of the conductor 240a and the conductor 246b that contacts the upper surface of the conductor 240b. At this time, a part of the insulator 284 in the region where the conductor 246a and the conductor 246b do not overlap with the insulator 284 may be removed (see FIGS. 21B to 21D).

[0373] Next, the insulator 286 is formed on the conductor 246a, the conductor 246b, and the insulator 284 (see FIGS. 4A to 4D). The insulator 286 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 286 may also be multi-layered. For example, a silicon nitride film may be formed by a sputtering method, and a silicon nitride film may be formed on the silicon nitride by a CVD method.

[0374] Through the above steps, a semiconductor device including the transistor 200 illustrated in Figures 4A to 4D can be manufactured. As illustrated in Figures 5 to 21, the transistor 200 can be manufactured by using the method for manufacturing a semiconductor device described in this embodiment. Note that when a semiconductor device including the transistor 200 illustrated in Figures 1A to 1D is manufactured, the semiconductor device may be manufactured without performing the steps illustrated in Figures 16 to 18.

[0375] <Applications of semiconductor devices> 22A and 22B, an example of a semiconductor device including a transistor 200 according to one embodiment of the present invention, which is different from those described in the above <Structural Example of Semiconductor Device> and the above <Modification of Semiconductor Device>, will be described below. Note that in the semiconductor device shown in FIG. 22A and FIG. 22B, structures having the same functions as those of the semiconductor device shown in <Modification of Semiconductor Device> (see FIG. 4A to FIG. 4D) are denoted by the same reference numerals. Note that in this section, the materials described in detail in the <Structural Example of Semiconductor Device> and <Modification of Semiconductor Device> can be used as the materials for forming the transistor 200.

[0376] 22A and 22B show a configuration in which multiple transistors (transistors 200_1 to 200_n) are encapsulated with an insulator 283 and an insulator 211. Note that although the multiple transistors appear to be aligned in the channel length direction in FIGS. 22A and 22B, this is not the only possible arrangement. The multiple transistors may be aligned in the channel width direction or may be arranged in a matrix. Furthermore, the transistors may be arranged without any regularity depending on the design.

[0377] 22A, a portion where the insulator 283 and the insulator 211 are in contact with each other (hereinafter, may be referred to as a sealing portion 265) is formed outside the plurality of transistors (transistors 200_1 to 200_n). The sealing portion 265 is formed so as to surround the plurality of transistors (also referred to as a transistor group). With this structure, the plurality of transistors can be enclosed by the insulator 283 and the insulator 211. Thus, a plurality of transistor groups surrounded by the sealing portion 265 are provided on the substrate.

[0378] Also, dicing lines (which may be called scribe lines, division lines, or cutting lines) may be provided overlapping the sealing portion 265. Since the substrate is divided along the dicing lines, a group of transistors surrounded by the sealing portion 265 is taken out as one chip.

[0379] 22A shows an example in which multiple transistors (transistors 200_1 to 200_n) are surrounded by one sealing portion 265, but the present invention is not limited to this. As shown in FIG 22B, multiple transistors may be surrounded by multiple sealing portions. In FIG 22B, multiple transistors are surrounded by a sealing portion 265a and further surrounded by an outer sealing portion 265b.

[0380] In this manner, by using a configuration in which a plurality of transistors (transistors 200_1 to 200_n) are surrounded by a plurality of sealing portions, the contact area between the insulator 283 and the insulator 212 increases, thereby improving the adhesion between the insulator 283 and the insulator 212. This makes it possible to more reliably seal the plurality of transistors.

[0381] In this case, a dicing line may be provided so as to overlap sealing portion 265a or sealing portion 265b, or a dicing line may be provided between sealing portion 265a and sealing portion 265b.

[0382] According to one embodiment of the present invention, a semiconductor device with little variation in transistor characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0383] The structures, methods, and the like described in this embodiment can be used in appropriate combination with the structures, methods, and the like described in other embodiments.

[0384] (Embodiment 2) In this embodiment, one mode of a semiconductor device will be described with reference to FIGS.

[0385] [Storage device 1] 23 illustrates an example of a semiconductor device (memory device) according to one embodiment of the present invention. In the semiconductor device of one embodiment of the present invention, a transistor 200 is provided above a transistor 300, and a capacitor 100 is provided above the transistors 300 and 200. Note that the transistor 200 described in the above embodiment can be used as the transistor 200.

[0386] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the off-state current of the transistor 200 is small, stored data can be retained for a long time by using the transistor 200 in a memory device. In other words, a refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the memory device can be sufficiently reduced.

[0387] 23, a wiring 1001 is electrically connected to a source of a transistor 300, and a wiring 1002 is electrically connected to a drain of the transistor 300. A wiring 1003 is electrically connected to one of a source and a drain of the transistor 200, a wiring 1004 is electrically connected to a first gate of the transistor 200, and a wiring 1006 is electrically connected to a second gate of the transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one electrode of the capacitor 100, and a wiring 1005 is electrically connected to the other electrode of the capacitor 100.

[0388] Moreover, the memory device shown in FIG. 23 can be arranged in a matrix to form a memory cell array.

[0389] <Transistor 300> The transistor 300 is provided on a substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 formed of a part of the substrate 311, and a low-resistance region 314a and a low-resistance region 314b functioning as a source region or a drain region. The transistor 300 may be either a p-channel type or an n-channel type.

[0390] Here, in the transistor 300 shown in FIG. 23, a semiconductor region 313 (a part of a substrate 311) in which a channel is formed has a convex shape. A conductor 316 is provided so as to cover the side and top surface of the semiconductor region 313 via an insulator 315. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN type transistor because it uses a convex portion of a semiconductor substrate. Note that an insulator that contacts the upper portion of the convex portion and functions as a mask for forming the convex portion may be provided. Note that, although a case where a convex portion is formed by processing a part of a semiconductor substrate has been shown here, a semiconductor film having a convex shape may be formed by processing an SOI substrate.

[0391] Note that the transistor 300 illustrated in FIG. 23 is just an example, and the present invention is not limited to this structure. An appropriate transistor may be used depending on the circuit configuration and driving method.

[0392] <Capacitive element 100> The capacitor 100 is provided above the transistor 200. The capacitor 100 includes a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric. Here, the insulator 130 is preferably an insulator that can be used as the insulator 286 described in the above embodiment.

[0393] For example, the conductor 112 over the conductor 240 and the conductor 110 can be formed at the same time. Note that the conductor 112 functions as a plug or a wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300.

[0394] 23, the conductor 112 and the conductor 110 are shown as having a single-layer structure, but are not limited to this structure and may have a stacked structure of two or more layers. For example, a conductor having barrier properties and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having barrier properties and a conductor having high conductivity.

[0395] The insulator 130 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like, and can be provided as a stacked layer or a single layer.

[0396] For example, it is preferable to use a laminated structure of a material with high dielectric strength, such as silicon oxynitride, and a high dielectric constant (high-k) material for the insulator 130. With this configuration, the capacitance element 100 can ensure sufficient capacitance by having an insulator with high dielectric constant (high-k), and the capacitance element 100 can have improved dielectric strength by having an insulator with high dielectric strength, thereby suppressing electrostatic breakdown of the capacitance element 100.

[0397] Examples of high dielectric constant (high-k) materials (materials with a high relative dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0398] On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide or resin with voids, etc.

[0399] <Wiring layer> Between each structure, a wiring layer having an interlayer film, wiring, plugs, etc. may be provided. Also, a plurality of wiring layers may be provided according to the design. Here, a conductor having a function as a plug or wiring may be collectively given the same symbol as a plurality of structures. Also, in this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0400] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 300. A conductor 328, a conductor 330, and the like that are electrically connected to the capacitor 100 or the transistor 200 are embedded in the insulator 320, the insulator 322, the insulator 324, and the insulator 326. The conductor 328 and the conductor 330 function as plugs or wirings.

[0401] The insulator functioning as an interlayer film may also function as a planarizing film that covers the uneven shape underneath. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0402] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Fig. 23, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. Furthermore, a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring.

[0403] Similarly, a conductor 218, a conductor constituting the transistor 200 (conductor 205), and the like are embedded in the insulators 210, 211, 212, 214, and 216. Note that the conductor 218 functions as a plug or wiring electrically connected to the capacitor 100 or the transistor 300. Furthermore, an insulator 150 is provided over the conductor 120 and the insulator 130.

[0404] Here, similarly to the insulator 241a and the insulator 241b shown in the above embodiment, the insulator 217 is provided in contact with the side surface of the conductor 218 functioning as a plug. The insulator 217 is provided in contact with the inner wall of the opening formed in the insulators 210, 211, 212, 214, and 216. That is, the insulator 217 is provided between the conductor 218 and the insulators 210, 211, 212, 214, and 216. Note that the conductor 205 can be formed in parallel with the conductor 218, and therefore the insulator 217 may be formed in contact with the side surface of the conductor 205.

[0405] As the insulator 217, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide may be used. Since the insulator 217 is provided in contact with the insulators 211, 212, 214, and 222, it is possible to prevent impurities such as water or hydrogen from the insulator 210 or the insulator 216 from being mixed into the oxide 230 through the conductor 218. In particular, silicon nitride is preferable because it has a high blocking property against hydrogen. In addition, it is possible to prevent oxygen contained in the insulator 210 or the insulator 216 from being absorbed by the conductor 218.

[0406] The insulator 217 can be formed by a method similar to that of the insulators 241a and 241b. For example, a silicon nitride film is formed by a PEALD method, and an opening reaching the conductor 356 is formed by anisotropic etching.

[0407] Examples of insulators that can be used as the interlayer film include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0408] For example, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, the parasitic capacitance generated between wirings can be reduced. Therefore, it is advisable to select a material according to the function of the insulator.

[0409] For example, the insulator 150, the insulator 210, the insulator 352, the insulator 354, etc. preferably have an insulator with a low relative dielectric constant. For example, the insulator preferably has silicon oxynitride, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having voids, or resin. Alternatively, the insulator preferably has a laminated structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen has been added, or silicon oxide having voids, and resin. Silicon oxide and silicon oxynitride are thermally stable, and therefore can be combined with a resin to form a laminated structure that is thermally stable and has a low relative dielectric constant. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic.

[0410] Furthermore, when a transistor using an oxide semiconductor is surrounded by an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. Therefore, the insulators 214, 211, 212, and 350 can be made of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen.

[0411] As an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer. Specifically, as an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, silicon nitride oxide, or silicon nitride may be used.

[0412] Conductors that can be used for wiring and plugs include materials containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Also, semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may be used.

[0413] For example, the conductor 328, the conductor 330, the conductor 356, the conductor 218, the conductor 112, etc. can be formed of a single layer or a stack of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above materials. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. Alternatively, it is preferable to form them from a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, the wiring resistance can be reduced.

[0414] <Wiring or plug of layer provided with oxide semiconductor> Note that when an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided near the oxide semiconductor. In that case, an insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and a conductor provided in the insulator having the excess oxygen region.

[0415] 23, for example, an insulator 241 may be provided between the insulator 224 and the insulator 280 having excess oxygen and the conductor 240. By providing the insulator 241 in contact with the insulator 222, the insulator 282, the insulator 283, and the insulator 284, the insulator 224 and the transistor 200 can be sealed with an insulator having barrier properties.

[0416] In other words, the insulator 241 can prevent excess oxygen contained in the insulator 224 and the insulator 280 from being absorbed by the conductor 240. Furthermore, the insulator 241 can prevent hydrogen, which is an impurity, from diffusing into the transistor 200 through the conductor 240.

[0417] As the insulator 241, an insulating material having a function of suppressing the diffusion of impurities such as water or hydrogen, and oxygen, may be used. For example, it is preferable to use silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide. In particular, silicon nitride is preferable because it has a high blocking property against hydrogen. In addition, other metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide may be used.

[0418] As in the above embodiment, the transistor 200 is preferably sealed with the insulators 211, 212, 214, 287, 282, 283, and 284. Such a structure can reduce the intrusion of hydrogen contained in the insulators 274, 150, and the like into the insulator 280 and the like.

[0419] Here, the conductor 240 penetrates the insulators 284, 283, and 282, and the conductor 218 penetrates the insulators 214, 212, and 211, but as described above, the insulator 241 is provided in contact with the conductor 240, and the insulator 217 is provided in contact with the conductor 218. This makes it possible to reduce hydrogen that is mixed into the inside of the insulators 211, 212, 214, 287, 282, 283, and 284 through the conductors 240 and 218. In this way, the transistor 200 can be more reliably sealed with the insulators 211, 212, 214, 287, 282, 283, 284, 241, and 217, and it is possible to reduce impurities such as hydrogen contained in the insulators 274 and the like from the outside.

[0420] Furthermore, as described in the above embodiment, the insulators 216, 224, 280, 250, and 274 are preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed, thereby reducing the hydrogen concentrations in the insulators 216, 224, 280, 250, and 274.

[0421] In this manner, the hydrogen concentration in the silicon-based insulating film in the vicinity of the transistor 200 can be reduced, and the hydrogen concentration in the oxide 230 can be reduced.

[0422] <Dicing line> In the following, a dicing line (sometimes called a scribe line, a dividing line, or a cutting line) that is provided when a large-area substrate is divided into individual semiconductor elements to extract multiple semiconductor devices in chip form will be described. As a dividing method, for example, first, grooves (dicing lines) for dividing the semiconductor elements are formed in the substrate, and then the substrate is cut along the dicing lines to divide (split) the substrate into multiple semiconductor devices.

[0423] 23, for example, it is preferable to design the region where the insulator 283 and the insulator 211 contact each other so as to overlap the dicing line. That is, openings are provided in the insulators 282, 280, 254, 224, 222, 216, 214, and 212 near the region that will become the dicing line provided on the outer edge of the memory cell having the multiple transistors 200.

[0424] That is, the insulator 211 and the insulator 283 are in contact with each other through the openings provided in the insulators 282, 280, 254, 224, 222, 216, 214, and 212. Also, openings may be provided in the insulators 282, 280, 254, 224, 222, 216, and 214, and the insulators 212 and 283 may be in contact with each other. For example, the insulators 212 and 283 may be formed using the same material and the same method. By providing the insulators 212 and 283 using the same material and the same method, the adhesion can be improved. For example, it is preferable to use silicon nitride.

[0425] With this structure, the transistor 200 can be surrounded by the insulator 211, the insulator 212, the insulator 214, the insulator 287, the insulator 282, the insulator 283, and the insulator 284. At least one of the insulators 211, 212, 214, the insulator 287, the insulator 282, the insulator 283, and the insulator 284 has a function of suppressing diffusion of oxygen, hydrogen, and water. Therefore, even if the substrate is divided into a plurality of chips by dividing the substrate into each circuit region in which the semiconductor element shown in this embodiment is formed, impurities such as hydrogen or water can be prevented from entering from the side direction of the divided substrate and diffusing into the transistor 200.

[0426] This structure can prevent excess oxygen in the insulator 280 and the insulator 224 from diffusing to the outside. Therefore, the excess oxygen in the insulator 280 and the insulator 224 is efficiently supplied to the oxide in which a channel is formed in the transistor 200. The oxygen can reduce oxygen vacancies in the oxide in which a channel is formed in the transistor 200. As a result, the oxide in which a channel is formed in the transistor 200 can be an oxide semiconductor with low density of defect states and stable characteristics. That is, fluctuations in the electrical characteristics of the transistor 200 can be suppressed and reliability can be improved.

[0427] In the memory device shown in Fig. 23, the shape of the capacitor 100 is a planar type, but the memory device shown in this embodiment is not limited to this. For example, the shape of the capacitor 100 may be a cylindrical type as shown in Fig. 24. In the memory device shown in Fig. 24, the configuration below the insulator 150 is similar to that of the semiconductor device shown in Fig. 23.

[0428] 24 includes an insulator 150 on an insulator 130, an insulator 142 on the insulator 150, a conductor 115 disposed in an opening formed in the insulator 150 and the insulator 142, an insulator 145 on the conductor 115 and the insulator 142, a conductor 125 on the insulator 145, and an insulator 152 on the conductor 125 and the insulator 145. Here, at least a portion of the conductor 115, the insulator 145, and the conductor 125 are disposed in the opening formed in the insulator 150 and the insulator 142.

[0429] The conductor 115 functions as the lower electrode of the capacitance element 100, the conductor 125 functions as the upper electrode of the capacitance element 100, and the insulator 145 functions as the dielectric of the capacitance element 100. The capacitance element 100 has a configuration in which the upper electrode and the lower electrode face each other across the dielectric not only on the bottom surface but also on the side surface in the openings of the insulators 150 and 142, and the capacitance per unit area can be increased. Therefore, the deeper the opening is, the larger the capacitance of the capacitance element 100 can be. Increasing the capacitance per unit area of ​​the capacitance element 100 in this way can promote miniaturization or high integration of semiconductor devices.

[0430] The insulator 152 may be made of an insulator that can be used for the insulator 280. The insulator 142 preferably functions as an etching stopper when forming an opening in the insulator 150, and may be made of an insulator that can be used for the insulator 214.

[0431] The shape of the openings formed in the insulator 150 and the insulator 142 when viewed from above may be a rectangle, a polygon other than a rectangle, a polygon with curved corners, or a circle including an ellipse. Here, it is preferable that the area of ​​the opening overlapping with the transistor 200 is large when viewed from above. With such a configuration, the occupation area of ​​a semiconductor device including the capacitor 100 and the transistor 200 can be reduced.

[0432] The conductor 115 is disposed in contact with the insulator 142 and an opening formed in the insulator 150. The upper surface of the conductor 115 preferably approximately coincides with the upper surface of the insulator 142. The lower surface of the conductor 115 is in contact with the conductor 110 through the opening of the insulator 130. The conductor 115 is preferably formed by an ALD method, a CVD method, or the like, and may be, for example, a conductor that can be used for the conductor 205.

[0433] The insulator 145 is disposed so as to cover the conductor 115 and the insulator 142. For example, the insulator 145 is preferably formed by an ALD method, a CVD method, or the like. The insulator 145 may be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like, and can be provided as a stacked layer or a single layer. For example, the insulator 145 can be an insulating film stacked in this order of zirconium oxide, aluminum oxide, and zirconium oxide.

[0434] Moreover, it is preferable to use a material with high dielectric strength, such as silicon oxynitride, or a high dielectric constant (high-k) material for the insulator 145. Alternatively, a laminated structure of a material with high dielectric strength and a material with high dielectric constant (high-k) may be used.

[0435] Examples of high-dielectric constant (high-k) materials (materials with a high relative dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium. By using such high-k materials, the capacitance of the capacitance element 100 can be sufficiently secured even if the insulator 145 is made thick. By making the insulator 145 thick, the leakage current occurring between the conductor 115 and the conductor 125 can be suppressed.

[0436] On the other hand, materials with high dielectric strength include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, resin, etc. For example, an insulating film formed in the order of silicon nitride formed by the ALD method, silicon oxide formed by the PEALD method, and silicon nitride formed by the ALD method can be used. By using such an insulator with high dielectric strength, the dielectric strength is improved and electrostatic breakdown of the capacitance element 100 can be suppressed.

[0437] The conductor 125 is disposed so as to fill the openings formed in the insulator 142 and the insulator 150. The conductor 125 is electrically connected to the wiring 1005 via the conductor 140 and the conductor 153. The conductor 125 is preferably formed by an ALD method, a CVD method, or the like, and may be formed using a conductor that can be used for the conductor 205, for example.

[0438] The conductor 153 is provided over the insulator 154 and is covered with the insulator 156. The conductor 153 may be any conductor that can be used for the conductor 112, and the insulator 156 may be any insulator that can be used for the insulator 152. Here, the conductor 153 is in contact with the top surface of the conductor 140 and functions as a terminal of the capacitor 100, the transistor 200, or the transistor 300.

[0439] The structures, methods, and the like described in this embodiment can be used in appropriate combination with the structures, methods, and the like described in other embodiments.

[0440] (Embodiment 3) <Modifications of the semiconductor device> In this embodiment, an example of a semiconductor device which is one embodiment of the present invention will be described with reference to FIGS. 25A to 25D.

[0441] Fig. 25A shows a top view of a semiconductor device according to one embodiment of the present invention. Figs. 25B to 25D are cross-sectional views of the semiconductor device. Fig. 25B is a cross-sectional view corresponding to a portion indicated by a dashed line A1-A2 in Fig. 25A. Fig. 25C is a cross-sectional view corresponding to a portion indicated by a dashed line A3-A4 in Fig. 25A. Fig. 25D is a cross-sectional view corresponding to a portion indicated by a dashed line A5-A6 in Fig. 25A. Note that some elements are omitted from the top view of Fig. 25A for clarity.

[0442] 25A to 25D, structures having the same functions as those of the structures constituting the semiconductor device shown in the previous embodiment are denoted by the same reference numerals. Note that, in this section, the materials described in detail in the previous embodiment can be used as the materials constituting the semiconductor device.

[0443] <<Modification 2 of Semiconductor Device>> The semiconductor device shown in Figures 25A to 25D is a modified example of the semiconductor device shown in Figures 4A to 4D. The semiconductor device shown in Figures 25A to 25D differs from the semiconductor device shown in Figures 4A to 4D in that it does not have insulator 211 and insulator 287.

[0444] At least a part of the structure constituting the transistor 200 shown in Figures 25A to 25D and a part of the structure provided around the transistor 200 are preferably formed by a sputtering method. For example, the insulator 212, the insulator 214, the insulator 216, the oxide film to be the oxide 230a, the oxide film to be the oxide 230b, the oxide film to be the oxide 243a and the oxide 243b, the insulator 254, the insulating film to be the insulator 280, the oxide film to be the oxide 230c, the oxide film to be the oxide 230d, the insulator 282, the insulator 283, and the like may be formed by a sputtering method. A film formed by a sputtering method is preferable because it has a low hydrogen concentration in the film. Therefore, the transistor 200 with a low hydrogen concentration can be manufactured.

[0445] In addition, the insulating films that become insulator 222, insulator 224, and insulator 250, insulator 284, insulator 274, the conductive films that become conductor 242a and conductor 242b, and the conductive films that become conductor 260 (conductor 260a and conductor 260b) may also be formed using a sputtering method.

[0446] With the above structure, the transistor 200 with a low hydrogen concentration can be manufactured without providing the insulator 287 formed using a material capable of trapping and fixing hydrogen. Furthermore, the number of steps for reducing the hydrogen concentration in the film, such as heat treatment, can be reduced, and the manufacturing time of the semiconductor device can be shortened.

[0447] It is preferable to deposit the insulators 212, 214, and 216 in succession without exposing them to the atmospheric environment. Depositing the films without exposing them to the atmosphere is preferable because it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the insulators 212, 214, and 216, and it is possible to keep the interface and the vicinity of the interface between the insulators 212 and 214, and the interface and the vicinity of the interface between the insulators 214 and 216 clean.

[0448] In addition, it is preferable to continuously form the oxide film that becomes the oxide 230a, the oxide film that becomes the oxide 230b, and the oxide film that becomes the oxide 243a and the oxide 243b without exposing them to the air environment. By forming the films without exposing them to the air, it is possible to prevent impurities or moisture from the air environment from adhering to the oxide film that becomes the oxide 230a, the oxide film that becomes the oxide 230b, and the oxide film that becomes the oxide 243a and the oxide 243b, and it is preferable to keep the interface and the vicinity of the interface between the oxide film that becomes the oxide 230a and the oxide film that becomes the oxide 230b, and the interface and the vicinity of the interface between the oxide film that becomes the oxide 230b and the oxide film that becomes the oxide 243a and the oxide 243b clean.

[0449] Moreover, it is preferable to deposit the insulating film that will become the insulator 254 and the insulating film that will become the insulator 280 in succession without exposing them to the atmospheric environment. Depositing the films without exposing them to the atmospheric environment can prevent impurities or moisture from the atmospheric environment from adhering onto the insulator 254 and the insulating film that will become the insulator 280, and is preferable because it can keep the interface and the vicinity of the interface between the insulator 254 and the insulating film that will become the insulator 280 clean.

[0450] The successive deposition may be performed using, for example, a multi-chamber deposition apparatus. The successive deposition is preferable because it makes it possible to reduce the manufacturing process time of a semiconductor device. The apparatus capable of successive deposition will be described later.

[0451] For example, it is preferable to use silicon nitride or the like as the insulators 212 and 283, and aluminum oxide or the like as the insulators 214 and 282. This can suppress impurities such as water and hydrogen from diffusing from the substrate side to the transistor 200 side through the insulators 212 and 214. Alternatively, it is possible to suppress oxygen contained in the insulators 224 and the like from diffusing to the substrate side through the insulators 212 and 214. It is also possible to suppress impurities such as water and hydrogen from entering the transistor 200 from the outside through the insulators 282 and 283. In this way, it is preferable to have a structure in which the transistor 200 is surrounded by the insulators 212, 214, 282, and 283, which have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0452] The above structure can reduce the hydrogen concentration in the transistor 200. For example, the hydrogen concentration in the transistor 200 measured by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3Specifically, the region is included in the insulator 224, the oxide 230a, the oxide 230c, etc. In other words, at least one of the insulator 224, the oxide 230a, the oxide 230b, and the oxide 230c has a hydrogen concentration obtained by SIMS of less than 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 Note that the region is not limited to the transistor 200, and may be included in a structure provided in the periphery of the transistor 200. An example of a structure provided in the periphery of the transistor 200 is the insulator 280.

[0453] 25A to 25D do not show the layers 244a and 244b shown in FIGS. 4A to 4D. Depending on the method for removing the layer 244A shown in the previous embodiment, the layers 244a and 244b may not be observed by a cross-sectional TEM or the like.

[0454] The layers 244a and 244b may be detected using EDX. For example, a region is detected in which the concentration of the main components (excluding oxygen) of the layers 244a and 244b obtained by elemental analysis using EDX is equal to or higher than the detection limit and equal to or lower than 1.0 atomic % on the side surface of the oxide 230b in the region overlapping with the conductor 242a and the conductor 242b. Alternatively, the concentration of the main components (excluding oxygen) of the layers 244a and 244b on the side surface of the oxide 230b in the region overlapping with the conductor 242a and the conductor 242b is higher than the concentration of the main components (excluding oxygen) of the layers 244a and 244b on the upper surface of the insulator 224 in the region not overlapping with the oxide 230b.

[0455] The structures, methods, and the like described in this embodiment can be used in appropriate combination with the structures, methods, and the like described in other embodiments.

[0456] (Embodiment 4) In this embodiment mode, one mode of a semiconductor device will be described with reference to FIGS.

[0457] [Storage device 2] An example of a semiconductor device (memory device) according to one embodiment of the present invention is illustrated in FIG.

[0458] <Memory device configuration example> Fig. 26 is a cross-sectional view of a semiconductor device having a memory device 290. The memory device 290 shown in Fig. 26 includes a capacitor device 292 in addition to the transistor 200 shown in Fig. 25A to Fig. 25D. Fig. 26 corresponds to a cross-sectional view of the transistor 200 in the channel length direction.

[0459] 26, structures having the same functions as those of the structures constituting the semiconductor device shown in the previous embodiment are denoted by the same reference numerals. Also in this section, the materials described in detail in the previous embodiment can be used as the materials constituting the semiconductor device.

[0460] The capacitance device 292 has a conductor 242b, an insulator 293 provided on the conductor 242b, and a conductor 294 provided on the insulator 293. That is, the capacitance device 292 configures a MIM (Metal-Insulator-Metal) capacitance. Note that one of a pair of electrodes of the capacitance device 292, that is, the conductor 242b, can also serve as a source electrode or a drain electrode of a transistor. Therefore, a part of the manufacturing process of the transistor can be used in the manufacturing process of the capacitance device 292, so that a semiconductor device with high productivity can be obtained. In addition, it is possible to reduce the area in which the transistor and the capacitance device are arranged.

[0461] The conductor 294 may be made of, for example, a material that can be used for the conductors 240a and 240b.

[0462] The insulator 293 may have a stacked structure of, for example, zirconium oxide, aluminum oxide, and zirconium oxide. For example, any material that can be used for the insulator 130 may be used for the insulator 293, and may be provided as a stacked layer or a single layer.

[0463] 26, an insulator 284 and an insulator 160 are stacked in this order as an interlayer film over the transistor 200 and the capacitor device 292. A conductor 166 electrically connected to the transistor 200 is embedded in the insulator 283, the insulator 284, and the insulator 160. The conductor 166 functions as a plug or a wiring.

[0464] A wiring layer may be provided on the insulator 160 and the conductor 166. For example, in Fig. 26, the insulator 162 and the insulator 164 are laminated in this order. Furthermore, the conductor 168 is formed on the insulator 162 and the insulator 164. The conductor 168 functions as a plug or a wiring.

[0465] It is preferable that the insulator 160 and the insulator 164 have a low relative dielectric constant. For example, the insulator 160 and the insulator 164 may be an insulator that can be used for the insulator 352, etc.

[0466] An insulator having a function of suppressing permeation of oxygen and impurities such as hydrogen may be used as the insulator 162. For example, an insulator that can be used for the insulator 350, etc. may be used as the insulator 162.

[0467] The memory devices 290 may be stacked. Fig. 27 shows a cross-sectional view of a configuration in which five memory devices 290 are stacked. As shown in Fig. 27, the memory devices 290 are electrically connected to each other via the conductors 240 and 166.

[0468] As shown in FIG. 27, a plurality of memory devices (memory devices 290_1 to 290_5) may be encapsulated and sealed with the insulator 283 and the insulator 212. Encapsulating and sealing a plurality of memory devices can simplify the process. By forming a part of the structure constituting the transistor 200 and a part of the structure provided around the transistor 200 by a sputtering method, the hydrogen concentration of the transistor 200 can be reduced. Thus, even when a different transistor 200 is formed above the transistor 200, the hydrogen concentration of the transistor 200 located below can be kept low. Therefore, when the memory devices 290 are stacked, the hydrogen concentration in the transistor 200 can be reduced by encapsulating and sealing a plurality of memory devices without sealing each memory device 290 individually.

[0469] The sealing of the multiple memory devices with the insulators 283 and 212 may be performed to comprehensively seal all of the multiple memory devices, or may be performed to comprehensively seal each of the multiple memory devices.

[0470] The memory devices may be arranged in the channel length direction, in the channel width direction, or in a matrix. They may also be arranged without any regularity depending on the design.

[0471] Furthermore, when the same material is used for the insulators 214 and 282, it is not necessary to provide either the insulator 214 or the insulator 282. This can reduce the number of steps.

[0472] 27, by stacking a plurality of memory devices (memory devices 290_1 to 290_5), the memory devices can be integrated and arranged without increasing the area occupied by the memory devices. In other words, a 3D memory device can be configured.

[0473] In addition, although the configuration in which each layer has one memory device is illustrated in Fig. 27, the present invention is not limited to this. As shown in the above <Application Example of Semiconductor Device>, each layer may include a plurality of memory devices, and the plurality of memory devices may be arranged in the channel length direction, in the channel width direction, or in a matrix. Also, they may be arranged without any regularity depending on the design.

[0474] <Modifications of memory device> 28A, 28B, and 29, an example of a semiconductor device including a transistor 200 according to one embodiment of the present invention and a capacitor device 292, which is different from those shown in the above <Configuration Example of Memory Device>, will be described below. Note that in the semiconductor device shown in FIG. 28A, 28B, and 29, structures having the same functions as those of the semiconductor device shown in the above embodiment and FIG. 26 are denoted by the same reference numerals. Note that in this section, the transistor 200 and the capacitor device 292 can be made of materials described in detail in the above embodiment and <Configuration Example of Memory Device>.

[0475] <<Memory Device Variation 1>> 28A and 28B, an example of a semiconductor device including a memory device 600 will be described. The memory device 600 includes a transistor 200a, a transistor 200b, a capacitance device 292a, and a capacitance device 292b.

[0476] Fig. 28A is a top view of a semiconductor device having a memory device 600. Fig. 28B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in Fig. 28A, and is also a cross-sectional view in the channel length direction of transistors 200a and 200b. Note that some elements are omitted from the top view of Fig. 28A for clarity.

[0477] As shown in FIG. 28B, the memory device 600 has a linear symmetrical configuration with the dashed line A3-A4 as the axis of symmetry. One of the source electrode or drain electrode of the transistor 200a and one of the source electrode or drain electrode of the transistor 200b are both configured as the conductor 242c. In addition, the conductor electrically connected to the transistor 200a and functioning as a plug and the conductor electrically connected to the transistor 200b and functioning as a plug are both configured as the conductor 240c. In this way, by configuring the two transistors, the two capacitance devices, and the connections between the wiring and the plugs as described above, a semiconductor device that can be miniaturized or highly integrated can be provided.

[0478] The configuration examples of the semiconductor device illustrated in FIGS. 25A to 25D and 26 can be referred to for the configurations and effects of the transistor 200a, the transistor 200b, the capacitor device 292a, and the capacitor device 292b.

[0479] <<Memory Device Modification 2>> FIG. 29 shows an example in which a memory unit 470 includes a transistor layer 413 including a transistor 200T and four memory device layers (memory device layers 415_1 to 415_4).

[0480] Each of the memory device layers 415_1 to 415_4 includes a plurality of memory devices 420. For the memory devices 420, for example, the memory device 290 shown in Fig. 26 or the memory device 600 shown in Fig. 28A and Fig. 28B can be used.

[0481] Memory device 420 is electrically connected to memory device 420 in a different memory device layer and transistor 200T in transistor layer 413 via conductor 424 and conductor 166.

[0482] The memory unit 470 is sealed by the insulator 212, the insulator 214, the insulator 282, and the insulator 283 (hereinafter, for convenience, this is referred to as a sealing structure). The insulator 274 is provided around the insulator 283. Furthermore, the conductor 440 is provided on the insulator 274, the insulator 283, and the insulator 212, and is electrically connected to the element layer 411.

[0483] Note that the insulators 212 and 283 are preferably made of a material having a high blocking property against hydrogen, and the insulators 214 and 282 are preferably made of a material having a function of capturing or fixing hydrogen.

[0484] For example, the material having a high blocking property against hydrogen includes silicon nitride, silicon oxynitride, etc. Furthermore, the material having a function of capturing or fixing hydrogen includes aluminum oxide, hafnium oxide, and oxide containing aluminum and hafnium (hafnium aluminate), etc.

[0485] Note that the crystal structure of the materials used for the insulators 212, 214, 282, and 283 is not particularly limited, and may be an amorphous or crystalline structure. For example, an amorphous aluminum oxide film is preferably used as a material having a function of trapping or fixing hydrogen. Amorphous aluminum oxide may trap and fix a larger amount of hydrogen than aluminum oxide with high crystallinity.

[0486] Further, an insulator 280 is provided inside the sealing structure. The insulator 280 has a function of releasing oxygen when heated. Alternatively, the insulator 280 has an excess oxygen region.

[0487] Here, the following model can be considered for the diffusion of excess oxygen in the insulator 280 and hydrogen in the oxide semiconductor in contact with the insulator 280.

[0488] Hydrogen present in the oxide semiconductor diffuses to other structures through the insulator 280 in contact with the oxide semiconductor. The hydrogen diffuses in the insulator 280 as follows: excess oxygen in the insulator 280 reacts with hydrogen in the oxide semiconductor to form an OH bond, and the hydrogen diffuses through the insulator 280. When the hydrogen atom having the OH bond reaches a material (typically the insulator 282) having a function of capturing or fixing hydrogen, the hydrogen atom reacts with an oxygen atom bonded to an atom (e.g., a metal atom) in the insulator 282, and is captured or fixed in the insulator 282. On the other hand, the oxygen atom having the OH bond is presumed to remain in the insulator 280 as excess oxygen. That is, there is a high probability that the excess oxygen in the insulator 280 plays a bridging role in the diffusion of the hydrogen.

[0489] In order to satisfy the above model, the manufacturing process of the semiconductor device is one of the important factors.

[0490] As an example, the insulator 280 containing excess oxygen is formed in an oxide semiconductor, and then the insulator 282 is formed. After that, heat treatment is preferably performed. Specifically, the heat treatment is performed in an atmosphere containing oxygen, an atmosphere containing nitrogen, or an atmosphere containing a mixture of oxygen and nitrogen at a temperature of 350° C. or higher, preferably 400° C. or higher. The heat treatment time is 1 hour or longer, preferably 4 hours or longer, and more preferably 8 hours or longer.

[0491] By the above heat treatment, hydrogen in the oxide semiconductor can diffuse outward through the insulator 280 and the insulator 282. That is, the absolute amount of hydrogen present in the oxide semiconductor and in the vicinity of the oxide semiconductor can be reduced.

[0492] After the heat treatment, the insulator 283 is formed. The insulator 283 is a material having a high blocking property against hydrogen, and therefore can prevent hydrogen diffused to the outside or hydrogen present on the outside from entering the inside, specifically, the oxide semiconductor or the insulator 280 side.

[0493] Note that the above heat treatment is performed after the insulator 282 is formed, but is not limited thereto. For example, the heat treatment may be performed after the transistor layer 413 is formed or after the memory device layers 415_1 to 415_3 are formed. When hydrogen is diffused outward by the heat treatment, hydrogen is diffused upward or laterally of the transistor layer 413. Similarly, when the heat treatment is performed after the memory device layers 415_1 to 415_3 are formed, hydrogen is diffused upward or laterally.

[0494] By using the above manufacturing process, the insulator 212 and the insulator 283 are bonded to each other, thereby forming the above-described sealing structure.

[0495] As described above, by using the above structure and manufacturing process, a semiconductor device including an oxide semiconductor with a reduced hydrogen concentration can be provided. For example, the oxide 230b or the oxide 230c included in the transistor 200T or the memory device 420 has a hydrogen concentration of 1×10 or less by SIMS. 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 has an area that is less than

[0496] According to the above, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device with excellent electrical characteristics can be provided.

[0497] The structure, the method, and the like described in this embodiment can be used in appropriate combination with the structure, the method, and the like described in other embodiments.

[0498] (Embodiment 5) In this embodiment, an apparatus that can be used for manufacturing a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

[0499] When manufacturing a semiconductor device according to one embodiment of the present invention, it is preferable to use a so-called multi-chamber apparatus having a plurality of treatment chambers in which different types of films can be successively formed. In each treatment chamber, a film formation process such as sputtering, CVD, ALD, etc. can be performed. For example, when one treatment chamber is a treatment chamber for performing sputtering (also called a sputtering chamber), a gas supply device, a gas purification device connected to the gas supply device, a vacuum pump, a target, etc. can be connected to the sputtering chamber.

[0500] In each treatment chamber, a cleaning treatment, a plasma treatment, a reverse sputtering treatment, an etching treatment, an ashing treatment, a heating treatment, etc. may be performed. By appropriately performing different treatments in each treatment chamber, an insulating film, a conductive film, and a semiconductor film can be formed without exposure to the atmosphere.

[0501] A typical example of a semiconductor film used in one embodiment of the present invention is an oxide semiconductor film. In particular, an oxide semiconductor film having a low impurity concentration and a low density of defect states (few oxygen vacancies) can be used to manufacture a transistor with excellent electrical characteristics. Here, a semiconductor film having a low impurity concentration and a low density of defect states is referred to as a highly pure intrinsic film or a substantially highly pure intrinsic film.

[0502] A highly-purified intrinsic or substantially highly-purified intrinsic oxide semiconductor film has a small number of carrier generation sources, and therefore the carrier concentration can be reduced. Therefore, a transistor in which a channel formation region is formed in the oxide semiconductor film rarely has electrical characteristics in which the threshold voltage is negative (also referred to as normally-on). In addition, a highly-purified intrinsic or substantially highly-purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low. In addition, a highly-purified intrinsic or substantially highly-purified intrinsic oxide semiconductor film has an extremely small off-state current and a channel width of 1×10 6 Even in a device with a channel length of 10 μm and a width of 1 μm, the off-state current is below the measurement limit of the semiconductor parameter analyzer, that is, 1×10-13 It is possible to obtain a characteristic of A or less.

[0503] Typical examples of impurities in an oxide semiconductor film include water and hydrogen. In this specification and the like, reducing or removing water and hydrogen from an oxide semiconductor film may be referred to as dehydration or dehydrogenation. Adding oxygen to an oxide semiconductor film may be referred to as oxygen addition, and a state in which oxygen is added and the oxide semiconductor film has more oxygen than the stoichiometric composition may be referred to as an excess oxygen state.

[0504] Here, by successively depositing different types of films, that is, an oxide semiconductor, an insulator or conductor located in a lower layer of the oxide semiconductor, and an insulator or conductor located in an upper layer of the oxide semiconductor, without exposure to the air, it is possible to form a substantially high-purity intrinsic oxide semiconductor film in which the concentration of impurities (particularly hydrogen and water) is reduced.

[0505] First, a structural example of an apparatus that can be used for manufacturing a semiconductor device of one embodiment of the present invention will be described in detail with reference to FIG. 30. By using the apparatus shown in FIG. 30, a semiconductor film, an insulator or conductor located under the semiconductor film, and an insulating film or conductive film located over the semiconductor film can be successively formed. Therefore, impurities (particularly hydrogen and water) that may enter the semiconductor film can be suppressed. The apparatus shown in FIG. 30 is not limited to successive formation of a stacked structure including a semiconductor film, but can also successively form insulating films made of different materials, conductive films made of different materials, and a stacked structure of an insulating film and a conductive film.

[0506] FIG. 30 is a schematic top view of a single-wafer type multi-chamber apparatus 4000.

[0507] The apparatus 4000 has an atmosphere-side substrate supply chamber 4010, an atmosphere-side substrate transfer chamber 4012 for transferring substrates from the atmosphere-side substrate supply chamber 4010, a load lock chamber 4020a for transferring the substrate and for switching the pressure inside the chamber from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure, an unload lock chamber 4020b for transferring the substrate and for switching the pressure inside the chamber from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure, a transfer chamber 4029 and a transfer chamber 4039 for transferring the substrate in a vacuum, a transfer chamber 4030a and a transfer chamber 4030b connecting the transfer chamber 4029 and the transfer chamber 4039, and a treatment chamber 4024a, a treatment chamber 4024b, a treatment chamber 4034a, a treatment chamber 4034b, a treatment chamber 4034c, a treatment chamber 4034d, and a treatment chamber 4034e for performing film formation or heating.

[0508] The multiple processing chambers can each perform different processes in parallel. Therefore, a stacked structure of different film types can be easily fabricated. Parallel processing can be performed up to the number of processing chambers. For example, the apparatus 4000 shown in FIG. 30 has seven processing chambers. Therefore, seven film formation processes can be performed consecutively using one apparatus (also referred to as in-situ in this specification) without being exposed to the atmosphere.

[0509] On the other hand, in a laminated structure, the number of layers that can be produced without exposing to the atmosphere is not necessarily the same as the number of processing chambers. For example, if the desired laminated structure has multiple layers of the same material, the layers can be provided in one processing chamber, so that a laminated structure with a greater number of layers than the number of processing chambers installed can be produced.

[0510] The atmosphere side substrate supply chamber 4010 also includes a cassette port 4014 for accommodating substrates, and an alignment port 4016 for aligning the substrates. Note that a configuration may be provided with a plurality of cassette ports 4014 (for example, three in FIG. 30).

[0511] The atmosphere side substrate transfer chamber 4012 is connected to the load lock chamber 4020a and the unload lock chamber 4020b. The transfer chamber 4029 is connected to the load lock chamber 4020a, the unload lock chamber 4020b, the transfer chamber 4030a, the transfer chamber 4030b, the processing chamber 4024a, and the processing chamber 4024b. The transfer chamber 4030a and the transfer chamber 4030b are connected to the transfer chamber 4029 and the transfer chamber 4039. The transfer chamber 4039 is connected to the transfer chamber 4030a, the transfer chamber 4030b, the processing chamber 4034a, the processing chamber 4034b, the processing chamber 4034c, the processing chamber 4034d, and the processing chamber 4034e.

[0512] A gate valve 4028 or a gate valve 4038 is provided at the connection between the chambers, and each chamber can be independently maintained in a vacuum state, except for the atmosphere side substrate supply chamber 4010 and the atmosphere side substrate transfer chamber 4012. The atmosphere side substrate transfer chamber 4012 has a transfer robot 4018. The transfer chamber 4029 has a transfer robot 4026, and the transfer chamber 4039 has a transfer robot 4036. The transfer robot 4018, the transfer robot 4026, and the transfer robot 4036 each have a plurality of movable parts and an arm that holds a substrate, and can transfer a substrate to each chamber.

[0513] The number of transfer chambers, processing chambers, load lock chambers, unload lock chambers and transport chambers is not limited to the above, and an optimum number can be provided depending on the installation space and process conditions.

[0514] In particular, when there are multiple transfer chambers, it is preferable to have two or more transfer chambers between one transfer chamber and another transfer chamber. For example, as shown in Fig. 30, when there are transfer chambers 4029 and 4039, it is preferable to arrange transfer chambers 4030a and 4030b in parallel between transfer chambers 4029 and 4039.

[0515] By arranging the transfer chamber 4030a and the transfer chamber 4030b in parallel, for example, a step in which the transfer robot 4026 carries a substrate into the transfer chamber 4030a and a step in which the transfer robot 4036 carries a substrate into the transfer chamber 4030b can be performed simultaneously. Also, a step in which the transfer robot 4026 carries a substrate out of the transfer chamber 4030b and a step in which the transfer robot 4036 carries a substrate out of the transfer chamber 4030a can be performed simultaneously. In other words, by driving multiple transfer robots simultaneously, production efficiency is improved.

[0516] 30 shows an example in which one transfer chamber has one transfer robot and is connected to multiple processing chambers, but the present invention is not limited to this structure. One transfer chamber may have multiple transfer robots.

[0517] In addition, one or both of the transfer chamber 4029 and the transfer chamber 4039 are connected to a vacuum pump and a cryopump via valves. Therefore, the transfer chamber 4029 and the transfer chamber 4039 are evacuated from atmospheric pressure to a low or medium vacuum (several hundred Pa to about 0.1 Pa) using a vacuum pump, and then the valve is switched and the cryopump is used to evacuate from the medium vacuum to a high or ultra-high vacuum (0.1 Pa to 1×10 -7 It is possible to evacuate to a pressure of approximately 10 Pa.

[0518] Also, for example, two or more cryopumps may be connected in parallel to one transfer chamber. By having multiple cryopumps, even if one cryopump is in regeneration, it is possible to use the other cryopumps to pump air. Note that regeneration is the process of releasing molecules (or atoms) that have accumulated in the cryopump. If a cryopump accumulates too many molecules (or atoms), its pumping capacity will decrease, so it is a good idea to regenerate it periodically.

[0519] The processing chambers 4024a, 4024b, 4034a, 4034b, 4034c, 4034d, and 4034e can each perform different processes in parallel. That is, in each processing chamber, a film formation process using sputtering, CVD, MBE, PLD, ALD, or the like, a heat treatment, or a plasma treatment can be performed on a substrate placed therein. In addition, a film formation process may be performed in the processing chamber after a heat treatment or a plasma treatment is performed.

[0520] The apparatus 4000 has multiple processing chambers, and thus can transport the substrate between processing steps without exposing it to the atmosphere, thereby preventing impurities from being adsorbed on the substrate. In addition, since each processing chamber can perform a film formation process for different types of films, a heat treatment process, or a plasma treatment process, the order of film formation, heat treatment, etc. can be freely determined.

[0521] Each processing chamber may be connected to a vacuum pump via a valve. As the vacuum pump, for example, a dry pump, a mechanical booster pump, or the like can be used.

[0522] Each processing chamber may be connected to a power source capable of generating plasma. The power source may be a DC power source, an AC power source, or a high-frequency (RF, microwave, etc.) power source. A pulse generator may be connected to the DC power source.

[0523] The processing chamber may be connected to a gas purification device via a gas supply device. The gas supply devices and gas purification devices may be provided in the same number as the number of gas types.

[0524] For example, when a film formation process by sputtering is performed in a process chamber, the process chamber may include a target, a backing plate connected to the target, a cathode arranged facing the target via the backing plate, an adhesion prevention plate, a substrate stage, etc. Also, for example, the substrate stage may include a substrate holding mechanism for holding a substrate, a back surface heater for heating the substrate from the back surface, etc.

[0525] The substrate stage is held in a generally vertical position relative to the floor during film formation, and is held in a generally horizontal position relative to the floor during substrate transfer. By holding the substrate stage generally vertical to the floor, the probability that dust or particles that may be mixed in during film formation will adhere to the substrate can be reduced more than if the substrate stage were held horizontal. However, if the substrate stage is held vertical (90°) relative to the floor, there is a risk that the substrate will fall, so the angle of the substrate stage relative to the floor is preferably 80° or more and less than 90°.

[0526] The configuration of the substrate stage is not limited to the above. For example, the substrate stage may be configured to be approximately horizontal with respect to the floor surface. In this configuration, the target may be placed below the substrate stage, and the substrate may be placed between the target and the substrate stage. The substrate stage may also include a jig for fixing the substrate so that the substrate does not fall, or a mechanism for fixing the substrate.

[0527] Furthermore, by providing an adhesion prevention plate in the processing chamber, it is possible to prevent the particles sputtered from the target from accumulating in unnecessary areas. It is also preferable to process the adhesion prevention plate so that the accumulated sputtered particles do not peel off. For example, a blasting process may be performed to increase the surface roughness, or the surface of the adhesion prevention plate may be provided with irregularities.

[0528] The backing plate has a function of holding the target, and the cathode has a function of applying a voltage (for example, a negative voltage) to the target.

[0529] Note that the target may be a conductor, an insulator, or a semiconductor. For example, when the target is an oxide semiconductor such as a metal oxide, an oxide semiconductor film can be formed in the treatment chamber. Even when the target is a metal oxide, an oxynitride semiconductor film can be formed by using nitrogen gas as a film formation gas.

[0530] Each processing chamber may be connected to a gas supply device via a gas heating mechanism. The gas heating mechanism is connected to a gas purification device via a gas supply device. The gas introduced into the processing chamber may have a dew point of -80°C or less, preferably -100°C or less, more preferably -120°C or less, and may be, for example, oxygen gas, nitrogen gas, or a rare gas (such as argon gas). The gas introduced into the processing chamber may be heated to 40°C or more and 400°C or less by the gas heating mechanism. The gas heating mechanism, gas supply device, and gas purification device may be provided in the same number as the number of gas types.

[0531] Each processing chamber may be connected to a turbo molecular pump and a vacuum pump via a valve, and each processing chamber may be provided with a cryotrap.

[0532] A cryotrap is a mechanism capable of adsorbing molecules (or atoms) with a relatively high melting point, such as water. A turbomolecular pump is excellent in productivity because it stably pumps large-sized molecules (or atoms) and requires little maintenance, but has a low pumping capacity for hydrogen and water. Therefore, a cryotrap can be used to improve the pumping capacity for water and the like. The temperature of the cryotrap refrigerator is 100K or less, preferably 80K or less. In addition, when a cryotrap has multiple refrigerators, it is preferable to change the temperature of each refrigerator, since this allows for efficient pumping. For example, the temperature of the first-stage refrigerator may be 100K or less, and the temperature of the second-stage refrigerator may be 20K or less.

[0533] The exhaust method of the processing chamber is not limited to this, and may be the same as the exhaust method of the connected transfer chamber (exhaust method of a cryopump and a vacuum pump). The exhaust method of the transfer chamber may be the same as the exhaust method of the processing chamber (exhaust method of a turbo molecular pump and a vacuum pump).

[0534] In particular, a combination of a vacuum pump and a cryotrap may be used as an exhaust means for the treatment chamber in which the oxide semiconductor film is formed. It is preferable that an exhaust means provided in the treatment chamber in which the oxide semiconductor film is formed has a function of adsorbing at least water molecules.

[0535] In addition, the partial pressure of hydrogen molecules in the treatment chamber for forming the oxide semiconductor film was 1×10 -2 Pa or less, and the partial pressure of water molecules is 1×10 -4 In addition, the pressure in the treatment chamber in which the oxide semiconductor film is formed in a standby state is preferably 8.0×10 Pa or less. -5 Pa or less, preferably 5.0×10 -5 Pa or less, more preferably 1.0×10 -5 The partial pressure of hydrogen molecules and the partial pressure of water molecules are values ​​when the sputtering chamber is in a standby state and when the sputtering chamber is in a film forming state (plasma is in a discharging state).

[0536] The total pressure and partial pressure of the process chamber can be measured using a mass spectrometer, for example, a quadrupole mass spectrometer (also called Q-mass) Qulee CGM-051 manufactured by ULVAC, Inc.

[0537] When the partial pressure of hydrogen molecules, the partial pressure of water molecules, and the pressure in the standby state in the treatment chamber are set to the above ranges, the impurity concentration in the oxide semiconductor film to be formed can be low.

[0538] In particular, by using each treatment chamber for a film formation process by sputtering, part of the configuration of the transistor 200 described in the above embodiment can be manufactured to have a stacked structure in which films are successively formed in situ.

[0539] In a method for manufacturing the transistor 200, the insulator 212, the insulator 214, and the insulator 216 are successively formed using the apparatus 4000. The oxide film 230A, the oxide film 230B, and the oxide film 243A are successively formed using the apparatus 4000. The insulating films to be the insulator 254 and the insulator 280 are successively formed using the apparatus 4000.

[0540] That is, the insulators 212, 214, and 216 can be formed in succession without exposure to the atmosphere. Also, the oxide films 230A, 230B, and 243A can be formed in succession without exposure to the atmosphere. Also, the insulating films that become the insulators 254 and 280 can be formed in succession without exposure to the atmosphere.

[0541] With the above-mentioned configuration, it is possible to form a laminated film from which impurities (typically, water, hydrogen, etc.) are thoroughly eliminated. In addition, since each interface of the laminated film is not exposed to the atmosphere, the impurity concentration is reduced.

[0542] Furthermore, for example, when heat treatment is performed in a treatment chamber, the treatment chamber may include a plurality of heating stages capable of storing substrates. The heating stages may be configured in multiple stages. By increasing the number of heating stages, a plurality of substrates can be simultaneously heat-treated, thereby improving productivity.

[0543] The heating mechanism that can be used in the processing chamber may be, for example, a heating mechanism that uses a resistance heating element for heating. Alternatively, it may be a heating mechanism that uses heat conduction or heat radiation from a medium such as a heated gas for heating. For example, RTAs (Rapid Thermal Anneals) such as GRTA (Gas Rapid Thermal Anneal) and LRTA (Lamp Rapid Thermal Anneal) can be used. LRTAs heat the workpiece by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps, and high pressure mercury lamps. GRTAs perform heat treatment using high-temperature gas. An inert gas is used as the gas.

[0544] The load lock chamber 4020a may include a substrate transfer stage, a backside heater for heating the substrate from the backside, etc. The load lock chamber 4020a increases the pressure from a reduced pressure state to atmospheric pressure, and when the pressure in the load lock chamber 4020a reaches atmospheric pressure, the substrate transfer stage receives the substrate from the transfer robot 4018 provided in the atmospheric side substrate transfer chamber 4012. Thereafter, the load lock chamber 4020a is evacuated to a reduced pressure state, and then the transfer robot 4026 provided in the transfer chamber 4029 receives the substrate from the substrate transfer stage.

[0545] The load lock chamber 4020a is connected to a vacuum pump and a cryopump via valves. The unload lock chamber 4020b may have the same configuration as the load lock chamber 4020a.

[0546] The atmosphere side substrate transfer chamber 4012 has a transfer robot 4018, so that the transfer robot 4018 can transfer substrates between the cassette port 4014 and the load lock chamber 4020a. A mechanism for suppressing the intrusion of dust or particles, such as a HEPA filter (High Efficiency Particulate Air Filter), may be provided above the atmosphere side substrate transfer chamber 4012 and the atmosphere side substrate supply chamber 4010. The cassette port 4014 can store a plurality of substrates.

[0547] By using the above-described apparatus 4000 to successively form an insulating film, a semiconductor film, and a conductive film without exposure to the atmosphere, it is possible to suitably suppress the intrusion of impurities into the semiconductor film.

[0548] As described above, by using the apparatus according to one embodiment of the present invention, a stacked structure including a semiconductor film can be manufactured by successive film formation. Therefore, impurities such as hydrogen and water that are taken into the semiconductor film can be suppressed, and a semiconductor film with a low density of defect states can be manufactured.

[0549] The structure, method, and the like described in this embodiment can be used in appropriate combination with the structure, method, and the like described in other embodiments.

[0550] (Embodiment 6) In this embodiment, a transistor using an oxide as a semiconductor (hereinafter may be referred to as an OS transistor) and a memory device including a capacitor (hereinafter may be referred to as an OS memory device) according to one embodiment of the present invention will be described with reference to FIGS. 31A, 31B, and 32A to 32H. The OS memory device is a memory device including at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the off-state current of the OS transistor is extremely small, the OS memory device has excellent retention characteristics and can function as a nonvolatile memory.

[0551] <Storage device configuration example> 31A shows an example of the configuration of an OS memory device. The memory device 1400 includes a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

[0552] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, and the like. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying a data signal read from a memory cell. Note that the above wiring is a wiring connected to a memory cell included in the memory cell array 1470, and will be described in detail later. The amplified data signal is output to the outside of the memory device 1400 as a data signal RDATA via the output circuit 1440. The row circuit 1420 includes, for example, a row decoder, a word line driver circuit, and the like, and can select a row to be accessed.

[0553] A low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 are supplied to the memory device 1400 from the outside as power supply voltages. In addition, control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input from the outside to the memory device 1400. The address signal ADDR is input to a row decoder and a column decoder, and the data signal WDATA is input to a write circuit.

[0554] The control logic circuit 1460 processes control signals (CE, WE, RE) input from the outside to generate control signals for the row decoder and column decoder. The control signal CE is a chip enable signal, the control signal WE is a write enable signal, and the control signal RE is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to these, and other control signals may be input as necessary.

[0555] The memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings. The number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC in one column, etc. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, etc.

[0556] 31A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, but the present embodiment is not limited to this. For example, as shown in FIG. 31B, the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap the memory cell array 1470 below.

[0557] 32A to 32H will be used to explain examples of the configuration of a memory cell that can be applied to the above-mentioned memory cell MC.

[0558] [DOSRAM] 32A to 32C show circuit configuration examples of a DRAM memory cell. In this specification and the like, a DRAM using a memory cell with one OS transistor and one capacitor may be called a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 1471 shown in FIG. 32A includes a transistor M1 and a capacitor CA. Note that the transistor M1 includes a gate (sometimes called a top gate) and a back gate.

[0559] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to a wiring BIL, a gate of the transistor M1 is connected to a wiring WOL, a back gate of the transistor M1 is connected to a wiring BGL, and a second terminal of the capacitance element CA is connected to a wiring CAL.

[0560] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. When writing and reading data, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. The threshold voltage of the transistor M1 can be increased or decreased by applying an arbitrary potential to the wiring BGL.

[0561] Here, the memory cell 1471 shown in Fig. 32A corresponds to the memory device shown in Fig. 26. That is, the transistor M1 corresponds to the transistor 200, and the capacitive element CA corresponds to the capacitive device 292.

[0562] The memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed. For example, the memory cell MC may be configured such that the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1472 shown in FIG. 32B. For example, the memory cell MC may be configured as a single-gate transistor, that is, a memory cell configured with a transistor M1 without a back gate, as in the memory cell 1473 shown in FIG. 32C.

[0563] When the semiconductor device described in the above embodiment is used for the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1, and the capacitor 100 can be used as the capacitor CA. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made very small. That is, since written data can be held by the transistor M1 for a long time, the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary. Furthermore, since the leakage current is very small, multi-valued data or analog data can be held in the memory cell 1471, the memory cell 1472, and the memory cell 1473.

[0564] Furthermore, in the DOSRAM, if a sense amplifier is provided so as to overlap under the memory cell array 1470 as described above, the bit line can be shortened. This reduces the bit line capacitance and the storage capacitance of the memory cell.

[0565] [NOSRAM] 32D to 32G show circuit configuration examples of a gain cell type memory cell having two transistors and one capacitor. The memory cell 1474 shown in FIG. 32D has a transistor M2, a transistor M3, and a capacitor CB. Note that the transistor M2 has a top gate (sometimes simply called a gate) and a back gate. In this specification and the like, a storage device having a gain cell type memory cell using an OS transistor as the transistor M2 may be called a nonvolatile oxide semiconductor RAM (NOSRAM).

[0566] A first terminal of the transistor M2 is connected to a first terminal of the capacitance element CB, a second terminal of the transistor M2 is connected to the wiring WBL, a gate of the transistor M2 is connected to the wiring WOL, and a back gate of the transistor M2 is connected to the wiring BGL. A second terminal of the capacitance element CB is connected to the wiring CAL. A first terminal of the transistor M3 is connected to the wiring RBL, a second terminal of the transistor M3 is connected to the wiring SL, and a gate of the transistor M3 is connected to the first terminal of the capacitance element CB.

[0567] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while holding data, and when reading data, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.

[0568] Here, the memory cell 1474 shown in Fig. 32D corresponds to the memory device shown in Fig. 23. That is, the transistor M2 corresponds to the transistor 200, the capacitor CB corresponds to the capacitor 100, the transistor M3 corresponds to the transistor 300, the wiring WBL corresponds to the wiring 1003, the wiring WOL corresponds to the wiring 1004, the wiring BGL corresponds to the wiring 1006, the wiring CAL corresponds to the wiring 1005, the wiring RBL corresponds to the wiring 1002, and the wiring SL corresponds to the wiring 1001.

[0569] Moreover, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be changed as appropriate. For example, the memory cell MC may be configured such that the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1475 shown in FIG. 32E. For example, the memory cell MC may be configured as a single-gate transistor, that is, a memory cell configured with a transistor M2 without a back gate, as in the memory cell 1476 shown in FIG. 32F. For example, the memory cell MC may...

Claims

1. A first insulator; a first oxide on the first insulator; a first conductor and a second conductor having a region in contact with an upper surface of the first oxide; a first layer having a region in contact with a first side of the first oxide; a second layer having a region in contact with a second side of the first oxide; a second insulator having a region disposed on the first insulator, a region disposed on the first layer, a region disposed on the second layer, a region disposed on the first conductor, and a region disposed on the second conductor; a third insulator provided on the second insulator and having an opening; a second oxide having a region disposed between the first conductor and the second conductor, a region disposed on the first oxide, and a region in contact with an inner wall of the opening; a fourth insulator having a region disposed on the second oxide and a region facing an inner wall of the opening with the second oxide interposed therebetween; a third conductor having a region disposed on the fourth insulator and a region facing an inner wall of the opening via the fourth insulator and the second oxide; Each of the first conductor and the second conductor has a curved surface between a side surface and a top surface, The radius of curvature of the curved surface is 3 nm or more and 10 nm or less, the second insulator has a region in contact with an upper surface of the first conductor and a region in contact with an upper surface of the second conductor, and does not have a region in contact with the third conductor; the second oxide has a region in contact with a side surface of the first conductor and a region in contact with a side surface of the second conductor, and does not have a region in contact with a top surface of the first conductor and a region in contact with a top surface of the second conductor; each of the first layer and the second layer includes a metal contained in the first conductor and a metal contained in the second conductor, and oxygen; A semiconductor device, wherein the first insulator has a region in contact with the second insulator, the region having a lower concentration of the metal than the first layer or the second layer.

2. In claim 1, The semiconductor device, wherein the first layer and the second layer each have a region having a thickness of 0.5 nm or more and 1.5 nm or less.

3. In claim 1 or 2, The semiconductor device wherein the metal is tantalum.

4. In any one of claims 1 to 3, The first oxide comprises indium, an element M (M is gallium, aluminum, yttrium, or tin), and zinc.

5. In any one of claims 1 to 3, The first oxide comprises indium.

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