Semiconductor device having germanium region disposed in semiconductor substrate

Abstract

PURPOSE: To provide a semiconductor device having a germanium region disposed in a semiconductor substrate.SOLUTION: A single-photon avalanche detector (SPAD) device includes a silicon substrate including a recess in an upper surface of the silicon substrate. A p-type region is arranged in the silicon substrate below a lower surface of the recess. An n-type avalanche region is arranged in the silicon substrate below the p-type region and meets the p-type region at a p-n junction. A germanium region is disposed within the recess over the p-n junction.SELECTED DRAWING: Figure 1

Description

[Background technology]

[0001] Single-photon avalanche diodes (SPADs) are solid-state photodetectors of the same family as photodiodes and avalanche photodiodes (APDs). Like photodiodes and APDs, SPADs are based on a semiconductor pn junction that can be illuminated with ionizing radiation such as gamma, x-ray, beta, and / or alpha along a broad portion of the electromagnetic spectrum, from ultraviolet (UV) through visible wavelengths to infrared (IR). In operation, photogenerated carriers are accelerated by the device's electric field to sufficient kinetic energy to overcome the ionization energy of the bulk material, knocking electrons out of the atoms of the bulk material. Large avalanches of current carriers grow exponentially and can be triggered from as few as a single photon-initiated carrier. SPADs are capable of detecting single photons, providing a short-duration trigger pulse that can be counted. However, they can also be used to obtain the arrival time of an incident photon due to the fast rate at which avalanches occur. Summary of the Invention [Problem to be solved by the invention]

[0002] Germanium single-photon avalanche diodes (Ge-SPADs) are a type of SPAD for operation in the eye-safe short-wave infrared (SWIR) region, but germanium itself has high dark count rate (DCR) material properties, especially at room temperature or above. [Means for solving the problem]

[0003] The present invention provides, in some embodiments, a single photon avalanche detector (SPAD) device including a silicon substrate, a p-type region, an n-type avalanche region, and a germanium region. The silicon substrate includes a recess in an upper surface of the silicon substrate. The p-type region is disposed in the silicon substrate below a lower surface of the recess. The n-type avalanche region is disposed in the silicon substrate below the p-type region and contacts the p-type region at a pn junction. The germanium region is disposed in the recess above the pn junction.

[0004] The present invention also provides, in some embodiments, a semiconductor structure including a semiconductor substrate, a silicon-based multiplication region, a germanium-based absorber region, and an electron channel. The silicon-based multiplication region is provided in the semiconductor substrate. The germanium-based absorber region is provided in the semiconductor substrate, and the germanium-based absorber region is disposed above the silicon-based multiplication region. The electron channel is between the silicon-based multiplication region and the germanium-based absorber region.

[0005] The invention further provides, in some embodiments, a method: receiving a semiconductor substrate; performing an ion implant to form a lateral connection region below an upper surface of the semiconductor substrate; performing another ion implant to form a vertical connection region, the vertical connection region and the lateral connection region contacting each other to form a guard ring; forming a recess in the upper surface of the semiconductor substrate, the recess being laterally surrounded by the guard ring and defined by a recessed upper surface of the semiconductor substrate and an interior sidewall of the semiconductor substrate; forming a germanium region in the recess. Effect of the Invention

[0006] Various embodiments of the present invention employ embedded separate absorption and multiplication (SAM) structures for commercial use. [Brief description of the drawings]

[0007] The accompanying drawings are included to provide a further understanding of the principles of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0008] [Figure 1] FIG. 1 is a cross-sectional view of several embodiments of an integrated chip having SPAD devices that include germanium regions embedded in a silicon substrate. [Diagram 2] FIG. 2 is a cross-sectional view of some embodiments of an integrated chip having SPAD devices that include germanium regions embedded in a silicon substrate. [Diagram 3] Figure 3A is a cross-sectional view of some embodiments of an integrated chip having a SPAD device including a germanium region embedded in a silicon substrate, and Figure 3B is a bandgap diagram of some embodiments of a SPAD device consistent with Figure 3A. [Figure 4] FIG. 4 is a cross-sectional view of several embodiments of an integrated chip having multiple SPAD devices, each of which includes a germanium region embedded in a silicon substrate. [Diagram 5] FIG. 5 is a cross-sectional view of several embodiments of an integrated chip having multiple SPAD devices, each of which includes a germanium region embedded in a silicon substrate. [Figure 6] 1 illustrates a manufacturing flow according to some embodiments. [Figure 7] 1 illustrates a manufacturing flow according to some embodiments. [Figure 8] 1 illustrates a manufacturing flow according to some embodiments. [Figure 9] 1 illustrates a manufacturing flow according to some embodiments. [Figure 10] 1 illustrates a manufacturing flow according to some embodiments. [Figure 11] 1 illustrates a manufacturing flow according to some embodiments. [Figure 12]1 illustrates a manufacturing flow according to some embodiments. [Figure 13] 1 illustrates a manufacturing flow according to some embodiments. [Figure 14] 1 illustrates a manufacturing flow according to some embodiments. [Figure 15] 11 illustrates another manufacturing flow according to another embodiment. [Figure 16] 11 illustrates another manufacturing flow according to another embodiment. [Figure 17] 11 illustrates another manufacturing flow according to another embodiment. [Figure 18] 11 illustrates another manufacturing flow according to another embodiment. [Figure 19] 11 illustrates another manufacturing flow according to another embodiment. [Figure 20] 11 illustrates another manufacturing flow according to another embodiment. [Figure 21] 11 illustrates another manufacturing flow according to another embodiment. [Figure 22] 11 illustrates another manufacturing flow according to another embodiment. [Figure 23] 11 illustrates another manufacturing flow according to another embodiment. [Figure 24] 11 illustrates another manufacturing flow according to another embodiment. [Diagram 25] 11 illustrates another manufacturing flow according to another embodiment. [Figure 26] 11 illustrates another manufacturing flow according to another embodiment. [Figure 27] 11 illustrates another manufacturing flow according to another embodiment. [Figure 28] 11 illustrates another manufacturing flow according to another embodiment. [Figure 29] 11 illustrates another manufacturing flow according to another embodiment. [Diagram 30] 1 is a flowchart of a manufacturing flow according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. To simplify the disclosure, specific examples of components and arrangements are described below. These are, of course, merely examples and are not intended to be limiting. For example, forming on a first feature or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which the first and second features are not in direct contact, but an additional feature is formed between the first and second features. Furthermore, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for purposes of simplicity and clarity and does not, in itself, dictate a relationship between the various embodiments and / or configurations discussed.

[0010] FIG. 1 illustrates a single photon avalanche detector (SPAD) device 100 according to some embodiments. The SPAD device 100 includes a silicon substrate 102 including a recess 104 in an upper surface 102u. A p-type region 106 is disposed in the silicon substrate below the lowermost recess 104. An n-type avalanche region 108 is disposed in the silicon substrate 102 below the p-type region 106 and contacts the p-type region 106 at a pn junction 110 corresponding to a photodiode in the silicon substrate 102. A germanium region 112 is disposed in the recess 104. The upper surface of the germanium region 112 may be at a depth (d) below the upper surface 102u of the silicon substrate 102 (see 112ub), may be level with the upper surface 102u of the substrate (see 112ul), or may be at a height (h) above the upper surface 102u of the substrate. In some embodiments, a gap is formed between the top of the p-type region 106 and the bottom surface of the germanium region 112. Intrinsic Silicon region 118 may be disposed. IntrinsicSilicon region 118 is configured to act as an electron channel between pn junction 110 and germanium region 112. Bias circuit 150 is configured to bias pn junction 110 to apply a voltage to SPAD device 100 that is greater than the avalanche breakdown voltage and to suppress SPAD device 100 after an avalanche occurs. Bias circuit 150 may be implemented using transistors and / or other active or passive elements located on or in silicon substrate 102 or in another substrate.

[0011] In one case, the germanium region 112 meets the silicon substrate 102 at a Ge-Si interface region 117. The Ge-Si interface region 117 is defined where the outer sidewall and lower surface of the germanium region 112 meet the inner sidewall and recessed upper surface of the silicon substrate 102, respectively. This Ge-Si interface region 117 is composed of a Ge-Si alloy having a lattice constant ranging between 56.6 nm and 54.3 nm. In one case, the Ge-Si alloy can have a thickness ranging from 1 angstrom to 20 nm and can have a U-shaped cross-section.

[0012] The n-type lateral connection region 114 extends laterally from the outer edge of the pn junction 110 past the outer wall of the germanium region 112. The n-type vertical connection region 116 extends upward from the outer edge of the n-type lateral connection region 114 to the upper surface 102u of the silicon substrate 102. In some cases, the n-type vertical connection region 116 laterally surrounds the germanium region 112 when viewed from above, so that the n-type lateral connection region 114 and / or the n-type vertical connection region 116 are also referred to as "guard rings." In some embodiments, the n-type avalanche region 108, the n-type lateral connection region 114, and the n-type vertical connection region 116, when viewed in cross section, collectively form a generally U-shaped cross-sectional profile that encapsulates the p-type region 106 and the germanium region 112.

[0013] In operation, the bias circuit 150 biases the pn junction 110 above the avalanche breakdown voltage. Under this bias condition, when an incident photon 152 (e.g., from a laser pulse) is absorbed in the absorption region 113 corresponding to the germanium region 112, an electron-hole pair is generated and an electron Intrinsic The electrons flow through silicon region 118 into multiplication region 115, which includes pn junction 110. The electrons are then accelerated in multiplication region 115, gaining sufficient kinetic energy to be impact ionized, creating a second electron-hole pair. The second electron and second electron-hole pair are similarly accelerated and impact ionized, creating further electron-hole pairs in multiplication region 115. Further impact ionization of holes and electrons rapidly creates a large avalanche current, which can be self-sustaining if the device is biased above the avalanche breakdown voltage. In these circumstances, the result is a detectable electronic signal that can be timed relative to the initial incident photon 152 (e.g., from the generation of a laser pulse). After detection, bias circuit 150 biases SPAD device 100 below the avalanche breakdown voltage for a fraction of a second to suppress the avalanche, after which SPAD device 100 returns to its quiescent state, ready to detect further incident photons.

[0014] In particular, the germanium regions 112 are disposed in recesses 104 in the upper surface 102u of the silicon substrate 102, which in some respects reduces the dark current rate (DCR) more than would be possible otherwise. In addition, the germanium regions 112 also provide better absorption (detection) of short wavelength infrared (SWIR) signals that do not occur in pure silicon-based SPADs. Thus, the SPAD device 100 is a germanium (Ge) in silicon (Si) SAM device. In this device, forming the germanium regions 112 in recesses 104 in the silicon substrate 102, rather than simply as a plateau on the upper surface of the substrate, offers several advantages.

[0015] 2 illustrates another embodiment of a SPAD device 100 according to some embodiments. The SPAD device 100 also includes a silicon substrate 102 including a recess 104 in an upper surface 102u. A p-type region 106 is disposed in the silicon substrate below the lowermost recess 104. An n-type avalanche region 108 is disposed in the silicon substrate 102 below the p-type region 106 and contacts the p-type region 106 at a pn junction 110. A germanium region 112 is disposed in the recess 104.

[0016] The n-type lateral connection region 114 extends laterally from the outer edge of the pn junction 110, past the outer wall of the germanium region 112. The n-type vertical connection region 116 extends upward from the outer edge of the n-type lateral connection region 114 to the upper surface 102u of the silicon substrate 102. In some cases, the n-type vertical connection region 116 laterally surrounds the germanium region 112 when viewed from above, so that the n-type lateral connection region 114 and / or the n-type vertical connection region 116 are also referred to as "guard rings." In some embodiments, the n-type avalanche region 108, the n-type lateral connection region 114, and the n-type vertical connection region 116, when viewed in cross section, collectively form a generally U-shaped cross-sectional profile that encapsulates the p-type region 106 and the germanium region 112.

[0017] In some embodiments, the SPAD device further aligns with the recess 104, and Intrinsic The silicon region 118 includes a p-type surface region 120 that laterally surrounds the silicon region 118. The p-type surface region is made of silicon, such as single crystal silicon. The p-type surface region 120 is Intrinsic It includes a base portion 120b having a central opening corresponding to silicon region 118, and includes a sidewall portion 120s extending upwardly along the outer sidewall of germanium region 112 (and / or the interior sidewall of recess 104 in the silicon substrate).

[0018] In some embodiments, the germanium region 112 further includes a bulk region corresponding to the absorber region 113, the bulk region and the absorber region 113 being: IntrinsicThe germanium region 112 is made of (undoped) germanium. The sidewall germanium region 126 extends continuously along the outer wall of the germanium region 112. The sidewall germanium region 126 is also p-type. The p-type surface region 120 and the sidewall germanium region help reduce leakage, thereby mitigating dark current caused by stress, misalignment, etc., that occurs at the Ge-Si interface region.

[0019] A cap 128, e.g., a p-type silicon cap, is disposed on the upper surface of the germanium region 112 to limit / prevent oxidation of the top surface of the germanium region 112. In the illustrated example, the cap 128 has an upper surface that is flush or level with the upper surface 102u of the silicon substrate, but in other cases, the upper surface of the cap 128 may be recessed below the upper surface of the silicon substrate, may be level with the top surface of the silicon substrate, or may be elevated above the upper surface of the silicon substrate. Furthermore, in the illustrated embodiment, the cap 128 has a lower surface that is in direct contact with and flush or level with the upper surfaces of the bulk germanium region and the sidewall germanium region 126. However, in other embodiments, the sidewall germanium region 126 is disposed within the outer periphery of the recess 104 and extends upward along the outer wall of the cap 128 to be level with the upper surface 102u of the silicon substrate 102.

[0020] The dielectric structure 132 may be made of, for example, a silicon diode or a low-k dielectric material and extends above the upper surface 102u of the substrate. A conductive contact 134, e.g., a metal contact, extends through the dielectric structure 132, and a metal line or conductive pad 136 is formed on the conductive contact. The metal line or conductive pad 133 is operably coupled to a bias circuit (e.g., bias circuit 150 of FIG. 1) and may include a semiconductor device formed in the silicon substrate 102 or another silicon substrate. For example, if the semiconductor device is formed in the silicon substrate 102, the semiconductor device may include a transistor including a fin and / or gate electrode disposed on the upper surface 102u of the substrate, or may include a transistor including a fin and / or gate electrode disposed on the lower surface 102l of the substrate, in which case a through silicon via may extend through the substrate to facilitate the operably coupling.

[0021] 3A, in some embodiments, the germanium region 112 includes an upper germanium region 122 having a first p-type doping concentration, and an intermediate germanium region 124 having a second p-type doping concentration, and a third p-type doping concentration, or Intrinsic3A includes a bottom germanium region 130 that is (undoped) germanium. The second p-type doping concentration is lower than the first p-type doping concentration, and if a non-zero dopant level is present, the third p-type doping concentration is lower than the second p-type doping concentration. In some cases, the first, second, and / or third p-type doping concentrations are substantially uniform / constant over their respective depths in the top germanium region 122, middle germanium region 124, and bottom germanium region 130, while in other cases, these doping concentrations exhibit a pronounced "kink" or discontinuity at the top and bottom edges of each region shown in FIG. 3A. In other cases, the change in doping concentration is more gradual and / or continuous over the entire depth of the germanium region 112. In some embodiments, the sidewall germanium region 126 extends continuously along the outer wall of the germanium region 112 and across the top germanium region 122, the middle germanium region 124, and the bottom germanium region 130. The use of these doped regions, shown in Figure 3A, facilitates the lensing function of the SPAD device, helping to improve jitter performance, thereby allowing carriers to flow more efficiently to the pn junction 110.

[0022] FIG. 3B illustrates an example of a band diagram consistent with some embodiments of the SPAD device of FIG. 3A. The band diagram includes a conduction band 350 and a valence band 352, with the left portion of the band diagram corresponding to n-type material (e.g., n-type avalanche region 108) and the right portion of the band diagram corresponding to p-type material (e.g., p+ germanium). The Fermi level of the device is indicated by line 354. As shown, interface states and / or deep traps are placed near the silicon / germanium heterojunction at the interface between the absorption region 113 and the multiplication region 115, which cause discontinuities in the valence and conduction bands. In particular, the valence band includes an S-shaped curve at the multiplication region 115, exhibiting a steep (e.g., vertical) rise at the interface between the absorption region 113 and the multiplication region 115, followed by a "dip" in the absorption region before returning to the maximum valence band energy. The conduction band also includes an S-shaped curve in the multiplication region 115, but this time the top of the S-shaped curve corresponds to a peak or apex followed by a "dip" in the absorption region before returning to the maximum conduction band energy.

[0023] 4 and 5 illustrate some embodiments in which a first and a second SPAD device are arranged side-by-side with a silicon substrate. In FIG. 4 and 5, the first SPAD device 100a and the second SPAD device 100b each have the features described in FIG. 2, so that the features labeled a and b have the same or similar structure and function as those described in FIG. 2 (e.g., 102a and 102b in FIG. 4 and 5 correspond to 102 in FIG. 2, and 106a, 106b in FIG. 4 and 5 correspond to 106 in FIG. 2). Thus, in FIG. 4 and 5, the first n-type vertical connection region 116a laterally surrounds the germanium region 112a of the first SPAD device 100a, and the second n-type vertical connection region 116b laterally surrounds the germanium region 112b of the second SPAD device 100b. A portion of the silicon substrate 402 separates the first n-type vertical connection region 116a from the second n-type vertical connection region 116b. In the embodiment of FIG. 4, this portion of the silicon substrate Intrinsic 5, an isolation structure 502, e.g., a deep trench isolation structure made of a dielectric material or including p-type silicon, separates the first n-type vertical connection region 116a from the second n-type vertical connection region 116b. It should be understood that any number of SPAD devices can be arranged in a silicon substrate, e.g., in an array including any number of rows and columns. Also, although FIGS. 4 and 5 show an example in which the first SPAD device 100a and the second SPAD device 100b correspond to the SPAD device 100 of FIG. 2, in other embodiments, the first SPAD device 100a and the second SPAD device 100b can correspond to the SPAD device 100 of FIG. 1 or FIG. 3A, and / or other illustrated embodiments, and / or combinations thereof.

[0024] Figures 6 to 14 show manufacturing flows according to some embodiments. Although Figures 6 to 14 are described with respect to methods, the structures disclosed in Figures 6 to 14 are not limited to these methods and may stand alone as structures unrelated to the methods.

[0025] In FIG. 6, a base semiconductor substrate 600 is received and a sacrificial oxide 602 is formed on the top surface of the semiconductor substrate. In some embodiments, the base semiconductor substrate 600 is a single crystal silicon wafer, but in other embodiments, the semiconductor substrate may be in other forms. For example, the base semiconductor substrate 600 may be a silicon on insulator substrate, a sapphire substrate, or a III-V substrate, etc. The sacrificial oxide 602 may be silicon dioxide or other silicon oxides, such as silicon oxynitride. The sacrificial oxide 602 may be formed by thermal oxidation, rapid thermal annealing, plasma deposition, chemical vapor deposition, spin-on, or other techniques. In some embodiments, the sacrificial oxide 602 has a thickness ranging between 30 Angstroms and 300 Angstroms, or between 75 Angstroms and 120 Angstroms, or about 90 Angstroms.

[0026] 7, a blanket p-type implant, such as a boron, aluminum, or indium implant, is performed to form buried p-type region 138 in the semiconductor substrate. Then, with the first photoresist mask in place, an n-type implant, such as a phosphorus, arsenic, or antimony implant, is performed to form n-type avalanche region 108 and n-type lateral connection region 114.

[0027] In FIG. 8, in some cases, the sacrificial oxide is removed and an epitaxial single crystal silicon region 900 is epitaxially formed on the upper surface of the base semiconductor substrate 600, thereby providing a single crystal silicon substrate. In some embodiments, the removal of the sacrificial oxide and the epitaxial formation of the epitaxial single crystal silicon region 900 are performed in situ. The in situ process helps ensure that the semiconductor substrate is oxide-free, thus promoting high quality crystal growth with fewer or no defects. Then, another sacrificial oxide layer 902 is formed on the epitaxial single crystal silicon region 900. In some cases, the sacrificial oxide layer 902 is formed by an in-situ steam generation (ISSG) process, but may also be formed by thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), etc. In some embodiments, the sacrificial oxide layer 902 has a thickness in the range between 30 Angstroms and 300 Angstroms, or between 75 Angstroms and 120 Angstroms, or about 90 Angstroms.

[0028] 8, a second photoresist mask 1002 is then formed over the sacrificial oxide layer 902, and with the second photoresist mask in place, an n-type implant, such as a phosphorus, arsenic, or antimony implant, is performed to form the n-type vertical connection region 116. Although FIG. 8 shows the outer edges of the n-type vertical connection region 116 aligned with the outer edges of the n-type lateral connection region 114, in other embodiments there may be a small offset between these outer edges, so that the edges of the n-type lateral connection region 114 may be shifted to the left or right relative to the outer edges of the n-type vertical connection region 116.

[0029] In FIG. 9, an undoped silicate glass (USG) region is formed having a thickness ranging between, for example, 200 Å and 1200 Å. A third photoresist mask (not shown) is then formed and, with the third photoresist mask in place, an etch is performed to form a recess 104 in the upper surface of the silicon substrate 102. In one case, the recess 104 can have a depth d of about 1 μm. Another oxide layer 1102 may be formed, for example by in-situ steam generation (ISSG), having a thickness ranging between 500 Å and 1000 Å that lines up with the lower surface and sidewalls of the recess 104 and extends above the upper surface of the semiconductor substrate.

[0030] 10, a fourth photomask 1202 is formed to form p-type region 106. P-type region 106 is formed at a depth d below the recessed surface and has a spaced distance d between the p-type region and the recessed surface. Intrinsic Silicon areas can be left.

[0031] In FIG. 11, a p-type surface region 120 is formed in a semiconductor substrate, which forms a p-type region 106 above the p-type region 106. IntrinsicSilicon region 118 remains. Further, germanium region 112 is formed, for example by epitaxial growth. Germanium region 112 is formed to have an upper surface that is recessed below the upper surface of silicon substrate 102. However, in other embodiments, germanium region 112 may be formed to have an upper surface that is level with or elevated above the upper surface of silicon substrate 102. In some cases, germanium region 112 forms a thin alloy with the silicon substrate as germanium grows, so that the germanium region contacts silicon substrate 102 at a Ge-Si interface region. The Ge-Si interface region is defined where the outer sidewall and lower surface of the germanium region contact the inner sidewall and recessed upper surface of the silicon substrate, respectively.

[0032] In FIG. 12, a cap 128 is formed over the germanium region 112. The formation of the cap 128 can be by an epitaxial growth process and can be completed in situ (e.g., in the same tool as that used to form the germanium region 112, in a controlled environment such as vacuum or nitrogen) to limit oxidation of the germanium region 112. In some cases, the cap 128 can be epitaxially grown p-type single crystal silicon and can have an upper surface elevated above the upper surface of the substrate, although the upper surface of the cap can be level with or below the upper surface of the substrate. An oxide 1502 can then be formed over the cap 128, for example, via rapid thermal annealing or as a native oxide.

[0033] 13, another ion implantation process is performed to form p-type sidewall germanium regions 126. In some cases, prior to this ion implantation, another photomask is formed and then, with the photomask in place, this ion implantation is performed to form p-type sidewall germanium regions 126.

[0034] In FIG. 14, a dielectric structure 132 is formed on an upper surface of a silicon substrate 102. A contact opening is formed through the dielectric structure 132 and a conductive contact 134, such as a metal contact, and a metal line or conductive pad 136 is formed on the conductive contact. The metal line or conductive pad 136 may then be operably coupled to a bias circuit, which may include a semiconductor device formed on the silicon substrate 102 or formed on another semiconductor substrate. For example, if the semiconductor device is formed on a semiconductor substrate, the semiconductor device may include a transistor including a fin and / or gate electrode disposed on an upper surface of the substrate, or may include a transistor including a fin and / or gate electrode disposed on a lower surface of the substrate, in which case a through-silicon via may extend through the substrate to facilitate the operably coupling.

[0035] Figures 15-21 illustrate alternative fabrication flows according to some embodiments. In contrast to Figures 6-14, which show the formation of a single SPAD device, Figures 15-21 show first and second SPAD devices formed directly adjacent to one another. The structures disclosed in Figures 15-21 are not limited to these methods and may stand alone as method independent structures.

[0036] In FIG. 15 (which corresponds in some respects to FIGS. 6-8), a base semiconductor substrate 600 is received and a blanket p-type implant is used to form a buried p-type region 138 in the semiconductor substrate. An n-type lateral connection region 114 is also formed, for example by forming a photomask and performing an ion implant. An epitaxial single crystal silicon region 900 is formed on an upper surface of the base semiconductor substrate 600 to form an n-type vertical connection region 116. In this example, the first and second n-type vertical connection regions 116a, 116b are laterally spaced apart by an isolation region of the semiconductor substrate. A sacrificial oxide 1802 is formed on an upper surface of the epitaxial single crystal silicon region 900.

[0037] In FIG. 16 (which in some respects corresponds to FIG. 9), an undoped silicate glass (USG) region is formed having a thickness ranging between, for example, 200 Angstroms and 1200 Angstroms. A third photoresist mask 1902 is then formed, and with the third photomask in place, an etch is performed to form a recess 104 in the upper surface of the silicon substrate. In one case, the recess can have a depth d of about 1 μm. Another oxide layer 1102 may be formed, for example by in situ water vapor generation (ISSG), aligned with the lower surface and sidewalls of the recess.

[0038] In Figure 17 (which corresponds in some respects to Figure 11), p-type regions 106a, 106b, p-type sidewall portion 120a, and p-type base portion 120b are formed in a semiconductor substrate. The p-type regions 106a, 106b are formed to a depth d below the recessed surface such that there is a gap between the p-type regions and the recessed surface. Intrinsic Silicon regions 118a, 118b may remain.

[0039] In FIG. 18 (which again corresponds in some respects to FIG. 11), germanium regions 112a, 112b are formed, for example by epitaxial growth. The germanium regions are formed to have upper surfaces recessed below the upper surface of the silicon substrate. However, in other embodiments, the germanium regions may be formed to have upper surfaces level with or elevated above the upper surface of the silicon substrate. In some cases, the germanium regions 112a, 112b form a thin alloy with the silicon substrate as the germanium is grown, so that the germanium regions contact the silicon substrate 102 at a Ge-Si interface region. The Ge-Si interface region is defined where the outer sidewall and lower surface of the germanium regions meet the inner sidewall and recessed upper surface of the silicon substrate, respectively.

[0040] In Figure 19 (which corresponds in some respects to Figure 12), silicon caps 128a, 128b are formed over germanium regions 112a, 112b, respectively. Formation of the silicon caps can be by an epitaxial growth process and can be completed in situ (e.g., in a controlled environment such as vacuum or nitrogen in the same manner as the germanium regions were formed) to limit oxidation of the germanium regions. In some cases, the epitaxially grown silicon caps are p-type. An oxide can then be formed over the silicon caps, for example, via rapid thermal annealing or as a native oxide.

[0041] In Figure 20 (which corresponds in some respects to Figure 13), another ion implantation process is performed to form p-type germanium regions 126a, 126b. In some cases, this ion implantation is preceded by forming another photomask, and then the ion implantation is performed with the photomask in place.

[0042] In FIG. 21 (which corresponds in some respects to FIG. 14), a dielectric is formed on an upper surface of a substrate. Contact openings are formed through the dielectric and conductive contacts 134, e.g., metal contacts, and metal lines or conductive pads 136 are formed on the conductive contacts. The metal lines or conductive pads may then be operatively coupled to bias and quench circuits, which may include semiconductor devices formed in a silicon substrate or other semiconductor substrates. For example, if the semiconductor device is formed in a semiconductor substrate, the semiconductor device may include transistors including fins and / or gate electrodes disposed on an upper surface of the substrate, or may include transistors including fins and / or gate electrodes disposed on a lower surface of the substrate, in which case a through-silicon via may extend through the substrate to facilitate operative coupling. Thus, in FIG. 21, outer walls of the first and second n-type vertical connection regions 116a, 116b (e.g., guard rings) may be spaced apart from one another by isolation regions corresponding to portions of a semiconductor substrate, in the case of FIG. 21, monocrystalline silicon.

[0043] Figures 22 to 29 show alternative manufacturing flows according to some embodiments. Although Figures 22 to 29 are described with respect to methods, the structures disclosed in Figures 22 to 29 are not limited to these methods and may stand alone as structures unrelated to the methods.

[0044] Figures 22-28 are generally consistent with Figures 15-21 described above and show adjacent SPAD devices. However, in Figure 29 (continued from Figure 28), isolation structures 502 are formed from the lower surface of the semiconductor substrate to isolate adjacent SPAD devices from each other. In some cases, isolation structures 502 may be formed by forming a photomask on the lower surface of the semiconductor substrate, then etching to form trenches in the lower surface of the semiconductor substrate, and then filling the trenches with a dielectric material. In other cases, isolation structures 502 may be formed by implanting ions (e.g., p-type dopants) into the lower surface of the substrate.

[0045] FIG. 30 is a flow chart of a manufacturing flow according to some embodiments. Although the method 3300 is shown and described as a series of operations and events, it should be understood that the method is not limited by the order of these operations and events. For example, some operations may occur in different orders and / or simultaneously with other operations or events than those shown and / or described herein. Also, not all operations shown are necessarily required to implement one or more aspects or embodiments of the present specification. Moreover, one or more operations described herein may be performed in one or more separate operations and / or phases.

[0046] In act 3302, a semiconductor substrate is received.

[0047] In operation 3304, ion implantation is performed to form a lateral connection region below the upper surface of the semiconductor substrate.

[0048] In operation 3306, ion implantation is performed to form a vertical connection region. The vertical connection region and the lateral connection region contact each other to form a guard ring.

[0049] In operation 3308, a recess is formed in the upper surface of the semiconductor substrate, the recess being laterally surrounded by the guard ring and defined by a recessed upper surface of the semiconductor substrate and an interior sidewall of the semiconductor substrate.

[0050] In an operation 3310, a germanium region is formed in the recess.

[0051] Thus, some embodiments provide a single photon avalanche detector (SPAD) device. The device includes a silicon substrate including a recess in an upper surface. A p-type region is disposed in the silicon substrate below a lower surface of the recess. An n-type avalanche region is disposed in the silicon substrate below the p-type region and contacts the p-type region at a pn junction. A germanium region is disposed in the recess above the pn junction.

[0052] Another embodiment provides a semiconductor structure including a silicon substrate and a silicon-based multiplication region embedded in the semiconductor substrate. A germanium-based absorber region is embedded in the semiconductor substrate. The germanium-based absorber region is disposed above the silicon-based multiplication region. An electron channel is disposed between the silicon-based multiplication region and the germanium-based absorber region.

[0053] Yet another embodiment provides a method: receiving a semiconductor substrate; performing ion implantation to form a lateral connection region below an upper surface of the semiconductor substrate; performing ion implantation to form a vertical connection region; the vertical connection region and the lateral connection region contacting one another to form a guard ring; forming a recess in the upper surface of the semiconductor substrate, the recess being laterally surrounded by the guard ring and defined by a recessed upper surface of the semiconductor substrate and an interior sidewall of the semiconductor substrate; forming a germanium region in the recess.

[0054] Additionally, spatially relative terms such as "below," "downward," "lower," "upward," "above," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein may be similarly interpreted accordingly. [Industrial Applicability]

[0055] The semiconductor structures and methods of the present invention can be applied to Single Photon Avalanche Detector (SPAD) devices. [Explanation of symbols]

[0056] 100 SPAD devices 100a First SPAD device 100b Second SPAD device 102 Silicon structure 102l lower surface 102u top surface 104 Recess 106, 106a, 106b p-type region 108, 108a, 108b n-type avalanche region 110, 110a, 110b pn junction 112, 112a, 112b Germanium region 112ua, 112ub, 112ul top surface 113 Absorption Area 114, 114a, 114b n-type lateral connection region 115 Multiplication region 116 n-type vertical connection region 116a First n-type vertical connection region 116b 2nd n type vertical connection area 117 Ge-S interface region 118, 118a, 118b Intrinsic Silicon Region 120 p-type surface area 120a p type side wall part 120b p-type base part 120s side wall part 122 Upper Germanium Region 124 Intermediate Germanium Region 126 p-type sidewall germanium region 126a, 126b p-type germanium region 128 Cap 128a, 128b Silicone Cap 130 Bottom Germanium Region 132 Dielectric Structure 134 Conductive Contact 136 Metal wire or conductive pad 138 Buried p-type region 150 Bias Circuit 152 incident photon 350 Conduction band 352 Valence Band 354 Fermi Level 402 Silicon Structure 502 Isolation structure 600 Semiconductor Structure 602, 1802 Sacrificial oxide 900 Epitaxial single crystal silicon region 902 Sacrificial oxide layer 1002 Second photoresist mask 1102 Oxide layer 1202 4th Photomask 1502 Oxide 1902 3rd photoresist mask 3300 method 3302, 3304, 3306, 3308, 3310 operation d Depth h Height

Claims

1. a silicon substrate including a recess in an upper surface; a p-type region disposed within the silicon substrate below a lower surface of the recess; an n-type avalanche region disposed in the silicon substrate below the p-type region and contacting the p-type region at a pn junction; a germanium region disposed in the recess overlying the pn junction; Including, A single photon avalanche detector (SPAD) device further comprising disposing an intrinsic silicon region between an uppermost portion of the p-type region and a lower surface of the germanium region, the intrinsic silicon region being an undoped silicon region.

2. 2. The SPAD device of claim 1, wherein the germanium region contacts the silicon substrate at a Ge-Si interface region comprised of a Ge-Si alloy, the Ge-Si interface region being defined where an outer sidewall and a lower surface of the germanium region contact an inner sidewall and a recessed upper surface of the silicon substrate, respectively.

3. an n-type lateral connection region extending laterally from an outer edge of the n-type avalanche region past an outer wall of the germanium region; an n-type vertical connection region extending upwardly from an outer edge of the n-type lateral connection region to an upper surface of the silicon substrate; The SPAD device of claim 1 further comprising:

4. The SPAD device of claim 1 , wherein the intrinsic silicon region is configured to act as an electron channel extending the entire distance between the pn junction and the germanium region.

5. The germanium region is an upper germanium region having a first p-type doping concentration; a lower germanium region having a second p-type doping concentration; 2. The SPAD device of claim 1, comprising:

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