Semiconductor Device

Abstract

To provide a solid-state imaging device with short image-capturing duration.SOLUTION: A first photodiode in a pixel in an n-th row and an m-th column is connected to a second photodiode in a pixel in an (n+1)-th row and the m-th column through a transistor. The first photodiode and the second photodiode receive light concurrently, the potential in accordance with the amount of received light is held first in a pixel in the n-th row and the m-th column, and the potential in accordance with the amount of received light is held in a pixel in the (n+1)-th row and the m-th column without performing a reset operation. Then, each potential is read out. Under a large amount of light, either the first photodiode or the second photodiode is used.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device and a driving method thereof. The present invention relates to a solid-state imaging device having a plurality of pixels, and a driving method thereof. The present invention relates to an electronic device having an imaging device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. For example, one embodiment of the present invention is The present invention relates to a process, a machine, a manufactur- ing method, or a method of manufacture. The present invention relates to a structure or composition of matter. One aspect of the present invention relates to a storage device, a processor, a method for driving the same, or a method for manufacturing the same.

[0003] In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor characteristics. Therefore, semiconductor elements such as transistors and diodes and semiconductor circuits are considered semiconductor devices. In addition, the present invention relates to a display device, a light-emitting device, a lighting device, an electro-optical device, a solid-state imaging device, and an electronic The devices and the like may include semiconductor elements and semiconductor circuits. Illumination devices, electro-optical devices, solid-state imaging devices, electronic devices, etc. also include semiconductor devices. There is. [Background technology]

[0004] CMOS sensors, which use the amplification function of MOS transistors, are a general-purpose photo sensor. Therefore, it is possible to manufacture the CMOS sensor in each pixel. This not only reduces the manufacturing cost of solid-state imaging devices, but also allows the photosensor and display element to be fabricated on the same substrate. In addition, the CMOS sensor has a smaller number of pixels than the CCD sensor. Since the driving voltage is low in all cases, the power consumption of the solid-state imaging device can be reduced.

[0005] In a solid-state imaging device using a CMOS sensor, when capturing an image, the charge in the photodiode The charge accumulation operation and the charge readout operation are performed row by row in sequence using a rolling shutter method. In addition, instead of the rolling shutter method, The global shutter method is used, in which charge accumulation is performed simultaneously on all pixels. In some cases, this is the case (see Non-Patent Document 1). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2009-141717 A [Non-patent literature]

[0007] [Non-Patent Document 1] M. Furuta et al, “A High-Speed, High-Sensitivity Digital CMOS Image Sensor With a Global Shutter and 12-bit Column-Parallel Cyclic A / D Converters”, IEEE Journal of Solid-State Circuits, April 2007, Vol. 42, No. 4, pp. 766-774 Summary of the Invention [Problem to be solved by the invention]

[0008] Regardless of whether it is a rolling shutter type or a global shutter type, it uses a CMOS sensor. In order to enable imaging under various environments, solid-state imaging devices have a wide dynamic range. There is a demand for improved image quality and shorter image capture intervals during continuous shooting.

[0009] For example, imaging in environments with low external light (such as at night or in a dark room) requires a photodiode. Since the light irradiated to the object is weak (low amount of light), the exposure time must be long. If the subject moves within the light period or if the solid-state imaging device is moved, the image will be distorted. Therefore, a longer exposure time results in a distorted image of the subject. There is a risk of forming image data.

[0010] In addition, as solid-state imaging devices become smaller, the area irradiated by light from the photodiode becomes smaller. This makes imaging even more difficult in environments with low external light intensity.

[0011] In addition, when capturing images of a fast-moving subject in succession, the image capturing interval should be made shorter. It is necessary.

[0012] In addition, low power consumption is also an important characteristic required for evaluating the performance of solid-state imaging devices. In particular, in portable electronic devices such as mobile phones, the power consumption of solid-state imaging devices is The high temperature leads to the disadvantage of shorter continuous use time.

[0013] One embodiment of the present invention provides a solid-state imaging device capable of improving the dynamic range. Another object of the present invention is to provide a method for improving the quality of a captured image. Another object of the present invention is to provide a solid-state imaging device or the like capable of achieving high-quality imaging. Another object of the present invention is to provide a solid-state imaging device or the like having a short pixel spacing. Another object of the present invention is to provide a solid-state imaging device or the like that consumes less power. An object of one embodiment is to provide a novel semiconductor device or the like.

[0014] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0015] One aspect of the present invention is a semiconductor device including a first circuit, a second circuit, and a sixth transistor. A method for driving a body device, comprising a first step, a second step, and a third step, and a fourth step, the first circuit includes a first photoelectric conversion element and a first transistor. the second circuit has a second photoelectric conversion element and a fourth transistor; a first photoelectric conversion element including a first transistor and a fifth transistor, and electrically connected to one of the source and drain of the first transistor. The other of the drains is electrically connected to one of the source and drain of the second transistor. The other of the source and the drain of the second transistor is electrically connected to the first node. a gate of the third transistor electrically connected to the first node; The element is electrically connected to one of the source and drain of the fourth transistor. The other of the source and the drain of the transistor is electrically connected to the second node, and The gate of the first transistor is electrically connected to the second node, and the source of the sixth transistor is Either the source or the drain of the second transistor is electrically connected to either the source or the drain of the second transistor. The other of the source and drain of the sixth transistor is connected to the fourth transistor. In the first step, the first transistor is electrically connected to one of the source and drain of the first transistor. The second transistor and the fourth transistor are in an off state, and in the first step, The second transistor and the sixth transistor are in an on-state, and in the first step, A first potential corresponding to the amount of light received by the photoelectric conversion element is written to the first node, and a second step In the step, the first and second transistors are in an off state, and in the second step, The fourth transistor and the sixth transistor are in an on state, and in the second step A second potential corresponding to the amount of light received by the second photoelectric conversion element is written to the second node, and a third switch is In the step, information according to the first potential is read out through a third transistor, In step 4, information according to the second potential is read out through the fifth transistor. The third and fourth steps are carried out after the first and second steps are completed. The present invention is characterized in that the above-mentioned is carried out in a time period of 100 minutes.

[0016] The first transistor is preferably a transistor including an oxide semiconductor. The second transistor and the fourth transistor are transistors including an oxide semiconductor. In addition, the sixth transistor is preferably a transistor including an oxide semiconductor. It is preferable to use a stencil.

[0017] The first photoelectric conversion element and the second photoelectric conversion element are photoelectric conversion elements having pin-type junctions. It can be used. Effect of the Invention

[0018] According to one embodiment of the present invention, there is provided a solid-state imaging device having an improved dynamic range. Alternatively, it is possible to provide a solid-state imaging device or the like that can improve the quality of captured images. Alternatively, a solid-state imaging device with a short imaging interval can be provided. It is possible to provide a solid-state imaging device with low power consumption. etc. can be provided.

[0019] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. Effects other than these may also be included. The above is self-evident from the description, drawings, claims, etc. Other effects can be extracted from the claims and other descriptions. [Brief description of the drawings]

[0020] [Figure 1] 1A and 1B illustrate a configuration example of an imaging device of one embodiment of the present invention. [Diagram 2] 1A to 1C are diagrams illustrating an example of the configuration of a pixel. [Diagram 3] 1A to 1C are diagrams illustrating an example of the configuration of a pixel. [Figure 4] 1A to 1C are diagrams illustrating an example of the configuration of a pixel. [Diagram 5] FIG. 2 illustrates an example of a circuit configuration of a pixel. [Figure 6] 4 is a timing chart illustrating an example of an imaging operation. [Figure 7] FIG. 4 is a circuit diagram illustrating an example of an imaging operation. [Figure 8] FIG. 4 is a circuit diagram illustrating an example of an imaging operation. [Figure 9] FIG. 4 is a circuit diagram illustrating an example of an imaging operation. [Figure 10] 4 is a timing chart illustrating an example of an imaging operation. [Figure 11] FIG. 4 is a circuit diagram illustrating an example of an imaging operation. [Figure 12] FIG. 4 is a circuit diagram illustrating an example of an imaging operation. [Figure 13] FIG. 2 illustrates an example of a circuit configuration of a pixel. [Figure 14] FIG. 2 illustrates an example of a circuit configuration of a pixel. [Figure 15] 1A and 1B illustrate a configuration example of an imaging device of one embodiment of the present invention. [Figure 16] FIG. 2 illustrates an example of a circuit configuration of a pixel. [Figure 17] 4 is a timing chart illustrating an example of an imaging operation. [Figure 18] FIG. 4 is a circuit diagram illustrating an example of an imaging operation. [Figure 19] FIG. 4 is a circuit diagram illustrating an example of an imaging operation. [Figure 20] FIG. 4 is a circuit diagram illustrating an example of an imaging operation. [Figure 21] FIG. 4 is a circuit diagram illustrating an example of an imaging operation. [Figure 22] FIG. 2 illustrates an example of a circuit configuration of a pixel. [Diagram 23] FIG. 1 is a diagram illustrating an example of the configuration of an imaging apparatus. [Figure 24] 1A to 1C illustrate an example of a transistor. [Diagram 25] FIG. 2 is a diagram for explaining an energy band structure. [Figure 26] 1A to 1C illustrate an example of a transistor. [Figure 27] FIG. 2 illustrates an example of a circuit configuration. [Figure 28] FIG. 2 illustrates an example of a circuit configuration. [Figure 29] FIG. 2 illustrates an example of a circuit configuration. [Diagram 30] 1A to 1C illustrate one embodiment of a transistor. [Diagram 31] 1A to 1C illustrate one embodiment of a transistor. [Diagram 32] 1A to 1C illustrate one embodiment of a transistor. [Diagram 33] 1A to 1C illustrate one embodiment of a transistor. [Diagram 34]1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. [Diagram 35] 1A and 1B are a photograph and a block diagram of a solid-state imaging device according to an embodiment. [Diagram 36] 2A to 2C are diagrams for explaining the specifications of a solid-state imaging element according to an embodiment. [Figure 37] FIG. 2 is a circuit diagram of a pixel included in the solid-state imaging device according to the embodiment. [Figure 38] 4 is a timing chart for explaining an imaging operation of the solid-state imaging element according to the embodiment. [Figure 39] 4A to 4C are diagrams for explaining an imaging operation of the solid-state imaging element according to the embodiment. [Diagram 40] 4 is a photograph of a subject captured by the solid-state imaging device according to the embodiment. [Diagram 41] FET Vg-Id characteristics and noise characteristics. [Diagram 42] FIG. 2 is a pixel layout diagram of a solid-state imaging element according to an embodiment. [Diagram 43] FIG. 13 is a diagram showing measurement results of a peripheral circuit according to an embodiment. [Diagram 44] 1A and 1B are a photograph showing the appearance of a solid-state imaging device and a diagram showing a layered structure of the solid-state imaging device. [Diagram 45] FIG. 1 is a block diagram showing a circuit configuration of a solid-state imaging device. [Diagram 46] FIG. 2 is a diagram showing the specifications of a solid-state imaging device. [Figure 47] FIG. 2 is a diagram showing a circuit configuration of a pixel. [Figure 48] A photograph taken with a solid-state imaging device. [Figure 49] A histogram of the gradation of a captured image. [Figure 50] Histograms of the gradation difference for each pixel using different imaging methods. [Figure 51] Histograms of the gradation difference for each pixel using different imaging methods. [Figure 52] The standard deviation of the gradation difference between two different frames out of five frames for each imaging method. [Figure 53] The exterior of the fan and a photograph of the fan rotating at high speed. [Figure 54] Power consumption measurement results. [Figure 55] 1A and 1B are a photograph showing the external appearance of a solid-state imaging device and an enlarged photograph of a pixel of the solid-state imaging device. [Figure 56] FIG. 2 is a diagram showing the specifications of a solid-state imaging device. [Figure 57] A photograph taken with a solid-state imaging device. [Figure 58] 1A and 1B are a block diagram of an optical flow system and a photograph showing the appearance of a solid-state imaging device. [Figure 59] FIG. 1 is a block diagram showing a circuit configuration of a solid-state imaging device. [Figure 60] FIG. 2 is a diagram showing the specifications of a solid-state imaging device. [Figure 61] FIG. 2 is a diagram showing a circuit configuration of a pixel. [Figure 62] 4 is a timing chart for explaining an imaging operation of the solid-state imaging element according to the embodiment. [Figure 63] FIG. [Figure 64] A photograph taken with a solid-state imaging device. [Figure 65] A photograph taken with a solid-state imaging device. [Figure 66] A photograph taken with a solid-state imaging device. [Figure 67] 11A and 11B are diagrams showing the measurement results of power consumption and energy consumption of a solid-state imaging device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. The present invention is not limited to the description of the following embodiments. In addition, in all the drawings for explaining the embodiment, the same parts or the same Parts having similar functions are given the same reference numerals, and repeated explanations thereof may be omitted. .

[0022] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wire." In addition, the term "electrode" or "wiring" may be used to refer to the plural "electrodes" or "wirings". This also includes cases where the "line" is formed as a single unit.

[0023] For example, in the present specification, it is explicitly stated that X and Y are connected. The cases are when X and Y are electrically connected and when X and Y are functionally connected. The case where X and Y are directly connected and the case where X and Y are directly connected are both considered to be disclosed in this specification. Therefore, the present invention is not limited to a specific connection relationship, for example, a connection relationship shown in a drawing or a sentence. Connections other than those shown in the drawings or text are also included in the drawings or text. Let us assume that.

[0024] Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). , etc.).

[0025] An example of a direct connection between X and Y is The elements that function as When a diode, display element, light-emitting element, load, etc. is not connected between X and Y, An element (e.g., a switch, transistor, or capacitor) that allows electrical connection between X and Y. (capacitor, inductor, resistor, diode, display element, light-emitting element, load, etc.) In this case, X and Y are connected.

[0026] An example of the case where X and Y are electrically connected is The elements that function as One or more diodes, display elements, light-emitting elements, loads, etc.) are connected between X and Y. The switch has a function of being controlled to be on and off. A switch can be in a conductive state (on) or a non-conductive state (off) to allow current to flow. The switch has the function of controlling whether or not current flows. When X and Y are electrically connected, X This also includes the case where and Y are directly connected.

[0027] An example of a case where X and Y are functionally connected is a case where a functional connection between X and Y is possible. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the potential level of signals, etc.) , voltage sources, current sources, switching circuits, amplifier circuits (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more external circuits (e.g., a memory circuit, a control circuit, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X If X is transmitted to Y, then X and Y are considered to be functionally connected. When X and Y are functionally connected, there is a direct connection between X and Y and a direct connection between X and Y. and the case where they are electrically connected to each other.

[0028] In addition, if it is explicitly stated that X and Y are electrically connected, When X and Y are electrically connected (i.e., when there is another element or circuit between X and Y), When X and Y are functionally connected (i.e., when X and Y are (X and Y are connected functionally with another circuit between them) and (X and Y are connected directly (i.e., when X and Y are connected without any other element or circuit between them) In other words, it is assumed that the above is disclosed in the present specification. If it is explicitly stated that it is connected, The same contents as those in the above case are deemed to be disclosed in the present specification, etc.

[0029] For example, the source (or the first terminal, etc.) of the transistor is connected via Z1 (or The drain (or second terminal, etc.) of the transistor is electrically connected to Z 2 (or not), it may be electrically connected to Y, or the source of the transistor (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. and another part of Z2 is directly connected to Y, It is possible to do so.

[0030] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor The terminals of the transistor (or the first terminal, etc.) are electrically connected to each other, and X, the source of the transistor (or the first terminal, etc.) 1 terminal, etc.), the drain (or second terminal, etc.) of the transistor, and Y. "The source (or the third) of the transistor is connected to the The drain (or second terminal, etc.) of the transistor is electrically connected to X. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Alternatively, "X is the source (or first terminal, etc.) of a transistor. The transistor is electrically connected to Y via a drain (or a second terminal, etc.) and a transistor is electrically connected to X via a drain (or a second terminal, etc.). The source (or first terminal, etc.) of a resistor, the drain (or second terminal, etc.) of a transistor ), Y is provided in this connection order. By using a simple expression method and specifying the order of connections in the circuit configuration, Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined based on the above.

[0031] Or, as another way of expressing it, for example, "the source (or first terminal, etc.) of a transistor is electrically connected to X through at least a first connection path, and the first connection path is , the second connection path does not have a second connection path, and the second connection path is a transistor The source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor The first connection path is a path via Z1, and the second connection path is a path between the transistor The drain (or second terminal, etc.) of the capacitor is electrically connected to Y through at least a third connection path. The third connection path does not include the second connection path, and the third connection path The connection path is the path through Z2. The source (or the first terminal, etc.) of the resistor is connected to the resistor via Z1 by at least the first connection path. and X is electrically connected to the first connection path, and the first connection path does not have a second connection path; The second connection path includes a connection path through a transistor, and the second connection path includes a drain of the transistor. (or the second terminal, etc.) is connected to Y via Z2 by at least a third connection path. The third connection path does not have the second connection path. Alternatively, the source (or the first terminal, etc.) of the transistor may be at least The first electrical path is electrically connected to X through Z1, and the first electrical path is The primary path does not have a second electrical path, and the second electrical path is a From the source (or first terminal, etc.) to the drain (or second terminal, etc.) of the transistor The drain (or second terminal, etc.) of the transistor is connected to at least a third The third connection path is electrically connected to Y through Z2 by an electrical path of The fourth electrical path does not include the fourth connection path, and the fourth electrical path is a drain of a transistor. (or second terminal, etc.) to the source (or first terminal, etc.) of the transistor. Using the same expression as these examples, the circuit configuration By defining the connection path in Distinguish between the first terminal (or the first terminal, etc.) and the drain (or the second terminal, etc.) to determine the technical scope. can be done.

[0032] Note that these expression methods are merely examples, and the present invention is not limited to these expression methods. , Y, Z1, and Z2 are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layer, etc.).

[0033] In addition, the circuit diagram shows independent components as if they are electrically connected to each other. Even if the components are the same, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film has the function of the wiring and The electrode functions as both components. The term "electrochemically connected" refers to a case where one conductive film has the functions of multiple components. This also falls within the scope of the above.

[0034] In this specification and the like, transistors can be formed using various substrates. The type of substrate is not limited to a specific one. An example of the substrate is a semiconductor substrate. Substrates (e.g. single crystal substrates or silicon substrates), SOI substrates, glass substrates, quartz substrates, Includes plastic substrates, metal substrates, stainless steel substrates, and stainless steel foil. Substrates for bonding, tungsten substrates, substrates with tungsten foil, flexible substrates, bonding Examples include laminated films, paper containing fibrous materials, and base films. Examples include barium borosilicate glass, aluminoborosilicate glass, or soda lime glass. An example of a flexible substrate is polyethylene terephthalate (PET). ), polyethylene naphthalate (PEN), and polyethersulfone (PES). The materials used are plastics that can be used for bonding, and synthetic resins that have flexibility, such as acrylic. Examples of films include vinyl, such as polyvinyl fluoride or polyvinyl chloride, polypropylene, Examples of the base film include polyester, polyamide, etc. In particular, semiconductor substrates, single crystal By manufacturing transistors using a substrate or SOI substrate, the characteristics, size, etc. A small-sized transistor with little variation in size or shape, high current capability, and When a circuit is constructed using such transistors, the circuit can be manufactured with low power consumption. This allows for reduced power consumption or higher circuit integration.

[0035] Note that a transistor is formed using a certain substrate and then transferred to another substrate. However, the transistor may be disposed on another substrate. In addition to the substrate on which the above-mentioned transistors can be formed, the substrates include paper substrates, cellophane substrates, and the like. substrates made of natural fibers (silk, cotton, hemp), synthetic fibers (nylon, Polyurethane, polyester) or regenerated fiber (acetate, cupra, rayon, regenerated These substrates include raw polyester, leather substrates, and rubber substrates. By using this, it is possible to form transistors with good characteristics and transistors with low power consumption. It is possible to manufacture devices that are less likely to break, are heat resistant, or are lighter or thinner.

[0036] In addition, the position, size, range, etc. of each component shown in the drawings are for the purpose of facilitating understanding of the invention. Therefore, the actual location, size, range, etc. may not be shown. The invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings. For example, In the actual manufacturing process, resist masks, etc., may be unintentionally damaged by etching or other processes. However, in order to make it easier to understand, these may be omitted.

[0037] In order to make the drawings easier to understand, especially in top views (also called "plan views"), Some components may be omitted. Also, some hidden lines may be omitted. There is a match.

[0038] In this specification, the terms "above" and "below" refer to the positional relationship of components directly above or below each other. For example, "the electrode on insulating layer A is directly in contact with the insulating layer A" is not limited to the above. If the expression is "electrode B", it is not necessary for electrode B to be formed directly on insulating layer A. The inclusion of other components between the edge layer A and the electrode B is not excluded.

[0039] The source and drain functions may also be different in some cases, such as when transistors of different polarities are used, or when When the direction of the current changes during operation of the circuit, the two are interchangeable depending on the operating conditions. Therefore, it is difficult to determine which is the source and which is the drain. In this specification, the terms source and drain may be used interchangeably. It shall be so.

[0040] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Straight" and "orthogonal" mean that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it includes the case where the angle is between 85° and 95°.

[0041] Also, a voltage is a potential and a reference potential (for example, a ground potential (GND potential) or a source potential). Therefore, voltage can be replaced with potential. be.

[0042] Even if a material is described as a "semiconductor," if its electrical conductivity is sufficiently low, it may be considered an "insulator." Therefore, it is possible to use "semiconductor" as "insulator". In this case, the boundary between "semiconductor" and "insulator" is unclear, and it is difficult to make a strict distinction between the two. Therefore, the terms "semiconductor" and "insulator" in this specification can be read interchangeably. There may be cases where this is possible.

[0043] In addition, even if a material is written as a "semiconductor," if the material has a sufficiently high electrical conductivity, it should be written as a "conductor." Therefore, it is possible to use "semiconductor" as "conductor". In this case, the boundary between "semiconductor" and "conductor" is vague, and it is difficult to make a strict distinction between the two. Therefore, the terms "semiconductor" and "conductor" in this specification can be read interchangeably. There may be cases where this is possible.

[0044] The impurities in a semiconductor are, for example, those other than the main components that make up the semiconductor. For example, Elements with less than 0.1 atomic percent can be considered impurities. The conductor's DOS (Density of State) increases and the carrier mobility In some cases, the semiconductor may become an oxide semiconductor, or the crystallinity may decrease. In the case of a semiconductor, impurities that change the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Elements, Group 14 elements, Group 15 elements, transition metals other than the main component, etc., in particular, for example, Hydrogen (also found in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen In the case of oxide semiconductors, for example, oxygen vacancies are formed due to the inclusion of impurities such as hydrogen. In addition, if the semiconductor is a silicon film, there may be a defect that changes the properties of the semiconductor. The pure substances include, for example, oxygen, Group 1 elements excluding hydrogen, Group 2 elements, Group 13 elements, and Group 1 elements. Group 5 elements, etc.

[0045] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. It does not indicate any order or ranking, such as the order of processes or stacking. In addition, even if a term is not accompanied by an ordinal number in this specification, etc., it is possible to confuse the constituent elements. In order to avoid this, ordinal numbers may be used in the claims. Even if a term has an ordinal number in the specification, a different ordinal number may be used in the claims. In addition, even if a term is given an ordinal number in this specification, In patent claims, ordinal numbers may be omitted.

[0046] Note that the "channel length" refers to, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is on, the gate electrode overlaps with the semiconductor (the part through which current flows). The source (source region or source electrode) in the region where the channel is formed The distance between the drain and the transistor (the drain region or the drain electrode). In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. In the detailed description, the channel length is any one value or the maximum value in the region where the channel is formed. , the minimum or average value.

[0047] Also, the "channel width" refers to, for example, the width of a semiconductor (or a semiconductor transistor when it is in the on state). The area where the gate electrode overlaps with the conductor (the part of the conductor where the current flows), or the channel is formed. The length of the part where the source and drain face each other in the region where the source and drain are connected. In a transistor, the channel width does not necessarily have the same value in all regions. That is, the channel width of a transistor may not be fixed to a single value. In this specification, the channel width is any one of the values ​​in the region where the channel is formed, This can be the maximum, minimum or average value.

[0048] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may vary. The effective channel width (hereinafter referred to as the effective channel width) shown in the top view of the transistor The channel width (hereinafter referred to as the apparent channel width) may be different. For example, In a transistor having a three-dimensional structure, the effective channel width is The effect of the channel width becomes larger than the apparent channel width shown in For example, in a transistor with a fine, three-dimensional structure, The percentage of the channel region that is formed on the side of the semiconductor, compared to the percentage of the channel region that is formed In that case, the apparent channel width shown in the top view may be larger. In this case, the effective channel width where the channel is actually formed is larger than the width of the channel formed by the MOSFET.

[0049] By the way, in a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order to obtain this, it is necessary to assume that the shape of the semiconductor is known. Unless k is precisely known, it is difficult to measure the effective channel width accurately.

[0050] Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are overlapped. The apparent channel length is the length of the area where the source and drain face each other. The width of the channel is called the surrounded channel width (SCW). In this specification, when simply referred to as channel width, may refer to enclosed channel width or apparent channel width. In this document, when the term "channel width" is used, it may refer to the effective channel width. Channel length, channel width, effective channel width, apparent channel width, enclosure channel The channel width, etc., can be determined by acquiring cross-sectional TEM images and analyzing those images. A value can be determined.

[0051] In addition, the field effect mobility of the transistor and the current value per channel width are calculated. In some cases, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0052] In addition, in this specification, a high power supply potential VDD (hereinafter, simply referred to as "VDD" or "H potential") The low power supply potential VSS is a power supply potential that is higher than the low power supply potential VSS. VSS (hereinafter simply referred to as "VSS" or "L potential") is the potential lower than the high power supply potential VDD. The lowest power supply potential is also referred to as VDD or VSS. For example, if VDD is at ground potential, VSS is at a potential lower than ground potential, and V When SS is at ground potential, VDD is at a potential higher than ground potential.

[0053] (Embodiment 1) In this embodiment, an imaging device of one embodiment of the present invention will be described with reference to drawings.

[0054] [Configuration example of imaging device 100] FIG. 1A is a plan view illustrating a configuration example of an imaging device 100 according to an embodiment of the present invention. 100 includes a pixel section 110, a first peripheral circuit 260 for driving the pixel section 110, and a second peripheral circuit 260 for driving the pixel section 110. The pixel section includes a first peripheral circuit 270, a second peripheral circuit 280, and a fourth peripheral circuit 290. 110 is a matrix of p rows and q columns (p and q are natural numbers of 2 or more). The first peripheral circuit 260 to the fourth peripheral circuit 290 include a plurality of pixels 111. 1 and has a function of supplying signals for driving a plurality of pixels 111. In the specification, the first peripheral circuit 260 to the fourth peripheral circuit 290 are referred to as "peripheral circuits." For example, the first peripheral circuit 260 is one of the peripheral circuits. It can be said to be a club.

[0055] The peripheral circuits include at least a logic circuit, a switch, a buffer, an amplifier, or a converter. The peripheral circuits may be formed on the substrate on which the pixel section 110 is formed. In addition, a part or the whole of the peripheral circuits may be implemented as semiconductor devices such as ICs. At least one of the first peripheral circuit 260 to the fourth peripheral circuit 290 may be omitted. For example, the function of either the first peripheral circuit 260 or the fourth peripheral circuit 290 may be changed to that of the first peripheral circuit 260 or the fourth peripheral circuit 290. In addition to the other of the first peripheral circuit 260 or the fourth peripheral circuit 290, Alternatively, one of the fourth peripheral circuits 290 may be omitted. The functions of either the second peripheral circuit 270 or the third peripheral circuit 280 are assigned to either the second peripheral circuit 270 or the third peripheral circuit 280. In addition to the other side circuit 280, one of the second peripheral circuit 270 or the third peripheral circuit 280 For example, the first peripheral circuit 260 to the fourth peripheral circuit 290 may be omitted. The functions of the other circuits are added to any one of the first peripheral circuit 260 to the fourth peripheral circuit 290 may be omitted.

[0056] As shown in FIG. 1B, in the pixel section 110 of the imaging device 100, the pixel 11 By arranging the pixels 111 at an angle, the row direction and the column direction This allows the pixel interval (pitch) of the image captured by the image capture device 100 to be shortened. This can improve the quality of the captured images.

[0057] [Example of pixel 111 configuration] The imaging device 100 has a pixel 111 that is composed of a plurality of sub-pixels 112. The pixel 112 is combined with a filter (color filter) that transmits light of a specific wavelength band. By this, it is possible to obtain information for realizing a color image display.

[0058] FIG. 2A is a plan view showing an example of a pixel 111 for acquiring a color image. The pixel 111 shown in (A) is provided with a color filter that transmits light in the red (R) wavelength band. The subpixel 112 (hereinafter also referred to as "subpixel 112R") transmits light in the green (G) wavelength band. A subpixel 112 (hereinafter also referred to as "subpixel 112G") is provided with a color filter that transmits light through the and a sub-pixel 112 (hereinafter referred to as The subpixel 112 has a pixel region 112B, which can function as a photosensor. Cut.

[0059] The subpixels 112 (subpixels 112R, 112G, and 112B) are connected to the wiring 131. , and are electrically connected to the wiring 141, the wiring 144, the wiring 146, and the wiring 135. The pixel 112R, the subpixel 112G, and the subpixel 112B are each connected to an independent wiring 137. In this specification, for example, the wiring connected to the pixel 111 in the nth row 144 and wiring 146 will be referred to as wiring 144[n] and wiring 146[n], respectively. For example, the wiring 137 connected to the pixel 111 in the mth column is referred to as wiring 137[m]. In FIG. 2A, the sub-pixel 112R of the pixel 111 in the m-th column is connected to The wiring 137 is connected to the wiring 137[m]R, and the wiring 137 connected to the subpixel 112G is connected to the wiring 137[ The wiring 137 connected to the subpixel 112B is indicated as wiring 137[m]G, and the wiring 137 connected to the subpixel 112B is indicated as wiring 137[m]B. The subpixel 112 is electrically connected to the peripheral circuitry via the wiring.

[0060] In addition, the imaging device 100 according to the present embodiment detects light of the same wavelength band from adjacent pixels 111. The sub-pixels 112 are provided with color filters that transmit light, and are connected via switches. In Figure 2(B), there is a matrix with n rows (n is a natural number between 1 and p) and m columns (m is a natural number between 1 and q). The pixel 111 has a sub-pixel 112 arranged in a pixel 111 arranged in a pixel array (n+1 rows and m columns) adjacent to the pixel 111. 2B shows an example of a connection between the sub-pixels 112 of the pixel 111 arranged in the n The sub-pixel 112R arranged in row m and column m and the sub-pixel 112R arranged in row (n+1) and column m are switched. The sub-pixels 112G and 112C are connected to each other via a switch 201. The subpixel 112G arranged in the +1 row and the m column is connected via the switch 202. , the sub-pixel 112B arranged in the nth row and the mth column, and the sub-pixel 112B arranged in the n+1th row and the mth column are They are connected via a switch 203 .

[0061] The color filters used for the subpixels 112 are not limited to red (R), green (G), and blue (B). As shown in FIG. 3(A), the colors cyan (C), yellow (Y) and magenta (M) are A color filter that transmits light may be used. By providing sub-pixels 112 that detect light in the 1000-nm range, a full-color image can be obtained. .

[0062] FIG. 3B shows color filters that transmit red (R), green (G), and blue (B) light, respectively. In addition to the sub-pixel 112 in which the color filter 111 is provided, a color filter that transmits yellow (Y) light is provided. FIG. 3(C) illustrates a pixel 111 having a subpixel 112 with a cyan (C A subpixel 11 is provided with a color filter that transmits yellow (Y) and magenta (M) light. In addition to the pixel 2, the pixel 112 has a color filter that transmits blue (B) light. The pixel 111 is illustrated. One pixel 111 detects light of four different wavelength bands. By providing the sub-pixels 112, the color reproducibility of the acquired image can be further improved.

[0063] For example, in FIG. 2A, a sub-pixel 112 detects a red wavelength band, The ratio of the number of sub-pixels 112 that detect the blue wavelength band to the number of sub-pixels 112 that detect the red wavelength band (or The ratio of the light receiving area (or the light receiving area ratio) does not necessarily have to be 1:1:1. As shown in FIG. 3(D), A Bayer array in which the pixel number ratio (light receiving area ratio) is red:green:blue=1:2:1 may also be used. The pixel number ratio (light receiving area ratio) may be red:green:blue=1:6:1.

[0064] The number of sub-pixels 112 provided in the pixel 111 may be one, but it is preferable that the number is two or more. By providing two or more sub-pixels 112 that detect the same wavelength band, redundancy is increased, and the imaging device This can improve the reliability of the device 100.

[0065] In addition, it acts as a filter by absorbing or reflecting light with wavelengths shorter than the wavelength of visible light, and by blocking infrared light. By using an IR (IR: Infrared) filter that transmits infrared light, infrared light is detected. The imaging device 100 can be realized. In addition, the filter can be used to detect wavelengths longer than the wavelength of visible light. UV (Ultra Viol) et) By using a filter, it is possible to realize an imaging device 100 that detects ultraviolet light. In addition, a scintillator that converts radiation into ultraviolet light or visible light is used as a filter. In this way, the imaging device 100 can function as a radiation detector for detecting X-rays, gamma rays, etc. can.

[0066] In addition, ND (Neutral Density) filters (light reducing filters) are also available. When a large amount of light is incident on the photoelectric conversion element (light receiving element), This can prevent the phenomenon of output saturation (hereinafter also referred to as "output saturation"). By combining ND filters with different amounts of light, the dynamic range of the imaging device can be expanded. It can be made bigger.

[0067] In addition to the above-mentioned filter, a lens may be provided in the pixel 111. An example of the arrangement of the pixel 111, the filter 602, and the lens 600 will be described with reference to a plan view. By providing 600, the incident light can be efficiently received by the photoelectric conversion element 220. Specifically, as shown in FIG. 4A, a lens 600 and a filter 602 (filter 602R, filter 602G, filter 602B), and pixel circuit 23 0 or the like, light 660 can be made incident on the photoelectric conversion element 220.

[0068] However, as shown in the area surrounded by the two-dot chain line, a part of the light 660 indicated by the arrow is reflected by the wiring layer 604. Therefore, as shown in Fig. 4(B), the light is blocked by a part of the A lens 600 and a filter 602 are formed on the conversion element 220 side to convert incident light into a photoelectric conversion element A structure that efficiently receives light from the photoelectric conversion element 220 is preferable. By doing so, it is possible to provide the imaging device 100 with high detection sensitivity.

[0069] [Example of circuit configuration of subpixel 112] Next, a specific example of the circuit configuration of the subpixel 112 will be described with reference to the circuit diagram of FIG. 5, a sub-pixel 112[n] of the pixel 111 in the nth row and a sub-pixel 112[n] of the pixel 111 in the n+1th row are A circuit configuration in which the subpixel 112[n+1] corresponding to the pixel 112 is electrically connected via a transistor 129 For example, the transistor 129 is connected to the switch 201, the switch 202, or the switch 2 It can function as 03.

[0070] Specifically, the sub-pixel 112[n] of the pixel 111 in the nth row has a photodiode PD [n] (photoelectric conversion element), transistor 121, transistor 123, and transistor In addition, the pixel 111 in the n+1th row includes a sub-pixel 112[n +1] is a photodiode PD[n+1], a transistor 125, and a transistor 127. , and a transistor 128.

[0071] In this embodiment, the transistors 121 to 129 are n-channel transistors. The case where transistors are used will be described as an example. In the case of 9, when the signal supplied to the gate is at H potential, the source and drain are in a conductive state (ON). When the potential is L, the transistor is in a non-conducting state (OFF state).

[0072] However, one embodiment of the present invention is not limited thereto. A p-channel transistor can also be used as 9. It is also possible to use a combination of a n-channel transistor and a p-channel transistor as appropriate.

[0073] In the circuit diagram of FIG. 5, either the anode or the cathode of the photodiode PD[n] is , and is electrically connected to a wiring 131 capable of supplying a potential VP. The other of the anode or cathode of [n] and the source or drain of the transistor 121 One of the terminals and one of the source and drain of the transistor 122 is connected to the node ND[n]. The other of the source and drain of the transistor 122 is electrically connected to a potential V The gate of the transistor 122 is electrically connected to a wiring 133 capable of supplying a potential PR The source or The other of the drains and the gate of the transistor 123 are electrically connected to a node FD[n]. The gate of the transistor 121 is electrically connected to a wiring 144[n] capable of supplying a potential TX. In addition, one of the source and drain of the transistor 123 is connected to a potential VO. 135, and the source or drain of the transistor 123. The other terminal is electrically connected to one of the source and drain of the transistor 124. The other of the source and the drain of the transistor 124 is electrically connected to the wiring 137[m]. The gate of the transistor 124 is electrically connected to a wiring 146[n] capable of supplying a potential SEL. In addition, one of the source and drain of the transistor 129 is connected to a node ND [n], and the gate of the transistor 129 is connected to the wiring 1 42.

[0074] In addition, either the anode or cathode of the photodiode PD[n+1] is connected to the potential VP. The photodiode PD[n+1] is electrically connected to the wiring 132 that can supply the current. The other of the anode or cathode and the source or drain of the transistor 125 , one of the source and drain of the transistor 126 is electrically connected to the node ND[n+1]. The other of the source and drain of the transistor 126 is connected to a potential VR. The gate of the transistor 126 is electrically connected to a supply wiring 134 and supplies a potential PR. The source or drain of the transistor 125 is electrically connected to the wiring 143 that can supply power. The other drain and the gate of the transistor 127 are electrically connected to a node FD[n+1]. The gate of the transistor 125 is electrically connected to a wiring 144[n+1] capable of supplying a potential TX. In addition, one of the source and drain of the transistor 127 is connected to the potential VO. A source or drain of the transistor 127 is electrically connected to the supply wiring 136. The other terminal is electrically connected to one of the source and drain terminals of the transistor 128. The other of the source and drain of the transistor 128 is electrically connected to the wiring 137[m]. The gate of the transistor 128 is connected to a wiring 146[n+1] that can supply a potential SEL. The other of the source and the drain of the transistor 129 is electrically connected to The input terminal ND[n+1] is electrically connected to the input terminal ND[n+1].

[0075] In addition, although the wiring 131 and the wiring 132 are shown separately in FIG. 5, they are shown as one common wiring. In addition, although the wiring 141 and the wiring 143 are shown separately in FIG. In addition, the wiring 135 and the wiring 136 are shown separately in FIG. , it may be a single common wiring.

[0076] <Example 1> Next, referring to FIG. 6 to FIG. 9, the imaging operation of the imaging device 100 using the global shutter method will be described. An example of the above will be described. In all the sub-pixels 112, the reset operation and the accumulation operation are performed simultaneously. By sequentially reading out the data, imaging can be performed using the global shutter method. Here, an example of the operation of the subpixel 112 is described for the subpixel 112[n] and the subpixel 112[n+ 1] will be used to explain.

[0077] FIG. 6 is a timing chart for explaining the operation of the subpixel 112, and FIGS. FIG. 1 is a circuit diagram showing an operation state of the element 112. In order to explain the driving method in an easy-to-understand manner, the wiring and nodes mentioned above are not marked with any special symbols. Except in cases where the potential is high or low, H potential or L potential is applied.

[0078] By using the global shutter method, the accumulation operations of all pixels 111 are performed within the same period. Therefore, as in the case of using the rolling shutter method, the accumulation operation The global shutter method does not cause distortion of the captured image due to the difference in the period during which the shutter is operated. The frame interval when the formula is used is shown in FIG. 6 as period 301. Period 301 is a reset This is the sum of the time required for the operation, accumulation operation, and readout operation of all rows of pixels.

[0079] In the operation example 1, the potential PA is set to the L potential and the transistor 129 is turned off. The image operation will be described. When the potential PA is set to the L potential, the sub-pixel 112[n] and the sub-pixel The elements 112[n+1] can be operated independently. The potential VP and the potential VO are set to the L potential. Let EL[n+1] be the L potential.

[0080] [Reset action] First, at time T1, the potentials PR and TX are set to H potential. The transistor 121 and the transistor 122 are turned on, and the node ND[n] and The node FD[n] becomes the H potential. Also, the transistor 125 and the transistor 126 are turned on. This causes the nodes ND[n+1] and FD[n+1] to go to the H potential. The operation resets the amount of charge held at node FD[n] and node FD[n+1]. The period from time T1 to time T2 is called the "reset period" (see FIG. 7A). The operation during the reset period is also called the "reset operation."

[0081] Although not shown in the figure, all the nodes F of the imaging device 100 during the reset period D[n] and node FD[n+1] are reset.

[0082] [Storage Operation] Next, at time T2, the potential PR is set to the L potential, and the potential TX is kept at the H potential. At time T2, the photodiode PD[n] and the photodiode PD[n A reverse bias is applied to the photodiode PD[n] and the photodiode PD[n]. When a reverse bias is applied to the photodiode PD[n+1], When light is incident on the photodiode PD[n] and the photodiode PD[n+1], The photodiode PD[n] and the photodiode PD[n+1] have electrodes from one to the other. (See Figure 7(B).) The amount of current changes according to the intensity of the light. That is, the light incident on the photodiode PD[n] and the photodiode PD[n+1] The higher the intensity of the light, the larger the current flow. Conversely, the charge flow from the photodiode PD[n] and the photodiode PD[n] also increases. The lower the intensity of the light incident on node PD[n+1], the smaller the amount of current. The charge flow from node D[n] and node FD[n+1] is also reduced. The potential of D[n] and node FD[n+1] changes more as the light intensity increases. The lower the intensity, the smaller the change.

[0083] Next, at time T3, the potential TX is set to the L potential. Then, the transistors 121 and The transistor 125 is turned off. By setting the node FD[n] and the node FD[n+1] in the off state, the photodiodes The charge transfer to the photodiode PD[n] and the photodiode PD[n+1] stops, and the node F The potentials of D[n] and node FD[n+1] are determined (see FIG. 8(A)). The period from time T2 to time T3 is also referred to as the “exposure period.” This is shown in Figure 6 as 11. The operation during the exposure period is also called the "accumulation operation."

[0084] [Read operation] Next, at time T4, the potential SEL supplied to the wiring 146[n] is set to the H potential. Here, the case where n is 1 (the first row) will be described. Just before supplying the potential, precharge the potential of the wire 137[m] to H potential. When the potential SEL supplied to the wiring 146[n] is set to an H potential, the transistor 124 When the node FD[n] is turned on, the potential of the wiring 137[m] drops at a rate that corresponds to the potential of the node FD[n]. At time T5, the potential SEL supplied to the wiring 146[n] is When the potential is set to L, the transistor 124 is turned off, and the potential of the wiring 137[m] is determined. At this time, the potential of the wiring 137[m] is measured to determine the light receiving potential of the sub-pixel 112[n]. The amount can be calculated.

[0085] Next, at time T5, the line 146[n+1] (here, the line 146 in the second row) is supplied with The potential SEL supplied to the wiring 146[n+1] is set to H potential. Immediately before this, the wiring 137[m] is precharged to an H potential. When the potential SEL supplied to the line 146[n+1] is set to H potential, the transistor 128 is turned on. The potential of the wiring 137[m] drops at a rate according to the potential of the node FD[n+1]. (See FIG. 9A.) At time T6, the potential SE When L is set to an L potential, the transistor 128 is turned off, and the potential of the wiring 137[m] is (See FIG. 9(B)). By measuring the potential of the wiring 137[m] at this time, The amount of light received by pixel 112[n+1] can be calculated.

[0086] In this manner, even after time T6, the potential of the wiring 137[m] is measured in order from the third row. In this way, the potential of the wiring 137[m] in the nth row and the (n+1)th row can be obtained. By measuring the potential of the wirings 137[m] in the p-th row to the p-th row, The amount of light received by each pixel 111 can be obtained. Image data of the captured object can be acquired. For example, from time T4 to time T5 The period during which the amount of light received for each row is acquired, such as the period until the reading The operation during the read-out period is also called a "read operation". can be appropriately determined. Note that the wiring 137 from the 1st column to the qth column connected to the nth row The potential measurement may be performed sequentially from the first row, or from the first row to the qth row simultaneously. Alternatively, the process may be performed in units of multiple rows.

[0087] In the global shutter method, the reset operation and accumulation operation are performed simultaneously for all pixels. Therefore, the potentials TX and PR may be changed simultaneously in the pixels of all columns.

[0088] During the period from the end of the accumulation operation to the start of the readout operation, the node F Since the charge is held in D, this period is also called the charge holding period. In this case, the reset and accumulation operations are performed simultaneously for all pixels, so the timing at which the exposure period ends is However, the readout operation is performed sequentially for each row of pixels, so the voltage The charge retention period differs for each row of pixels. For example, the charge retention period for the first row of pixels is The charge retention period of the pixels in the second row is from time T3 to time T 5. In this way, the readout operation is performed for each row, so the readout period begins. The timing at which the charge retention period begins is different for each row. It becomes long.

[0089] When capturing an image with a uniform number of gray levels, ideally all pixels have the same potential. However, if the length of the charge retention period differs from row to row, If the charge stored in node FD leaks over time, the pixel output The potential of the signal is different for each row, and image data with different gradations for each row is obtained. Put away.

[0090] Therefore, the transistors 121 and 125 are transistors with extremely low off-state current. It is preferable to use a transistor having a large off-state current. By using a transistor with a low current consumption, even imaging using the global shutter method The charge retention periods of the nodes FD[n] and FD[n+1] are different. In other words, the global shutter method is used to capture images. Even if the charge retention period is different, the change in the gradation of the image data is kept small. The quality of the captured image can be improved.

[0091] In this specification and the like, the driving method shown in Operation Example 1 will be referred to as the normal GS driving method. do.

[0092] When the normal GS driving method is performed using the circuit configuration shown in FIG. 5, image data for the nth row and There is a possibility that the image data of the n+1th row may be mixed. It is preferable to use a transistor having a very low off-state current. By using significantly lower transistors, the mixing of the image data can be suppressed.

[0093] According to one aspect of the present invention, the quality of a captured image can be improved.

[0094] <Example 2> Next, an example of the operation of the imaging device 100 that realizes high-speed imaging will be described with reference to FIGS. 10 to 12. FIG. 10 is a timing chart for explaining the operation of the subpixel 112, and FIG. 12 is a circuit diagram showing an operation state of the sub-pixel 112. As shown in FIG.

[0095] The frame interval in the second operation example is shown as a period 302 in FIG. 10. The period 302 is This is the sum of the time required for the reset operation, the accumulation operation, and the readout operation of the pixels in all rows.

[0096] In the second operation example, the potential PA is set to the H potential and the transistor 129 is turned on. The image operation will be described. By setting the potential PA to H potential, the potential of the subpixel 112[n] The photodiode PD[n] and the photodiode PD [n+1] can be connected in parallel and used simultaneously. In addition, as in the first example of operation, the potential VR is set to the H potential, and the potentials VP and The potential SEL[n] and the potential VO are set as the L potential. The potential is taken as

[0097] [Reset action] First, at time T1, the potentials PR and TX are set to H potential. The transistor 121 and the transistor 122 are turned on, and the node ND[n] and The node FD[n] becomes the H potential. Also, the transistor 125 and the transistor 126 are turned on. This causes the nodes ND[n+1] and FD[n+1] to go to the H potential. The operation resets the amount of charge held at node FD[n] and node FD[n+1]. It is set (see FIG. 11(A)).

[0098] In addition, in the second operation example, since the transistor 129 is in the on state, during the reset period Either the transistor 122 or the transistor 126 may be turned off. Although not shown in the figure, all the nodes of the image pickup device 100 are reset during the reset period. Node FD[n] and node FD[n+1] are reset.

[0099] [Storage Operation] Next, at time T2, the potential PR is set to the L potential. The potential TX supplied to the wiring 144[n] is set to an L potential. At time T2, the photodiode PD[n] and the photodiode A reverse bias is applied to the photodiode PD[n+1]. and photodiode PD[n+1] is reverse biased. When light is incident on the photodiode PD[n] and the photodiode PD[n+1], The other of the electrodes of the photodiode PD[n] and the photodiode PD[n+1] Current flows in one direction (see Figure 11(B)). As mentioned above, the amount of current at this time is changes according to the light intensity. Therefore, the potential of node FD[n] becomes higher as the light intensity increases. The change is large, and the lower the light intensity the smaller the change.

[0100] Next, at time T3, the potential TX supplied to the wiring 144[n] is set to an L potential. Then, the transistor 121 is turned off, and the potential of the node FD[n] is determined (see FIG. See 12(A). ).

[0101] Next, at time T3, the potential TX supplied to the wiring 144[n+1] is set to the H potential. Then, the amount of light received by the photodiode PD[n] and the photodiode PD[n+1] is The potential of the node FD[n+1] changes in response to this (see FIG. 12B).

[0102] Next, at time T4, the potential TX supplied to the wiring 144[n+1] is set to the L potential. Then, the transistor 125 is turned off, and the potential of the node FD[n+1] is determined. The exposure period in the operation example 2 is shown as period 312 in FIG.

[0103] After completing the nth row accumulation operation, the n+1th row accumulation operation is performed without performing a reset operation. , the frame interval can be shortened.

[0104] [Read operation] The read operation can be performed in the same manner as in the first operation example.

[0105] In operation example 2, photodiode PD[n] and photodiode PD[n+1] are connected in parallel. Therefore, if the amount of incident light is the same, node F will be connected in a shorter time than in operation example 1. The potentials of D[n] and node FD[n+1] can be determined. The frame interval can be shortened.

[0106] In addition, after the accumulation operation on the nth row is completed, the accumulation operation on the n+1th row is performed without performing the reset operation. This allows the frame interval to be shortened. This means that the image capture interval is short, enabling high-speed image capture. It is possible to provide a solid-state imaging device that can

[0107] The reset operation and the accumulation operation are performed, for example, by connecting the wiring 144[n] to odd-numbered rows and the wiring 144[n+1 ] may be arranged as an even number of rows. Also, the other electrode of the photodiode PD may be connected to a common By increasing the number of pixels, the accumulation operation can be performed more continuously. The other electrode of the photodiode in each pixel is shared, and A consecutive accumulation operations are performed. After storing charges in the charge storage area of ​​each pixel in sequence, the image data of each pixel is read out in sequence. This makes it possible to obtain consecutive frames of image data at short time intervals. According to one aspect of the present invention, a solid-state imaging device with a short imaging interval can be provided.

[0108] In this specification and the like, the driving method shown in Operation Example 2 will be referred to as the high-speed GS driving method. do.

[0109] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0110] (Embodiment 2) In this embodiment, another example of the circuit configuration of the subpixel 112 will be described with reference to the drawings.

[0111] The photodiode PD of the subpixel 112 has one of the anode and the cathode connected to a node ND, and the other of the anode or cathode is connected to wiring 131 (or wiring 13 2) may be electrically connected (see FIG. 13(A)). In this case, the potential VR is set to the L potential. By setting the potential VP to the H potential, the imaging device 100 is operated in the same manner as in the above-described operation example. It is possible.

[0112] A capacitor 151 may be provided at the node FD of the subpixel 112 (see FIG. 13B). By providing the capacitor 151, the retention time of the image data in the node FD is increased. In addition, the dynamic range of the imaging device 100 can be increased.

[0113] In addition, one of the source and drain of the transistor 122 is electrically connected to the node FD[n]. In addition, one of the source and drain of the transistor 126 may be connected to a node It may be electrically connected to FD[n+1] (see FIG. 14(A)).

[0114] In addition, a transistor 154 that can function similarly to the transistor 122 is provided. Also, a transistor 155 that can function similarly to the transistor 126 may be used. (See FIG. 14B). One of the source and drain is electrically connected to a node FD[n], and the other of the source and drain is connected to a wiring 133. The gate is electrically connected to a wiring that can supply a potential PR. Either the source or the drain of the transistor 155 is electrically connected to the node FD[n+1]. The other of the source and drain is electrically connected to the wiring 134, and the gate is connected to a potential It is electrically connected to a wiring capable of supplying PR.

[0115] By providing a transistor 154 in addition to the transistor 122, the required Therefore, the operation speed of the imaging device 100 can be increased. In addition, the transistor 122, the transistor 126, the transistor 154, and the transistor If at least one of the registers 155 is operable, a reset operation can be performed. This makes it possible to improve the reliability of the imaging device 100.

[0116] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0117] (Embodiment 3) In this embodiment, an imaging device 1100 according to one embodiment of the present invention will be described with reference to the drawings. The imaging device 1100 shown in this embodiment is the same as the imaging device 100 shown in the above embodiment. The dynamic range can be further improved compared to the conventional method. FIG. 11 is a plan view showing a configuration example of an imaging device 1100 according to an embodiment of the present invention. The imaging device may have the same configuration as the imaging device 100 shown in the embodiment, but the pixel 111 may be In this embodiment, the imaging device 1100 has a different configuration from the imaging device 100. The difference (the configuration of the sub-pixel) will be described. The configuration of the imaging device 1100 is the same as that of the imaging device 100 shown in the above embodiment. The explanation is cited.

[0118] [Example of circuit configuration of subpixel 1112] A specific example of the circuit configuration of the sub-pixel 1112 included in the imaging device 1100 will be described. The device 1100 includes a pixel 111 in either an odd-numbered row or an even-numbered row, and a subpixel 1112 in either an odd-numbered row or an even-numbered row. In this embodiment, the odd-numbered pixels 111 are used as the sub-pixels 112. In this example, sub-pixel 1112 is used for pixel 111 in an even-numbered row, and sub-pixel 112 is used for pixel 111 in an even-numbered row. Therefore, in this embodiment, n is an odd number between 1 and p.

[0119] The subpixel 1112 is obtained by adding a transistor 152 to the subpixel 112 shown in the above embodiment. FIG. 16 shows a configuration of a sub-pixel 1112[n] of a pixel 111[n] and a The subpixel 112[n+1] of the pixel 11[n+1] is electrically connected to the transistor 129. An example of a circuit configuration for connecting to the

[0120] The sub-pixel 1112[n] includes a photodiode PD[n] (photoelectric conversion element), a transistor 121, a transistor 123, a transistor 124, and a transistor 152. In the subpixel 1112[n] shown in FIG. Either the anode or the cathode is electrically connected to a wiring 131 capable of supplying a potential VP. The other of the anode or cathode of the photodiode PD[n] is connected to a transistor. The transistor 152 is electrically connected to either the source or the drain of the transistor 15 The other of the source and drain of transistor 2 is electrically connected to node ND[n]. The gate of the transistor 152 is electrically connected to a wiring 161[n] capable of supplying a potential PB. can be.

[0121] FIG. 16 illustrates a case where an n-channel transistor is used as the transistor 152. However, it is also possible to use p-channel transistors. This can be the same as the imaging device 100, so a detailed description of this embodiment will not be given. Omitted.

[0122] The imaging device 1100 has the transistor 129 in an off state and the transistor 152 in an on state. Alternatively, imaging can be performed using a normal GS driving method similar to that of the imaging device 100. In addition, the imaging device 1100 has the transistors 129 and 152 in an on state. Therefore, imaging can be performed using the same high-speed GS driving method as the imaging device 100. The imaging device 1100 has the transistor 129 in an on state and the transistor 152 in an off state. By using this mode, the output saturation is unlikely to occur even when the amount of light incident on the light receiving element is large. That is, the imaging device 1100 can perform imaging by the driving method. Even when the amount of incoming light is large, accurate imaging is possible with the high-speed GS driving method. The imaging device 1100 has a further improved dynamic range than the imaging device 100. It is possible.

[0123] <Example 3> Next, using Figs. 17 to 21, we will explain how to achieve high-speed imaging that is less likely to cause output saturation even under high light intensity. An example of the operation of the imaging device 1100 that can be realized will be described. 18 to 21 are timing charts illustrating the operation of the subpixel 1112. FIG.

[0124] The frame interval in the operation example 3 is shown as a period 303 in FIG. 17. The period 303 is This is the sum of the time required for the reset operation, the accumulation operation, and the readout operation of the pixels in all rows.

[0125] [Reset action] First, at time T1, the potential PB is set to the L potential. The potential is set to H potential. Then, the transistor 152 is turned off, and the transistor 12 1. The transistor 122 is turned on, and the nodes ND[n] and FD[n] The transistor 125 and the transistor 126 are turned on, and the This operation causes the node ND[n+1] and the node FD[n+1] to go to the H potential. The charge held in node FD[n] and node FD[n+1] is reset ( See Figure 18.

[0126] In addition, as in the second operation example, since the transistor 129 is in the on state, during the reset period During this time, either the transistor 122 or the transistor 126 is in an off state. Although not shown in the figure, all of the imaging device 1100 may be reset during the reset period. Node FD[n] and node FD[n+1] are reset.

[0127] [Storage Operation] Next, at time T2, the potential PR is set to the L potential. The potential TX supplied to the wiring 144[n] is set to an L potential. At time T2, the photodiode PD[n+1] has a reverse bias. A reverse bias is applied to the photodiode PD[n+1]. When light is incident on the photodiode PD[n+1], the photodiode PD A current flows from the other electrode of [n+1] to one electrode of [n+1] (see FIG. 19). As mentioned above, the amount of current at this time changes according to the light intensity. Therefore, the current of node FD[n] The higher the light intensity, the greater the change in potential; the lower the light intensity, the smaller the change in potential.

[0128] Next, at time T3, the potential TX supplied to the wiring 144[n] is set to an L potential. Then, the transistor 121 is turned off, and the potential of the node FD[n] is determined (see FIG. See paragraph 20.)

[0129] Next, at time T3, the potential TX supplied to the wiring 144[n+1] is set to the H potential. Then, the voltage at node FD[n+1] changes according to the amount of light received by photodiode PD[n+1]. The position changes (see Figure 21).

[0130] Next, at time T4, the potential TX supplied to the wiring 144[n+1] is set to the L potential. Then, the transistor 121 is turned off, and the potential of the node FD[n+1] is determined. The exposure period in the operation example 3 is shown as period 313 in FIG.

[0131] After completing the nth row accumulation operation, the n+1th row accumulation operation is performed without performing a reset operation. , the frame interval can be shortened.

[0132] [Read operation] The read operation can be performed in the same manner as in the operation example 1 shown in the above embodiment.

[0133] Unlike the operation example 2, the operation example 3 does not use the photodiode PD[n] but uses a photodiode Since only PD[n+1] is used, output saturation, which tends to occur when a large amount of light is incident on the photodetector, is prevented. Peace is difficult to achieve.

[0134] In this specification and the like, the driving method shown in Operation Example 3 is referred to as a high-illuminance, high-speed GS driving method. The imaging device 1100 shown in this embodiment is a normal GS driving method, a high-speed GS driving method, and In addition, imaging can be performed using a high-illuminance, high-speed GS driving method. If this is done, it is possible to realize an imaging device that has a wide dynamic range and is capable of high-speed imaging.

[0135] As shown in FIG. 22, the pixel 111[n+1] has a subpixel 1112[ The subpixel 1112[n+1] shown in FIG. 1, a transistor 153 is added to the subpixel 112 shown.

[0136] In the subpixel 1112[n+1] shown in FIG. One of the node and the cathode is electrically connected to a wiring 132 capable of supplying a potential VP. The other of the anode or cathode of the photodiode PD[n+1] is connected to a transistor. The source or drain of the transistor 153 is electrically connected to the The other of the source and drain of 53 is electrically connected to a node ND[n+1]. In addition, the gate of the transistor 153 is electrically connected to a wiring 161[n+1] capable of supplying a potential PC. are connected to the network.

[0137] As shown in FIG. 22, a transistor 153 is provided in addition to a transistor 152. The photodiode used in the high-illumination, high-speed GS driving method is photodiode PD[n] The photodiode PD[n+1] can be used instead. At this time, the photodiode PD[n] and the photodiode PD[n+1] are switched appropriately. By using this, it is possible to reduce the deterioration of the photodiode and improve the reliability of the imaging device. can.

[0138] FIG. 22 illustrates a case where an n-channel transistor is used as the transistor 152. However, it is also possible to use a p-channel transistor.

[0139] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0140] (Embodiment 4) In this embodiment, the imaging device 100 is a CMOS image sensor, which is a type of solid-state imaging device. An example of the configuration using a filter will be described with reference to FIGS. 23 to 26. The pixel region 251 is a cross-sectional view of a part of the pixel 111 included in the imaging device 100. The peripheral circuit region 252 is a cross-sectional view of a portion of the peripheral circuitry of the imaging device 100. FIG. 24 shows an enlarged view of the transistor 241 shown in FIG. An enlarged view of the transistor 281 is shown in FIG. An enlarged view is shown in FIG.

[0141] The imaging device 100 exemplified in this embodiment has an insulating layer 102 on a substrate 101. The photoelectric conversion element 220 having a pin-type junction formed on the substrate 102 is provided. The switching element 220 includes a p-type semiconductor layer 221, an i-type semiconductor layer 222, and an n-type semiconductor layer 223. In addition, the photoelectric conversion element 220 has a p-type semiconductor layer 221 and an n-type semiconductor layer 222 in a plan view. The i-type semiconductor layer 222 is sandwiched between the conductor layers 223. 20 is composed of a p-type semiconductor layer 221 and an n-type semiconductor layer 223 without an i-type semiconductor layer 222. By providing the i-type semiconductor layer 222 in the photoelectric conversion element 220, the light receiving sensitivity can be improved. The photoelectric conversion element 220 exemplified in this embodiment can be the same as that exemplified in the above embodiment. The photodiode PD can function as a

[0142] Intrinsic semiconductors (i-type semiconductors) ideally contain no impurities and have a forbidden Fermi level. The semiconductor is located almost in the center of the band, but in this specification, the donor impurities or By adding impurities as acceptors, the Fermi level is positioned almost in the center of the forbidden band. Intrinsic semiconductors also include semiconductors that have been converted into intrinsic semiconductors. Even if a semiconductor contains pure substances, as long as it is in a state where it can function as an intrinsic semiconductor, The semiconductor is included in the intrinsic semiconductor.

[0143] The substrate 101 may be a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate, or the like. In addition, a plate, a semiconductor substrate, or the like that can withstand the processing temperature of this embodiment can be used. A plastic substrate having thermal resistance may be used. An example of such a substrate is a semiconductor substrate ( For example, single crystal substrate or silicon substrate), SOI (SOI: Silicon on Ins ulator) substrate, glass substrate, quartz substrate, plastic substrate, metal substrate, stainless steel Steel substrate, substrate with stainless steel foil, tungsten substrate, tungsten A substrate with a ten-foil is one example of a glass substrate, such as barium borosilicate glass. Examples of such glass include acid glass, aluminoborosilicate glass, and soda-lime glass.

[0144] After the photoelectric conversion element 220 and the pixel circuit 230 are formed, the photoelectric conversion element 220 and the pixel circuit 230 are polished by mechanical polishing or etching. Alternatively, the substrate 101 may be removed using a method such as the following. Any material that allows the light detected by the photoelectric conversion element 220 to pass therethrough may be used.

[0145] The insulating layer 102 may be made of aluminum oxide, magnesium oxide, silicon oxide, or silicon oxynitride. gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide Oxide materials such as tantalum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, as well as silicon nitride Nitride materials such as silicon oxynitride, aluminum nitride, and aluminum oxynitride The insulating layer 102 can be formed as a single layer or a multilayer. It can be formed by using a D method, a thermal oxidation method, a coating method, a printing method, or the like.

[0146] The p-type semiconductor layer 221, the i-type semiconductor layer 222, and the n-type semiconductor layer 223 are formed, for example, by After forming an island-shaped i-type semiconductor layer 222 on the insulating layer 102, This can be achieved by forming a mask on the i-type semiconductor layer 222 and selectively introducing an impurity element into a part of the i-type semiconductor layer 222. The introduction of impurity elements can be performed, for example, by ion implantation with mass separation or by injection without mass separation. This can be done by using an ion doping method. After the introduction of the impurity element, the mask is removed. .

[0147] The p-type semiconductor layer 221, the i-type semiconductor layer 222, and the n-type semiconductor layer 223 are single crystal semiconductors. , polycrystalline semiconductors, microcrystalline semiconductors, nanocrystalline semiconductors, semi-amorphous semiconductors, amorphous semiconductors For example, the semiconductor layer can be made of amorphous silicon or microcrystalline germanium. In addition, compound semiconductors such as silicon carbide and gallium arsenide can be used. can be used.

[0148] For forming the p-type semiconductor layer 221, the i-type semiconductor layer 222, and the n-type semiconductor layer 223 When silicon is used as the material, the p-type impurity element is, for example, a group 13 element. As the n-type impurity element, for example, a group 15 element can be used. can be done.

[0149] In addition, for example, when the semiconductor layer is formed of SOI, the insulating layer 102 is a BOX layer (B OX (buried oxide) may also be used.

[0150] In addition, the imaging device 100 shown in this embodiment includes a p-type semiconductor layer 221 and an i-type semiconductor layer 222. 2, and an insulating layer 103 and an insulating layer 104 are provided on the n-type semiconductor layer 223. The insulating layer 104 can be formed using the same material and method as the insulating layer 102. Either the insulating layer 103 or the insulating layer 104 may be omitted, or an insulating layer may be stacked. It may be layered.

[0151] In addition, the imaging device 100 shown in this embodiment has an insulating layer having a flat surface on the insulating layer 104. The insulating layer 105 is formed using the same material and method as the insulating layer 102. The insulating layer 105 can be made of a low dielectric constant material (low-k material), siloxane, or the like. Alternatively, polysilicon resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. may be used. In addition, the surface of the insulating layer 105 is polished by chemical mechanical polishing (CMP). A chemical mechanical polishing (CMP) process may be performed. By performing CMP, the unevenness of the sample surface is reduced, and the insulating layer and conductive layer that will be formed later are easily removed. The coverage of the conductive layer can be improved.

[0152] An opening 224 is formed in the insulating layer 103 to the insulating layer 105 in a region where the insulating layer 103 to the insulating layer 105 overlap with the p-type semiconductor layer 221. An opening 22 is formed in a region of the insulating layer 103 to the insulating layer 105 that overlaps with the n-type semiconductor layer 223. In addition, a contact plug 106 is formed in the opening 224 and the opening 225. The contact plug 106 is formed by depositing a conductive material in an opening in the insulating layer. The conductive material is, for example, tungsten, polysilicon, etc. In addition, although not shown, the material can be The side and bottom surfaces are covered with a barrier layer (diffusion layer) made of a titanium layer, a titanium nitride layer, or a laminate of these layers. In this case, the barrier layer is also referred to as the contact plug. There is.

[0153] In addition, an electrode 226 and an electrode 227 are formed on the insulating layer 105. In the opening 224, the p-type semiconductor layer 221 is electrically connected to the p-type semiconductor layer 221 via the contact plug 106. The electrode 227 is connected to the contact plug 106 in the opening 225. It is electrically connected to the n-type semiconductor layer 223 via a

[0154] In addition, an insulating layer 107 is formed to cover the electrodes 226 and 227. The insulating layer 7 can be formed using the same material and method as the insulating layer 105. 7 The surface may be subjected to CMP treatment. By performing CMP treatment, the unevenness of the sample surface is reduced. This can reduce the amount of deposition of the insulating layer and the conductive layer formed thereafter, thereby improving the coverage of the insulating layer and the conductive layer formed thereafter.

[0155] The electrodes 226 and 227 are made of aluminum, titanium, chromium, nickel, copper, or yttrium. Lithium, zirconium, molybdenum, manganese, silver, tantalum, or tungsten, etc. The metal or alloy containing this metal as the main component can be used as a single layer structure or a multilayer structure. For example, a single-layer structure of a copper film containing manganese, or an aluminum film laminated on a titanium film, Two-layer structure, a two-layer structure in which an aluminum film is laminated on a tungsten film, a copper-magnesium- Two-layer structure with copper film laminated on aluminum alloy film, two-layer structure with copper film laminated on titanium film A two-layer structure in which a copper film is laminated on a tungsten film, a titanium film or titanium nitride film and its titanium An aluminum film or a copper film is laminated on the titanium film or the titanium nitride film, and then the aluminum film or the copper film is laminated on the titanium film or the titanium nitride film. A three-layer structure in which a titanium film or titanium nitride film is formed on the A film and an aluminum film or a copper film are layered on the molybdenum film or the molybdenum nitride film. A three-layer structure in which a molybdenum film or molybdenum nitride film is formed on top of the laminate. For example, a three-layer structure is used in which a copper film is laminated on a tungsten film, and a tungsten film is then formed on top of that. In addition, titanium, tantalum, tungsten, molybdenum, chromium, nickel, An alloy film or a nitride film made of one or more of ZnO, ... It may be used.

[0156] In addition, indium tin oxide, zinc oxide, indium oxide containing tungsten oxide, oxide Indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, Indium tin oxide containing titanium, indium zinc oxide, indium with silicon oxide Conductive materials containing oxygen, such as aluminum tin oxide, and conductive materials containing nitrogen, such as titanium nitride and tantalum nitride. A conductive material may be used. In addition, the above-mentioned material containing a metal element and a conductive material containing oxygen may be used. Also, a laminated structure combining the above-mentioned material containing a metal element and It is also possible to use a laminated structure in which a conductive material containing nitrogen is combined. The product of a combination of a material containing an element, a conductive material containing oxygen, and a conductive material containing nitrogen It may also be a layered structure.

[0157] The photoelectric conversion element 220 detects light 660 incident from the insulating layer 102 side.

[0158] The transistor included in the pixel 111 may be provided overlapping with the photoelectric conversion element. A transistor 241 and a transistor 246 are provided above the photoelectric conversion element 220 . Specifically, the transistor 241 and the transistor 246 are disposed between the insulating layer 108 and the insulating layer 109. The insulating layer 107 is provided with an insulating film 107 interposed therebetween.

[0159] In this embodiment, the transistor 241, the transistor 246, and the transistor 289 is shown as a top-gate transistor, but a bottom-gate transistor may also be used. It can also be used as a star.

[0160] In addition, the transistor may be an inverted staggered transistor or a forward staggered transistor. It is also possible to use a gate electrode. It is also possible to use a dual-gate transistor with a structure in which the transistor is sandwiched between two gates. The present invention is not limited to a transistor having a double-gate structure, but may be applied to a multi-gate transistor having multiple channel formation regions. Alternatively, the transistor may be a gate type transistor, for example a double gate type transistor.

[0161] In addition, the above transistors are available in planar, FIN, and TRI-GATE types. It is possible to use transistors of various configurations, such as tri-gate type and tri-gate type.

[0162] The transistors may have the same structure or different structures. The size of the transistor (e.g., channel length and channel width) may be This can be adjusted appropriately using transistors.

[0163] When the multiple transistors in the imaging device 100 all have the same structure, The transistors can be fabricated at the same time in the same process.

[0164] The transistor 241 has an electrode 243 that can function as a gate electrode and a source electrode 244 that can function as a gate electrode. 2, an electrode 244 that can function as either a source or drain electrode; The other electrode 245 can function as the drain electrode, and the other electrode 246 can function as the gate insulating layer. The semiconductor layer 242 includes an insulating layer 117 that can be used as a semiconductor layer (see FIG. 24).

[0165] In FIG. 23, a transistor 241 is provided with a and one of the source and drain electrodes of the transistor 246. In both cases, the electrode 245 is used to form an electrode that can be used for the The embodiment is not limited to this. and one of the source and drain electrodes of the transistor 246. Alternatively, different electrodes may be used to form electrodes that can function in different ways.

[0166] The insulating layer 108 prevents the diffusion of impurities such as oxygen, hydrogen, water, alkali metals, and alkaline earth metals. It is preferable to form the insulating film using an insulating film having a function of preventing the formation of the oxide film. Silicon oxide nitride, silicon nitride, silicon oxide nitride, gallium oxide, hafnium oxide Examples of such oxides include yttrium oxide, aluminum oxide, and aluminum oxide nitride. As insulating films, silicon nitride, gallium oxide, hafnium oxide, yttrium oxide, and oxide By using aluminum or the like, impurities diffusing from the photoelectric conversion element 220 side can be prevented from The insulating layer 108 can be prevented from reaching the surface 242 by sputtering. The insulating layer 108 can be formed by a method such as a CVD method, a vapor deposition method, or a thermal oxidation method. These materials can be used in a single layer or in a laminated form.

[0167] The insulating layer 109 can be formed of the same material and by the same method as the insulating layer 102. When an oxide semiconductor is used as the conductor layer 242, the insulating layer 108 is required to have a stoichiometric composition. It is preferable to form the insulating layer by using an insulating layer containing more oxygen than oxygen. When an insulating layer contains more oxygen than the oxygen that fills it, some of the oxygen is released by heating. Insulating layers that contain more oxygen than meets the theoretical composition have a higher oxygen content than the oxygen that is converted into oxygen atoms in the TDS analysis. The amount of oxygen released is calculated to be 1.0 x 10 18 atoms / cm 3 More than 3.0x, preferably 10 20 atoms / cm 3 The insulating layer is as above. The surface temperature of the film is in the range of 100°C to 700°C or 100°C to 500°C. The range is preferably 100-200 mm.

[0168] In addition, an insulating layer that contains more oxygen than the stoichiometric composition is The treatment of adding oxygen can be carried out under an oxygen atmosphere. Heat treatment, ion implantation equipment, ion doping equipment, or plasma processing equipment is used. The gas for adding oxygen is: 16 O 2 or 18 O 2 Acids such as The gas used in the present specification may be nitrogen gas, nitrous oxide gas, ozone gas, or the like. The process of adding oxygen is also called "oxygen doping process."

[0169] The semiconductor layers of the transistors 241, 246, and 289 are single crystal. Semiconductor, polycrystalline semiconductor, microcrystalline semiconductor, nanocrystalline semiconductor, semi-amorphous semiconductor For example, the insulating film can be formed using amorphous silicon, microcrystalline silicon, or the like. Ruthenium, etc. can be used. Silicon carbide, gallium arsenide, oxide semiconductor, etc. For example, compound semiconductors such as nitride semiconductors, organic semiconductors, etc. can be used.

[0170] In this embodiment, an example in which an oxide semiconductor is used as the semiconductor layer 242 will be described. In the present embodiment, the semiconductor layer 242 is divided into a semiconductor layer 242a, a semiconductor layer 242b, and a A case where a semiconductor layer 242c and a semiconductor layer 242b are laminated will be described.

[0171] The semiconductor layer 242a, the semiconductor layer 242b, and the semiconductor layer 242c are made of In or Ga. It is formed from a material containing one or both of them. Typically, In-Ga oxide (In and Ga) is used. In-Zn oxide (oxide containing In and Zn), In-M-Zn oxide ( An oxide containing In, element M, and Zn. Element M is Al, Ti, Ga, Y, Zr, La, One or more elements selected from Ce, Nd, or Hf that have stronger bonding strength with oxygen than In. It is a rare metal element.

[0172] The semiconductor layer 242a and the semiconductor layer 242c are formed by removing the metal elements constituting the semiconductor layer 242b. In particular, it is preferable that the metal layer is made of a material containing one or more kinds of the same metal element. When the material is used, the interface between the semiconductor layer 242a and the semiconductor layer 242b and the semiconductor layer This can prevent the occurrence of interface states at the interface between the semiconductor layer 242c and the semiconductor layer 242b. This makes it difficult for carriers to be scattered or captured at the interface, and the field effect mobility of the transistor is improved. In addition, it is possible to reduce the variation in the threshold voltage of the transistor. Therefore, it is possible to realize a semiconductor device having good electrical characteristics. It becomes.

[0173] The thickness of the semiconductor layer 242a and the semiconductor layer 242c is preferably 3 nm or more and 100 nm or less. The thickness of the semiconductor layer 242b is set to be 3 nm or more and 50 nm or less. 0 nm or less, preferably 3 nm to 100 nm, and more preferably 3 nm to 50 nm m or less.

[0174] The semiconductor layer 242b is an In-M-Zn oxide, and the semiconductor layer 242a and the semiconductor When the layer 242c is also an In-M-Zn oxide, the semiconductor layer 242a and the semiconductor layer 242 c = In:M:Zn=x 1 :y 1 :z 1 [Atomic ratio], semiconductor layer 242b is In:M:Z n=x 2 :y 2 :z 2 [Atomic ratio], y 1 / x 1 y 2 / x 2 is greater than The semiconductor layer 242a, the semiconductor layer 242c, and the semiconductor layer 242b are selected so as to For more information, see y 1 / x 1 y 2 / x 2 The semiconductor layer 242a is 1.5 times larger than the , semiconductor layer 242c, and semiconductor layer 242b. More preferably, y 1 / x 1 y 2 / x 2 The semiconductor layer 242a, the semiconductor layer 242c, and the semiconductor layer 242b. More preferably, y 1 / x 1 y 2 / x 2 More than 3 The semiconductor layers 242a, 242c, and 242b are formed so that the At this time, in the semiconductor layer 242b, y 1 x 1 If the transistor This is preferable because it can provide stable electrical properties to y 1 x 1 When it becomes more than three times , the field effect mobility of the transistor is reduced, so y 1 x 1 Less than three times the By configuring the semiconductor layer 242a and the semiconductor layer 242c as described above, The dielectric layer 242a and the semiconductor layer 242c are less susceptible to oxygen deficiency than the semiconductor layer 242b. It can be a layer.

[0175] When the semiconductor layer 242a and the semiconductor layer 242c are made of In-M-Zn oxide, Z The content of In and element M, excluding n and O, is preferably less than 50 atomic % In. More preferably, the element M is 50 atomic % or more, and more preferably, the element In is less than 25 atomic %. The element M is 75 atomic % or more. The semiconductor layer 242b is an In-M-Zn oxide. When the oxide is a Zn-based alloy, the content of In and the element M, excluding Zn and O, is preferably 25% by weight. atomic % or more, element M is less than 75 atomic %, and more preferably In is 34a at least 66 atomic %, and element M is less than 66 atomic %.

[0176] For example, a semiconductor layer 242a containing In or Ga and a semiconductor layer 242c: In:Ga:Zn=1:3:2, 1:3:4, 1:3:6, 1:6:4, Or In-Ga-Zn oxide formed using a target with an atomic ratio of 1:9:6, etc. In-Ga oxide formed using a target with an atomic ratio of In:Ga=1:9 In addition, the semiconductor layer 242b may be made of In:Ga Zn=3:1:2, 1:1:1, 5:5:6, or 4:2:4.1 atomic ratio The In-Ga-Zn oxide formed using a target can be used. The atomic ratios of the inorganic layer 242a and the semiconductor layer 242b are calculated by subtracting the above atomic ratios from the atomic ratios as an error. This includes a fluctuation of plus or minus 20%.

[0177] In order to provide a transistor using the semiconductor layer 242b with stable electrical characteristics, The impurities and oxygen vacancies in the semiconductor layer 242b are reduced to make the semiconductor layer 242b highly intrinsic. It is preferable that the oxide semiconductor layer be an oxide semiconductor layer that can be regarded as intrinsic or substantially intrinsic. The channel forming region in the semiconductor layer 242b is a semiconductor layer that can be regarded as intrinsic or substantially intrinsic. It is preferable to set the above.

[0178] Note that an oxide semiconductor layer that can be regarded as substantially intrinsic is an oxide semiconductor layer having a carrier density of , 1×10 17 / cm 3 Less than 1×10 15 / cm 3 Less than or equal to 1 × 10 13 / cm 3 The term "oxide semiconductor layer" refers to an oxide semiconductor layer having a thickness of less than 100 nm.

[0179] [Energy band structure of oxide semiconductors] Here, the semiconductor layer 242a, the semiconductor layer 242b, and the semiconductor layer 242c are stacked. The function and effect of the semiconductor layer 242 formed in the above-mentioned manner will be described with reference to the energy band shown in FIG. The explanation will be given using a structural diagram. Figure 25 shows the energy distribution of the portion indicated by the dashed line C1-C2 in Figure 24. FIG. 25 is a diagram showing the energy band structure of the channel formation region of the transistor 241. The figure shows the band structure.

[0180] In Figure 25, Ec382, Ec383a, Ec383b, Ec383c, and Ec386 are The insulating layer 109, the semiconductor layer 242a, the semiconductor layer 242b, the semiconductor layer 242c, and the insulating The energy of the conduction band minimum of layer 117 is shown.

[0181] Here, the difference between the vacuum level and the conduction band minimum energy (also called "electron affinity") is The energy difference between the vacant level and the top of the valence band (also called the ionization potential) The energy gap is calculated by subtracting the energy gap from the spectroscopic ellipsometer ( It can be measured using HORIBA JOBIN YVON UT-300. The energy difference between the unoccupied level and the top of the valence band was determined by ultraviolet photoelectron spectroscopy (UPS). iolet Photoelectron Spectroscopy (PHI) It can be measured using a VersaProbe.

[0182] The In-Ga target with an atomic ratio of In:Ga:Zn=1:3:2 was used. The energy gap of a-Zn oxide is about 3.5 eV and the electron affinity is about 4.5 eV. In addition, the In- The energy gap of Ga-Zn oxide is about 3.4 eV and the electron affinity is about 4.5 eV. In addition, the In was formed using a target with an atomic ratio of In:Ga:Zn=1:3:6. The energy gap of Ga-Zn oxide is about 3.3 eV, and the electron affinity is about 4.5 eV. In addition, the I was formed using a target with an atomic ratio of In:Ga:Zn=1:6:2. The energy gap of n-Ga-Zn oxide is about 3.9 eV, and the electron affinity is about 4.3 eV. In addition, the film was formed using a target with an atomic ratio of In:Ga:Zn=1:6:8. The energy gap of In-Ga-Zn oxide is about 3.5 eV, and the electron affinity is about 4.4 e V. In addition, a target with an atomic ratio of In:Ga:Zn=1:6:10 was used. The energy gap of the In-Ga-Zn oxide is about 3.5 eV and the electron affinity is about 4. The energy of the target is 5 eV. The atomic ratio of In:Ga:Zn is 1:1:1. The energy gap of the synthesized In-Ga-Zn oxide is about 3.2 eV, and the electron affinity is about 4 .7 eV. In addition, a target with an atomic ratio of In:Ga:Zn=3:1:2 was used. The energy gap of the formed In-Ga-Zn oxide is about 2.8 eV, and the electron affinity is about It is 5.0 eV.

[0183] Since the insulating layer 109 and the insulating layer 117 are insulators, Ec382 and Ec386 are Closer to the vacuum level (lower electron affinity) than 3a, Ec383b, and Ec383c .

[0184] Also, Ec383a is closer to the vacuum level than Ec383b. is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0 .15eV or more and 2eV or less, 1eV or less, 0.5eV or less, or 0.4eV or less It is preferable that the level is close to an unoccupied level.

[0185] Also, Ec383c is closer to the vacuum level than Ec383b. is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0 .15eV or more and 2eV or less, 1eV or less, 0.5eV or less, or 0.4eV or less It is preferable that the level is close to an unoccupied level.

[0186] In addition, in the vicinity of the interface between the semiconductor layer 242a and the semiconductor layer 242b, and in the vicinity of the interface between the semiconductor layer 242b and the semiconductor layer 242a, In the vicinity of the interface with the semiconductor layer 242c, a mixed region is formed, so that the energy of the conduction band minimum That is, at these interfaces, the levels are almost nonexistent or nonexistent. stomach.

[0187] Therefore, in the stacked structure having the above energy band structure, the electrons Therefore, the interface between the semiconductor layer 242a and the insulating layer 107, Or, even if a level exists at the interface between the semiconductor layer 242c and the insulating layer 117, the level In addition, the boundary between the semiconductor layer 242a and the semiconductor layer 242b is There is almost no level at the interface between the semiconductor layer 242c and the semiconductor layer 242b. Therefore, the movement of electrons in the region is not hindered. The transistor 241 having a conductor stack structure can achieve high field effect mobility. Cut.

[0188] As shown in FIG. 24, the interface between the semiconductor layer 242a and the insulating layer 109 and the semiconductor layer 2 In the vicinity of the interface between 42c and the insulating layer 117, a trap level 390 due to impurities and defects is formed. However, the semiconductor layer 242a and the semiconductor layer 242c are provided to form a semiconductor This can keep the layer 242b away from the trap level.

[0189] In particular, in the transistor 241 illustrated in this embodiment, the upper surface of the semiconductor layer 242b is a semiconductor The lower surface of the semiconductor layer 242b is in contact with the semiconductor layer 242a. In this manner, the semiconductor layer 242b is covered with the semiconductor layer 242a and the semiconductor layer 242c. By doing so, the influence of the trap levels can be further reduced.

[0190] However, if the energy difference between Ec383a or Ec383c and Ec383b is small, In this case, electrons in the semiconductor layer 242b may exceed the energy difference and reach the trap level. When electrons are captured in the trap level, a negative fixed charge is generated at the interface of the insulating layer, The threshold voltage of the transistor is shifted in the positive direction.

[0191] Therefore, the energy difference between Ec383a and Ec383c and Ec383b is When each of these is set to 0.1 eV or more, preferably 0.15 eV or more, the threshold voltage of the transistor is Since the voltage fluctuation is reduced and the electrical characteristics of the transistor can be improved, I wish.

[0192] The band gaps of the semiconductor layer 242a and the semiconductor layer 242c are It is preferable that the band gap is wider than that of b.

[0193] According to one embodiment of the present invention, a transistor with little variation in electrical characteristics can be provided. Therefore, a semiconductor device with little variation in electrical characteristics can be realized. According to one embodiment of the present invention, a highly reliable transistor can be realized. Therefore, a semiconductor device with excellent performance can be realized.

[0194] In addition, the band gap of oxide semiconductors is 2 eV or more, so A transistor that uses an oxide semiconductor for a semiconductor layer can have an extremely small off-state current. Specifically, the off-current per 1 μm of channel width is 1×10 -20 A less than 1×10 -22 A, more preferably less than 1×10 -24Less than A That is, the on / off ratio can be set to 20 digits or more and 150 digits or less.

[0195] According to one embodiment of the present invention, a transistor with low power consumption can be realized. As a result, an imaging device or semiconductor device with low power consumption can be realized.

[0196] In addition, since an oxide semiconductor has a wide band gap, a semiconductor device using an oxide semiconductor is not available. According to one aspect of the present invention, an imaging device having a wide operating temperature range is provided. and a semiconductor device.

[0197] The above-mentioned three-layer structure is an example. For example, the semiconductor layer 242a or the semiconductor layer 242c Alternatively, one of the layers may be omitted.

[0198] [Oxide semiconductors] Here, oxide semiconductors that can be used for the semiconductor layer 242 will be described in detail.

[0199] When an oxide semiconductor is used as the semiconductor layer, CAAC-OS (C Axis Alig ned Crystalline Oxide Semiconductor), polycrystalline Oxide semiconductor, microcrystalline oxide semiconductor, nc-OS (nano Crystalline The material can be a semiconductor such as amorphous oxide semiconductor. can.

[0200] The CAAC-OS film is one of oxide semiconductor films having a plurality of crystal parts aligned along the c-axis.

[0201] Transmission Electron Microscope (TEM) A bright-field image and a combined diffraction pattern of the CAAC-OS film were obtained by using a microscope. By observing the TEM image, multiple crystalline regions can be confirmed. On the other hand, the high-resolution TEM image also shows clear boundaries between crystals, i.e. grain boundaries. Therefore, the CAAC-OS film is It can be said that the decrease in electron mobility caused by grain boundaries is unlikely to occur.

[0202] When a high-resolution TEM image of the cross section of the CAAC-OS film was observed from a direction roughly parallel to the sample surface, It can be seen that the metal atoms are arranged in layers in the crystal part. Each layer of metal atoms is The CAAC-OS film is formed on the surface (also called the surface on which the film is formed) or on the upper surface. The CAAC-OS film has a shape similar to that of the crystalline silicon film, and is aligned parallel to the surface on which the CAAC-OS film is formed or the upper surface.

[0203] The high-resolution TEM images of the cross section and the plan view show that the crystalline part of the CAAC-OS film It can be seen that the film has an orientation.

[0204] In the CAAC-OS film, the orientation of the a-axis and the b-axis is random between different crystal regions. The c-axis is parallel to the normal vector of the surface on which the film is formed or the upper surface. do.

[0205] The crystalline portion is formed when the CAAC-OS film is formed or when a crystallization process such as a heat treatment is performed. As described above, the c-axis of the crystal is aligned along the surface on which the CAAC-OS film is formed or along the surface on which the CAAC-OS film is formed. The orientation of the CAAC-OS film is parallel to the normal vector of the top surface. When the shape of the CAAC-OS film is changed by etching, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is formed. Or it may not be parallel to the normal vector of the upper surface.

[0206] Furthermore, the distribution of c-axis oriented crystal parts in the CAAC-OS film does not need to be uniform. For example, the crystals in the CAAC-OS film grow from the top surface of the CAAC-OS film. When the crystal is formed by the above method, the region near the top surface has more c-axis oriented crystals than the region near the surface on which the crystal is formed. In addition, the CAAC-OS film containing impurities may have a high ratio of impurities. The doped region changes and regions with different proportions of c-axis oriented crystals are formed. This sometimes happens.

[0207] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. The impurities include hydrogen, carbon, and The elements are other than the main components of the oxide semiconductor film, such as silicon and transition metal elements. The elements that bond to oxygen more strongly than the metal elements that form the oxide semiconductor film, such as arsenic, are oxidized. By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, reducing its crystallinity. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide have an atomic radius of Since the molecular radius is large, when the cation is contained in the oxide semiconductor film, the The impurities in the oxide semiconductor film may cause the atomic arrangement to be disturbed, which may result in a decrease in crystallinity. Objects can act as carrier traps or carrier generation sources.

[0208] The CAAC-OS film is an oxide semiconductor film having a low density of defect states. Oxygen vacancies in the semiconductor film can become carrier traps or trap hydrogen, It can be a carrier source.

[0209] A material with a low impurity concentration and a low defect level density (few oxygen vacancies) is called a high-purity intrinsic or The term "substantially high-purity intrinsic" refers to a highly-purified intrinsic oxide semiconductor film. Since the carrier generation source is small, the carrier density can be reduced. A transistor using an oxide semiconductor film has electrical characteristics in which the threshold voltage is negative ( Also called marion.) It is rare for it to become high purity genuine or substantially high purity genuine. The oxide semiconductor film has few carrier traps. A transistor using such a material has small fluctuation in electrical characteristics and is highly reliable. Note that it takes a long time for charges trapped in the carrier traps in the oxide semiconductor film to be released. The charge is long and can behave like a fixed charge. In addition, a transistor using an oxide semiconductor film having a high density of defect states has unstable electrical characteristics. There are cases.

[0210] In addition, the electrical characteristics of transistors using CAAC-OS films were improved by irradiation with visible light or ultraviolet light. The fluctuation is small.

[0211] Next, the polycrystalline oxide semiconductor film will be described.

[0212] In the polycrystalline oxide semiconductor film, crystal grains can be confirmed in a high-resolution TEM image. The crystal grains contained in the crystalline oxide semiconductor film are, for example, 2 nm to 30 nm in a high-resolution TEM image. The particle size is 0 nm or less, 3 nm to 100 nm or 5 nm to 50 nm. In addition, in the case of polycrystalline oxide semiconductor films, crystal grain boundaries can often be confirmed by high-resolution TEM images. There is a match.

[0213] The polycrystalline oxide semiconductor film has a plurality of crystal grains, and the crystal orientation between the plurality of crystal grains is may be different.

[0214] Next, a microcrystalline oxide semiconductor film will be described.

[0215] The microcrystalline oxide semiconductor film has a region where crystals can be confirmed in a high-resolution TEM image. The microcrystalline oxide semiconductor film has a crystal structure including a region where a crystal part is not clearly observed and a region where a crystal part is not clearly observed. The crystal part contained in the crystal has a size of 1 nm to 100 nm or 1 nm to 10 nm. In particular, the fineness is often between 1 nm and 10 nm, or between 1 nm and 3 nm. The oxide semiconductor film having nanocrystals (nc) is called nc -OS(nanocrystalline oxide semiconductor) In the nc-OS film, for example, the grain boundaries are clearly identified in high-resolution TEM images. It may not be possible to recognize

[0216] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or more). The atomic arrangement has periodicity in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, the nc-OS film may be indistinguishable from an amorphous oxide semiconductor film. For example, an XRD apparatus that uses X-rays with a diameter larger than that of the crystal part for an nc-OS film may be used. When the structure was analyzed using the out-of-plane method, the crystal plane was not shown. In addition, the probe diameter ( For example, electron diffraction (also called selected area electron diffraction) is performed using an electron beam of 50 nm or more. On the other hand, for the nc-OS film, Nanobeam electron diffraction using an electron beam with a probe diameter close to or smaller than the size of the crystal part In addition, nanobeam electron diffraction was performed on the nc-OS film. In some cases, a bright area with a circular shape (ring shape) may be observed. When nanobeam electron diffraction was performed on the -OS film, multiple spots were observed within the ring-shaped region. This may be the case.

[0217] The nc-OS film is an oxide semiconductor film that has higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the nc-OS film, there is no regularity in the crystal orientation between different crystal parts. The S film has a higher density of defect states than the CAAC-OS film.

[0218] Therefore, the nc-OS film may have a higher carrier density than the CAAC-OS film. An oxide semiconductor film with high carrier density may have high electron mobility. A transistor using an nc-OS film can have high field-effect mobility. The nc-OS film has a higher defect density than the CAAC-OS film, which leads to carrier trapping. Therefore, the transistor using the nc-OS film is Compared to transistors using S films, the electrical characteristics fluctuate greatly and the reliability is low. However, the nc-OS film can be formed even if it contains a relatively large amount of impurities. Therefore, it is easier to form than the CAAC-OS film, and it can be used preferably depending on the application. Therefore, a semiconductor device having a transistor using an nc-OS film may be In some cases, the device can be manufactured with high productivity.

[0219] Next, the amorphous oxide semiconductor film will be described.

[0220] The amorphous oxide semiconductor film is an oxide semiconductor film in which the atomic arrangement in the film is irregular and does not have a crystal part. An example is an oxide semiconductor film that has an amorphous state, such as quartz.

[0221] In the amorphous oxide semiconductor film, no crystalline parts can be confirmed in a high-resolution TEM image.

[0222] When the structure of the amorphous oxide semiconductor film is analyzed using an XRD device, out-of-p In the lane analysis, no peaks indicating crystal planes were detected. When electron diffraction is performed on a conductive film, a halo pattern is observed. When nanobeam electron diffraction is performed on a conductive film, no spots are observed, and a halo pattern is observed. Observed.

[0223] The amorphous oxide semiconductor film is an oxide semiconductor film containing a high concentration of impurities such as hydrogen. In addition, the amorphous oxide semiconductor film has a high density of defect states.

[0224] An oxide semiconductor film having a high impurity concentration and a high density of defect states has carrier traps and carrier The most common source of this problem is the oxide semiconductor film.

[0225] Therefore, the amorphous oxide semiconductor film has a higher carrier density than the nc-OS film. Therefore, a transistor using an amorphous oxide semiconductor film has a normally-on Therefore, it is difficult to obtain normally-on electrical characteristics from transistors that require normally-on electrical characteristics. The amorphous oxide semiconductor film has a high density of defect states. Therefore, the number of carrier traps may increase. The transistors using this film have a higher current density than transistors using CAAC-OS and nc-OS films. The electrical characteristics may vary significantly, resulting in a transistor with low reliability.

[0226] Next, a single crystal oxide semiconductor film will be described.

[0227] A single-crystal oxide semiconductor film has a low impurity concentration and a low density of defect states (few oxygen vacancies). Therefore, the carrier density can be reduced. A transistor using a crystalline oxide semiconductor film rarely has normally-on electrical characteristics. In addition, since the single crystal oxide semiconductor film has a low impurity concentration and a low density of defect states, Therefore, the rear trap may be reduced. The resulting transistor has small fluctuations in electrical characteristics and is highly reliable.

[0228] Note that the oxide semiconductor film has a high density when the number of defects is small. The higher the crystallinity, the higher the density. In addition, the oxide semiconductor film has a low concentration of impurities such as hydrogen. The density is increased. The single crystal oxide semiconductor film has a higher density than the CAAC-OS film. The CAAC-OS film has a higher density than the microcrystalline oxide semiconductor film. The amorphous oxide semiconductor film has a higher density than the microcrystalline oxide semiconductor film. The density of the oxide semiconductor film is higher than that of the amorphous oxide semiconductor film.

[0229] Note that the oxide semiconductor film has a structure that exhibits physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure may have a structure such as the following. Amorphous-like Ox The resulting film is called an ide semiconductor membrane.

[0230] The size of the crystals in the amorphous-like OS film and the nc-OS film was calculated. Measurements can be performed using high-resolution TEM images. 4 The crystals are It has a layered structure, with two Ga-Zn-O layers between In-O layers. 4 The unit cell of this crystal has three In-O layers and six Ga-Zn-O layers, for a total of nine layers. The layers are stacked in the c-axis direction. Therefore, the spacing between adjacent layers is is approximately the same as the lattice spacing (also called the d value) of the (009) plane, and crystal structure analysis has revealed that The value is expected to be 0.29 nm. Therefore, we focus on the lattice fringes in the high-resolution TEM image. In the area where the lattice spacing is 0.28 nm or more and 0.30 nm or less, The lattice fringes of InGaZnO 4 The lattice fringes of the ab plane of the crystal are The maximum length of the region to be covered was determined for the amorphous-like OS membrane and the nc-OS membrane. The size of the crystal part of the film is used. Note that the size of the crystal part is selected to be 0.8 nm or more. evaluate.

[0231] The oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, or a CA The AC-OS film may be a laminate film having two or more kinds of films.

[0232] By the way, even if the oxide semiconductor film is a CAAC-OS film, it is possible to partially form an nc-OS film. Therefore, the CAAC-OS film is considered to have a good diffraction pattern. The ratio of the area where the diffraction pattern of the CAAC-OS film is observed in a certain range (C It can be expressed as the AAC conversion rate. For example, a good quality CAAC-OS In the case of a membrane, the CAAC content is 50% or more, preferably 80% or more, and more preferably 90% or more. 0% or more, and more preferably 95% or more. The percentage of the area where the CAAC pattern is observed is denoted as the non-CAAC rate.

[0233] The oxide semiconductors applicable to the semiconductor layers 242a, 242b, and 242c An example of the oxide is an oxide containing indium. When indium is contained, the carrier mobility (electron mobility) increases. In addition, oxide semiconductors have the following properties: It is preferable to include the element M. The element M is preferably aluminum, gallium, yttrium, or the like. Other elements that can be used for element M include boron, silicon, and Titanium, iron, nickel, germanium, yttrium, zirconium, molybdenum, These include lanthanum, cerium, neodymium, hafnium, tantalum, and tungsten. However, the element M may be a combination of two or more of the above elements. For example, it is an element that has a high bond energy with oxygen. In addition, when an oxide semiconductor contains zinc, When the oxide contains zinc, for example, the oxide is easily crystallized.

[0234] However, the oxide semiconductor is not limited to an oxide containing indium. For example, zinc tin oxide, gallium tin oxide, and gallium oxide may be used.

[0235] In addition, oxide semiconductors are made of oxides with a large energy gap. The energy gap is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.8 eV or more. The energy is set to 3.8 eV or less, and more preferably, to 3 eV or more and 3.5 eV or less.

[0236] The effect of impurities in an oxide semiconductor will be described below. In order to stabilize the electrical characteristics of the oxide semiconductor, it is necessary to reduce the impurity concentration in the oxide semiconductor and to achieve a low carrier density. It is effective to increase the carrier density of oxide semiconductors by 1× 10 17 pieces / cm 3 Less than 1×10 15 pieces / cm 3 Less than or equal to 1 × 10 13 pieces / cm 3 In order to reduce the impurity concentration in the oxide semiconductor, the impurity concentration in the adjacent film is It is preferable to also reduce the intensity.

[0237] For example, silicon in an oxide semiconductor can become a carrier trap or a carrier generation source. Therefore, the silicon concentration in the oxide semiconductor is measured by secondary ion mass spectrometry (SIMS). Secondary Ion Mass Spectrometry (1×1 0 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than, more Preferably 2 x 10 18 atoms / cm 3Less than.

[0238] Furthermore, when hydrogen is contained in an oxide semiconductor, the carrier density may be increased. The hydrogen concentration of the oxide semiconductor was 2×10 20 atoms / cm 3 below, Preferably 5 x 10 19 atoms / cm 3 Less than or equal to 1×10 19 atom s / cm 3 Less than 5×10, more preferably 18 atoms / cm 3 The following applies. Also, When nitrogen is contained in an oxide semiconductor, the carrier density may increase. The nitrogen concentration of the semiconductor is 5×10 19 atoms / cm 3 Less than, preferred Or 5×10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 The following applies.

[0239] In order to reduce the hydrogen concentration in the oxide semiconductor, the insulating layer 109 in contact with the semiconductor layer 242 is It is preferable to reduce the hydrogen concentration in the insulating layer 109 and the insulating layer 117. The hydrogen concentration in the sample was 2×10 20 atoms / cm 3 Less than or equal to 5x 10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 below , and more preferably 5 × 10 18 atoms / cm 3In addition, the oxide semiconductor In order to reduce the nitrogen concentration, it is preferable to reduce the nitrogen concentration in the insulating layer 109 and the insulating layer 117. The nitrogen concentration of the insulating layer 109 and the insulating layer 117 is preferably 5×10 1 9 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 The following is more preferred: Or 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 The following applies.

[0240] In this embodiment, first, a semiconductor layer 242a is formed on an insulating layer 109, and then the semiconductor layer 242 A semiconductor layer 242b is formed on the substrate 242a.

[0241] Note that the oxide semiconductor layer is preferably formed by a sputtering method. For this purpose, RF sputtering, DC sputtering, AC sputtering, etc. can be used. The sputtering method, or AC sputtering method, can form films with better uniformity than the RF sputtering method. can.

[0242] In the present embodiment, the semiconductor layer 242a is formed using an In-Ga-Zn oxide target (In :Ga:Zn=1:3:2) was used to deposit a 20 nm thick In-Ga The semiconductor layer 242a is formed of a-Zn oxide. The constituent elements and composition applicable to the semiconductor layer 242a are This is not limited to the above.

[0243] In addition, oxygen doping treatment may be performed after the semiconductor layer 242a is formed.

[0244] Next, the semiconductor layer 242b is formed on the semiconductor layer 242a. As the layer 242b, an In-Ga-Zn oxide target (In:Ga:Zn=1:1:1) was used. ) to form a 30 nm thick In-Ga-Zn oxide film by sputtering. However, the constituent elements and compositions applicable to the semiconductor layer 242b are not limited to those described above. stomach.

[0245] In addition, an oxygen doping treatment may be performed after the semiconductor layer 242b is formed.

[0246] Next, impurities such as moisture or hydrogen contained in the semiconductor layers 242a and 242b are removed. In order to further reduce the amount of fluorine and to highly purify the semiconductor layers 242a and 242b, A heat treatment may be carried out.

[0247] For example, the process may be carried out under a reduced pressure atmosphere, an inert atmosphere such as nitrogen or a rare gas, an oxidizing atmosphere, or an ultra-dry atmosphere. Dry air (measured using a CRDS (cavity ring down laser spectroscopy) type dew point meter The moisture content when the air is cooled should be 20 ppm or less (-55°C in terms of dew point), preferably 1 ppm or less. The semiconductor layer 242a and the semiconductor layer 242b are exposed to a fluorine-containing gas (preferably air) atmosphere of 10 ppb or less. The oxidizing atmosphere is an oxidizing atmosphere such as oxygen, ozone, or nitrogen oxide. An inert atmosphere is an atmosphere containing 10 ppm or more of oxidizing gases. This refers to an atmosphere in which the gas concentration is less than 10 ppm and which is filled with nitrogen or a rare gas.

[0248] In addition, by performing a heat treatment, the oxygen contained in the insulating layer 109 is removed at the same time as the impurities are released. The semiconductor layer 242a and the semiconductor layer 242b are diffused. It is possible to reduce the oxygen deficiency of 242b. In addition, after heat treatment in an inert gas atmosphere, Heat treatment is performed in an atmosphere containing oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. Note that the heat treatment may be performed at any time after the formation of the semiconductor layer 242b. For example, heat treatment may be performed after selective etching of the semiconductor layer 242b.

[0249] The heat treatment is carried out at a temperature of 250° C. to 650° C., preferably 300° C. to 500° C. The treatment time should be within 24 hours. Heat treatment for more than 24 hours will lead to a decrease in productivity. Therefore, it is not desirable.

[0250] Next, a resist mask is formed on the semiconductor layer 242b. The insulating layer 242a and the semiconductor layer 242b are selectively etched. A part of 109 may be etched, forming a protrusion on insulating layer 109.

[0251] The semiconductor layer 242a and the semiconductor layer 242b can be etched by a dry etching method or a wafer etching method. After etching is completed, the resist mask is removed. Remove.

[0252] The transistor 241 is provided on the semiconductor layer 242b and in contact with a part of the semiconductor layer 242b. , electrodes 244 and 245. Electrodes 244 and 245 (the same layer The other electrodes or wirings formed by the method described above are formed using the same materials as the electrodes 226. It is possible.

[0253] The transistor 241 has a semiconductor layer 242b, an electrode 244, and an electrode 245. The semiconductor layer 242c includes a semiconductor layer 242b, an electrode 244, and a conductor layer 242c. It contacts a portion of each of the electrodes 245 .

[0254] In this embodiment, the semiconductor layer 242c is grown using an In-Ga-Zn oxide target (In:Ga The semiconductor layer 24 is formed by a sputtering method using a metal oxide film (Zn:Zn=1:3:2). The constituent elements and compositions applicable to 2c are not limited to those described above. For example, a semiconductor layer Gallium oxide may be used as the semiconductor layer 242c. may be carried out.

[0255] The transistor 241 further includes an insulating layer 117 over the semiconductor layer 242c. The insulating layer 117 can function as a gate insulating layer. The insulating layer 117 may be formed by performing oxygen doping treatment. good.

[0256] After the semiconductor layer 242c and the insulating layer 117 are formed, a mask is formed on the insulating layer 117, and the semiconductor layer 242c is The insulating layer 242c and a portion of the insulating layer 117 are selectively etched to form an island-shaped semiconductor layer 24 2c, and the insulating layer 117 may be an island-shaped layer.

[0257] The transistor 241 also has an electrode 243 on the insulating layer 117. The electrodes 226 and the wiring 230 may be made of the same material as the electrodes 226. The method can be formed by the method.

[0258] In this embodiment, an example in which the electrode 243 is a laminate of the electrodes 243a and 243b is shown. For example, the electrode 243a is made of tantalum nitride, and the electrode 243b is made of copper. 243a acts as a barrier layer to prevent the diffusion of copper elements. Therefore, a high-performance semiconductor device can be realized.

[0259] The transistor 241 further includes an insulating layer 118 that covers the electrode 243. The insulating layer 118 can be formed using the same material and method as the insulating layer 102. An elemental doping process may be performed, and a CMP process may be performed on the surface of the insulating layer 118.

[0260] In addition, an insulating layer 113 is provided over the insulating layer 118. The insulating layer 113 has the same structure as the insulating layer 105. The insulating layer 113 can be formed by performing a CMP process on the surface of the insulating layer 113. By performing CMP, the unevenness of the sample surface is reduced, and the insulating film formed later is In addition, the insulating layer 113 and the insulating layer 118 can be formed by applying a heat treatment to the insulating layer 113 and the conductive layer. An opening is formed in the portion. A contact plug 114 is formed in the opening. do.

[0261] In addition, on the insulating layer 113, a wiring 261, a wiring 265, and a wiring 267 (the same as these) are provided. The wiring 267 is formed on the insulating layer 1. 13 and an opening provided in the insulating layer 118, an electrode is connected via a contact plug 114. The wiring 265 is electrically connected to the insulating layer 113 and the insulating layer 118. The contact plug 114 is electrically connected to the electrode 244 through an opening formed in the It has been done.

[0262] In addition, the imaging device 100 includes wiring 261, wiring 265, and wiring 267 (which are arranged in the same layer as these). The insulating layer 115 covers the insulating layer 115 (including other electrodes or wiring formed by the method described above). The insulating layer 115 can be formed using the same material and method as the insulating layer 105. The surface may be subjected to CMP treatment. By performing CMP treatment, the unevenness of the sample surface is reduced. This can improve the coverage of the insulating layer and conductive layer that will be formed later. An opening is formed in a part of 5.

[0263] In addition, on the insulating layer 115, a wiring 263 and a wiring 266 (formed in the same layer as these) are provided. In addition, other electrodes or wirings (including electrodes or wirings connected to the substrate) are formed.

[0264] In addition, the wiring 263 and the wiring 266 (other electrodes or wirings formed in the same layer as these) Each of the insulating layers is connected to the other through an opening and a contact plug formed in the insulating layer. It can be electrically connected to wiring in one layer or electrodes in another layer.

[0265] In addition, an insulating layer 116 is provided to cover the wiring 263 and the wiring 266. The insulating layer 116 is It can be formed of the same material and by the same method as the insulating layer 105. A CMP process may be performed on the surface.

[0266] 23 corresponds to, for example, the transistor 121. By providing a transistor that constitutes a pixel on the transistor 220, a photoelectric conversion element Therefore, the light receiving sensitivity of the imaging device 100 can be improved. In addition, the imaging device 100 can be realized in which the light receiving sensitivity is not easily reduced even when the resolution is increased. It is possible.

[0267] As an example of a transistor constituting a peripheral circuit, the transistor 281 shown in FIG. A larger cross-sectional view is shown in FIG. 26(A). Also, an enlarged cross-sectional view of the transistor 282 shown in FIG. FIG. 26B shows an example of the transistor 281 in this embodiment. When transistor 281 is an n-channel transistor, I will explain it below.

[0268] The transistor 281 includes an i-type semiconductor layer 283 in which a channel is formed, a p-type semiconductor layer 285 , an insulating layer 286, an electrode 287, and a side wall 288. A low concentration p-type impurity region 284 is provided in the region overlapping with 288 .

[0269] The i-type semiconductor layer 283 of the transistor 281 is the same as the i-type semiconductor layer of the photoelectric conversion element 220. The conductor layer 222 can be formed in the same process at the same time. The p-type semiconductor layer 285 is formed in the same process as the p-type semiconductor layer 221 of the photoelectric conversion element 220. can be formed simultaneously.

[0270] The insulating layer 286 can function as a gate insulating layer, and the electrode 287 can function as a gate electrode. The low concentration p-type impurity region 284 is formed by forming an electrode 287 and before forming a side wall 288. It can be formed by introducing an impurity element using the pole 287 as a mask. That is, the low concentration p-type impurity region 284 can be formed by a self-alignment method. The low-concentration p-type impurity region 284 has the same conductivity type as the p-type semiconductor layer 285. The concentration of the impurity added is less than that of the p-type semiconductor layer 285 .

[0271] The transistor 282 has a similar configuration to the transistor 281, but has a low concentration p-type impurity region. Instead of the region 284 and the p-type semiconductor layer 285, a low concentration n-type impurity region 294 and an n-type semiconductor layer 2 The difference is that it has a .

[0272] The n-type semiconductor layer 295 of the transistor 282 is It can be formed simultaneously with the n-type semiconductor layer 223 in the same process. As in Example 1, the lightly doped n-type impurity region 294 can be formed in a self-aligned manner. The low-concentration n-type impurity region 294 has the same conductivity type as the n-type semiconductor layer 295. The concentration of the impurity that imparts the n-type semiconductor layer is lower than that of the n-type semiconductor layer 295.

[0273] In addition, various films such as metal films, semiconductor films, and inorganic insulating films disclosed in the present specification and the like are formed by sputtering. It can be formed by the plasma CVD method, but other methods such as thermal CVD (C It may be formed by chemical vapor deposition (CVD). As an example of the D method, MOCVD (Metal Organic Chemical Vapor Deposition) Deposition method and ALD (Atomic Layer Deposition) method. You may also use the on method.

[0274] Thermal CVD is a film formation method that does not use plasma, so defects can occur due to plasma damage. This has the advantage that the

[0275] In the thermal CVD method, the source gas and the oxidizing agent are fed into the chamber at the same time, and the pressure inside the chamber is raised to atmospheric pressure. The film is formed by reacting the reactants near or on the substrate under reduced pressure and depositing them on the substrate. It is also possible.

[0276] In addition, in the ALD method, the pressure inside the chamber is set to atmospheric pressure or reduced pressure, and the source gas for the reaction is sequentially The gas may then be introduced into the chamber, and the gas introduction sequence may be repeated to form a film. For example, by switching between two or more switching valves (also called high-speed valves), The source gases are sequentially supplied to the chamber, and the first source gas is supplied to the chamber so as not to mix the source gases. Inert gas (argon, nitrogen, etc.) is introduced simultaneously with or after the feed gas. In addition, when an inert gas is introduced at the same time, the inert gas is The second source gas may be introduced simultaneously with the introduction of the inert gas. Also, instead of introducing an inert gas, the first source gas is discharged by evacuation. The first source gas is adsorbed on the surface of the substrate to form a first layer. The second layer is deposited on the first layer by reacting with the second source gas introduced later. This process is repeated several times while controlling the gas introduction sequence until a thin film of the desired thickness is formed. By doing so, a thin film with excellent step coverage can be formed. The thickness of the thin film depends on the order of gas introduction. The thickness can be precisely adjusted by changing the number of times the process is repeated. Suitable for making thin FETs (Field Effect Transistors). is.

[0277] The thermal CVD method such as the MOCVD method or the ALD method may be used in the above-described embodiments. It can form various films such as metal films, semiconductor films, and inorganic insulating films. For example, In-Ga In the case of forming a -Zn-O film, trimethylindium, trimethylgallium, and dimethyl Methyl zinc is used. The chemical formula for trimethylindium is In(CH 3) 3 is The chemical formula for trimethylgallium is Ga(CH 3 ) 3 Also, dimethyl zinc The chemical formula is Zn(CH 3 ) 2 In addition, the combination is not limited to these, and may be any combination. Instead of triethylgallium, triethylgallium (chemical formula Ga(C 2 H 5 ) 3 ) can also be used. Dimethyl zinc can be replaced by diethyl zinc (chemical formula Zn(C 2 H 5 ) 2 ) can also be used. can.

[0278] For example, when forming a hafnium oxide film using a film forming apparatus that uses ALD, the solvent and Liquids containing hafnium precursor compounds (such as hafnium alkoxides and tetrakisdimethylamine) The raw material gas is vaporized hafnium amide (TDMAH, etc.) and oxidized As an agent, ozone (O 3 Two types of gases are used: tetrakisdimethylamide hafnium The chemical formula for nium is Hf[N(CH 3 ) 2 ] 4 In addition, other material liquids include tetrahydrofuran. Examples include kis(ethylmethylamido)hafnium.

[0279] For example, when forming an aluminum oxide film using a film forming apparatus that uses ALD, a solvent and a liquid containing an aluminum precursor compound (e.g., trimethylaluminum (TMA)) The raw gas is oxidized and H 2 Two types of gases are used: trimethylammonia, trimethylphenylacetone, and trimethylphenylacetone. The chemical formula for aluminum is Al(CH 3 ) 3Other liquid materials include Tris(diisopropyl alcohol, Methylamido)aluminum, triisobutylaluminum, aluminum tris(2, 2,6,6-tetramethyl-3,5-heptanedionate).

[0280] For example, when forming a silicon oxide film using a deposition system that uses ALD, The chlorine contained in the adsorbed material is removed, and the oxidizing gas (O 2 , nitrous oxide) radicals are supplied to react with the adsorbate.

[0281] For example, when forming a tungsten film using a deposition system that uses ALD, the WF 6 G S and B 2 H 6 The gases are introduced repeatedly in sequence to form an initial tungsten film, and then WF 6 Gas and H 2 The gases are introduced repeatedly in sequence to form a tungsten film. 2 H 6 gas Instead of SiH 4 A gas may also be used.

[0282] For example, an oxide semiconductor film, such as In-Ga-Zn-O, can be formed by a film formation apparatus using ALD. When forming a film, In(CH 3 ) 3 Gas and O 3 Gases were introduced repeatedly in sequence to O layer, and then Ga(CH 3 ) 3 Gas and O 3 The gases were repeatedly introduced in sequence to form GaO layer, and then Zn(CH 3 ) 2 Gas and O 3 The gas was introduced repeatedly in sequence to form ZnO The order of these layers is not limited to this example. By forming mixed compound layers such as In-Ga-O layers, In-Zn-O layers, and Ga-Zn-O layers, It is also acceptable to 3 H obtained by bubbling inert gas such as Ar instead of gas 2 O Gas may be used, but it should not contain H. 3 It is preferable to use In(CH 3 ) 3 Instead of gas, In(C 2 H 5 ) 3 Gas may also be used. 3 ) 3 Instead of gas, Ga(C 2 H 5 ) 3 Gas may also be used. 3 ) 2 Gas You may use it.

[0283] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0284] (Embodiment 5) The peripheral circuits and pixel circuits include OR circuits, AND circuits, NAND circuits, and NOR circuits. Logic circuits, inverter circuits, buffer circuits, shift register circuits, flip-flop circuits circuits, encoder circuits, decoder circuits, amplifier circuits, analog switch circuits, integrator circuits, differentiation Circuits, memory elements, and the like can be provided as appropriate.

[0285] In this embodiment, a semiconductor device used for a peripheral circuit and a pixel circuit will be described with reference to FIGS. An example of a CMOS circuit that can be used is shown in FIG. 27(A) to FIG. 27(E). In the circuit diagram, an oxide semiconductor is used as the transistor in order to clearly show that the transistor is formed using an oxide semiconductor. The circuit symbol for a transistor using solid semiconductors is marked with "OS."

[0286] The CMOS circuit shown in FIG. 27A includes a p-channel transistor 281 and an n-channel The transistors 282 are connected in series and the gates of the transistors are connected together. 2 shows an example of the configuration of an inverter circuit.

[0287] The CMOS circuit shown in FIG. 27B includes a p-channel transistor 281 and an n-channel The transistors 282 are connected in parallel to form a so-called analog switch circuit. is.

[0288] The circuit shown in FIG. 27C is a source or drain of an n-channel transistor 289. One of the electrodes is connected to the gate of a p-channel transistor and one of the electrodes of a capacitor 257. The circuit shown in FIG. 27(D) is a configuration example of a so-called memory element. One of the source and drain of an n-channel transistor 289 is connected to the capacitor 257. 1 shows an example of the configuration of a so-called memory element connected to one electrode.

[0289] The circuits shown in FIG. 27(C) and FIG. 27(D) are the source or drain of the transistor 289. The charge input from the other input can be held at node 256. By using a transistor using an oxide semiconductor as the first transistor, the device can be used for a long period of time. The transistor 281 can hold a charge of 6. A transistor including an oxide semiconductor in a semiconductor layer may be used.

[0290] The circuit shown in FIG. 27(E) shows an example of the configuration of a photosensor. The source or the drain of the transistor 292 is formed using an oxide semiconductor in a semiconductor layer in which a channel is formed. One of the drains is electrically connected to the photodiode 291, and the other of the drains is connected to the source of the transistor 292. The other of the source and drain is electrically connected to the gate of transistor 293 through node 254. A transistor in which an oxide semiconductor is used for a semiconductor layer in which a channel is formed. 292 can make the off current extremely small, so the off current is determined according to the amount of light received. Therefore, the potential of the node 254 is unlikely to fluctuate. In addition, an imaging device with high linearity can be realized.

[0291] In addition, the peripheral circuits include a shift register circuit 1800 and a buffer circuit 19 shown in FIG. 00 may be provided in the peripheral circuit. A register circuit 1810, a buffer circuit 1910, and an analog switch circuit 2100 are combined. Each vertical output line 2110 is connected to an analog switch circuit 2100. The analog switch circuit 2100 outputs an output signal to an output line 2200. The shift register circuit 1810 and the buffer circuit 1910 enable sequential selection.

[0292] In the circuit diagram shown in the above embodiment, the wiring 137 (OUT) is An integrating circuit as shown in FIG. 29(B) or FIG. 29(C) may be connected. This increases the signal-to-noise ratio of the readout signal, making it possible to detect weaker light. That is, the sensitivity of the imaging device can be increased.

[0293] FIG. 29(A) shows an integrator circuit using an operational amplifier circuit (also called an OP amp). The inverting input terminal of the amplifier circuit is connected to the wiring 137 via a resistor R. The non-inverting input terminal is connected to the ground potential. The output terminal of the operational amplifier is connected to the and connected to the inverting input terminal of the operational amplifier circuit.

[0294] FIG. 29(B) shows an integrating circuit using an operational amplifier circuit having a different configuration from that shown in FIG. 29(A). The inverting input terminal of the operational amplifier circuit is connected to the wiring 137 (OUT The non-inverting input terminal of the operational amplifier circuit is connected to the ground potential. The output terminal of the path is connected to the inverting input terminal of the operational amplifier circuit via a capacitive element C2.

[0295] FIG. 29(C) shows a configuration of an operational amplifier circuit different from that shown in FIG. 29(A) and FIG. 29(B). The non-inverting input terminal of the operational amplifier is connected to the wiring 137 via a resistor R. The inverting input terminal of the operational amplifier circuit is connected to the output terminal of the operational amplifier circuit. The resistor R and the capacitor C constitute a CR integrator circuit. This configures a gain buffer.

[0296] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0297] (Embodiment 6) In this embodiment, a transistor that can be used for the transistor described in the above embodiment will be described. An example of the configuration of the star will be described with reference to FIGS.

[0298] [Bottom-gate transistor] The transistor 410 illustrated in FIG. 30A1 is a bottom-gate transistor. The transistor 410 is a channel protective transistor having a semiconductor layer 242. An insulating layer 209 that can function as a channel protection layer is provided on the channel formation region. The electrode 24 can be formed of the same material and by the same method as the insulating layer 117. A portion of electrode 245 and a portion of electrode 246 are formed on insulating layer 209 .

[0299] By providing an insulating layer 209 on the channel formation region, the electrodes 244 and 245 are formed. Therefore, the electrode 244 and the electrode 245 can be prevented from being exposed. This can prevent the semiconductor layer 242 from becoming thin when the semiconductor layer 45 is formed. A transistor with good electrical characteristics can be realized.

[0300] The transistor 411 shown in FIG. 30A2 has a back gate electrode over the insulating layer 118. The transistor 410 differs from the transistor 410 in that it has a functioning electrode 213. The electrode 213 is It can be formed using the same materials and methods as those of 243.

[0301] In general, the back gate electrode is formed of a conductive layer, and the gate electrode and the back gate electrode form a semiconductor. The back gate electrode is disposed so as to sandwich the channel forming region of the layer. The back gate electrode can function in the same manner as the gate electrode. Alternatively, the back gate electrode may be set to the GND potential or any other potential. By changing the gate electrode independently, the threshold voltage of the transistor can be changed. It can be made into a

[0302] Both the electrode 243 and the electrode 213 can function as a gate electrode. The insulating layer 117, the insulating layer 209, and the insulating layer 118 function as gate insulating layers. It is possible.

[0303] When one of the electrodes 243 and 213 is referred to as a "gate electrode," the other is referred to as a "back electrode." For example, in the transistor 411, the electrode 213 is When referring to a "gate electrode," the electrode 243 may be referred to as a "back gate electrode." When the electrode 213 is used as a "gate electrode", the transistor 411 is a top gate. In addition, the electrodes 243 and 213 can be considered as a type of transistor. One of them may be called the "first gate electrode" and the other the "second gate electrode." be.

[0304] By providing the electrode 243 and the electrode 213 with the semiconductor layer 242 interposed therebetween, 3 and the electrode 213 are set to the same potential, the region in which carriers flow in the semiconductor layer 242 The area becomes larger in the film thickness direction, so the amount of carrier movement increases. As the on-current of the transistor 411 increases, the field effect mobility also increases.

[0305] Therefore, the transistor 411 is a transistor having a large on-current relative to its area. That is, the area occupied by the transistor 411 is determined for the required on-current. According to one aspect of the present invention, the area occupied by a transistor can be reduced. Therefore, according to one embodiment of the present invention, a highly integrated semiconductor device can be realized. It is possible.

[0306] In addition, since the gate electrode and the back gate electrode are formed of a conductive layer, they can be electrically connected to the outside of the transistor. The function of preventing the electric field generated from acting on the semiconductor layer in which the channel is formed (especially static electricity It has an electrostatic shielding function against

[0307] In addition, the electrodes 243 and 213 each have a function of blocking an electric field from the outside. Therefore, the electric charges of the charged particles generated on the insulating layer 109 side or above the electrode 213 are transferred to the semiconductor layer 2. This does not affect the channel formation region of the gate 42. As a result, stress tests (e.g., negative Applying electric charge - GBT (Gate Bias-Temperature) stress test ) degradation is suppressed, and the on-current rise voltage at different drain voltages is This effect is achieved when the electrodes 243 and 213 are of the same potential. This occurs when the potentials are the same or different.

[0308] The BT stress test is a type of accelerated test that measures the transistor damage caused by long-term use. The change in the characteristics of the BT (i.e., aging) can be evaluated in a short time. The amount of change in the threshold voltage of a transistor before and after a stress test is used to check reliability. The smaller the change in threshold voltage before and after the BT stress test, the Therefore, it can be said that this is a highly reliable transistor.

[0309] In addition, the electrode 243 and the electrode 213 are provided, and the electrode 243 and the electrode 213 are set to the same potential. This reduces the amount of variation in threshold voltage. At the same time, the variation in electrical characteristics caused by the semiconductor device is reduced.

[0310] In addition, a transistor with a back gate electrode is called a +GBT, which applies a positive charge to the gate. The change in threshold voltage before and after the stress test was also observed for transistors without a back gate electrode. Smaller than Sta.

[0311] In addition, when light is incident from the back gate electrode side, the back gate electrode is made of a material having a light blocking property. By forming the semiconductor layer from a conductive film, light is prevented from entering the semiconductor layer from the back gate electrode side. This prevents the semiconductor layer from being photodegraded and the threshold voltage of the transistor is shifted. This can prevent deterioration of electrical characteristics such as the occurrence of

[0312] According to one embodiment of the present invention, a transistor with high reliability can be provided. A highly reliable semiconductor device can be realized.

[0313] The transistor 420 illustrated in FIG. 30B1 is a bottom-gate transistor. The transistor 420 is a channel protection transistor having a structure similar to that of the transistor 41. 2. It has a structure similar to that of the semiconductor layer 242, except that the insulating layer 209 covers the semiconductor layer 242. In addition, a portion of the insulating layer 209 overlapping the semiconductor layer 242 is selectively removed to form an opening. At the opening, the semiconductor layer 242 and the electrode 244 are electrically connected. In the opening formed by selectively removing a part of the insulating layer 209 overlapping with the semiconductor layer 42, The insulating layer 209 overlaps with the channel forming region. The region can function as a channel protection layer.

[0314] The transistor 421 illustrated in FIG. 30B2 has a back gate electrode over the insulating layer 118. It differs from transistor 420 in that it has a functioning electrode 213 .

[0315] By providing the insulating layer 209, the semiconductor layer 2 generated during the formation of the electrode 244 and the electrode 245 is prevented from being damaged. Therefore, when the electrodes 244 and 245 are formed, the semiconductor 42 is prevented from being exposed. Thinning of the layer 242 can be prevented.

[0316] In addition, the transistors 420 and 421 are the same as the transistors 410 and The distance between the electrodes 244 and 243 and the distance between the electrodes 245 and 243 are smaller than the distance between the electrodes 244 and 243. Therefore, the parasitic capacitance between the electrodes 244 and 243 is reduced. In addition, the parasitic capacitance between the electrode 245 and the electrode 243 can be reduced. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided.

[0317] [Top-gate transistor] The transistor 430 illustrated in FIG. 31A1 is a top-gate transistor. The transistor 430 has a semiconductor layer 242 on the insulating layer 109. 42 and the insulating layer 109, an electrode 244 in contact with a part of the semiconductor layer 242 and a semiconductor layer The semiconductor layer 242, the electrode 244, and the electrode 24 9 has an insulating layer 117 thereon, and an electrode 243 is provided on the insulating layer 117 .

[0318] The transistor 430 is connected between the electrodes 243 and 244, and between the electrodes 243 and 244. Since the electrodes 243 and 244 do not overlap, the parasitic capacitance between the electrodes 243 and 244 and the The parasitic capacitance between the electrode 243 and the electrode 245 can be reduced. After forming the semiconductor layer 242, the electrode 243 is used as a mask to introduce the impurity element 255 into the semiconductor layer 242. By introducing the impurity into the semiconductor layer 242, an impurity region is formed in a self-aligned manner in the semiconductor layer 242. According to one embodiment of the present invention, the electrical characteristics of the A good transistor can be realized.

[0319] The impurity element 255 is introduced by an ion implantation device, an ion doping device, or a plasma This can be done using a processing device.

[0320] The impurity element 255 is, for example, at least one of Group 13 elements or Group 15 elements. In addition, when an oxide semiconductor is used for the semiconductor layer 242, In this case, the impurity element 255 is at least one of a rare gas, hydrogen, and nitrogen. It is also possible to use elements.

[0321] The transistor 431 shown in FIG. 31A2 has an electrode 213 and an insulating layer 217. The transistor 431 is formed on the insulating layer 109. The electrode 213 is provided with an insulating layer 217 formed on the electrode 213. The electrode 213 can function as a back gate electrode. The insulating layer 217 can function as a gate insulating layer. and methods.

[0322] Like the transistor 411, the transistor 431 has a large on-state current relative to its area. That is, for the required on-current, the transistor 4 According to one aspect of the present invention, the area occupied by the transistor 31 can be reduced. Therefore, according to one aspect of the present invention, a highly integrated semiconductor device can be manufactured. It is possible to realize a body device.

[0323] The transistor 440 illustrated in FIG. 31B1 is a top-gate transistor. The transistor 440 is formed by forming the semiconductor layer 2 after forming the electrode 244 and the electrode 249. The transistor 430 differs from the transistor 430 in that the transistor 42 is formed. The transistor 441 has an electrode 213 and an insulating layer 217. In the transistor 440 and the transistor 441, a part of the semiconductor layer 242 A portion of the semiconductor layer 242 is formed on an electrode 244 , and another portion of the semiconductor layer 242 is formed on an electrode 245 .

[0324] Like the transistor 411, the transistor 441 has a large on-state current relative to the area it occupies. That is, for the required on-current, the transistor 4 According to one aspect of the present invention, the area occupied by the transistor 41 can be reduced. Therefore, according to one aspect of the present invention, a highly integrated semiconductor device can be manufactured. It is possible to realize a body device.

[0325] After forming the electrode 243, the transistor 440 and the transistor 441 are also connected to the electrode 24. 3 as a mask to introduce an impurity element 255 into the semiconductor layer 242, According to one aspect of the present invention, an impurity region can be formed in a self-aligned manner in the semiconductor substrate 242. A transistor with favorable electrical characteristics can be realized. This makes it possible to realize a highly integrated semiconductor device.

[0326] [s-channel transistor] In the transistor 450 illustrated in FIG. 32, the upper surface and side surfaces of the semiconductor layer 242b are FIG. 32A is a top view of the transistor 450. 32(B) is a cross-sectional view of the portion indicated by the dashed line X1-X2 in FIG. 32(A) (channel FIG. 32(C) is a cross-sectional view in the longitudinal direction. 4 is a cross-sectional view (cross-sectional view in the channel width direction) of the portion.

[0327] By providing the semiconductor layer 242 on the protrusions provided on the insulating layer 109, the semiconductor layer 242b The side surface of the transistor 450 can also be covered with the electrode 243. The semiconductor layer 242b can be electrically surrounded by the electric field. In this way, the structure of a transistor in which the semiconductor is electrically surrounded by the electric field of the conductive film is This is called a surrounded channel (s-channel) structure. A transistor with a channel structure is also called an "s-channel transistor." It is also called an "s-channel transistor."

[0328] In the s-channel structure, a channel is formed in the entire semiconductor layer 242b (bulk). In the s-channel structure, the drain current of the transistor is increased. In addition, the electric field of the electrode 243 can be used to obtain a larger on-state current. As a result, the entire channel formation region formed in the semiconductor layer 242b can be depleted. Therefore, in the s-channel structure, the off-state current of the transistor can be further reduced. It is possible.

[0329] In addition, by making the protrusion of the insulating layer 109 high and reducing the channel width, The n-nel structure can increase the on-current and reduce the off-current. In addition, when forming the semiconductor layer 242b, the exposed semiconductor layer 242a may be removed. In this case, the side surfaces of the semiconductor layer 242a and the semiconductor layer 242b may be aligned.

[0330] 33, a transistor 451 is provided below the semiconductor layer 242 with an insulating layer interposed therebetween. An electrode 213 may be provided. FIG. 33A is a top view of the transistor 451. 33(B) is a cross-sectional view of the portion indicated by the dashed line X1-X2 in FIG. 33(C) is a cross-sectional view of the portion indicated by the dashed line Y1-Y2 in FIG. 33(A).

[0331] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0332] (Embodiment 7) In this embodiment, an example of an electronic device using an imaging device according to one embodiment of the present invention will be described. do.

[0333] Examples of electronic devices using an imaging device according to one embodiment of the present invention include display devices such as televisions and monitors, Lighting equipment, desktop or notebook personal computers, word processors The digital content is stored on a recording medium such as a DVD (Digital Versatile Disc). Image reproducing devices that reproduce still or moving images, portable CD players, radios, tape recorders, etc. Coders, headphone stereos, stereos, navigation systems, table clocks, wall-mounted clocks meters, cordless telephone handsets, transceivers, mobile phones, car phones, portable game consoles, tabs Laptop terminals, large game machines such as pachinko machines, calculators, personal digital assistants, electronic organizers, electronic books Books, electronic translators, voice input devices, video cameras, digital still cameras, electric shavers, Microwave ovens and other high-frequency heating devices, electric rice cookers, electric washing machines, vacuum cleaners, water heaters, electric fans , hair dryers, air conditioners, humidifiers, dehumidifiers and other air conditioning equipment, dishwashers, Dryers, clothes dryers, futon dryers, electric refrigerators, electric freezers, electric refrigerator-freezers, DNA Storage freezers, flashlights, tools such as chainsaws, smoke detectors, medical equipment such as dialysis machines, Fax machines, printers, multi-function printers, automated teller machines (ATMs), vending machines In addition, emergency exit lights, traffic lights, conveyor belts, elevators, escalators, etc. data center, industrial robots, energy storage systems, energy leveling and storage for smart grids In addition, fuel-powered engines and non-aqueous secondary batteries are also used. Mobile objects propelled by electric motors using electric power are also included in the category of electronic devices. The above-mentioned moving body may be, for example, an electric vehicle (EV), a hybrid vehicle that combines an internal combustion engine and an electric motor, or a hybrid vehicle that combines an internal combustion engine and an electric motor. Hybrid electric vehicles (HEV), plug-in hybrid electric vehicles (PHEV), and their tires and wheels tracked vehicles, including electric-assist bicycles, motorbikes, motorcycles, Electric wheelchairs, golf carts, small or large boats, submarines, helicopters, aircraft, location shooting Examples include satellites, space probes, interplanetary probes, and spacecraft.

[0334] FIG. 34A shows a video camera, which includes a first housing 941, a second housing 942, a display unit 943, The operation key 944, the lens 945, the connection part 946, etc. 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connection portion 946. The angle between the first housing 941 and the second housing 942 can be changed by the connection part 946. The image on the display unit 943 is transmitted between the first housing 941 and the second housing 94 at the connection unit 946. 2. The focal point of the lens 945 may be set to the position shown in FIG. can be equipped with an imaging device according to one aspect of the present invention.

[0335] FIG. 34B shows a mobile phone. A housing 951 includes a display unit 952, a microphone 957, and a speaker. The device includes a display 954, a camera 959, an input / output terminal 956, and an operation button 955. The imaging device of one embodiment of the present invention can be used for 959.

[0336] FIG. 34C shows a digital camera, which includes a housing 921, a shutter button 922, and a microphone 9 23, a light emitting unit 927, a lens 925, etc. The imaging device according to the present invention may include an imaging device according to the present invention.

[0337] FIG. 34D shows a portable game machine, which includes a housing 901, a housing 902, a display unit 903, and a display unit 904. 904, microphone 905, speaker 906, operation keys 907, stylus 908, camera 909, etc. The portable game machine shown in FIG. and a display unit 904, but the number of display units that the portable game machine has is not limited to this. The imaging device of one embodiment of the present invention can be used as the camera 909.

[0338] FIG. 34E shows a wristwatch-type information terminal, which includes a housing 931, a display unit 932, and a wristband 9 The display unit 932 may be a touch panel. The imaging device according to one embodiment of the present invention can be used for the laser 909.

[0339] FIG. 34(F) shows a portable data terminal, which includes a first housing 911, a display unit 912, a camera 919, etc. The display unit 912 has a touch panel function that allows input and output of information. The imaging device of one embodiment of the present invention can be used for the camera 909.

[0340] Note that the electronic device is not limited to the above-described electronic devices as long as it includes the imaging device according to one embodiment of the present invention. Needless to say, this is not possible.

[0341] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is. EXAMPLES

[0342] The solid-state imaging device 800 shown in the above embodiment was fabricated, and imaging data was acquired. 5(A) is a photograph showing the appearance of the fabricated solid-state imaging device. A pixel array is made up of multiple pixels arranged in a matrix. el) and peripheral circuits (Row Driver) for supplying signals to each pixel. and Column Driver) are provided outside the pixel area. The driver is an A / D converter that converts analog data into digital data. FIG. 35B is a block diagram showing the configuration of the solid-state imaging device 800. The specifications of the solid-state imaging device 800 are shown in the center column of FIG.

[0343] FIG. 37 shows a circuit diagram of a pixel included in the solid-state imaging device 800. The pixel has a circuit configuration similar to that of the pixel shown in the above embodiment. The 800 uses a sharing transistor for each pixel. The transistor 829 functions as a The transistor 821 in FIG. This corresponds to the transistor 121 or the transistor 125 shown in FIG. The transistor 821 functions as a transfer transistor.

[0344] In this example, the transistor 829 and the transistor 821 are formed using an oxide semiconductor. did.

[0345] 38 is a timing chart illustrating the imaging operation of the solid-state imaging device 800. As shown in FIG. 1, the pixels corresponding to Tx1 to Txn are sequentially reset and exposed. Then, The pixels in each row are read out in sequence and converted to digital data by the A / D converter. do.

[0346] As shown in FIG. 39, the transistors 821 are sequentially turned on by dividing the transistors into Tx1 to Txn. By doing so, exposures are continuously performed at short intervals. In addition, the image data can be captured sequentially after continuous exposure. Next, read and convert the signal into digital data. / slow read out enables high-speed continuous imaging, and the A / D converter requires no special High speed is not required. Therefore, the area occupied by the peripheral circuits can be reduced. The power consumption of the side circuits can be reduced.

[0347] In addition, in this imaging method, the time from exposure to readout differs depending on the pixel row. By using a FET that uses an oxide semiconductor for the transistor 821, the charge leakage from the node FD is This is possible by reducing the number of phototransistors. By sharing the diode, multiple nodes FD can be charged individually. Compensates for degradation in image quality caused by time reduction.

[0348] FIG. 40 shows an image captured by the solid-state imaging device 800 of a rotating object at about 6000 rpm. Here, the start timing of Exposure Tx1 and Exposure Tx2 The time interval between Tx1 and Tx2 is 300 μs. )) with the image captured by the pixel corresponding to Tx2 (Figure 40(B)). In other words, the proposed imaging operation rotates the camera in a short time. It was confirmed that continuous imaging was possible at intervals. In addition, this imaging operation reduced the number of peripheral circuits However, there is no need for particularly high speed. EXAMPLES

[0349] Silicon n-channel FET (Nch-Si), silicon p-channel FET (Pch-Si) and CAAC-OS-FET using In-Ga-Zn oxide (also called "CAAC-IGZO-FET"). The horizontal axis of FIG. 41(A) shows the voltage between the gate and source. The vertical axis of 41(A) indicates the current flowing through the drain. The direction of the current flowing through the input is reversed, so the obtained value is multiplied by -1. The voltage between the source and drain was set to 1.9 V (−1.9 V for p-channel FET).

[0350] FIG. 41B shows the noise characteristics of the above-mentioned FET.

[0351] As shown in Fig. 41(A) and Fig. 41(B), the driving performance of the CAAC-IGZO-FET has improved with miniaturization. In addition to improved power, it is suggested that the device has a noise advantage over Nch-Si-FETs. Therefore, the effectiveness of solid-state imaging devices that do not use Nch-Si-FETs can be expected. Based on these considerations, all pixel transistors are constructed with CAAC-IGZO-FETs, and the driver Peripheral circuits such as drivers and A / D conversion circuits are implemented using Pch-Si-FETs and CAAC-IGZO- A solid-state image sensor constructed using CMOS with FET (also called "hybrid CMOS"). The specifications of the prototype solid-state image sensor are shown in the right column of Figure 36. This is shown in the figure.

[0352] The pixel layout diagram is shown in Figure 42. The prototype solid-state imaging device has a front side i The fill factor is 31%, but the back By applying side illumination, 100% fill facto r is possible.

[0353] The measurement results of the peripheral circuit are shown in Figure 43. The column driver synchronizes with the clock (CCK) It was confirmed that the image data output enable signal (COUT) was being output. CAAC-IGZO FET / Pch-Si FET hybrid CMOS solid-state imaging The actual operation of the peripheral circuits of the element was confirmed. EXAMPLES

[0354] A solid-state imaging device 810 was manufactured as the display device according to the above embodiment, and imaging data was acquired. FIG. 44(A) is a photograph showing the appearance of the fabricated solid-state imaging device 810. FIG. 45B is a schematic diagram showing a layered structure of the solid-state imaging device 810. FIG. 8 is a block diagram showing the circuit configuration of the solid-state imaging device 810. , as shown in Figure 46.

[0355] The solid-state imaging device 810 is arranged in a matrix in a pixel area (Pixel Array). The solid-state imaging device 810 also includes a peripheral circuit (Ro Driver, Column Driver, and A / D Converter etc.) are provided outside the pixel area.

[0356] The Row Driver controls the pixels that read out the image data acquired by imaging. The A / D converter selects the image data that is read out. It has the function of converting analog data to digital data. Column Driver sequentially selects image data (digital data) to be transferred to the outside of the solid-state imaging device 810 It has functions.

[0357] All the transistors in the pixel area are CAAC-IGZO-FETs. There is no need to provide pixel transistors on the silicon substrate, and the flat panel display can be provided on the silicon substrate. This allows the area of ​​the photodiode to be enlarged to the size of a subpixel. It is expected that the light sensitivity of the solid-state image sensor 810 will be improved. Because it uses the front side illumination method that captures light from the top The fill factor is 31% due to the influence of the upper wiring, but the back side If llumination can be applied, the fill factor will be 100%. It is possible.

[0358] The solid-state imaging device 810 is a Pch-Si-FET with a technology size of 0.18 μm and a Hybrid process using CAAC-IGZO-FET with a technology size of 0.35 μm The die size is 6.5 mm × 6.0 mm. The pixel of the pixel 810 is composed of two sub-pixels. In order to support Bayer patterns and other patterns when performing image grading, two sub-sampling methods are available. In this configuration, sub-pixels belonging to different pixels are sandwiched between the sub-pixels (see FIG. 47).

[0359] In the solid-state imaging device 810 according to the above embodiment, the photodiode PD is shared between the sub-pixels. A method of imaging in which the photodiodes are connected between the sub-pixels (also called the "continuous imaging sharing method"). An imaging method that does not share the optical PD (also called the "continuous imaging non-sharing method"). ) is possible, as well as an imaging method in which sub-pixels are independent pixels (also called the "normal imaging method"). It is possible to set the above in accordance with the object to be imaged and the purpose of image capture.

[0360] <Imaging method> Each imaging method will be described below.

[0361] [Continuous image sharing method] First, we will explain the continuous imaging sharing method. When the transistor 829 is turned on, the sub-pixels are combined into one pixel. By combining the photodiodes PD of each subpixel, a highly sensitive pixel can be created. The pixel driving method is to drive the sub-pixels TX1, TX2, ..., TXn of all pixels. The sub-pixels of each row are reset and exposed in sequence, and the sub-pixels of each row are read out in sequence. The signal is then converted to digital data by the A / D converter. This allows continuous imaging without changing the focus.

[0362] The reset operation is performed by a reset transistor, a transistor 821 which is a transfer transistor, The transistor 829 is turned on to turn on the photodiode PD and sh of the corresponding subpixel. The wiring path (the wiring connecting the transistors 829 of the two pixels) is reset. The exposure operation is performed by charging the transistor 821 and the transistor 82 When the photodiodes 9 are turned on, the photocurrent of the n photodiodes PD is The read operation is performed by turning on the selection transistor. The source follower output of the amplification transistor is connected to the A / D converter connected to the OUT wiring. This is done by converting the signal into digital data using a digital camera.

[0363] [Continuous imaging non-sharing method] Next, we will explain the continuous imaging non-sharing method. The transistor is turned off and each sub-pixel is treated as an independent pixel. The sub-pixels corresponding to TX1 to TXn of all pixels are sequentially reset and exposed. The sub-pixels of each row are read out sequentially, and the digital data is output to the A / D converter. In other words, a continuous image capture method is possible. Unlike the aring method, the photodiodes of each subpixel are not shared, so the sensitivity is low. However, since there is no contribution from sharing paths that can be noise sources, This is advantageous.

[0364] [Normal imaging method] Finally, a normal imaging method will be described. In this method, the transistor 829 is turned off. The pixel driving method is to drive all the pixels TX1 to TX2. The sub-pixels corresponding to each row of pixels Xn are reset and exposed simultaneously. The pixels are read out in sequence and converted into digital data by the A / D converter. That is, imaging similar to that achieved with a normal image sensor becomes possible.

[0365] <Imaging results> In the continuous imaging sharing method, continuous imaging non-sharing method, and normal imaging method In order to confirm that imaging is possible with a uniform light source from a stationary light source, the solid-state imaging device 810 was Light was irradiated and an image was taken using the imaging method described above.

[0366] Specifically, the continuous image sharing method (hereinafter referred to as "method A"), the continuous image sharing method Using the ring method, only the sub-pixels corresponding to TX1 are captured (hereafter referred to as "method B"), continuous shooting Image sharing method captures only the sub-pixels corresponding to TX2 (hereafter referred to as "method C") , Continuous imaging non-sharing method (hereinafter referred to as "D method"), continuous imaging non- Sharing method captures only the sub-pixels corresponding to TX1 (hereinafter referred to as "E method"); Continuous imaging non-sharing method captures only sub-pixels corresponding to TX2 (hereinafter, "F The seven imaging methods used were: The light source was a metal halide lens manufactured by Hayashi Watch Co., Ltd. The image capture reset time was 90 μs and the exposure time was was set to 180 μs.

[0367] The captured image is shown in FIG. 48, the gradation histogram of the captured image is shown in FIG. 49, and the different imaging methods are shown in FIG. Figures 50 and 51 show histograms of the gradation difference for each pixel based on the formula, and In this case, the standard deviation of the gray level difference between two different frames out of five frames is shown in FIG. The "gradation" in the figure is the output digital value after A / D conversion of the captured image. The larger the value, the brighter the light, and the smaller the value, the darker the light. In order to compare the raw noise in each imaging method, including the contribution of ath, The raw image data shown here is not CDS processed. Includes noise that can be cancelled by CDS (Compensated Double Sampling) I am.

[0368] [Imaging results using the continuous imaging sharing method] First, we confirmed the continuous image sharing method. Specifically, for TX1 and TX2, Check the effect on captured images of capturing images by capturing images of corresponding sub-pixels in succession in a short period of time. Therefore, the TX1 image and TX2 image of the A system, the TX1 image and the TX1 image of the B system, The TX2 images of the TX2 and C systems were compared. These are the captured images that should match.

[0369] TX1 image and TX2 image of A system, TX1 image of A system and TX1 image of B system, The average difference between the TX2 image and the TX2 image of the C method is shown in the histogram of Fig. 49(A). The histogram shapes are almost the same at 0.11, 0.15, and 0.08 gradations, respectively. It can be seen that.

[0370] In addition, the gradation difference between the TX1 image and the TX2 image of the A system, and the TX1 image and the TX The gradation difference between the TX2 image of the A system and the TX2 image of the C system is shown in Fig. 5. From the histograms in Figure 50(A), Figure 50(B), and Figure 50(C), the standard deviations are 15.91, respectively. , 8.12, and 7.30. Regarding the gradation difference between the TX1 image and the TX2 image of the A system, The standard deviation estimated from the standard deviations of 12.02 and 12.30 of each histogram in Figure 49(A) Difference (12.02 2 +12.30 2 ) 1 / 2 = 17.20, so the pixel plane It can be seen that the distribution is within the range estimated from the variation.

[0371] The gradation difference between the TX1 image of the A system and the TX1 image of the B system, and the TX2 image of the A system and the T Regarding the gradation difference with the X2 image, the standard deviations in Figure 52 are 5.19 to 8.35 and 5.50 to Since the distribution is similar to that of 8.08, it is consistent with the distribution estimated from the inter-frame variation. It can be seen that.

[0372] Based on the above, in the continuous image sharing method, the sub- It was found that each pixel can capture an image independently using the same photodiode.

[0373] [Imaging results using the continuous imaging non-sharing method] Next, we confirmed the continuous imaging non-sharing method. The effect of capturing images by capturing images of the sub-pixels corresponding to X2 in succession in a short period of time was examined. To confirm, the TX1 image and the TX2 image of the D system, and the TX1 image and the TX1 image of the E system are The images were compared between the TX2 image of the D system and the TX2 image of the F system. is the range of deviation in the irradiated light intensity due to the difference in the positions of the sub-pixels corresponding to TX1 and TX2. These are captured images that should match within the range.

[0374] TX1 image and TX2 image of D type, TX1 image of D type and TX1 image of E type, The average difference between the TX2 image and the F-type TX2 image is shown in the histogram of Fig. 49(B). The histogram shapes are almost the same at 0.61, 0.66, and 0.33 gradations. You can understand.

[0375] In addition, the gradation difference between the TX1 image and the TX2 image of the D system, and the TX1 image of the D system and the TX Figure 50 shows the difference in gradation between the TX2 image of the D system and the TX2 image of the F system. From the histograms in Figures 50(D), 50(E), and 50(F), the standard deviations are 9.14 and 4. The gradation difference between the TX1 and TX2 images of the D system is shown in Fig. 4. The standard deviation (7. 61 2 +7.40 2 )1 / 2 = 10.61, so the in-plane variation of the pixels It can be seen that the distribution is within the estimated range.

[0376] The gradation difference between the TX1 image of the D system and the TX1 image of the E system, and the TX2 image of the D system and the T Regarding the gradation difference with the X2 image, the standard deviations in Fig. 52 are 2.75 to 3.68 and 3.22. The distribution is estimated based on the inter-frame variation, since the values ​​are about the same as 3.89. It can be seen that.

[0377] For the above reasons, in the continuous imaging non-sharing method, TX1 and TX2 are supported. It can be seen that the captured image can be obtained independently by using the corresponding sub-pixels.

[0378] [Image capture results using normal imaging method] Next, we checked the normal imaging method. Specifically, the sub-pixels corresponding to TX1 and TX2 In order to confirm the effect of simultaneous or independent imaging on the captured image, TX1 image and TX2 image of type E, TX1 image and TX1 image of type G, TX The 2 images and the G-type TX2 images are compared. These images are taken with TX1 and TX2 The positions of the sub-pixels corresponding to the respective images should be consistent within the range of deviation in the illumination light intensity. It is an image.

[0379] TX1 image and TX2 image of G system, TX1 image of E system and TX1 image of G system, The average difference between the TX2 image and the G-type TX2 image is shown in the histogram of Fig. 49(C). The histogram shapes are almost the same at 0.55, 0.37, and 0.79 gradations. You can understand.

[0380] In addition, the gradation difference between the TX1 image and the TX2 image of the G system, the TX1 image of the E system and the TX The gradation difference between the TX2 image of the F system and the TX2 image of the G system is shown in Fig. 5. From the histograms in Fig. 1(A), Fig. 51(B), and Fig. 51(C), the standard deviations are 8.91 and 8.92, respectively. 4.92 and 4.12. The gradation difference between the G-type TX1 image and the TX2 image is shown in Fig. The standard deviation (8 .twenty three 2 +7.89 2 ) 1 / 2 = 11.40, it is due to the in-plane variation of the pixels. It can be seen that the distribution is within the range estimated from the above.

[0381] The difference in tone between a TX1 image in the G mode and a TX1 image in the E mode, and between a TX2 image in the G mode and a T image in the F mode. Regarding the gradation difference with the X2 image, the standard deviations in Fig. 52 are 2.75 to 4.86 and 2.93. The distribution is estimated from the frame-to-frame variation, because it is about the same as 3.95. It can be seen that.

[0382] Based on the above, in the normal imaging method and the continuous imaging sharing method, TX1, TX2 It was found that a similar captured image could be obtained using the sub-pixels corresponding to

[0383] [Comparison of sensitivity between continuous imaging sharing method and continuous imaging non-sharing method] Next, we compared the sensitivity of the continuous imaging sharing method and the continuous imaging non-sharing method. By doing so, we were able to confirm the effect of improving sensitivity by turning on the sharing transistor. In both imaging methods, the metal halide lamp LA-180 manufactured by Hayashi Watch Co., Ltd. Images were taken when the light intensity was changed and uniform light was irradiated from Me-R4. The shot time was 90 μs and the exposure time was 180 μs. After performing CDS processing on the software using the reset image in each imaging method, Regarding the relationship between the amount of light (irradiation light intensity x irradiation time) and the output digital value (gradation value) after A / D conversion, I asked for a representative.

[0384] The input voltage of the A / D conversion circuit (corresponding to the source follower output voltage of the pixel) and the grayscale value are From this relationship, the sensitivity can be calculated by finding the relationship between the grayscale value and the source follower output voltage of the pixel. As a result, as shown in Figure 46, the continuous imaging sharing method and the continuous imaging non-s The sensitivity of the haring method is 0.224V / (lx·s) and 0.196V / (lx·s), respectively. s).

[0385] This shows that turning on the sharing transistor improves sensitivity by about 14%. We were able to confirm this. We expect that further improvement in sensitivity will be achieved by optimizing the sharing path. .

[0386] Next, to demonstrate that the above imaging method allows short-term continuous imaging, a solid-state imaging device 81 The image was taken of a fan rotating at high speed at 0 (see Fig. 53(A)). Therefore, the image of the shadow of the fan was actually captured. The fan speed was set to 6000 rpm, and the image capture interval was set to 300 μs. The captured images at the sub-pixels corresponding to X1 and TX2 are shown in FIG. 53(B) and FIG. 53(C). Here, a reset image and an all-white image are captured in advance, and then each is set to gradation 0 and gradation 2. The contrast is adjusted by processing the image to 55 using software. In FIG. 53C, when comparing the captured images at the sub-pixels corresponding to TX1 and TX2, A deviation of approximately 11° was confirmed, which is equivalent to the angle of rotation at 6000 rpm in a period of 300 μs. In other words, it was confirmed that the above imaging method makes it possible to capture images continuously in a short period of time.

[0387] [Short-term continuous imaging] Next, the power consumption of the solid-state imaging device 810 was measured when the imaging interval was 300 μs. The results of the force measurement are shown in FIG. 54(A). In FIG. 54(A), The breakdown of power consumption in the solid-state imaging device 810 is also shown. It was W.

[0388] Next, a conventional solid-state imaging device (an image sensor for a high-speed camera disclosed in Non-Patent Document 1) will be described. The power consumption of the conventional solid-state imaging device was compared with that of the solid-state imaging device 810. A comparison of the body imaging device 810 is shown in FIG. 54(B). In FIG. 54(B), the FOM (Figure FOM=power consumption÷(number of Merit) er of pixels×frame rate×resolution of A / In the solid-state imaging device 810, the imaging interval is 300 Since it is possible to capture images at 3333 fps, the FOM is 1.58 pW / On the other hand, the image resolution of conventional solid-state imaging devices is 514×530, A / D converter resolution is 12bit, 3500fps Since the power consumption at is 1W, the FOM is 87.40pW / (pixel×fp s×bit). When comparing the FOMs of the two imaging methods, the power consumption of the solid-state imaging device 810 is The power consumption of the solid-state imaging device 810 is about 1 / 55 of that of the conventional solid-state imaging device. It was confirmed that this device has an advantage in terms of power consumption compared to solid-state imaging devices.

[0389] The solid-state imaging device according to one embodiment of the present invention does not require a high-speed A / D conversion circuit and therefore consumes low power. According to one aspect of the present invention, a Pch-Si-FET and a CAAC-IGZ Peripheral circuits such as A / D conversion circuits, row drivers, and column drivers can be constructed using only O-FETs. In addition, the pixel circuit can be constructed only with CAAC-IGZO-FET and photodiode. Therefore, according to one aspect of the present invention, a Pch-Si-FET and a CAAC- It is possible to realize a stacked CMOS of IGZO-FET. This makes it possible to realize a CMOS configuration that does not require EXAMPLES

[0390] A solid-state imaging device 820 was manufactured as the display device according to the above embodiment. 1 is a photograph showing the appearance of a fabricated solid-state imaging device 820.

[0391] The solid-state imaging device 820 is arranged in a matrix in a pixel area (Pixel Array). The solid-state imaging device 820 also includes a peripheral circuit (Ro Driver, Column Driver, and A / D Converter etc.) are provided outside the pixel area.

[0392] The Row Driver controls the pixels that read out the image data acquired by imaging. The A / D converter selects the image data that is read out. It has the function of converting analog data to digital data. Column Driver sequentially selects image data (digital data) to be transferred to the outside of the solid-state imaging device 820 It has functions.

[0393] FIG. 55(B) is an enlarged photograph of one pixel 825 shown in FIG. 55(A). The pixel region includes a photodiode and a plurality of transistors. All the transistors are CAAC-IGZO-FETs. There is no need to provide a phototransistor, and the area of ​​the photodiode provided on the silicon substrate can be increased. This is expected to improve the light sensitivity of the solid-state imaging device 820. The body imaging device 820 is a front side imager that captures irradiated light from the top surface of the chip. Because of the ination method, the fill factor is 30% due to the influence of the upper wiring. However, if back and side illumination can be applied, A fill factor of 0.00% is possible.

[0394] The specifications of the solid-state imaging device 820 are shown in FIG. A Si-FET with a technology size (channel length) of 0.18 μm and a The device was fabricated using a hybrid process that uses a 3.35 μm CAAC-IGZO-FET. Oh, the die size is 6.5mm x 6.0mm.

[0395] The image of the object rotating at about 400 rpm captured by the solid-state imaging device 820 is shown in FIG. ) is shown. Note that FIG. 57(A-1) is an image of a stationary subject. 7(A-1) and 57(A-2) are images captured using the global shutter method. In addition, a smartphone (commercially available) with a camera mounted on it rotates at about 400 rpm. The image of the object is shown in FIG. 57(B-2). Note that FIG. 57(B-1) shows the image of the object in a stationary state. 57(B-1) and 57(B-2) are images of a subject in a rolling state. This is an image captured using a fast shutter method.

[0396] As shown in FIG. 57(B-2), when a rotating subject is captured using the rolling shutter method, On the other hand, from Figure 57(A-2), it can be seen that the image obtained is significantly distorted. When capturing an image of a rotating subject using the shutter method, an image with almost no distortion of the subject can be obtained. It can be seen that... EXAMPLES

[0397] In an optical flow system consisting of a DSP and an image sensor (imaging device), In order to obtain optical flow with high accuracy, high-speed imaging is required. The flow calculation does not require all images. Therefore, the conventional high frame rate image A range sensor is not necessarily effective because it captures many unnecessary images and consumes high power.

[0398] Therefore, the solid-state imaging device 830 according to the above embodiment is manufactured, and the solid-state imaging device 830 is used. The present invention proposes an optical flow system 880 that uses the solid-state imaging device 8 according to the above embodiment. The 30 is capable of continuous imaging at 100μs intervals, equivalent to 10,000fps. It is possible to read out at 1 fps. Therefore, when using the solid-state imaging device 830, The power consumption can provide enough imaging data to calculate optical flow.

[0399] FIG. 58(A) shows a block diagram of an optical flow system 880. (B) is a photograph showing the appearance of the fabricated solid-state imaging device 830. In the Stem 880, in order to reduce the burden on the power supply system, a solid-state imaging The device 830 captures two images at high speed and performs optical filtering by the DSP block 835. -Before calculation begins, the captured images are read out at a slow speed.

[0400] The solid-state imaging device 830 is arranged in a matrix in a pixel area (Pixel Array). The solid-state imaging device 830 also includes a peripheral circuit (Ro Driver, Column Driver, and A / D Converter FIG. 59 shows a block diagram of the solid-state imaging device 830. vinegar.

[0401] The Row Driver controls the pixels that read out the image data acquired by imaging. The A / D converter selects the image data that is read out. It has the function of converting analog data to digital data. Column Driver sequentially selects image data (digital data) to be transferred to the outside of the solid-state imaging device 830 It has functions.

[0402] A pixel has a photodiode and a plurality of transistors. All the transistors are CAAC-IGZO-FETs. This eliminates the need for a large-area photodiode on a silicon substrate. It can be made into

[0403] The specifications of the solid-state imaging device 830 are shown in FIG. A Si-FET with a technology size (channel length) of 0.18 μm and a It was fabricated using a hybrid process using a 3.35μm CAAC-IGZO-FET.

[0404] The solid-state imaging device 830 is a short interval continuous cap It is possible to capture two images at a short interval and perform low-frame readout. The readout can be done at any rate.

[0405] The DSP block 835 creates an optical flow from the two images. The circuit diagram of the pixel 830 is shown in Figure 61. A pixel has two sub-pixels. Each subpixel has four transistors, one photodiode, and one shared transistor. The two sub-pixels in a pixel are connected via a shared transistor. The LEDs can be shared. Also, considering the possibility of colorization, the Bayer PD is used. In order to accommodate turns, a subpixel belonging to another pixel is inserted between the two subpixels. The pixel transistor is composed of CAAC-IGZO FET. This improves the charge retention characteristics of the FD, enabling low-speed readout without degradation of image quality. This will be possible.

[0406] As shown in the timing chart of FIG. 62, the solid-state imaging device 830 sequentially transmits TX1 and TX2. By making the next exposure active, exposures are performed continuously at short intervals. The image data is read out row by row and A / D converted. Capturing / slow read out enables high-speed continuous imaging and A / D Since the converter is not required to be particularly fast, low power consumption can be expected.

[0407] Fan A rotates at 6500 rpm and fan B rotates at 10000 rpm. The optical flow was calculated from the captured images. At 1 fps, the capturing interval is 100 μs and 1000 μs. As an example, we calculated the optical flow for capturing int The measured waveform when erval is 100 μs is shown in Figure 63.

[0408] In Fig. 64(A) to Fig. 64(C), the capturing interval is 100 μs. 64(A) is a TX1 image, and FIG. 64(B) is a TX2 image. Figure 64(C) shows the optical flow calculated by the Lucas-Kanade method. In addition, in Fig. 65(A) to Fig. 65(C), the capturing interval is 10 The images shown are from 00 μs. Figure 65(A) is the TX1 image, and Figure 65(B) is the TX2 image. Figure 65(C) shows the optical flow calculated by the Lucas-Kanade method. It shows.

[0409] From Fig. 64(A) and Fig. 64(B) and Fig. 65(A) and Fig. 65(B), You can see the difference in the angle at which each fan rotates during the adapting interval. Also, from Figure 64(C), when the capturing interval is 100μs, On the other hand, in Figure 65(C), the optical flow of the capt Since the cooling interval is long at 1000μs, the flow direction of fan A is It even looks like the flow of Fan B is calculated as counter-rotating. Therefore, the optical field can be accurately determined from the images obtained by the solid-state imaging device 830 through high-speed continuous imaging. It was confirmed that it was possible to obtain low.

[0410] Next, to show that there is almost no degradation in image quality even at slow readout speeds, we set the frame rate Images of a stationary fan were taken at 1 fps and 60 fps. Figure 66(A) shows an image captured at a frame rate of 1 fps. The images shown are taken at a frame rate of 60 fps. It can be confirmed that the fan can be photographed.

[0411] In addition, the uniform surface at frame rates of 1 fps and 60 fps was The light source was imaged and the grayscale difference between the first and last lines of the readout was estimated. The gradation difference when shooting at a frame rate of 1 fps is 0.16, and at a frame rate of 60 fps The gradation difference when the image was captured was estimated to be 0.064. It was confirmed that the image quality is hardly degraded even at low frame rates due to the high frame rate.

[0412] In addition, in order to confirm the effect of reducing the power consumption of the solid-state imaging device 830, The power consumption and energy consumption per frame were measured under three conditions. The measurement results are shown in Figure 1. With condition 1 as the standard, the power of condition 2, which only lowers the frequency, is The power consumption in condition 3, which also lowered the voltage, was 92.3% of that in condition 1. It can be seen that the energy consumption per frame under condition 3 is lower than that under condition 1. At low frame rates, not only the frequency but also the voltage can be reduced, so the It was confirmed that this system has a high power-saving effect, which can reduce the energy consumption of the system.

[0413] For example, if a solid-state imaging device 830 with 128×128 pixels captures an image with 8-bit gradation, Consider the case where the image is captured at 00 fps and the optical flow is calculated at 1 fps. The power of the device 830 is 7.9 μW (= 9.2 μW / (240×80) from condition 3 in FIG. 67(B). )×(128×128)). By using this technology, it is possible to realize an optical flow system with high accuracy and low instantaneous power consumption. [Explanation of symbols]

[0414] 103 Insulating layer 104 Insulating layer 105 Insulating layer 106 Contact plug 107 Insulating layer 108 Insulating layer 109 Insulating Layer 110 Pixel section 111 pixels 112 subpixels 113 Insulating Layer 114 Contact plug 115 Insulating Layer 116 Insulating Layer 117 Insulating Layer 118 Insulating Layer 121 Transistor 122 Transistor 123 Transistor 124 Transistor 125 Transistor 126 Transistor 127 Transistor 128 Transistors 129 Transistor 131 Wiring 132 Wiring 133 Wiring 134 Wiring 135 Wiring 136 Wiring 137 Wiring 141 Wiring 142 Wiring 143 Wiring 144 Wiring 146 Wiring 151 Capacitive element 152 Transistor 153 Transistor 154 Transistor 155 Transistor 161 Wiring 201 Switch 202 Switch 203 Switch 205 Insulating layer 209 Insulating Layer 213 Electrode 217 Insulating Layer 220 Photoelectric conversion element 221 p-type semiconductor layer 222 i-type semiconductor layer 223 n-type semiconductor layer 224 Aperture 225 Aperture 226 Electrode 227 Electrode 230 Pixel Circuit 241 Transistor 242 Semiconductor layer 243 Electrode 244 electrode 245 Electrode 246 Transistor 249 Electrode 251 pixel area 252 Peripheral Circuit Area 254 nodes 255 Impurity elements 256 nodes 257 Capacitive element 260 Peripheral Circuits 261 Wiring 263 Wiring 265 Wiring 266 Wiring 267 Wiring 270 Peripheral Circuits 280 Peripheral Circuits 281 Transistor 282 Transistor 283 i-type semiconductor layer 284 Low concentration p-type impurity region 285 p-type semiconductor layer 286 Insulating Layer 287 Electrode 288 Side wall 289 Transistor 290 Peripheral Circuits 291 Photodiode 292 Transistor 293 Transistor 294 Low concentration n-type impurity region 295 n-type semiconductor layer 301 period 302 period 303 period 311 period 312 period 313 period 382 Ec 386 Ec 390 Trap Levels 410 Transistor 411 Transistor 420 Transistor 421 Transistor 430 Transistor 431 Transistor 440 Transistor 441 Transistor 450 Transistors 451 Transistor 600 Lens 602 Filter 604 Wiring layer 660 light 800 Solid-state imaging device 810 Solid-state imaging device 820 Solid-state imaging device 821 Transistor 825 pixels 829 Transistor 830 Solid-state imaging device 835 DSP Blocks 880 Optical Flow System 901 Case 902 Case 903 Display section 904 Display section 905 Mike 906 Speaker 907 Operation Key 908 Stylus 909 Camera 911 Case 912 Display section 919 Camera 921 Case 922 Shutter button 923 Mike 925 Lens 927 Light emitting part 931 Case 932 Display section 933 Wristband 939 Camera 941 Case 942 Case 943 Display section 944 Operation Key 945 Lens 946 Connection 951 Case 952 Display section 954 Speaker 955 Button 956 Input / output terminal 957 Mike 959 Camera 1100 Imaging device 1112 subpixels 1800 Shift register circuit 1810 Shift register circuit 1900 Buffer circuit 1910 Buffer circuit 2100 Analog Switch Circuit 2110 Vertical output line 2200 output line 112B subpixel 112G subpixel 112R subpixel 242a Semiconductor layer 242b Semiconductor layer 242c Semiconductor layer 243a electrode 243b Electrode 383a Ec 383b Ec 383c Ec 602B Filter 602G Filter 602R Filter

Claims

[Claim 1] a first transistor to a sixth transistor, a first photoelectric conversion element, and a second photoelectric conversion element; the first photoelectric conversion element is electrically connected to one of a source and a drain of the first transistor; the other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor; the other of the source and the drain of the second transistor is electrically connected to the gate of the third transistor; the second photoelectric conversion element is electrically connected to one of a source and a drain of the fourth transistor; the other of the source and the drain of the fourth transistor is electrically connected to the gate of the fifth transistor; one of a source and a drain of the sixth transistor is electrically connected to one of a source and a drain of the second transistor; the other of the source and the drain of the sixth transistor is electrically connected to one of the source and the drain of the fourth transistor; in a first step, the first transistor and the fourth transistor are in an off state, the second transistor and the sixth transistor are in an on state, and a first potential corresponding to an amount of light received by the second photoelectric conversion element is written to a gate of the third transistor; In a second step, information corresponding to the first potential is read out via the third transistor; in a third step, the first transistor and the second transistor are in an off state, the fourth transistor and the sixth transistor are in an on state, and a second potential corresponding to an amount of light received by the second photoelectric conversion element is written to a gate of the fifth transistor; In a fourth step, information corresponding to the second potential is read out via the fifth transistor. Semiconductor device.

Images