Semiconductor Device

Abstract

To provide a semiconductor device that has a structure in which a Ni plating layer is formed on an electrode exposing from an opening in an organic insulation layer, and improves reliability of the Ni plating layer.SOLUTION: A semiconductor device includes a chip, an electrode formed on the chip, an inorganic insulation layer covering the electrode, an organic insulation layer covering the inorganic insulation layer, the organic insulation layer having a second opening formed therein, exposing an inner peripheral edge of the inorganic insulation layer between the first opening and the second opening, and a Ni plating layer covering the electrode in the first opening and covering the inner peripheral edge of the inorganic insulation layer in the second opening. The organic insulation layer has a second outer wall located inside a first outer wall of the inorganic insulation layer.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 (FIG. 4) discloses a semiconductor device including a semiconductor substrate, an aluminum film (electrode), a polyimide film (organic insulating layer), and a Ni plating film (Ni plating layer). The aluminum film is formed on the semiconductor substrate. The polyimide film is formed on the aluminum film and has an opening that exposes the aluminum film. The Ni plating film is formed on the aluminum film exposed from the opening in the polyimide film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2018 / 167925A1 Summary of the Invention [Problem to be solved by the invention]

[0004] The organic insulating layer has a property of having low adhesion to Ni. Therefore, when a Ni plating layer is formed on an electrode exposed through an opening in the organic insulating layer, the Ni plating layer forms a gap extending toward the electrode between the organic insulating layer and the Ni plating layer. As a result, the connection of the Ni plating layer to the electrode becomes insufficient, and the reliability of the Ni plating layer decreases.

[0005] One embodiment of the present invention provides a semiconductor device capable of improving the reliability of a Ni plating layer in a structure in which the Ni plating layer is formed on an electrode exposed from an opening in an organic insulating layer. [Means for solving the problem]

[0006] One embodiment of the present invention includes a chip, an electrode formed on the chip, and a coating for the electrode, From the first openingThe electrode is exposed. No a first insulating layer that covers the inorganic insulating layer and that has a first opening; Open end of At intervals from having an open end formed The present invention provides a semiconductor device including: an organic insulating layer having a second opening and exposing an inner periphery of the inorganic insulating layer in a region between the first opening and the second opening; and a Ni plating layer covering the electrode in the first opening and covering the inner periphery of the inorganic insulating layer in the second opening.

[0007] In this semiconductor device, the Ni plating layer covers the inner periphery of the inorganic insulating layer, which has higher adhesion to Ni than the organic insulating layer. This makes it possible to distance the gap formation area from the electrode and simultaneously suppress the formation of gaps extending toward the electrode. Compared to a structure in which the inner periphery of the inorganic insulating layer is not exposed, the area in which the gap is formed between the inorganic insulating layer and the organic insulating layer can be reduced. This improves the reliability of the Ni plating layer.

[0008] The above and other objects, features and advantages of the present invention will become apparent from the following detailed description of the embodiments with reference to the accompanying drawings. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention. [Diagram 2] FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1 together with the outer surface plating layer according to the first embodiment. [Diagram 3] FIG. 3 is an enlarged view of region III shown in FIG. [Figure 4A] FIG. 4A is a corresponding view to FIG. 3 and is an enlarged view showing an outer surface plating layer according to the second embodiment. [Figure 4B] FIG. 4B is a corresponding view to FIG. 3 and is an enlarged view showing the outer surface plating layer according to the third embodiment. [Figure 4C] FIG. 4C is a corresponding view to FIG. 3 and is an enlarged view showing the outer surface plating layer according to the fourth embodiment. [Figure 4D]FIG. 4D is a corresponding view to FIG. 3 and is an enlarged view showing the outer surface plating layer according to the fifth embodiment. [Figure 5A] FIG. 5A is a cross-sectional view for explaining an example of a method for manufacturing the semiconductor device shown in FIG. [Figure 5B] FIG. 5B is a cross-sectional view showing a step subsequent to FIG. 5A. [Figure 5C] FIG. 5C is a cross-sectional view showing a step subsequent to FIG. 5B. [Figure 5D] FIG. 5D is a cross-sectional view showing a step subsequent to FIG. 5C. [Figure 5E] FIG. 5E is a cross-sectional view showing a step subsequent to FIG. 5D. [Figure 5F] FIG. 5F is a cross-sectional view showing a step subsequent to FIG. 5E. [Figure 5G] FIG. 5G is a cross-sectional view showing a step subsequent to FIG. 5F. [Figure 5H] FIG. 5H is a cross-sectional view showing a step subsequent to FIG. 5G. [Figure 5I] FIG. 5I is a cross-sectional view showing a step subsequent to FIG. 5H. [Figure 5J] FIG. 5J is a cross-sectional view showing a step subsequent to FIG. 5I. [Figure 5K] FIG. 5K is a cross-sectional view showing a step subsequent to FIG. 5J. [Figure 5L] FIG. 5L is a cross-sectional view showing a step subsequent to FIG. 5K. [Figure 5M] FIG. 5M is a cross-sectional view showing a step subsequent to FIG. 5L. [Figure 5N] FIG. 5N is a cross-sectional view showing a step subsequent to FIG. 5M. [Figure 5O] FIG. 5O is a cross-sectional view showing a step subsequent to FIG. 5N. [Figure 6] FIG. 6 is a diagram corresponding to FIG. 2 and is a cross-sectional view showing a semiconductor device according to a second embodiment of the present invention together with an outer surface plating layer according to the first embodiment. [Figure 7] FIG. 7 is an enlarged view of region VII shown in FIG. [Figure 8A] FIG. 8A is a view corresponding to FIG. 7 and is an enlarged view showing the outer surface plating layer according to the second embodiment. [Figure 8B] FIG. 8B is a view corresponding to FIG. 7 and is an enlarged view showing the outer surface plating layer according to the third embodiment. [Figure 8C] FIG. 8C is a corresponding view to FIG. 7 and is an enlarged view showing the outer surface plating layer according to the fourth embodiment. [Figure 8D] FIG. 8D is a corresponding view to FIG. 7 and is an enlarged view showing the outer surface plating layer according to the fifth embodiment. [Figure 9] FIG. 9 is a plan view showing a semiconductor device according to a third embodiment of the present invention. [Figure 10] FIG. 10 is an enlarged view of a region X shown in FIG. [Figure 11] FIG. 11 is a cross-sectional view taken along line XI-XI shown in FIG. [Figure 12] FIG. 12 is a cross-sectional view taken along line XII-XII shown in FIG. [Figure 13] FIG. 13 is an enlarged view of region XIII shown in FIG. [Figure 14] FIG. 14 is an enlarged view of region XIV shown in FIG. [Figure 15] FIG. 15 is a cross-sectional view corresponding to FIG. 12, showing a semiconductor device according to a fourth embodiment of the present invention. [Figure 16] FIG. 16 is an enlarged view of region XVI shown in FIG. [Figure 17] FIG. 17 is an enlarged view of region XVII shown in FIG. [Figure 18] FIG. 18 is a plan view seen from one side of a semiconductor package in which the semiconductor device according to the first to fourth embodiments is incorporated. [Figure 19] FIG. 19 is a plan view of the semiconductor package shown in FIG. 18 as viewed from the other side. [Figure 20] FIG. 20 is a perspective view of the semiconductor package shown in FIG. [Figure 21] FIG. 21 is an exploded perspective view of the semiconductor package shown in FIG. [Figure 22] FIG. 22 is a cross-sectional view taken along the line XXII-XXII shown in FIG. [Diagram 23]FIG. 23 is a circuit diagram of the semiconductor package shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Fig. 1 is a plan view showing a semiconductor device 1 according to a first embodiment of the present invention. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1 together with an outer surface plating layer 42 according to a first embodiment. Fig. 3 is an enlarged view of region III shown in Fig. 2.

[0011] 1 to 3, in this embodiment, the semiconductor device 1 is a SiC semiconductor device including a SiC chip 2 (chip). The SiC chip 2 includes a SiC single crystal made of a hexagonal crystal. The SiC single crystal made of a hexagonal crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, and the like. In this embodiment, the SiC chip 2 is made of a 4H-SiC single crystal, but does not exclude other polytypes.

[0012] The SiC chip 2 is formed in a rectangular parallelepiped shape. The SiC chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and side surfaces 5A, 5B, 5C, and 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape (square shape in this embodiment) in a plan view (hereinafter simply referred to as "plan view") seen from their normal direction Z.

[0013] The thickness of the SiC chip 2 may be 40 μm or more and 300 μm or less. The thickness of the SiC chip 2 may be 40 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or less, or 250 μm or more and 300 μm or less. The thickness of the SiC chip 2 is preferably 60 μm or more and 150 μm or less.

[0014] The first main surface 3 and the second main surface 4 face the c-plane of the SiC single crystal. The first main surface 3 faces the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 faces the carbon surface ((000-1) surface) of the SiC single crystal. The second main surface 4 may be a rough surface having either one or both of grinding marks and annealing marks. The annealing marks are marks caused by laser irradiation. The second main surface 4 may be an ohmic surface having annealing marks.

[0015] The first main surface 3 and the second main surface 4 may have an off angle inclined at a predetermined off angle in a predetermined off direction with respect to the c-plane of the SiC single crystal. The off direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off angle is preferably inclined at an angle of 0° or more and 10° or less in the off direction. The off angle may be 0° or more and 6° or less. The off angle may be 0° or more and 2° or less, 2° or more and 4° or less, or 4° or more and 6° or less.

[0016] The off angle is preferably more than 0° and not more than 4.5°. The off angle may be 3° or more and not more than 4.5°. In this case, the off angle is preferably 3° or more and not more than 3.5° or less, or 3.5° or more and not more than 4°. The off angle may be 1.5° or more and not more than 3°. In this case, the off angle is preferably 1.5° or more and not more than 2° or less, or 2° or more and not more than 2.5°.

[0017] The side surfaces 5A to 5D include a first side surface 5A, a second side surface 5B, a third side surface 5C, and a fourth side surface 5D. The first side surface 5A and the second side surface 5B extend along a first direction X and face a second direction Y intersecting the first direction X. The third side surface 5C and the fourth side surface 5D extend along the second direction Y and face the first direction X. The second direction Y is specifically perpendicular to the first direction X.

[0018] The first side surface 5A and the second side surface 5B are formed by the a-plane of the SiC single crystal. When the normal direction Z is taken as a reference, the first side surface 5A and the second side surface 5B may form an inclined surface inclined in the c-axis direction (

[0001] direction) of the SiC single crystal with respect to the normal direction Z. When the normal direction Z is set to 0°, the first side surface 5A and the second side surface 5B may be inclined at an angle corresponding to the off angle with respect to the normal direction Z. The angle corresponding to the off angle may be equal to the off angle, or may be an angle greater than 0° and less than the off angle.

[0019] The third side surface 5C and the fourth side surface 5D are formed by an m-plane of a SiC single crystal. The third side surface 5C and the fourth side surface 5D extend planarly along the normal direction Z. Specifically, the third side surface 5C and the fourth side surface 5D are formed substantially perpendicular to the first main surface 3 and the second main surface 4.

[0020] The side surfaces 5A to 5D may be cleaved or ground surfaces. The length of the side surfaces 5A to 5D may be 0.1 mm or more and 10 mm or less. The length of the side surfaces 5A to 5D is preferably 0.5 mm or more and 2.5 mm or less.

[0021] In this embodiment, the SiC chip 2 has a layered structure including an n+ type SiC substrate 6 and an n type SiC epitaxial layer 7. The second main surface 4 and parts of the side surfaces 5A-5D of the SiC chip 2 are formed by the SiC substrate 6. The first main surface 3 and parts of the side surfaces 5A-5D of the SiC chip 2 are formed by the SiC epitaxial layer 7.

[0022] The n-type impurity concentration of SiC epitaxial layer 7 is lower than the n-type impurity concentration of SiC substrate 6. The n-type impurity concentration of SiC substrate 6 may be not less than 1.0×10 18 cm -3 and not more than 1.0×10 21 cm -3. The n-type impurity concentration of SiC epitaxial layer 7 may be not less than 1.0×10 15 cm -3 and not more than 1.0×10 18 cm -3.

[0023] The thickness of the SiC substrate 6 may be 40 μm or more and 250 μm or less. The thickness of the SiC substrate 6 may be 40 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, or 200 μm or more and 250 μm or less. The thickness of the SiC substrate 6 is preferably 40 μm or more and 150 μm or less. By thinning the SiC substrate 6, the resistance value of the SiC substrate 6 can be reduced.

[0024] The thickness of the SiC epitaxial layer 7 may be 1 μm or more and 50 μm or less. The thickness of the SiC epitaxial layer 7 may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less. The thickness of the SiC epitaxial layer 7 is preferably 5 μm or more and 15 μm or less.

[0025] The SiC chip 2 includes an active region 8 and an outer region 9. The active region 8 is a region including an SBD (Schottky Barrier Diode) as an example of a functional device (diode). The active region 8 is formed in the center of the SiC chip 2 and spaced inward from the side surfaces 5A to 5D in a plan view. The active region 8 is formed in a quadrangle shape having four sides parallel to the side surfaces 5A to 5D in a plan view.

[0026] The outer region 9 is a region outside the active region 8. The outer region 9 is formed in a region between the side surfaces 5A to 5D and the active region 8. The outer region 9 is formed in a ring shape (specifically, endless shape) surrounding the active region 8 in a plan view.

[0027] The semiconductor device 1 includes an n-type diode region 10 formed in a surface layer portion of the first main surface 3 in the active region 8. The diode region 10 is formed in the center of the first main surface 3. The diode region 10 may have any planar shape. The diode region 10 may be formed in a quadrangle shape having four sides parallel to the side surfaces 5A to 5D in a plan view.

[0028] In this embodiment, the diode region 10 is formed by utilizing a part of the SiC epitaxial layer 7. The n-type impurity concentration of the diode region 10 is equal to the n-type impurity concentration of the SiC epitaxial layer 7. The n-type impurity concentration of the diode region 10 may exceed the n-type impurity concentration of the SiC epitaxial layer 7. In this case, the diode region 10 is formed by introducing an n-type impurity into a surface portion of the SiC epitaxial layer 7.

[0029] In the outer region 9, a guard region 11 containing p-type impurities is formed in a surface layer portion of the first main surface 3. The p-type impurities in the guard region 11 may be activated or not activated. The guard region 11 is formed in a band shape extending along the diode region 10 in a plan view. Specifically, the guard region 11 is formed in a ring shape (specifically, endless shape) surrounding the diode region 10 in a plan view.

[0030] As a result, the guard region 11 is formed as a guard ring region. The guard region 11 defines the active region 8 (diode region 10). The planar shape of the active region 8 (diode region 10) is adjusted by the planar shape of the guard region 11. The guard region 11 may be formed in a polygonal ring shape or a circular ring shape in a plan view.

[0031] The semiconductor device 1 includes a main surface insulating layer 12 formed on the first main surface 3. The main surface insulating layer 12 may have a laminated structure including a silicon oxide layer and a silicon nitride layer. The main surface insulating layer 12 may have a single layer structure made of a silicon oxide layer or a silicon nitride layer. In this embodiment, the main surface insulating layer 12 has a single layer structure made of a silicon oxide layer.

[0032] The main surface insulating layer 12 has a contact opening 13 that exposes the diode region 10. The contact opening 13 also exposes the inner peripheral edge of the guard region 11. The planar shape of the contact opening 13 is arbitrary. The contact opening 13 may be defined in a quadrangle shape having four sides parallel to the side surfaces 5A to 5D in a plan view.

[0033] The periphery of the main surface insulating layer 12 is exposed from the side surfaces 5A to 5D. In this embodiment, the periphery of the main surface insulating layer 12 is continuous with the side surfaces 5A to 5D. The periphery of the main surface insulating layer 12 may be formed at a distance inward from the side surfaces 5A to 5D. In this case, the main surface insulating layer 12 exposes a portion of the first main surface 3 located in the outer region 9.

[0034] The thickness of the main surface insulating layer 12 may be 0.1 μm or more and 10 μm or less. The thickness of the main surface insulating layer 12 may be 0.1 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. The thickness of the main surface insulating layer 12 is preferably 0.5 μm or more and 5 μm or less.

[0035] The semiconductor device 1 includes a first principal surface electrode 21 (electrode) formed on the first principal surface 3. The first principal surface electrode 21 is connected to the diode region 10 and the guard region 11 in the contact opening 13. The first principal surface electrode 21 is drawn out from the contact opening 13 onto the principal surface insulating layer 12. The periphery of the first principal surface electrode 21 is formed on the principal surface insulating layer 12 with a space inward from the side surfaces 5A to 5D. As a result, the first principal surface electrode 21 exposes the periphery of the principal surface insulating layer 12.

[0036] The thickness T1 of the first principal surface electrode 21 may be 10 μm or more and 100 μm or less. The thickness T1 may be 10 μm or more and 20 μm or less, 20 μm or more and 40 μm or less, 40 μm or more and 60 μm or less, 60 μm or more and 80 μm or less, or 80 μm or more and 100 μm or less. The thickness T1 is preferably 20 μm or more and 60 μm or less.

[0037] Specifically, the first principal surface electrode 21 has a laminated structure including a barrier electrode 22 and a main electrode 23 laminated in this order from the first principal surface 3 side. The barrier electrode 22 is formed in a film shape along the first principal surface 3 and the main surface insulating layer 12. The barrier electrode 22 forms a Schottky junction with the diode region 10. This forms an SBD having the first principal surface electrode 21 as an anode and the diode region 10 as a cathode. In other words, the first principal surface electrode 21 is the anode electrode of the SBD.

[0038] The barrier electrode 22 may include at least one of a Ti layer, a Pd layer, a Cr layer, a V layer, a Mo layer, a W layer, a Pt layer, and a Ni layer. The thickness of the barrier electrode 22 may be 0.01 μm or more and 1 μm or less. The thickness of the barrier electrode 22 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0039] The main electrode 23 is formed in the form of a film on the barrier electrode 22. The main electrode 23 covers the entire main surface of the barrier electrode 22. The main electrode 23 is made of an Al-based metal layer. Specifically, the main electrode 23 includes at least one of a pure Al layer (an Al layer made of Al with a purity of 99% or more), an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer.

[0040] The main electrode 23 may have a laminated structure in which two or more of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer are laminated in any order. The main electrode 23 may have a single-layer structure made of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, or an AlSiCu alloy layer. The main electrode 23 preferably has a single-layer structure made of an AlSi alloy layer, an AlCu alloy layer, or an AlSiCu alloy layer.

[0041] The thickness of the main electrode 23 exceeds the thickness of the barrier electrode 22. The thickness of the main electrode 23 may be 10 μm or more and 100 μm or less. The thickness of the main electrode 23 may be 10 μm or more and 20 μm or less, 20 μm or more and 40 μm or less, 40 μm or more and 60 μm or less, 60 μm or more and 80 μm or less, or 80 μm or more and 100 μm or less. The thickness of the main electrode 23 is preferably 20 μm or more and 60 μm or less. Since the thickness of the barrier electrode 22 is extremely small compared to the thickness of the main electrode 23, the thickness T1 of the first principal surface electrode 21 is approximated to the thickness of the main electrode 23.

[0042] The semiconductor device 1 includes an insulating layer 24 covering the first principal surface electrodes 21 on the first principal surface 3. In FIG. 1, the insulating layer 24 is shown by hatching. Specifically, the insulating layer 24 is formed on the principal surface insulating layer 12. The periphery of the insulating layer 24 is formed with a space inward from the side surfaces 5A to 5D. As a result, the insulating layer 24 exposes the periphery of the principal surface insulating layer 12.

[0043] The periphery of the insulating layer 24 defines dicing streets 25 between the side surfaces 5A to 5D. The dicing streets 25 eliminate the need to physically cut the insulating layer 24 when cutting the semiconductor device 1 from the wafer. This allows the semiconductor device 1 to be smoothly cut from the wafer, and simultaneously prevents peeling and deterioration of the insulating layer 24. As a result, the insulating layer 24 can adequately protect objects to be protected, such as the SiC chip 2 and the first principal surface electrode 21.

[0044] The width of the dicing street 25 may be 1 μm or more and 25 μm or less. The width of the dicing street 25 is the width in a direction perpendicular to the direction in which the dicing street 25 extends. The width of the dicing street 25 may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, or 20 μm or more and 25 μm or less.

[0045] The insulating layer 24 has a pad opening 26 that exposes the first principal surface electrode 21. The pad opening 26 exposes the first principal surface electrode 21 in a region surrounded by the contact opening 13 in a plan view. The pad opening 26 may surround the contact opening 13 in a region outside the contact opening 13 in a plan view. The pad opening 26 may have any planar shape. The pad opening 26 may be formed in a quadrangle shape having four sides parallel to the side surfaces 5A to 5D in a plan view.

[0046] Specifically, the insulating layer 24 has a laminated structure including an inorganic insulating layer 30 and an organic insulating layer 31 laminated in this order from the SiC chip 2 side. The inorganic insulating layer 30 is formed in a film shape along the principal surface insulating layer 12 and the first principal surface electrode 21. The inorganic insulating layer 30 includes a first inner wall 32 and a first outer wall 33. The first inner wall 32 of the inorganic insulating layer 30 defines a first opening 34 that exposes a part of the first principal surface electrode 21. The first opening 34 forms a part of the pad opening 26.

[0047] The first opening 34 is defined within a region surrounded by the contact opening 13 in a plan view. The first opening 34 may surround the contact opening 13 from outside the contact opening 13 in a plan view. The first opening 34 may have any planar shape. The first opening 34 may be defined in a quadrangle shape having four sides parallel to the side surfaces 5A to 5D in a plan view.

[0048] The first outer wall 33 of the inorganic insulating layer 30 is formed at a distance inward from the side surfaces 5A to 5D and exposes the peripheral edge portion of the main surface insulating layer 12. The inorganic insulating layer 30 defines a part of the dicing street 25 between itself and the side surfaces 5A to 5D. The first outer wall 33 may be formed in a quadrangle shape having four sides parallel to the side surfaces 5A to 5D in a plan view.

[0049] The angle formed between the first inner wall 32 (the first outer wall 33) and the main surface of the first main surface electrode 21 within the inorganic insulating layer 30 may be 30° or more and 90° or less. It is preferable that the angle formed between the first inner wall 32 (the first outer wall 33) and the main surface of the first main surface electrode 21 within the inorganic insulating layer 30 is 45° or more and less than 90°. The angle of the first inner wall 32 (the first outer wall 33) is defined by the angle formed between the straight line connecting the lower end portion and the upper end portion of the first inner wall 32 (the first outer wall 33) and the main surface of the first main surface electrode 21.

[0050] The inorganic insulating layer 30 has a property of high adhesion to Ni. The inorganic insulating layer 30 includes at least one of a silicon oxide layer and a silicon nitride layer. The inorganic insulating layer 30 may have a laminated structure including a silicon oxide layer and a silicon nitride layer laminated in this order from the SiC chip 2 side. The inorganic insulating layer 30 may have a single-layer structure composed of a silicon oxide layer or a silicon nitride layer. It is preferable that the inorganic insulating layer 30 contains an insulating material different from the main surface insulating layer 12. In this form, the inorganic insulating layer 30 has a single-layer structure composed of a silicon nitride layer.

[0051] It is preferable that the thickness T2 of the inorganic insulating layer 30 is less than the thickness T1 of the first main surface electrode 21 (T2 < T1). The thickness T2 may be 0.1 μm or more and 10 μm or less. The thickness T2 may be 0.1 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. It is preferable that the thickness T2 is 1 μm or more and 5 μm or less. It is particularly preferable that the thickness T2 is 1 μm or more and 2 μm or less.

[0052] The organic insulating layer 31 is formed in a film shape on the inorganic insulating layer 30. The organic insulating layer 31 includes a second inner wall 35 and a second outer wall 36. The second inner wall 35 of the organic insulating layer 31 defines a second opening 37 that exposes a part of the first main surface electrode 21. In this form, the second inner wall 35 is formed in a curved shape that is recessed toward the inorganic insulating layer 30 side.

[0053] 3, the second opening 37 communicates with the first opening 34 of the inorganic insulating layer 30, and forms a pad opening 26 between the second opening 37 and the first opening 34. The second opening 37 is defined within a region surrounded by the contact opening 13 in a plan view. The second opening 37 may surround the contact opening 13 from outside the contact opening 13 in a plan view. The second opening 37 may have any planar shape. The second opening 37 may be defined in a quadrangle shape having four sides parallel to the side surfaces 5A to 5D in a plan view.

[0054] The second opening 37 is spaced apart from the first opening 34 and surrounds the first opening 34, exposing a portion of the inorganic insulating layer 30. Specifically, the organic insulating layer 31 exposes a portion of the main surface of the inorganic insulating layer 30 as an inner peripheral edge 38 in the region between the first opening 34 and the second opening 37.

[0055] The width W of the inner peripheral edge 38 of the inorganic insulating layer 30 may be more than 0 μm and not more than 10 μm. The width W may be more than 0 μm and not more than 1 μm, 1 μm or more and not more than 2 μm, 2 μm or more and not more than 4 μm, 4 μm or more and not more than 6 μm, 6 μm or more and not more than 8 μm, or 8 μm or more and not more than 10 μm. The width W is preferably 1 μm or more and not more than 5 μm. The width W is arbitrary, but is preferably not more than the thickness T2 of the inorganic insulating layer 30 (W≦T2). The width W is particularly preferably 1 μm or more and not more than 2 μm.

[0056] In this embodiment, the second outer wall 36 of the organic insulating layer 31 is formed in a curved shape recessed toward the inorganic insulating layer 30. The second outer wall 36 is formed on the inorganic insulating layer 30 with a space inward from the side surfaces 5A to 5D, and defines a part of the dicing street 25 between the organic insulating layer 31 and the side surfaces 5A to 5D. This causes the organic insulating layer 31 to expose the peripheral portion of the main surface insulating layer 12. The second outer wall 36 may be formed in a quadrangle shape having four sides parallel to the side surfaces 5A to 5D in a plan view.

[0057] The second outer wall 36 of the organic insulating layer 31 may be formed on the main surface insulating layer 12 across the first outer wall 33 of the inorganic insulating layer 30. In this case, the dicing street 25 is partitioned by the second outer wall 36 of the organic insulating layer 31.

[0058] The angle formed between the second inner wall 35 (second outer wall 36) of the organic insulating layer 31 and the main surface of the inorganic insulating layer 30 within the organic insulating layer 31 may be 30° or more and 90° or less. It is preferable that the angle formed between the second inner wall 35 (second outer wall 36) and the main surface of the inorganic insulating layer 30 within the organic insulating layer 31 is 45° or more and less than 90°. The angle of the second inner wall 35 (second outer wall 36) is defined by the angle formed between the straight line connecting the lower end portion and the upper end portion of the second inner wall 35 (second outer wall 36) and the main surface of the inorganic insulating layer 30.

[0059] The organic insulating layer 31 has a property of having lower adhesion to Ni compared to the inorganic insulating layer 30. The organic insulating layer 31 contains a negative-type or positive-type photosensitive resin. The organic insulating layer 31 may contain at least one of polyimide, polyamide, and polybenzoxazole. In this form, the organic insulating layer 31 contains polyimide.

[0060] It is preferable that the organic insulating layer 31 has a thickness T3 (T2 < T3) exceeding the thickness T2 of the inorganic insulating layer 30. The ratio T3 / T2 of the thickness T3 of the organic insulating layer 31 to the thickness T2 of the inorganic insulating layer 30 may be more than 1 and 10 or less. The ratio T3 / T2 may be more than 1 and 2 or less, 2 or more and 4 or less, 4 or more and 6 or less, 6 or more and 8 or less, or 8 or more and 10 or less. It is preferable that the ratio T3 / T2 is 2 or more and 6 or less.

[0061] The thickness T3 may be 1 μm or more and 50 μm or less. The thickness T3 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less. It is preferable that the thickness T3 is 5 μm or more and 30 μm or less.

[0062] The semiconductor device 1 includes a rough surface region 39 formed on an exposed surface of the first principal surface electrode 21 exposed from the pad opening 26 (first opening 34 of the inorganic insulating layer 30). The rough surface region 39 includes a recess formed in a region directly below the first inner wall 32 of the inorganic insulating layer 30. As a result, the first inner wall 32 of the inorganic insulating layer 30 includes a portion overhanging the rough surface region 39.

[0063] The semiconductor device 1 includes a pad electrode 40 formed in the pad opening 26. The pad electrode 40 includes a Ni plating layer 41 formed on the first principal surface electrode 21 in the pad opening 26. The Ni plating layer 41 covers the first principal surface electrode 21 in the first opening 34, and covers the inner periphery 38 of the inorganic insulating layer 30 in the second opening 37. The Ni plating layer 41 has an outer surface formed at a distance from the principal surface of the organic insulating layer 31 (insulating layer 24) toward the first principal surface electrode 21. In this embodiment, the Ni plating layer 41 covers the organic insulating layer 31 in the second opening 37.

[0064] 3, the Ni plating layer 41 has a first portion 41A covering the first principal surface electrode 21 and a second portion 41B covering the inner peripheral edge 38 of the inorganic insulating layer 30. The first portion 41A of the Ni plating layer 41 fills the rough surface region 39 in the first opening 34 to cover the first principal surface electrode 21. The first portion 41A covers the entire first inner wall 32 of the inorganic insulating layer 30 and protrudes from the opening end of the first opening 34 toward the opening end of the second opening 37. The first portion 41A is connected to the first inner wall 32 of the inorganic insulating layer 30 and has a first connection portion extending in the thickness direction of the inorganic insulating layer 30.

[0065] The second portion 41B of the Ni plating layer 41 is drawn out from the first portion 41A towards the organic insulating layer 31 within the second opening 37. The second portion 41B is formed in an arc shape that starts from the opening end of the first opening 34 and faces the organic insulating layer 31.

[0066] The second part 41B covers the inner peripheral edge 38 of the inorganic insulating layer 30 within the second opening 37. As a result, the second part 41B faces the first main surface electrode 21 with the inner peripheral edge 38 of the inorganic insulating layer 30 interposed therebetween. The second part 41B is connected to the main surface of the inorganic insulating layer 30 and has a second connection portion extending in the width direction of the inorganic insulating layer 30.

[0067] In this form, the second part 41B further covers the second inner wall 35 of the organic insulating layer 31 within the second opening 37. The second part 41B covers the region on the inorganic insulating layer 30 side with respect to the middle portion of the second inner wall 35 of the organic insulating layer 31. In other words, the second part 41B covers the organic insulating layer 31 such that the exposed area of the second inner wall 35 (organic insulating layer 31) exceeds the hidden area of the second inner wall 35 (organic insulating layer 31). Thus, the Ni plating layer 41 is formed such that the first part 41A and the second part 41B engage from different two directions with the opening end of the first opening 34.

[0068] The Ni plating layer 41 has a thickness T4 (T2 < T4) that exceeds the thickness T2 of the inorganic insulating layer 30. The thickness T4 is less than the thickness T3 of the organic insulating layer 31 (T4 < T3). The thickness T4 exceeds the value obtained by adding the width W of the inner peripheral edge 38 to the thickness T2 of the inorganic insulating layer 30 (T2 + W < T4). This is the condition for the Ni plating layer 41 to contact the second inner wall 35 of the organic insulating layer 31. The thickness T4 is defined by the thickness of the Ni plating layer 41 with reference to the main surface of the first main surface electrode 21.

[0069] The ratio T4 / T2 of the thickness T4 of the Ni plating layer 41 to the thickness T2 of the inorganic insulating layer 30 may be greater than 1 and less than or equal to 5. The ratio T4 / T2 may be greater than 1 and less than or equal to 2, greater than or equal to 2 and less than or equal to 3, greater than or equal to 3 and less than or equal to 4, or greater than or equal to 4 and less than or equal to 5.

[0070] The thickness T4 may be 0.1 μm or more and 15 μm or less. The thickness T4 may be 0.1 μm or more and 1 μm or less, 1 μm or more and 3 μm or less, 3 μm or more and 6 μm or less, 6 μm or more and 9 μm or less, 9 μm or more and 12 μm or less, or 12 μm or more and 15 μm or less. The thickness T4 is preferably 2 μm or more and 8 μm or less.

[0071] The pad electrode 40 is made of a metal material different from the Ni plating layer 41, and includes an outer plating layer 42 that covers the outer surface of the Ni plating layer 41 in the second opening 37. The outer plating layer 42 has a thickness T5 (T5 < T4) that is less than the thickness T4 of the Ni plating layer 41. The outer plating layer 42 covers the second inner wall 35 of the organic insulating layer 31 in the second opening 37.

[0072] The outer plating layer 42 has a terminal surface 42A that is externally connected via a conductive bonding material (e.g., solder). The terminal surface 42A is located on the Ni plating layer 41 side with respect to the main surface of the organic insulating layer 31 (the opening end of the second opening 37). Thereby, the outer plating layer 42 exposes a part of the second inner wall 35 of the organic insulating layer 31.

[0073] In this form, the outer plating layer 42 has a laminated structure including a Pd plating layer 43 and an Au plating layer 44 laminated in this order from the Ni plating layer 41 side. The Pd plating layer 43 is formed in a film shape along the outer surface of the Ni plating layer 41. The Pd plating layer 43 covers the Ni plating layer 41 at a distance from the opening end of the second opening 37 toward the inorganic insulating layer 30 side. The Pd plating layer 43 covers the second inner wall 35 of the organic insulating layer 31 in the second opening 37.

[0074] The Pd plating layer 43 has a thickness that is less than the thickness T4 of the Ni plating layer 41. The thickness of the Pd plating layer 43 may be 0.01 μm or more and 1 μm or less. The thickness of the Pd plating layer 43 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0075] The Au plating layer 44 is formed in the form of a film along the outer surface of the Pd plating layer 43. The Au plating layer 44 covers the Pd plating layer 43 at a distance from the opening end of the second opening 37 toward the inorganic insulating layer 30. The Au plating layer 44 covers the second inner wall 35 of the organic insulating layer 31 within the second opening 37.

[0076] The Au plating layer 44 has a thickness less than the thickness T4 of the Ni plating layer 41. The Au plating layer 44 may have a thickness of 0.01 μm or more and 1 μm or less. The Au plating layer 44 may have a thickness of 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0077] The outer surface plating layer 42 can take various forms as shown in FIGS. 4A to 4D.

[0078] Fig. 4A is a corresponding view to Fig. 3 and is an enlarged view showing the outer surface plating layer 42 according to the second embodiment. Below, differences from the outer surface plating layer 42 according to the first embodiment will be described.

[0079] 4A, in this embodiment, the outer surface plating layer 42 has a single layer structure made of an Au plating layer 44. The Au plating layer 44 is formed in a film shape along the outer surface of the Ni plating layer 41. The Au plating layer 44 covers the Ni plating layer 41 with a gap from the opening end of the second opening 37 toward the inorganic insulating layer 30. The Au plating layer 44 covers the second inner wall 35 of the organic insulating layer 31 within the second opening 37.

[0080] Fig. 4B is a corresponding view to Fig. 3 and is an enlarged view showing the outer surface plating layer 42 according to the third embodiment. Below, differences from the outer surface plating layer 42 according to the first embodiment will be described.

[0081] 4B, in this embodiment, the outer surface plating layer 42 has a single-layer structure made of a Pd plating layer 43. The Pd plating layer 43 is formed in a film shape along the outer surface of the Ni plating layer 41. The Pd plating layer 43 covers the Ni plating layer 41 with a gap from the opening end of the second opening 37 toward the inorganic insulating layer 30. The Pd plating layer 43 covers the second inner wall 35 of the organic insulating layer 31 within the second opening 37.

[0082] Fig. 4C is a corresponding view to Fig. 3 and is an enlarged view showing the outer surface plating layer 42 according to the fourth embodiment. Below, differences from the outer surface plating layer 42 according to the first embodiment will be described.

[0083] 4C, in this embodiment, the outer surface plating layer 42 has a single-layer structure made of an Ag plating layer 45. The Ag plating layer 45 is formed in a film shape along the outer surface of the Ni plating layer 41. The Ag plating layer 45 covers the Ni plating layer 41 with a gap from the opening end of the second opening 37 toward the inorganic insulating layer 30. The Ag plating layer 45 covers the second inner wall 35 of the organic insulating layer 31 within the second opening 37.

[0084] The Ag plating layer 45 has a thickness less than the thickness T4 of the Ni plating layer 41. The Ag plating layer 45 may have a thickness of 0.01 μm or more and 1 μm or less. The Ag plating layer 45 may have a thickness of 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0085] Fig. 4D is a corresponding view to Fig. 3 and is an enlarged view showing the outer surface plating layer 42 according to the fifth embodiment. Below, differences from the outer surface plating layer 42 according to the first embodiment will be described.

[0086] 4D, the outer surface plating layer 42 has a layered structure including a Pd plating layer 43, an Au plating layer 44 and an Ag plating layer 45, which are layered in this order from the Ni plating layer 41 side.

[0087] The Pd plating layer 43 is formed in the form of a film along the outer surface of the Ni plating layer 41. The Pd plating layer 43 covers the Ni plating layer 41 at a distance from the opening end of the second opening 37 toward the inorganic insulating layer 30. The Pd plating layer 43 covers the second inner wall 35 of the organic insulating layer 31 within the second opening 37.

[0088] The Au plating layer 44 is formed in the form of a film along the outer surface of the Pd plating layer 43. The Au plating layer 44 covers the Pd plating layer 43 at a distance from the opening end of the second opening 37 toward the inorganic insulating layer 30. The Au plating layer 44 covers the second inner wall 35 of the organic insulating layer 31 within the second opening 37.

[0089] The Ag plating layer 45 is formed in a film shape along the outer surface of the Au plating layer 44. The Ag plating layer 45 covers the Au plating layer 44 with a gap from the opening end of the second opening 37 toward the inorganic insulating layer 30. The Ag plating layer 45 covers the second inner wall 35 of the organic insulating layer 31 within the second opening 37.

[0090] 2 again, the semiconductor device 1 includes a second principal surface electrode (rear surface electrode) 46 formed on the second principal surface 4. The second principal surface electrode 46 covers the entire area of ​​the second principal surface 4. The second principal surface electrode 46 forms an ohmic contact with the second principal surface 4. The second principal surface electrode 46 is formed as a cathode electrode of the SBD.

[0091] The second principal surface electrode 46 includes at least one of a Ti layer, a Ni layer, a Pd layer, an Au layer, and an Ag layer. The second principal surface electrode 46 may have a laminated structure in which at least two of a Ti layer, a Ni layer, a Pd layer, an Au layer, and an Ag layer are laminated in any order. The second principal surface electrode 46 may have a single layer structure consisting of a Ti layer, a Ni layer, a Pd layer, an Au layer, and an Ag layer. The second principal surface electrode 46 preferably includes a Ti layer as an ohmic electrode. In this embodiment, the second principal surface electrode 46 has a laminated structure including a Ti layer, a Ni layer, a Pd layer, an Au layer, and an Ag layer laminated in this order from the second principal surface 4 side.

[0092] 5A to 5O are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device 1 shown in FIG.

[0093] 5A, first, a SiC epitaxial wafer 50 serving as a base of the SiC chip 2 is prepared. The SiC epitaxial wafer 50 has a laminated structure including a SiC wafer 51 and a SiC epitaxial layer 52. The SiC wafer 51 serves as a base of the SiC substrate 6. The SiC epitaxial layer 52 serves as a base of the SiC epitaxial layer 7. The SiC epitaxial layer 52 is formed by epitaxially growing SiC from the main surface of the SiC wafer 51.

[0094] The SiC epitaxial wafer 50 has a first wafer main surface 53 on one side and a second wafer main surface 54 on the other side. The first wafer main surface 53 and the second wafer main surface 54 correspond to the first main surface 3 and the second main surface 4 of the SiC chip 2, respectively.

[0095] A plurality of device regions 55 each corresponding to a semiconductor device 1 and cutting lines 56 dividing the device regions 55 are set on the SiC epitaxial wafer 50. In FIG. 5A, one device region 55 is shown, and the other regions are omitted (the same applies to FIGS. 5B to 5O below). The device regions 55 are set in a matrix shape along the first direction X and the second direction Y. The cutting lines 56 are set in a lattice shape extending along the first direction X and the second direction Y.

[0096] 5B, the main parts of the functional devices are formed in each device region 55. In this form, n-type impurities and / or p-type impurities are selectively introduced into the surface layer portion of the first wafer main surface 53 to form the n-type diode region 10 and the p-type guard region 11. The n-type impurities and / or p-type impurities are introduced into the surface layer portion of the first wafer main surface 53 by ion implantation via an ion implantation mask (not shown).

[0097] 5C, a main surface insulating layer 12 is formed on the first wafer main surface 53. The main surface insulating layer 12 may be formed by a CVD (Chemical Vapor Deposition) method and / or an oxidation treatment method (for example, a thermal oxidation treatment method).

[0098] 5D, a resist mask 57 having a predetermined pattern is formed on the main surface insulating layer 12. The resist mask 57 exposes a region in the main surface insulating layer 12 where the contact opening 13 is to be formed, and covers the other regions. Next, unnecessary portions of the main surface insulating layer 12 are removed by etching via the resist mask 57. The etching may be wet etching and / or dry etching. As a result, the contact opening 13 is formed in the main surface insulating layer 12.

[0099] 5E, a base electrode layer 58 that serves as a base for the first principal surface electrode 21 is formed on the principal surface insulating layer 12. The base electrode layer 58 has a laminated structure including a barrier electrode 22 and a main electrode 23 that are laminated in this order from the principal surface insulating layer 12 side. The barrier electrode 22 and the main electrode 23 may each be formed by a sputtering method and / or a vapor deposition method.

[0100] Next, referring to FIG. 5F, a resist mask 59 having a predetermined pattern is formed on the base electrode layer 58. The resist mask 59 exposes a region of the base electrode layer 58 where the first principal surface electrode 21 is to be formed, and covers the other regions. Next, unnecessary portions of the base electrode layer 58 are removed by etching via the resist mask 59. The etching method may be a wet etching method and / or a dry etching method. As a result, the first principal surface electrode 21 is formed on the principal surface insulating layer 12.

[0101] Next, referring to FIG. 5G, the inorganic insulating layer 30 is formed on the main surface insulating layer 12 so as to cover the first main surface electrode 21. In this embodiment, the inorganic insulating layer 30 has a single layer structure made of a silicon nitride layer. The inorganic insulating layer 30 may have a layered structure including a silicon oxide layer and a silicon nitride layer layered in this order from the SiC epitaxial wafer 50 side. The inorganic insulating layer 30 may be formed by a CVD method.

[0102] 5H, a resist mask 60 having a predetermined pattern is formed on the inorganic insulating layer 30. The resist mask 60 exposes regions of the inorganic insulating layer 30 where the first openings 34 and the dicing streets 25 are to be formed, and covers the other regions.

[0103] Next, unnecessary portions of the inorganic insulating layer 30 are removed by etching through the resist mask 60. The etching may be wet etching and / or dry etching. As a result, first openings 34 exposing the first principal surface electrodes 21 and dicing streets 25 extending in a grid pattern along the cutting lines 56 are formed in the inorganic insulating layer 30.

[0104] 5I, the organic insulating layer 31 is formed on the main surface insulating layer 12 so as to cover the first main surface electrode 21 and the inorganic insulating layer 30. The organic insulating layer 31 is formed by applying polyimide, as an example of a photosensitive resin, to the first wafer main surface 53 side.

[0105] 5J, the organic insulating layer 31 is exposed to light in a pattern corresponding to the second openings 37 and the dicing streets 25, and then developed. As a result, the second openings 37 that expose the first principal surface electrodes 21, and the dicing streets 25 that extend in a grid pattern along the lines to cut 56 are formed in the organic insulating layer 31.

[0106] The second opening 37 of the organic insulating layer 31 is formed to surround the first opening 34 of the inorganic insulating layer 30 with a space therebetween. This results in the formation of the organic insulating layer 31 that exposes the inner peripheral edge 38 of the inorganic insulating layer 30 in the region between the first opening 34 and the second opening 37.

[0107] 5K, a rough surface region 39 is formed on a portion of the first principal surface electrode 21 exposed from the first opening 34 and the second opening 37. The rough surface region 39 is formed by a zincate treatment method (zinc substitution treatment method) on the exposed portion of the first principal surface electrode 21.

[0108] 5L, a Ni plating layer 41 is formed on the portion of the first principal surface electrode 21 exposed from the first opening 34 and the second opening 37. The Ni plating layer 41 is formed by depositing Ni on the first principal surface electrode 21 by electrolytic plating or electroless plating (electroless plating in this embodiment). This forms the Ni plating layer 41 that covers the first principal surface electrode 21 in the first opening 34 and covers the inner periphery 38 of the inorganic insulating layer 30 in the second opening 37. The specific structure of the Ni plating layer 41 is as described above, and therefore will not be described.

[0109] 5M, an outer surface plating layer 42 is formed on the outer surface of the Ni plating layer 41 in the second opening 37. The outer surface plating layer 42 includes at least one of a Pd plating layer 43, an Au plating layer 44, and an Ag plating layer 45. The outer surface plating layer 42 is formed by depositing any material of Pd, Au, and Ag on the first principal surface electrode 21 by electrolytic plating or electroless plating (electroless plating in this embodiment).

[0110] 5N, the SiC epitaxial wafer 50 is thinned to a desired thickness by grinding the second wafer main surface 54. The second wafer main surface 54 may be ground by a chemical mechanical polishing (CMP) method. After the grinding step of the second wafer main surface 54, an annealing process may be performed on the second wafer main surface 54. The annealing process may be performed by a laser irradiation method. As a result, the second wafer main surface 54 (second main surface 4) becomes an ohmic surface.

[0111] Next, referring to FIG. 5O, a second principal surface electrode 46 is formed on the second wafer principal surface 54. The second principal surface electrode 46 may be formed by a sputtering method, a vapor deposition method, and / or a plating method. Thereafter, the SiC epitaxial wafer 50 is cut or cleaved along the dicing streets 25 to cut out a plurality of semiconductor devices 1. Through the steps including those described above, the semiconductor device 1 is manufactured.

[0112] As described above, the semiconductor device 1 includes the SiC chip 2, the first principal surface electrode 21, the inorganic insulating layer 30, the organic insulating layer 31, and the Ni plating layer 41. The first principal surface electrode 21 is formed on the SiC chip 2. The inorganic insulating layer 30 covers the first principal surface electrode 21 and has a first opening 34 that exposes the first principal surface electrode 21. The organic insulating layer 31 covers the inorganic insulating layer 30 and has a second opening 37 that is spaced apart from the first opening 34 and surrounds the first opening 34, exposing the inner periphery 38 of the inorganic insulating layer 30 in the region between the first opening 34 and the second opening 37. The Ni plating layer 41 is connected to the first principal surface electrode 21 in the first opening 34 and covers the inner periphery 38 of the inorganic insulating layer 30 in the second opening 37.

[0113] The inorganic insulating layer 30 has a property of high adhesion to Ni, while the organic insulating layer 31 has a property of low adhesion to Ni compared to the inorganic insulating layer 30. Therefore, for example, when the inorganic insulating layer 30 is not present or when the organic insulating layer 31 is formed flush with the inorganic insulating layer 30, the Ni plating layer 41 forms a gap extending toward the first principal surface electrode 21 between the organic insulating layer 31 and the Ni plating layer 41. As a result, the connection of the Ni plating layer 41 to the first principal surface electrode 21 becomes insufficient, and the reliability of the Ni plating layer 41 decreases.

[0114] Therefore, the semiconductor device 1 employs a structure in which an organic insulating layer 31 is formed to expose an inner peripheral edge 38 of an inorganic insulating layer 30 having high adhesion to Ni, and a Ni plating layer 41 covers the inner peripheral edge 38 of the inorganic insulating layer 30. In this case, the Ni plating layer 41 forms, between the inorganic insulating layer 30 and the organic insulating layer 31, a first connection portion extending in the thickness direction of the inorganic insulating layer 30 and a second connection portion extending in the width direction of the inorganic insulating layer 30.

[0115] This allows the gap formation region to be kept away from the first principal surface electrode 21, and at the same time, the formation of gaps extending toward the first principal surface electrode 21 can be appropriately suppressed. Also, compared to a case in which the inner peripheral edge 38 of the inorganic insulating layer 30 does not exist, the gap formation region between the inorganic insulating layer 30 and the organic insulating layer 31 can be reduced. Therefore, the reliability of the Ni plating layer 41 can be improved.

[0116] In the semiconductor device 1, the second portion 41B of the Ni plating layer 41 covers an area on the inorganic insulating layer 30 side relative to a middle portion of the second inner wall 35 of the organic insulating layer 31. In other words, the second portion 41B of the Ni plating layer 41 covers the organic insulating layer 31 such that the concealed area of ​​the second inner wall 35 (organic insulating layer 31) is less than the exposed area of ​​the second inner wall 35 (organic insulating layer 31). Such a Ni plating layer 41 can appropriately reduce the area in which gaps are formed.

[0117] The semiconductor device 1 further includes an outer plating layer 42 that covers the outer surface of the Ni plating layer 41. With this structure, the formation of a gap between the organic insulating layer 31 and the Ni plating layer 41 is suppressed, so that the intrusion of the plating solution into the gap can be suppressed. This makes it possible to suppress abnormal film formation of the outer plating layer 42 that originates from the gap. As a result, it is possible to suppress connection failure of the Ni plating layer 41 caused by abnormal film formation of the outer plating layer 42, and at the same time, it is possible to suppress peeling (connection failure) of the outer plating layer 42.

[0118] Specifically, the outer surface plating layer 42 can include at least one of a Pd plating layer 43, an Au plating layer 44, and an Ag plating layer 45. This can prevent connection failure of the Ni plating layer 41 caused by abnormal film formation of the Pd plating layer 43, the Au plating layer 44, and the Ag plating layer 45. At the same time, peeling (connection failure) of the Pd plating layer 43, the Au plating layer 44, and the Ag plating layer 45 can be prevented.

[0119] Fig. 6 is a cross-sectional view corresponding to Fig. 2, showing a semiconductor device 61 according to a second embodiment of the present invention together with an outer surface plating layer 42 according to the first embodiment. Fig. 7 is an enlarged view of region VII shown in Fig. 6. Hereinafter, structures corresponding to those described with respect to the semiconductor device 1 will be given the same reference numerals and descriptions thereof will be omitted.

[0120] 6 and 7, the organic insulating layer 31 exposes the inner peripheral edge 38 of the inorganic insulating layer 30 in the region between the first opening 34 and the second opening 37. The width W of the inner peripheral edge 38 of the inorganic insulating layer 30 is arbitrary, but is preferably greater than the thickness T2 of the inorganic insulating layer 30 (T2 <W)。

[0121] The ratio W / T2 of the width W of the inner peripheral edge 38 to the thickness T2 of the inorganic insulating layer 30 may be more than 1 and not more than 10. The ratio W / T2 may be more than 1 and not more than 2, 2 to 4, 4 to 6, 6 to 8, or 8 to 10. The ratio W / T2 is preferably 2 to 5. The width W may be more than 0 μm and not more than 10 μm. The width W may be more than 0 μm and not more than 2 μm, 2 to 4 μm, 4 to 6 μm, 6 to 8 μm, or 8 to 10 μm.

[0122] The Ni plating layer 41 is formed on the first principal surface electrode 21 in the pad opening 26. The Ni plating layer 41 covers the first principal surface electrode 21 in the first opening 34, and covers the inner peripheral edge 38 of the inorganic insulating layer 30 in the second opening 37. The Ni plating layer 41 has an outer surface formed at a distance from the main surface of the organic insulating layer 31 (insulating layer 24) toward the first principal surface electrode 21. The Ni plating layer 41 covers the inner peripheral edge 38 of the inorganic insulating layer 30 at a distance from the organic insulating layer 31 in the second opening 37.

[0123] Specifically, the Ni plating layer 41 has a first portion 41A covering the first principal surface electrode 21 and a second portion 41B covering the inner peripheral edge 38 of the inorganic insulating layer 30. The first portion 41A of the Ni plating layer 41 fills the rough surface region 39 in the first opening 34 to cover the first principal surface electrode 21. The first portion 41A covers the entire first inner wall 32 of the inorganic insulating layer 30 in the first opening 34 and protrudes from the opening end of the first opening 34 toward the opening end of the second opening 37. The first portion 41A is connected to the first inner wall 32 of the inorganic insulating layer 30 and has a first connection portion extending in the thickness direction of the inorganic insulating layer 30.

[0124] The second portion 41B of the Ni plating layer 41 is drawn out from the first portion 41A towards the organic insulating layer 31 side within the second opening 37. The second portion 41B is formed in an arc shape that starts from the opening end of the first opening 34 and faces the second inner wall 35 of the organic insulating layer 31.

[0125] The second part 41B covers the inner peripheral edge 38 of the inorganic insulating layer 30 within the second opening 37. In this form, the second part 41B partially covers the inner peripheral edge 38 of the inorganic insulating layer 30 at an interval from the second inner wall 35 of the organic insulating layer 31 to the first inner wall 32 side of the inorganic insulating layer 30 within the second opening 37 such that a part of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed.

[0126] Thereby, the Ni plating layer 41 exposes a part of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire second inner wall 35 of the organic insulating layer 31. The second part 41B faces the first main surface electrode 21 with the inner peripheral edge 38 of the inorganic insulating layer 30 interposed therebetween. The second part 41B is connected to the main surface of the inorganic insulating layer 30 and has a second connection part extending in the width direction of the inorganic insulating layer 30.

[0127] The Ni plating layer 41 has a thickness T4 (T2 < T4) exceeding the thickness T2 of the inorganic insulating layer 30. The thickness T4 is less than the thickness T3 of the organic insulating layer 31 (T4 < T3). The thickness T4 is less than the value obtained by adding the width W of the inner peripheral edge 38 to the thickness T2 of the inorganic insulating layer 30 (T4 < T2 + W). This is the condition for the Ni plating layer 41 to expose the second inner wall 35 of the organic insulating layer 31. The thickness T4 is defined by the thickness of the Ni plating layer 41 with reference to the main surface of the first main surface electrode 21.

[0128] The ratio T4 / T2 of the thickness T4 of the Ni plating layer 41 to the thickness T2 of the inorganic insulating layer 30 may be greater than 1 and less than or equal to 5. The ratio T4 / T2 may be greater than 1 and less than or equal to 2, greater than or equal to 2 and less than or equal to 3, greater than or equal to 3 and less than or equal to 4, or greater than or equal to 4 and less than or equal to 5. The thickness T4 may be 0.1 μm or more and 10 μm or less. The thickness T4 may be 0.1 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less.

[0129] The outer plating layer 42 covers the outer surface of the Ni plating layer 41 within the second opening 37. The outer plating layer 42 has a thickness T5 (T5 < T4) that is less than the thickness T4 of the Ni plating layer 41. In this form, the outer plating layer 42 partially covers the inner peripheral edge 38 of the inorganic insulating layer 30 at a distance from the second inner wall 35 of the organic insulating layer 31 toward the first inner wall 32 of the inorganic insulating layer 30 within the second opening 37.

[0130] The outer plating layer 42 has a terminal surface 42A that is externally connected via a conductive bonding material (e.g., solder). The terminal surface 42A is located on the Ni plating layer 41 side with respect to the main surface of the organic insulating layer 31 (the opening end of the second opening 37). Thereby, the outer plating layer 42 exposes a part of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire second inner wall 35 of the organic insulating layer 31 within the second opening 37.

[0131] Specifically, the outer plating layer 42 has a laminated structure including a Pd plating layer 43 and an Au plating layer 44 laminated in this order from the Ni plating layer 41 side. The Pd plating layer 43 is formed in a film shape along the outer surface of the Ni plating layer 41. The Pd plating layer 43 covers the Ni plating layer 41 at a distance from the opening end of the second opening 37 toward the inorganic insulating layer 30 side. The Pd plating layer 43 partially covers the inner peripheral edge 38 of the inorganic insulating layer 30 at a distance from the second inner wall 35 of the organic insulating layer 31 toward the first inner wall 32 of the inorganic insulating layer 30 within the second opening 37 such that a part of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. Thereby, the Pd plating layer 43 exposes a part of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire second inner wall 35 of the organic insulating layer 31 within the second opening 37.

[0132] The Pd plating layer 43 has a thickness that is less than the thickness T4 of the Ni plating layer 41. The thickness of the Pd plating layer 43 may be 0.01 μm or more and 1 μm or less. The thickness of the Pd plating layer 43 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0133] The Au plating layer 44 is formed in a film shape along the outer surface of the Pd plating layer 43. The Au plating layer 44 covers the Pd plating layer 43 with a gap from the opening end of the second opening 37 toward the inorganic insulating layer 30. The Au plating layer 44 partially covers the inner peripheral edge 38 of the inorganic insulating layer 30 with a gap from the second inner wall 35 of the organic insulating layer 31 toward the first inner wall 32 of the inorganic insulating layer 30 in the second opening 37 so that a part of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. As a result, the Au plating layer 44 exposes a part of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire area of ​​the second inner wall 35 of the organic insulating layer 31 in the second opening 37.

[0134] The Au plating layer 44 has a thickness less than the thickness T4 of the Ni plating layer 41. The Au plating layer 44 may have a thickness of 0.01 μm or more and 1 μm or less. The Au plating layer 44 may have a thickness of 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0135] In this embodiment, an example has been described in which the outer plating layer 42 is formed to expose the entire area of ​​the second inner wall 35 of the organic insulating layer 31. However, an outer plating layer 42 that covers a portion of the second inner wall 35 of the organic insulating layer 31 may also be used. In this case, at least one of the Pd plating layer 43 and the Au plating layer 44 may cover a portion of the second inner wall 35 of the organic insulating layer 31. The outer plating layer 42 may take various forms as shown in Figs. 8A to 8D.

[0136] Fig. 8A is a corresponding view to Fig. 7, and is an enlarged view showing the outer surface plating layer 42 according to the second embodiment. Below, differences from the outer surface plating layer 42 according to the first embodiment will be described.

[0137] 8A, in this embodiment, the outer surface plating layer 42 has a single-layer structure made of an Au plating layer 44. The Au plating layer 44 is formed in a film shape along the outer surface of the Ni plating layer 41. The Au plating layer 44 partially covers the inner peripheral edge 38 of the inorganic insulating layer 30 at a distance from the second inner wall 35 of the organic insulating layer 31 toward the first inner wall 32 of the inorganic insulating layer 30 in the second opening 37 so that a part of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed.

[0138] The Au plating layer 44 covers the Ni plating layer 41 with a gap from the opening end of the second opening 37 toward the inorganic insulating layer 30. As a result, the Au plating layer 44 exposes part of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire area of ​​the second inner wall 35 of the organic insulating layer 31 in the second opening 37. The Au plating layer 44 may cover part of the second inner wall 35 of the organic insulating layer 31.

[0139] Fig. 8B is a corresponding view to Fig. 7, and is an enlarged view showing the outer surface plating layer 42 according to the third embodiment. Below, differences from the outer surface plating layer 42 according to the first embodiment will be described.

[0140] 8B, in this embodiment, the outer surface plating layer 42 has a single-layer structure made of a Pd plating layer 43. The Pd plating layer 43 is formed in a film shape along the outer surface of the Ni plating layer 41. The Pd plating layer 43 partially covers the inner peripheral edge 38 of the inorganic insulating layer 30 at a distance from the second inner wall 35 of the organic insulating layer 31 toward the first inner wall 32 of the inorganic insulating layer 30 in the second opening 37 so that a part of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed.

[0141] The Pd plating layer 43 covers the Ni plating layer 41 with a gap from the opening end of the second opening 37 toward the inorganic insulating layer 30. As a result, the Pd plating layer 43 exposes part of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire second inner wall 35 of the organic insulating layer 31 in the second opening 37. The Pd plating layer 43 may cover part of the second inner wall 35 of the organic insulating layer 31.

[0142] Fig. 8C is a corresponding view to Fig. 7 and is an enlarged view showing outer surface plating layer 42 according to the fourth embodiment. Below, differences from outer surface plating layer 42 according to the first embodiment will be described.

[0143] 8C, in this embodiment, the outer surface plating layer 42 has a single-layer structure made of an Ag plating layer 45. The Ag plating layer 45 is formed in a film shape along the outer surface of the Ni plating layer 41. The Ag plating layer 45 partially covers the inner peripheral edge 38 of the inorganic insulating layer 30 at a distance from the second inner wall 35 of the organic insulating layer 31 toward the first inner wall 32 of the inorganic insulating layer 30 in the second opening 37 so that a part of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed.

[0144] The Ag plating layer 45 covers the Ni plating layer 41 with a gap from the opening end of the second opening 37 toward the inorganic insulating layer 30. As a result, the Ag plating layer 45 exposes a part of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire area of ​​the second inner wall 35 of the organic insulating layer 31 in the second opening 37. The Ag plating layer 45 may cover a part of the second inner wall 35 of the organic insulating layer 31.

[0145] The Ag plating layer 45 has a thickness less than the thickness T4 of the Ni plating layer 41. The Ag plating layer 45 may have a thickness of 0.01 μm or more and 1 μm or less. The Ag plating layer 45 may have a thickness of 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0146] Fig. 8D is a corresponding view to Fig. 7 and is an enlarged view showing outer surface plating layer 42 according to the fifth embodiment. Below, differences from outer surface plating layer 42 according to the first embodiment will be described.

[0147] 8D, the outer surface plating layer 42 has a layered structure including a Pd plating layer 43, an Au plating layer 44 and an Ag plating layer 45, which are layered in this order from the Ni plating layer 41 side.

[0148] The Pd plating layer 43 is formed in a film shape along the outer surface of the Ni plating layer 41. The Pd plating layer 43 partially covers the inner peripheral edge 38 of the inorganic insulating layer 30 at a distance from the second inner wall 35 of the organic insulating layer 31 to the first inner wall 32 of the inorganic insulating layer 30 in the second opening 37 so that a part of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. The Pd plating layer 43 covers the Ni plating layer 41 at a distance from the opening end of the second opening 37 to the inorganic insulating layer 30. As a result, the Pd plating layer 43 exposes a part of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire area of ​​the second inner wall 35 of the organic insulating layer 31 in the second opening 37.

[0149] The Au plating layer 44 is formed in a film shape along the outer surface of the Pd plating layer 43. The Au plating layer 44 partially covers the inner peripheral edge 38 of the inorganic insulating layer 30 at a distance from the second inner wall 35 of the organic insulating layer 31 to the first inner wall 32 of the inorganic insulating layer 30 in the second opening 37 so that a part of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. The Au plating layer 44 covers the Pd plating layer 43 at a distance from the opening end of the second opening 37 to the inorganic insulating layer 30. As a result, the Au plating layer 44 exposes a part of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire area of ​​the second inner wall 35 of the organic insulating layer 31 in the second opening 37.

[0150] The Ag plating layer 45 is formed in a film shape along the outer surface of the Au plating layer 44. The Ag plating layer 45 partially covers the inner peripheral edge 38 of the inorganic insulating layer 30 at a distance from the second inner wall 35 of the organic insulating layer 31 to the first inner wall 32 of the inorganic insulating layer 30 in the second opening 37 so that a part of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. The Ag plating layer 45 covers the Au plating layer 44 at a distance from the opening end of the second opening 37 to the inorganic insulating layer 30. As a result, the Ag plating layer 45 exposes a part of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire area of ​​the second inner wall 35 of the organic insulating layer 31 in the second opening 37. At least one of the Pd plating layer 43, the Au plating layer 44, and the Ag plating layer 45 may cover a part of the second inner wall 35 of the organic insulating layer 31.

[0151] As described above, the semiconductor device 61 can achieve the same effects as those described for the semiconductor device 1. In particular, the Ni plating layer 41 of the semiconductor device 61 covers the inner peripheral edge 38 of the inorganic insulating layer 30 at a distance from the organic insulating layer 31 within the second opening 37. This makes it possible to prevent an undesired gap from being formed between the organic insulating layer 31 and the Ni plating layer 41. This ensures that the reliability of the Ni plating layer 41 is improved.

[0152] Furthermore, the semiconductor device 61 includes an outer plating layer 42 that covers the outer surface of the Ni plating layer 41. With this structure, no gap is formed between the organic insulating layer 31 and the Ni plating layer 41, so that the outer plating layer 42 can be appropriately formed along the outer surface of the Ni plating layer 41. Therefore, connection failure of the Ni plating layer 41 caused by abnormal film formation of the outer plating layer 42 can be appropriately suppressed, and at the same time, peeling (connection failure) of the outer plating layer 42 can be appropriately suppressed.

[0153] Specifically, the outer surface plating layer 42 can include at least one of a Pd plating layer 43, an Au plating layer 44, and an Ag plating layer 45. This can prevent connection failure of the Ni plating layer 41 caused by abnormal film formation of the Pd plating layer 43, the Au plating layer 44, and the Ag plating layer 45. At the same time, peeling (connection failure) of the Pd plating layer 43, the Au plating layer 44, and the Ag plating layer 45 can be prevented.

[0154] FIG. 9 is a plan view showing a semiconductor device 101 according to a third embodiment. FIG. 10 is an enlarged view of region X shown in FIG. 9. FIG. 11 is a cross-sectional view taken along line XI-XI shown in FIG. 10. FIG. 12 is a cross-sectional view taken along line XII-XII shown in FIG. 9. FIG. 13 is an enlarged view of region XIII shown in FIG. 12. FIG. 14 is an enlarged view of region XIV shown in FIG. 12. In the following, structures corresponding to those described with respect to the semiconductor device 1 will be denoted by the same reference symbols and will not be described.

[0155] 9 to 14, a semiconductor device 101 is a SiC semiconductor device in which a MISFET (Metal Insulator Semiconductor Field Effect Transistor), as an example of a functional device, is formed in an active region 8 instead of an SBD.

[0156] The semiconductor device 101 includes a SiC chip 2, a main surface insulating layer 12, a first main surface electrode 21, an insulating layer 24, a pad electrode 40, and a second main surface electrode (rear surface electrode) 46. In Fig. 9, the insulating layer 24 is indicated by hatching. The first main surface 3 and the second main surface 4 of the SiC chip 2 are formed in a quadrangular shape (rectangular shape in this embodiment) in a plan view.

[0157] The first side surface 5A and the second side surface 5B extend along the first direction X and face a second direction Y that intersects with the first direction X. The first side surface 5A and the second side surface 5B form short sides of the SiC chip 2. The third side surface 5C and the fourth side surface 5D extend along the second direction Y and face the first direction X. The third side surface 5C and the fourth side surface 5D form long sides of the SiC chip 2.

[0158] The length of the first side surface 5A (second side surface 5B) may be 0.1 mm or more and 8 mm or less. The length of the first side surface 5A (second side surface 5B) is preferably 0.1 mm or more and 2.5 mm or less. The length of the third side surface 5C (fourth side surface 5D) may be 0.2 mm or more and 16 mm or less. The length of the third side surface 5C (fourth side surface 5D) is preferably 0.5 mm or more and 5 mm or less.

[0159] As in the first embodiment, the SiC chip 2 has a layered structure including a SiC substrate 6 and a SiC epitaxial layer 7. The SiC substrate 6 is formed as a drain region of the MISFET. The SiC epitaxial layer 7 is formed as a drift region of the MISFET.

[0160] In this embodiment, the SiC epitaxial layer 7 has a different n-type impurity concentration along the normal direction Z. Specifically, the SiC epitaxial layer 7 includes a high concentration region 102 having a high n-type impurity concentration, and a low concentration region 103 having a lower n-type impurity concentration than the high concentration region 102.

[0161] The high concentration region 102 is formed in a region on the first main surface 3 side. The low concentration region 103 is formed in a region on the second main surface 4 side with respect to the high concentration region 102. The thickness of the high concentration region 102 is less than the thickness of the low concentration region 103. The thickness of the high concentration region 102 is less than half the total thickness of the SiC epitaxial layer 7.

[0162] The n-type impurity concentration of high concentration region 102 may be 1.0×10 16 cm -3 or more and 1.0×10 18 cm -3 or less. The n-type impurity concentration of low concentration region 103 may be 1.0×10 15 cm -3 or more and 1.0×10 16 cm -3 or less. Of course, the n-type impurity concentration of SiC epitaxial layer 7 may have a concentration gradient in which the n-type impurity concentration gradually decreases from SiC substrate 6 toward first main surface 3, within a range of 1.0×10 15 cm -3 or more and 1.0×10 18 cm -3 or less.

[0163] The active region 8 is formed in the center of the SiC chip 2 and spaced inward from the side surfaces 5A-5D in a plan view. The active region 8 is formed in a rectangular shape having four sides parallel to the side surfaces 5A-5D in a plan view. On the other hand, the outer region 9 is formed in a rectangular ring shape surrounding the active region 8 in a plan view.

[0164] The semiconductor device 101 includes a plurality of trench gate structures 104 formed on the first main surface 3 in the active region 8. The plurality of trench gate structures 104 are each formed in a band shape extending along a first direction X and are formed at intervals in a second direction Y. The plurality of trench gate structures 104 are formed in stripes extending along the first direction X in a plan view.

[0165] In this embodiment, the multiple trench gate structures 104 extend in a strip shape from the periphery on one side (the third side surface 5C side) to the periphery on the other side (the fourth side surface 5D side) in the active region 8. The multiple trench gate structures 104 cross the intermediate portion between the periphery on one side and the periphery on the other side in the active region 8.

[0166] The length of each trench gate structure 104 may be 1 mm or more and 10 mm or less. The length of each trench gate structure 104 may be 1 mm or more and 2 mm or less, 2 mm or more and 4 mm or less, 4 mm or more and 6 mm or less, 6 mm or more and 8 mm or less, or 8 mm or more and 10 mm or less. The length of each trench gate structure 104 is preferably 2 mm or more and 6 mm or less. The total extension per unit area of ​​one trench gate structure 104 may be 0.5 μm / μm2 or more and 0.75 μm / μm2 or less.

[0167] Each trench gate structure 104 includes a gate trench 105, a gate insulating layer 106, and a gate electrode 107. In Figure 10, the gate insulating layer 106 and the gate electrode 107 are indicated by hatching.

[0168] The gate trench 105 is formed in the SiC epitaxial layer 7. The gate trench 105 includes a sidewall and a bottom wall. The sidewall forming the long side of the gate trench 105 is formed by the a-plane of the SiC single crystal. The sidewall forming the short side of the gate trench 105 is formed by the m-plane of the SiC single crystal.

[0169] The sidewall of the gate trench 105 may extend along the normal direction Z. In the SiC chip 2, the angle that the sidewall of the gate trench 105 forms with the first main surface 3 may be not less than 90° and not more than 95° (for example, not less than 91° and not more than 93°). The sidewall of the gate trench 105 may be formed substantially perpendicular to the first main surface 3. The gate trench 105 may be formed in a tapered shape in which the opening width narrows from the first main surface 3 toward the bottom wall.

[0170] The bottom wall of the gate trench 105 is located in the high concentration region 102. The bottom wall of the gate trench 105 faces the c-plane of the SiC single crystal. The bottom wall of the gate trench 105 has an off angle inclined toward the a-axis direction with respect to the c-plane of the SiC single crystal. The bottom wall of the gate trench 105 may be formed parallel to the first main surface 3. The bottom wall of the gate trench 105 may be formed in a curved shape toward the second main surface 4.

[0171] The gate trench 105 has a first depth D1. The first depth D1 may be 0.5 μm or more and 3 μm or less. The first depth D1 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less.

[0172] The width of the gate trench 105 along the second direction Y may be 0.1 μm or more and 2 μm or less. The width of the gate trench 105 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, or 1.5 μm or more and 2 μm or less.

[0173] The opening edge portion of the gate trench 105 includes an inclined portion that slopes downward from the first main surface 3 toward the inside of the gate trench 105. The opening edge portion of the gate trench 105 is a portion that connects the first main surface 3 and the side wall of the gate trench 105. The inclined portion of the gate trench 105 is formed in a curved shape recessed toward the SiC chip 2. The inclined portion of the gate trench 105 may be formed in a curved shape toward the gate trench 105. The inclined portion of the gate trench 105 relieves electric field concentration at the opening edge portion of the gate trench 105.

[0174] The gate insulating layer 106 includes at least one of silicon oxide, silicon nitride, aluminum oxide, zirconium oxide, and tantalum oxide. The gate insulating layer 106 may have a laminated structure in which a silicon oxide layer and a silicon nitride layer are laminated in any order. The gate insulating layer 106 may have a single-layer structure made of a silicon oxide layer or a silicon nitride layer. In this embodiment, the gate insulating layer 106 has a single-layer structure made of a silicon oxide layer.

[0175] The gate insulating layer 106 is formed in a film shape along the inner wall of the gate trench 105, and defines a recess space within the gate trench 105. The gate insulating layer 106 includes a first region 108, a second region 109, and a third region 110. The first region 108 is formed along the side wall of the gate trench 105. The second region 109 is formed along the bottom wall of the gate trench 105. The third region 110 partially covers the first main surface 3 through the opening edge portion of the gate trench 105.

[0176] The thickness of the first region 108 may be 0.01 μm or more and 0.2 μm or less. The thickness of the second region 109 may be 0.05 μm or more and 0.5 μm or less. The thickness of the second region 109 may be greater than the thickness of the first region 108. The thickness of the third region 110 may be 0.05 μm or more and 0.5 μm or less. The thickness of the third region 110 may be greater than the thickness of the first region 108.

[0177] The gate insulating layer 106 includes a bulge 111 that bulges toward the inside of the gate trench 105 at the opening edge. The bulge 111 is formed at the connection between the first region 108 and the third region 110 of the gate insulating layer 106. The bulge 111 is formed in a curved shape that bulges toward the inside of the gate trench 105. The bulge 111 narrows the opening of the gate trench 105 at the opening edge. A gate insulating layer 106 that does not have a bulge 111 may be formed. A gate insulating layer 106 having a uniform thickness may be formed.

[0178] The gate electrode 107 is embedded in the gate trench 105 with the gate insulating layer 106 sandwiched therebetween. Specifically, the gate electrode 107 is embedded in a recess space defined by the gate insulating layer 106 in the gate trench 105. The gate electrode 107 has an electrode surface exposed from an opening of the gate trench 105. The electrode surface of the gate electrode 107 is formed in a curved shape recessed toward the bottom wall of the gate trench 105. The electrode surface of the gate electrode 107 is narrowed by a bulging portion 111 of the gate insulating layer 106.

[0179] The gate electrode 107 is made of a conductive material other than a metal material. The gate electrode 107 is preferably made of conductive polysilicon. In this embodiment, the gate electrode 107 includes p-type polysilicon doped with p-type impurities.

[0180] The p-type impurity concentration of the gate electrode 107 may be 1.0×10 18 cm −3 or more and 1.0×10 22 cm −3 or less. The p-type impurity of the gate electrode 107 may include at least one of boron, aluminum, indium, and gallium. The sheet resistance of the gate electrode 107 may be 10 Ω / □ or more and 500 Ω / □ or less (about 200 Ω / □ in this embodiment). The thickness of the gate electrode 107 may be 0.5 μm or more and 3 μm or less.

[0181] The semiconductor device 101 includes a first low resistance layer 112 covering the gate electrode 107. The first low resistance layer 112 covers the gate electrode 107 in the gate trench 105. The first low resistance layer 112 forms a part of the trench gate structure 104.

[0182] The first low-resistance layer 112 includes a conductive material having a sheet resistance less than the sheet resistance of the gate electrode 107. The sheet resistance of the first low-resistance layer 112 may be 0.01 Ω / □ or more and 10 Ω / □ or less. The thickness of the first low-resistance layer 112 may be 0.01 μm or more and 3 μm or less. The thickness of the first low-resistance layer 112 is preferably less than the thickness of the gate electrode 107.

[0183] First low-resistance layer 112 specifically includes a polycide layer. The polycide layer is formed by silicidizing a surface layer portion of gate electrode 107 with a metal material. That is, the electrode surface of gate electrode 107 is formed of first low-resistance layer 112. Specifically, the polycide layer is made of a p-type polycide layer containing p-type impurities added to gate electrode 107. The polycide layer preferably has a resistivity of 10 μΩ·cm or more and 110 μΩ·cm or less.

[0184] The sheet resistance in the gate trench 105 in which the gate electrode 107 and the first low resistance layer 112 are embedded is less than the sheet resistance of the gate electrode 107 alone. The sheet resistance in the gate trench 105 is preferably less than or equal to the sheet resistance of n-type polysilicon doped with n-type impurities. The sheet resistance in the gate trench 105 is approximated to the sheet resistance of the first low resistance layer 112. The sheet resistance in the gate trench 105 may be greater than or equal to 0.01 Ω / □ and less than or equal to 10 Ω / □. The sheet resistance in the gate trench 105 is preferably less than 10 Ω / □.

[0185] The first low resistance layer 112 may contain at least one of TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, and WSi2. Among these species, NiSi, CoSi2, and TiSi2 are particularly suitable as a polycide layer forming the first low resistance layer 112, since they have relatively small resistivity values ​​and temperature dependence. The first low resistance layer 112 is most preferably made of CoSi2, which has the property of being less likely to diffuse into other regions.

[0186] The first low-resistance layer 112 includes a contact portion in contact with the gate insulating layer 106. Specifically, the contact portion of the first low-resistance layer 112 is in contact with the third region 110 (the bulging portion 111) of the gate insulating layer 106. This makes it possible to suppress a current path between the first low-resistance layer 112 and the SiC epitaxial layer 7. In particular, a design in which the contact portion of the first low-resistance layer 112 is connected to a relatively thick corner portion of the gate insulating layer 106 is effective in reducing the risk of a current path.

[0187] By embedding p-type polysilicon, which has a work function different from that of n-type polysilicon, in the gate trench 105, the gate threshold voltage Vth can be increased by about 1 V. However, p-type polysilicon has a sheet resistance several tens of times (approximately 20 times) higher than the sheet resistance of n-type polysilicon. Therefore, when p-type polysilicon is used as the material for the gate electrode 107, energy loss increases with an increase in the parasitic resistance in the gate trench 105 (hereinafter simply referred to as "gate resistance").

[0188] Therefore, in the semiconductor device 101, a first low-resistance layer 112 (p-type polycide) is formed on the gate electrode 107 (p-type polysilicon). The first low-resistance layer 112 can reduce the sheet resistance in the gate trench 105 while allowing an increase in the gate threshold voltage Vth.

[0189] For example, the structure having the first low-resistance layer 112 can reduce the sheet resistance to 1 / 100 or less compared to a structure not having the first low-resistance layer 112. The structure having the first low-resistance layer 112 can reduce the sheet resistance to 1 / 5 or less compared to the gate electrode 107 including n-type polysilicon.

[0190] This reduces the gate resistance, allowing the current to be efficiently diffused along the trench gate structure 104. That is, the first low-resistance layer 112 is formed as a current diffusion layer that diffuses the current in the gate trench 105. In particular, in the case of a gate trench 105 having a length on the order of millimeters (length of 1 mm or more), it takes time to transmit the current, but the first low-resistance layer 112 can appropriately suppress the switching delay.

[0191] According to the structure having the first low-resistance layer 112, it is not necessary to increase the p-type impurity concentration in the SiC epitaxial layer 7 in order to increase the gate threshold voltage Vth. Therefore, it is possible to appropriately increase the gate threshold voltage Vth while suppressing an increase in the channel resistance.

[0192] The semiconductor device 101 includes a plurality of trench source structures 121 formed in regions between adjacent trench gate structures 104. The plurality of trench source structures 121 are formed at intervals in the second direction Y in a manner to sandwich one trench gate structure 104 therebetween.

[0193] The plurality of trench source structures 121 are each formed in a belt shape extending along the first direction X. The plurality of trench source structures 121 are formed in a stripe shape extending along the first direction X in a plan view.

[0194] The pitch PS between the central portions of the trench source structures 121 adjacent to each other in the second direction Y may be 1 μm or more and 5 μm or less. The pitch PS may be 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, or 4 μm or more and 5 μm or less. The pitch PS is preferably 1.5 μm or more and 3 μm or less.

[0195] Each trench source structure 121 includes a source trench 122, a source insulating layer 123, and a source electrode 124. In Figure 10, the source electrode 124 is indicated by hatching.

[0196] The source trench 122 is formed in the SiC epitaxial layer 7. The source trench 122 includes a sidewall and a bottom wall. The sidewall forming the long side of the source trench 122 is formed by the a-plane of the SiC single crystal. The sidewall forming the short side of the source trench 122 is formed by the m-plane of the SiC single crystal.

[0197] The bottom wall of the source trench 122 is located in the high concentration region 102. The bottom wall of the source trench 122 is located in a region on the second main surface 4 side with respect to the bottom wall of the gate trench 105. The bottom wall of the source trench 122 is located in a region between the bottom wall of the gate trench 105 and the low concentration region 103 with respect to the normal direction Z.

[0198] The bottom wall of the source trench 122 faces the c-plane of the SiC single crystal. The bottom wall of the source trench 122 has an off angle inclined toward the a-axis direction with respect to the c-plane of the SiC single crystal. The bottom wall of the source trench 122 may be formed parallel to the first main surface 3. The bottom wall of the source trench 122 may be formed in a curved shape toward the second main surface 4.

[0199] The source trench 122 has a second depth D2 that is greater than the first depth D1 of the gate trench 105. A ratio DS / DG of the second depth D2 to the first depth D1 may be 1.5 or greater, provided that the source trench 122 is located within the high concentration region 102. The ratio DS / DG is preferably 2 or greater.

[0200] The second depth D2 may be 0.5 μm to 10 μm. The second depth D2 may be 0.5 μm to 1 μm, 1 μm to 2 μm, 2 μm to 4 μm, 4 μm to 6 μm, 6 μm to 8 μm, or 8 μm to 10 μm. The source trench 122 may be formed having a second depth D2 that is approximately equal to the first depth D1.

[0201] The source trench 122 includes a first trench portion 125 and a second trench portion 126. The first trench portion 125 is formed on the opening side of the source trench 122. The first trench portion 125 has a first width W1 in the second direction Y. The first trench portion 125 may be formed in a tapered shape in which the first width W1 narrows from the first main surface 3 toward the bottom wall side.

[0202] The first trench portion 125 is preferably formed in a region on the first main surface 3 side with respect to the bottom wall of the gate trench 105. That is, the depth of the first trench portion 125 is preferably less than the first depth D1 of the gate trench 105. The first trench portion 125 may be formed to cross the bottom wall of the gate trench 105. That is, the depth of the first trench portion 125 may exceed the first depth D1 of the gate trench 105.

[0203] The depth of the first trench portion 125 may be 0.1 μm or more and 2 μm or less. The depth of the first trench portion 125 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, or 1.5 μm or more and 2 μm or less.

[0204] The first width W1 of the first trench portion 125 may be greater than or equal to the width of the gate trench 105, or may be less than the width of the gate trench 105. The first width W1 preferably exceeds the width of the gate trench 105. The first width W1 may be 0.1 μm or more and 2 μm or less. The first width W1 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, or 1.5 μm or more and 2 μm or less.

[0205] The second trench portion 126 is formed on the bottom wall side of the source trench 122. The second trench portion 126 is formed in a region between the first trench portion 125 and the bottom of the SiC epitaxial layer 7 in relation to the normal direction Z, and crosses the bottom wall of the gate trench 105. In relation to the normal direction Z, the depth of the second trench portion 126 based on the first trench portion 125 preferably exceeds the first depth D1 of the gate trench 105.

[0206] The second trench portion 126 has a second width W2 that is less than the first width W1 in the second direction Y. The second width W2 may be equal to or greater than the width of the gate trench 105, or may be less than the width of the gate trench 105, provided that the second width W2 is less than the first width W1.

[0207] The second width W2 may be 0.1 μm or more and less than 2 μm. The second width W2 may be 0.1 μm or more and less than 2 μm. The second width W2 may be 0.1 μm or more and less than 0.5 μm, 0.5 μm or more and less than 1 μm, 1 μm or more and less than 1.5 μm, or 1.5 μm or more and less than 2 μm. Of course, the second trench portion 126 may be formed to have the second width W2 that is approximately equal to the first width W1.

[0208] The overall opening width of source trench 122 is preferably formed to be approximately the same as the opening width of gate trench 105. The opening width of source trench 122 being approximately the same as the opening width of gate trench 105 means that the opening width of source trench 122 is within a range of ±20% of the opening width of gate trench 105.

[0209] The sidewall of the second trench portion 126 may extend along the normal direction Z. In the SiC chip 2, the angle that the sidewall of the second trench portion 126 forms with the first main surface 3 may be 90° or more and 95° or less (for example, 91° or more and 93° or less). The sidewall of the second trench portion 126 may be formed approximately perpendicular to the first main surface 3. The second trench portion 126 may be formed in a tapered shape in which the second width W2 narrows from the first trench portion 125 toward the bottom wall side.

[0210] The source insulating layer 123 includes at least one of silicon oxide, silicon nitride, aluminum oxide, zirconium oxide, and tantalum oxide. The source insulating layer 123 may have a laminated structure in which a silicon oxide layer and a silicon nitride layer are laminated in any order. The source insulating layer 123 may have a single-layer structure made of a silicon oxide layer or a silicon nitride layer. In this embodiment, the source insulating layer 123 has a single-layer structure made of a silicon oxide layer.

[0211] The source insulating layer 123 is formed in a film shape along the inner wall of the source trench 122, and defines a recess space within the source trench 122. Specifically, the source insulating layer 123 is formed in a film shape along the inner wall of the source trench 122 so as to expose the first trench portion 125 and cover the second trench portion 126.

[0212] As a result, the source insulating layer 123 defines a recess space in the second trench portion 126. The source insulating layer 123 has a sidewall window portion 127 through which the first trench portion 125 is exposed.

[0213] The source insulating layer 123 includes a first region 128 and a second region 129. The first region 128 is formed along a side wall of the source trench 122. The second region 129 is formed along a bottom wall of the source trench 122. The thickness of the first region 128 is less than the thickness of the second region 129. The thickness of the first region 128 may be not less than 0.01 μm and not more than 0.2 μm. The thickness of the second region 129 may be not less than 0.05 μm and not more than 0.5 μm.

[0214] The thickness of the first region 128 may be approximately equal to the thickness of the first region 128 of the gate insulating layer 106. The thickness of the second region 129 may be approximately equal to the thickness of the second region 129 of the gate insulating layer 106. A source insulating layer 123 having a uniform thickness may be formed.

[0215] The source electrode 124 is embedded in the source trench 122 with the source insulating layer 123 therebetween. Specifically, the source electrode 124 is embedded in a first trench portion 125 and a second trench portion 126 with the source insulating layer 123 therebetween.

[0216] The source electrode 124 is embedded in a recess space defined by the second trench portion 126 on the bottom wall side of the source trench 122. The source electrode 124 has a sidewall contact portion 130 in contact with the sidewall of the first trench portion 125 exposed from the sidewall window portion 127 on the opening side of the source trench 122.

[0217] The source electrode 124 has an electrode surface exposed from the opening of the source trench 122. The electrode surface of the source electrode 124 is formed in a curved shape recessed toward the bottom wall of the source trench 122. The electrode surface of the source electrode 124 may be formed parallel to the first main surface 3.

[0218] In the normal direction Z, the thickness of the source electrode 124 may be 0.5 μm to 10 μm. The thickness of the source electrode 124 may be 0.5 μm to 1 μm, 1 μm to 2 μm, 2 μm to 4 μm, 4 μm to 6 μm, 6 μm to 8 μm, or 8 μm to 10 μm.

[0219] The source electrode 124 is made of a conductive material other than a metal material. The source electrode 124 is preferably made of conductive polysilicon. In this embodiment, the source electrode 124 includes p-type polysilicon doped with p-type impurities.

[0220] The p-type impurity concentration of the source electrode 124 may be equal to or greater than 1.0×10 18 cm −3 and equal to or less than 1.0×10 22 cm −3. The p-type impurity concentration of the source electrode 124 is preferably equal to the p-type impurity concentration of the gate electrode 107. The p-type impurity of the source electrode 124 may include at least one of boron, aluminum, indium, and gallium.

[0221] The semiconductor device 101 includes a second low-resistance layer 131 covering the source electrode 124. The second low-resistance layer 131 covers the source electrode 124 in the source trench 122. The second low-resistance layer 131 forms a part of the trench source structure 121. The second low-resistance layer 131 has a similar structure to the first low-resistance layer 112. The second low-resistance layer 131 will be described mutatis mutandis with the description of the first low-resistance layer 112.

[0222] The semiconductor device 101 includes a p-type body region 141 formed in a surface layer portion of the first main surface 3 in the active region 8. The body region 141 defines the active region 8. The p-type impurity concentration of the body region 141 is lower than the p-type impurity concentrations of the gate electrode 107 and the source electrode 124. The peak value of the p-type impurity concentration of the body region 141 may be not less than 1.0×10 17 cm -3 and not more than 1.0×10 19 cm -3.

[0223] The body region 141 covers the sidewall of the gate trench 105 and the sidewall of the source trench 122 in a surface portion of the first main surface 3. The body region 141 is formed in a region on the first main surface 3 side of the bottom wall of the gate trench 105. The body region 141 faces the gate electrode 107 with the gate insulating layer 106 interposed therebetween.

[0224] The body region 141 is formed in a region on the first trench portion 125 side with respect to the second trench portion 126. The body region 141 covers the first trench portion 125. The body region 141 is connected to a sidewall contact portion 130 of the source electrode 124 exposed from the first trench portion 125. This allows the body region 141 to be source-grounded in the SiC chip 2. The body region 141 may cover a portion of the second trench portion 126. In this case, the body region 141 may face the source electrode 124 with a portion of the source insulating layer 123 sandwiched therebetween.

[0225] The semiconductor device 101 includes an n+ type source region 142 formed in a surface layer portion of a body region 141. The source region 142 is formed along a gate trench 105. The peak value of the n-type impurity concentration of the source region 142 exceeds the peak value of the n-type impurity concentration of the high concentration region 102. The peak value of the n-type impurity concentration of the source region 142 may be 1.0×10 18 cm -3 or more and 1.0×10 21 cm -3 or less.

[0226] The source region 142 covers the sidewall of the gate trench 105 and the sidewall of the source trench 122 in a surface layer portion of the body region 141. The source region 142 faces the gate electrode 107 with the gate insulating layer 106 interposed therebetween. The source region 142 preferably faces the first low-resistance layer 112 with the gate insulating layer 106 interposed therebetween.

[0227] The source region 142 is further formed in a region on the first trench portion 125 side with respect to the second trench portion 126. The source region 142 covers the first trench portion 125. The source region 142 is connected to the sidewall contact portion 130 of the source electrode 124 exposed from the first trench portion 125. As a result, the source region 142 is source-grounded within the SiC chip 2.

[0228] In this embodiment, the source region 142 has a concealed portion that is concealed by the third region 110 of the gate insulating layer 106 on the first main surface 3, and an exposed portion that is exposed from the third region 110. The entire area of ​​the source region 142 may be covered by the third region 110.

[0229] A portion of the source region 142 along the sidewall of the gate trench 105 defines a channel of the MISFET between the high concentration region 102 in the body region 141. The ON / OFF of the channel is controlled by a gate electrode 107.

[0230] The semiconductor device 101 includes a plurality of p+ type contact regions 143 formed in a surface layer portion of the first main surface 3 in the active region 8. The peak value of the p-type impurity concentration of each contact region 143 exceeds the peak value of the p-type impurity concentration of the body region 141. The peak value of the p-type impurity concentration of each contact region 143 may be 1.0×10 18 cm -3 or more and 1.0×10 21 cm -3 or less.

[0231] The multiple contact regions 143 are formed in regions along the multiple source trenches 122, respectively. Specifically, the multiple contact regions 143 are formed in a one-to-multiple relationship with each corresponding source trench 122. The multiple contact regions 143 are formed at intervals along the corresponding source trench 122, respectively. The multiple contact regions 143 are formed at intervals from the gate trench 105, respectively.

[0232] Each contact region 143 covers a corresponding first trench portion 125. Each contact region 143 is interposed between the sidewall contact portion 130 of the source electrode 124 and the source region 142 in the corresponding first trench portion 125. Each contact region 143 is further interposed between the sidewall contact portion 130 of the source electrode 124 and the body region 141 in the corresponding first trench portion 125.

[0233] As a result, each contact region 143 is electrically connected to the source electrode 124, the body region 141, and the source region 142. Each contact region 143 is source-grounded within the SiC chip 2.

[0234] A portion of each contact region 143 covering the first trench portion 125 is drawn out toward the gate trench 105. A portion of each contact region 143 covering the first trench portion 125 is formed in a region on the first main surface 3 side with respect to the bottom of the body region 141. A portion of each contact region 143 covering the first trench portion 125 may extend to an intermediate region between the gate trench 105 and the source trench 122.

[0235] Each contact region 143 further covers a corresponding second trench portion 126. Each contact region 143 faces the source electrode 124 in the corresponding second trench portion 126, with the source insulating layer 123 sandwiched therebetween.

[0236] Each contact region 143 further covers the bottom wall of the corresponding source trench 122. Each contact region 143 faces the source electrode 124 across the bottom wall of the corresponding source trench 122. The bottom of each contact region 143 may be formed parallel to the bottom wall of the corresponding source trench 122.

[0237] The semiconductor device 101 includes a plurality of p-type deep well regions 144 formed in a surface layer portion of the first main surface 3 in the active region 8. The peak value of the p-type impurity concentration of each of the deep well regions 144 is less than the peak value of the p-type impurity concentration of the contact region 143.

[0238] The peak value of the p-type impurity concentration of each deep well region 144 may be equal to or greater than the peak value of the p-type impurity concentration of the body region 141, or may be less than the peak value of the p-type impurity concentration of the body region 141. The peak value of the p-type impurity concentration of each deep well region 144 may be equal to or greater than 1.0×10 17 cm -3 and equal to or less than 1.0×10 19 cm -3.

[0239] The deep well regions 144 are formed in a one-to-one correspondence with the source trenches 122. Each deep well region 144 is formed in a strip shape extending along the corresponding source trench 122 in a plan view. Each deep well region 144 is formed in the high concentration region 102. Each deep well region 144 is formed in a region on the second main surface 4 side with respect to the body region 141. Each deep well region 144 is continuous with the body region 141.

[0240] Each deep well region 144 includes a portion covering the corresponding second trench portion 126. Each deep well region 144 includes a portion covering the corresponding second trench portion 126 with the contact region 143 in between. Each deep well region 144 further includes a portion covering the bottom wall of the corresponding source trench 122. Each deep well region 144 includes a portion covering the bottom wall of the corresponding source trench 122 with the contact region 143 in between.

[0241] Each deep well region 144 has a bottom located on the second main surface 4 side with respect to the bottom wall of the gate trench 105. The bottom of each deep well region 144 may be formed parallel to the bottom wall of each source trench 122. The multiple deep well regions 144 are preferably formed to a constant depth.

[0242] Each deep well region 144 forms a pn junction with the high concentration region 102. A depletion layer extends from this pn junction toward the gate trench 105. The depletion layer may overlap the bottom wall of the gate trench 105.

[0243] In the semiconductor device 101 having only a pn junction diode, the problem of electric field concentration in the SiC chip 2 is small because the semiconductor device 101 has no trench. Each deep well region 144 brings the trench gate type MISFET closer to the structure of a pn junction diode. This allows the electric field in the SiC chip 2 to be alleviated in the trench gate type MISFET.

[0244] The deep well region 144 having a bottom portion on the second main surface 4 side with respect to the bottom wall of the gate trench 105 can appropriately alleviate electric field concentration in the gate trench 105 by a depletion layer. Narrowing the pitch PS between the multiple source trenches 122 (deep well regions 144) is effective in alleviating electric field concentration and improving the breakdown voltage.

[0245] It is preferable that the deep well regions 144 are formed to a constant depth. This makes it possible to prevent the breakdown voltage (e.g., breakdown resistance) of the SiC chip 2 from being limited by each deep well region 144, thereby making it possible to appropriately improve the breakdown voltage.

[0246] By using the source trenches 122, the deep well regions 144 can be appropriately formed in a relatively deep region of the SiC chip 2. Since the deep well regions 144 can be formed along the source trenches 122, the occurrence of variations in the depths of the multiple deep well regions 144 can be appropriately suppressed.

[0247] In this embodiment, a part of the high concentration region 102 is interposed in a region between the plurality of deep well regions 144. This makes it possible to reduce the JFET (Junction Field Effect Transistor) resistance in the region between the plurality of deep well regions 144.

[0248] In this embodiment, the bottom of each deep well region 144 is located in the high concentration region 102. This allows a current path to be formed in the region directly below each deep well region 144 in the high concentration region 102 in the lateral direction parallel to the first main surface 3. As a result, the current spreading resistance can be reduced. In this structure, the low concentration region 103 increases the breakdown voltage of the SiC chip 2.

[0249] The main surface insulating layer 12 covers the entire first main surface 3. The main surface insulating layer 12 covers the source region 142 and the contact region 143 in the active region 8. Specifically, the main surface insulating layer 12 covers the entire source region 142 and the entire contact region 143 in a cross-sectional view along the second direction Y in the active region 8. The main surface insulating layer 12 covers the entire source region 142 and the entire contact region 143 in a plan view.

[0250] More specifically, the main surface insulating layer 12 covers the source electrode 124 across the first trench portion 125 in the active region 8. The main surface insulating layer 12 covers the sidewall contact portion 130 of the source electrode 124 on the first main surface 3.

[0251] The main surface insulating layer 12 has a plurality of contact openings 151 exposing the plurality of source electrodes 124 in the active region 8, respectively. The plurality of contact openings 151 are formed in a one-to-one correspondence with the plurality of source electrodes 124. Each contact opening 151 may be formed in a strip shape extending along the trench source structure 121. Each contact opening 151 is formed within a region surrounded by the sidewall of the source trench 122 (first trench portion 125) in a plan view.

[0252] Each contact opening 151 exposes the source electrode 124 at an interval from the sidewall of the source trench 122 (first trench portion 125) toward the inside of the source trench 122. The contact opening 151 exposes only the source electrode 124. An edge portion of the contact opening 151 is formed in a curved shape toward the inside of the contact opening 151.

[0253] A recess 152 recessed toward the bottom wall of the source trench 122 is formed on the electrode surface of the source electrode 124. The recess 152 may be formed in a strip shape extending along the trench source structure 121. The recess 152 is formed within a region surrounded by the sidewall of the source trench 122 (first trench portion 125) in a plan view.

[0254] The recess 152 is formed at an interval from the sidewall of the source trench 122 (first trench portion 125) toward the inside of the source trench 122. The recess 152 exposes the second low-resistance layer 131. The recess 152 may penetrate the second low-resistance layer 131. The contact opening 151 communicates with the recess 152 of the source electrode 124.

[0255] The periphery of the main surface insulating layer 12 is exposed from the side surfaces 5A to 5D. In this embodiment, the periphery of the main surface insulating layer 12 is continuous with the side surfaces 5A to 5D. The periphery of the main surface insulating layer 12 may be formed at a distance inward from the side surfaces 5A to 5D. In this case, the main surface insulating layer 12 exposes a portion of the first main surface 3 located in the outer region 9.

[0256] The thickness of the main surface insulating layer 12 may be 0.1 μm or more and 10 μm or less. The thickness of the main surface insulating layer 12 may be 0.1 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. The thickness of the main surface insulating layer 12 is preferably 0.5 μm or more and 5 μm or less.

[0257] The first principal surface electrode 21 is formed on the principal surface insulating layer 12. The thickness T1 of the first principal surface electrode 21 may be 1 μm or more and 100 μm or less. The thickness T1 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 40 μm or less, 40 μm or more and 60 μm or less, 60 μm or more and 80 μm or less, or 80 μm or more and 100 μm or less. The thickness T1 is preferably 20 μm or more and 60 μm or less.

[0258] The first principal surface electrode 21 includes a gate principal surface electrode 153, a gate wiring electrode 154, and a source principal surface electrode 155. A gate voltage is applied to the gate principal surface electrode 153 (gate wiring electrode 154). The gate voltage may be 10 V or more and 50 V or less (for example, about 30 V). A source voltage is applied to the source principal surface electrode 155. The source voltage may be a reference voltage (for example, a GND voltage).

[0259] The gate principal surface electrode 153 is formed in the active region 8. The gate principal surface electrode 153 is formed in a region on the first side surface 5A side in a plan view. Specifically, the gate principal surface electrode 153 is formed in the center of the first side surface 5A in a plan view. The gate principal surface electrode 153 may be formed in a corner portion connecting any two of the side surfaces 5A to 5D in a plan view. The gate principal surface electrode 153 may be formed in a quadrangular shape in a plan view.

[0260] The gate wiring electrode 154 is drawn out from the gate principal surface electrode 153 and extends in a strip shape along the periphery of the active region 8. In this embodiment, the gate wiring electrode 154 extends along the first side surface 5A, the third side surface 5C, and the fourth side surface 5D, and divides the inside of the active region 8 from three directions. The gate wiring electrode 154 is electrically connected to the gate electrode 107 via the principal surface insulating layer 12. An electrical signal from the gate principal surface electrode 153 is transmitted to the gate electrode 107 via the gate wiring electrode 154.

[0261] The source principal surface electrode 155 is formed in the active region 8 at a distance from the gate principal surface electrode 153 and the gate wiring electrode 154. The source principal surface electrode 155 covers the region defined by the gate principal surface electrode 153 and the gate wiring electrode 154, and is formed in a C-shape in plan view.

[0262] The source principal surface electrode 155 is electrically connected to the source electrode 124 via the contact opening 151. That is, in this embodiment, the source principal surface electrode 155 made of a metal material is electrically connected to the source electrode 124 made of conductive polysilicon.

[0263] The first principal surface electrode 21 (the gate principal surface electrode 153, the gate wiring electrode 154, and the source principal surface electrode 155) each has a laminated structure including a barrier electrode 22 and a main electrode 23 laminated in this order from the SiC chip 2 side.

[0264] In this embodiment, the barrier electrode 22 includes at least one of a Ti layer and a TiN layer. The barrier electrode 22 preferably has a laminated structure including a Ti layer and a TiN layer laminated in this order from the side of the SiC chip 2. The barrier electrode 22 may have a single layer structure consisting of a Ti layer or a TiN layer.

[0265] The thickness of the barrier electrode 22 may be 0.01 μm or more and 1 μm or less. The thickness of the barrier electrode 22 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0266] The main electrode 23 is formed in the form of a film on the barrier electrode 22. The main electrode 23 covers the entire main surface of the barrier electrode 22. The main electrode 23 has a resistance value less than the resistance value of the barrier electrode 22. The main electrode 23 is made of an Al-based metal layer. Specifically, the main electrode 23 includes at least one of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer.

[0267] The main electrode 23 may have a laminated structure in which two or more of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer are laminated in any order. The main electrode 23 may have a single-layer structure made of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, or an AlSiCu alloy layer. The main electrode 23 preferably has a single-layer structure made of an AlSi alloy layer, an AlCu alloy layer, or an AlSiCu alloy layer.

[0268] The thickness of the main electrode 23 exceeds the thickness of the barrier electrode 22. The thickness of the main electrode 23 may be 10 μm or more and 100 μm or less. The thickness of the main electrode 23 may be 10 μm or more and 20 μm or less, 20 μm or more and 40 μm or less, 40 μm or more and 60 μm or less, 60 μm or more and 80 μm or less, or 80 μm or more and 100 μm or less. The thickness of the main electrode 23 is preferably 20 μm or more and 60 μm or less. Since the thickness of the barrier electrode 22 is extremely small compared to the thickness of the main electrode 23, the thickness T1 of the first principal surface electrode 21 is approximated to the thickness of the main electrode 23.

[0269] The insulating layer 24 covers the first principal surface electrode 21 on the first principal surface 3. In Fig. 9, the insulating layer 24 is shown by hatching. Specifically, the insulating layer 24 is formed on the principal surface insulating layer 12. The periphery of the insulating layer 24 is formed with a gap inward from the side surfaces 5A to 5D. As a result, the insulating layer 24 exposes the periphery of the principal surface insulating layer 12.

[0270] The periphery of the insulating layer 24 defines dicing streets 25 between the side surfaces 5A to 5D. The dicing streets 25 eliminate the need to physically cut the insulating layer 24 when cutting the semiconductor device 101 from the wafer. This allows the semiconductor device 101 to be smoothly cut from the wafer, and simultaneously prevents the insulating layer 24 from peeling off or deteriorating. As a result, the insulating layer 24 can adequately protect objects to be protected, such as the SiC chip 2 and the first principal surface electrode 21.

[0271] The width of the dicing street 25 may be 1 μm or more and 25 μm or less. The width of the dicing street 25 is the width in a direction perpendicular to the direction in which the dicing street 25 extends. The width of the dicing street 25 may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, or 20 μm or more and 25 μm or less.

[0272] The insulating layer 24 has a pad opening 26 that exposes the first principal surface electrode 21. In this embodiment, the pad opening 26 includes a gate pad opening 161 that exposes the gate principal surface electrode 153 and a source pad opening 162 that exposes the source principal surface electrode 155. The gate pad opening 161 may be formed in a polygonal shape having four sides parallel to the side surfaces 5A to 5D in a plan view. The source pad opening 162 may be formed in a polygonal shape having four sides parallel to the side surfaces 5A to 5D in a plan view. The planar shapes of the gate pad opening 161 and the source pad opening 162 are arbitrary.

[0273] Specifically, the insulating layer 24 has a laminated structure including an inorganic insulating layer 30 and an organic insulating layer 31 laminated in this order from the SiC chip 2 side. The inorganic insulating layer 30 is formed in a film shape along the principal surface insulating layer 12, the gate principal surface electrode 153, and the source principal surface electrode 155. The inorganic insulating layer 30 includes a first gate inner wall 163, a first source inner wall 164, and a first outer wall 165. Hereinafter, the first gate inner wall 163, the first source inner wall 164, and the first outer wall 165 may be collectively referred to as the first wall surface.

[0274] The first gate inner wall 163 defines a first gate opening 166 that exposes a portion of the gate principal surface electrode 153. The first gate opening 166 forms a portion of the gate pad opening 161. The first gate opening 166 has a planar shape similar to the planar shape of the gate principal surface electrode 153, and exposes an inner portion of the gate principal surface electrode 153. The planar shape of the first gate opening 166 is arbitrary. The first gate opening 166 may be defined in a polygonal shape having four sides parallel to the side surfaces 5A to 5D in a plan view.

[0275] The first source inner wall 164 defines a first source opening 167 that exposes a part of the source principal surface electrode 155. The first source opening 167 forms a part of the source pad opening 162. The first source opening 167 has a planar shape similar to the planar shape of the source principal surface electrode 155, and exposes an inner part of the source principal surface electrode 155. The planar shape of the first source opening 167 is arbitrary. The first source opening 167 may be defined in a polygonal shape having four sides parallel to the side surfaces 5A to 5D in a plan view.

[0276] The first outer wall 165 of the inorganic insulating layer 30 is formed at a distance inward from the side surfaces 5A to 5D, and defines a part of the dicing street 25 between the inorganic insulating layer 30 and the side surfaces 5A to 5D. This allows the inorganic insulating layer 30 to expose the peripheral portion of the main surface insulating layer 12. The first outer wall 165 may be formed in a quadrangle shape having four sides parallel to the side surfaces 5A to 5D in a plan view.

[0277] The angle that the first wall surface of the inorganic insulating layer 30 forms with the principal surface of the first principal surface electrode 21 within the inorganic insulating layer 30 may be 30° or more and 90° or less. The angle that the first wall surface forms with the principal surface of the first principal surface electrode 21 within the inorganic insulating layer 30 is preferably 45° or more and less than 90°. The angle of the first wall surface is defined by the angle that a straight line connecting the lower end and the upper end of the first wall surface forms with the principal surface of the first principal surface electrode 21.

[0278] The inorganic insulating layer 30 has a property of high adhesion to Ni. The inorganic insulating layer 30 includes at least one of a silicon oxide layer and a silicon nitride layer. The inorganic insulating layer 30 may have a laminated structure including a silicon oxide layer and a silicon nitride layer laminated in this order from the SiC chip 2 side. The inorganic insulating layer 30 may have a single layer structure made of a silicon oxide layer or a silicon nitride layer. It is preferable that the inorganic insulating layer 30 includes an insulating material different from the main surface insulating layer 12. In this embodiment, the inorganic insulating layer 30 has a single layer structure made of a silicon nitride layer.

[0279] The thickness T2 of the inorganic insulating layer 30 is preferably less than the thickness T1 of the first main surface electrode 21 (T2 < T1). The thickness T2 may be 0.1 μm or more and 10 μm or less. The thickness T2 may be 0.1 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. The thickness T2 is preferably 1 μm or more and 5 μm or less. The thickness T2 is particularly preferably 1 μm or more and 2 μm or less.

[0280] The organic insulating layer 31 is formed in a film shape on the inorganic insulating layer 30. The organic insulating layer 31 includes a second gate inner wall 168, a second source inner wall 169, and a second outer wall 170. Hereinafter, the second gate inner wall 168, the second source inner wall 169, and the second outer wall 170 may be collectively referred to as the second wall surface.

[0281] Referring to FIG. 13, in this form, the second gate inner wall 168 is formed in a curved shape that is recessed toward the inorganic insulating layer 30 side. The second gate inner wall 168 defines a second gate opening 171 that exposes a part of the gate main surface electrode 153. The second gate opening 171 has a planar shape similar to the planar shape of the gate main surface electrode 153 and exposes the inner part of the gate main surface electrode 153. The planar shape of the second gate opening 171 is arbitrary. The second gate opening 171 may be defined in a polygonal shape having four sides parallel to the sides 5A to 5D in a plan view.

[0282] The second gate opening 171 communicates with the first gate opening 166 of the inorganic insulating layer 30 and forms a gate pad opening 161 with the first gate opening 166. The second gate opening 171 surrounds the first gate opening 166 at an interval from the first gate opening 166 and exposes a part of the inorganic insulating layer 30. Specifically, the organic insulating layer 31 exposes a part of the main surface of the inorganic insulating layer 30 as a gate inner peripheral edge 172 in the region between the first gate opening 166 and the second gate opening 171.

[0283] The width WG of the gate inner periphery 172 may be more than 0 μm and not more than 10 μm. The width WG may be more than 0 μm and not more than 1 μm, 1 μm or more and not more than 2 μm, 2 μm or more and not more than 4 μm, 4 μm or more and not more than 6 μm, 6 μm or more and not more than 8 μm, or 8 μm or more and not more than 10 μm. The width WG is preferably 1 μm or more and not more than 5 μm. The width WG is arbitrary, but is preferably not more than the thickness T2 of the inorganic insulating layer 30 (WG≦T2). The width WG is particularly preferably 1 μm or more and not more than 2 μm.

[0284] 14, in this embodiment, the second source inner wall 169 is formed in a curved shape recessed toward the inorganic insulating layer 30. The second source inner wall 169 defines a second source opening 173 that exposes a part of the source principal surface electrode 155. The second source opening 173 has a planar shape similar to the planar shape of the source principal surface electrode 155, and exposes an inner part of the source principal surface electrode 155. The planar shape of the second source opening 173 is arbitrary. The second source opening 173 may be defined in a polygonal shape having four sides parallel to the side surfaces 5A to 5D in a plan view.

[0285] The second source opening 173 communicates with the first source opening 167 of the inorganic insulating layer 30, and forms a source pad opening 162 between the second source opening 173 and the first source opening 167. The second source opening 173 surrounds the first source opening 167 at a distance from the first source opening 167, and exposes a part of the inorganic insulating layer 30. Specifically, the organic insulating layer 31 exposes a part of the main surface of the inorganic insulating layer 30 as a source inner peripheral edge 174 in the region between the first source opening 167 and the second source opening 173.

[0286] The width WS of the source inner periphery 174 may be more than 0 μm and not more than 10 μm. The width WS may be more than 0 μm and not more than 1 μm, 1 μm or more and not more than 2 μm, 2 μm or more and not more than 4 μm, 4 μm or more and not more than 6 μm, 6 μm or more and not more than 8 μm, or 8 μm or more and not more than 10 μm. The width WS is preferably 1 μm or more and not more than 5 μm. The width WS is arbitrary, but is preferably not more than the thickness T2 of the inorganic insulating layer 30 (WS≦T2). The width WS is particularly preferably 1 μm or more and not more than 2 μm.

[0287] In this embodiment, the second outer wall 170 of the organic insulating layer 31 is formed in a curved shape recessed toward the inorganic insulating layer 30. The second outer wall 170 is formed on the inorganic insulating layer 30 with a space inward from the side surfaces 5A to 5D, and defines a part of the dicing street 25 between the organic insulating layer 31 and the side surfaces 5A to 5D. This causes the organic insulating layer 31 to expose the peripheral portion of the main surface insulating layer 12. The second outer wall 170 may be formed in a quadrangle shape having four sides parallel to the side surfaces 5A to 5D in a plan view.

[0288] The second outer wall 170 of the organic insulating layer 31 may be formed on the main surface insulating layer 12 across the first outer wall 165 of the inorganic insulating layer 30. In this case, the second outer wall 170 of the organic insulating layer 31 defines a dicing street 25.

[0289] The angle that the second wall surface of the organic insulating layer 31 forms with the main surface of the inorganic insulating layer 30 within the organic insulating layer 31 may be 30° or more and 90° or less. The angle that the second wall surface forms with the main surface of the inorganic insulating layer 30 within the organic insulating layer 31 is preferably 45° or more and less than 90°. The angle of the second wall surface is defined by the angle that a straight line connecting the lower end and the upper end of the second wall surface forms with the main surface of the inorganic insulating layer 30.

[0290] The organic insulating layer 31 has a property of having lower adhesion to Ni compared to the inorganic insulating layer 30. The organic insulating layer 31 contains a negative-type or positive-type photosensitive resin. The organic insulating layer 31 may contain at least one of polyimide, polyamide, and polybenzoxazole. In this form, the organic insulating layer 31 contains polyimide.

[0291] The organic insulating layer 31 preferably has a thickness T3 (T2 < T3) that exceeds the thickness T2 of the inorganic insulating layer 30. The ratio T3 / T2 of the thickness T3 of the organic insulating layer 31 to the thickness T2 of the inorganic insulating layer 30 may be greater than 1 and 10 or less. The ratio T3 / T2 may be greater than 1 and 2 or less, 2 or more and 4 or less, 4 or more and 6 or less, 6 or more and 8 or less, 8 or more and 10 or less. The ratio T3 / T2 is preferably 2 or more and 6 or less.

[0292] The thickness T3 may be 1 μm or more and 50 μm or less. The thickness T3 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less. The thickness T3 is preferably 5 μm or more and 30 μm or less.

[0293] In this form, the rough surface region 39 of the first main surface electrode 21 includes the gate rough surface region 175 and the source rough surface region 176. The gate rough surface region 175 is formed on the exposed surface exposed from the gate pad opening 161 (the first gate opening 166 of the inorganic insulating layer 30) in the gate main surface electrode 153. The gate rough surface region 175 includes a depression formed in the region directly below the first gate inner wall 163. As a result, the first gate inner wall 163 includes a portion that overhangs the gate rough surface region 175.

[0294] The source rough surface region 176 is formed on the exposed surface exposed from the source pad opening 162 (the first source opening 167 of the inorganic insulating layer 30) in the source main surface electrode 155. The source rough surface region 176 includes a depression formed in the region directly below the first source inner wall 164. As a result, the first source inner wall 164 includes a portion that overhangs the source rough surface region 176.

[0295] In this embodiment, the pad electrode 40 includes a gate pad electrode 181 and a source pad electrode 182. The gate pad electrode 181 includes a first Ni plating layer 183 formed on the gate principal surface electrode 153 in the gate pad opening 161. The first Ni plating layer 183 corresponds to the Ni plating layer 41 according to the first embodiment.

[0296] The first Ni plating layer 183 covers the gate principal surface electrode 153 in the first gate opening 166, and covers the gate inner periphery 172 of the inorganic insulating layer 30 in the second gate opening 171. The first Ni plating layer 183 has an outer surface formed at a distance from the principal surface of the organic insulating layer 31 (insulating layer 24) toward the gate principal surface electrode 153. The first Ni plating layer 183 covers the organic insulating layer 31 in the second gate opening 171.

[0297] 13, the first Ni plating layer 183 specifically has a first portion 183A covering the gate principal surface electrode 153 and a second portion 183B covering the gate inner periphery 172 of the inorganic insulating layer 30. As shown in FIG.

[0298] The first portion 183A of the first Ni plating layer 183 fills the gate rough surface region 175 in the first gate opening 166 and covers the gate main surface electrode 153. The first portion 183A covers the entire first gate inner wall 163 of the inorganic insulating layer 30 and protrudes from the opening end of the first gate opening 166 toward the opening end of the second gate opening 171. The first portion 183A is connected to the first gate inner wall 163 of the inorganic insulating layer 30 and has a first connection portion extending in the thickness direction of the inorganic insulating layer 30.

[0299] The second portion 183B of the first Ni plating layer 183 is drawn out from the first portion 183A towards the organic insulating layer 31 within the second gate opening 171. The second portion 183B is formed in an arc shape that starts from the opening end of the first gate opening 166 and faces the organic insulating layer 31.

[0300] The second part 183B covers the gate inner peripheral edge 172 of the inorganic insulating layer 30 within the second gate opening 171. As a result, the second part 183B faces the gate main surface electrode 153 with the gate inner peripheral edge 172 of the inorganic insulating layer 30 interposed therebetween. The second part 183B is connected to the main surface of the inorganic insulating layer 30 and has a second connection portion extending in the width direction of the inorganic insulating layer 30.

[0301] In this form, the second part 183B further covers the second gate inner wall 168 of the organic insulating layer 31 within the second gate opening 171. The second part 183B covers the region on the inorganic insulating layer 30 side with respect to the middle portion of the second gate inner wall 168 of the organic insulating layer 31. In other words, the second part 183B covers the organic insulating layer 31 such that the exposed area of the second gate inner wall 168 (organic insulating layer 31) exceeds the hidden area of the second gate inner wall 168 (organic insulating layer 31). Thus, the first Ni plating layer 183 is formed such that the first part 183A and the second part 183B engage from different two directions with the opening end of the first gate opening 166.

[0302] The first Ni plating layer 183 has a thickness T4 (T2 < T4) that exceeds the thickness T2 of the inorganic insulating layer 30. The thickness T4 is less than the thickness T3 of the organic insulating layer 31 (T3 < T4). The thickness T4 exceeds the value (T2 + WG) obtained by adding the width WG of the gate inner peripheral edge 172 to the thickness T2 of the inorganic insulating layer 30 (T2 + WG < T4). This is the condition for the first Ni plating layer 183 to contact the second gate inner wall 168 of the organic insulating layer 31. The thickness T4 is defined by the thickness of the first Ni plating layer 183 with respect to the main surface of the gate main surface electrode 153.

[0303] The ratio T4 / T2 of the thickness T4 of the first Ni plating layer 183 to the thickness T2 of the inorganic insulating layer 30 may be greater than 1 and less than or equal to 5. The ratio T4 / T2 may be greater than 1 and less than or equal to 2, greater than or equal to 2 and less than or equal to 3, greater than or equal to 3 and less than or equal to 4, or greater than or equal to 4 and less than or equal to 5.

[0304] The thickness T4 may be 0.1 μm or more and 15 μm or less. The thickness T4 may be 0.1 μm or more and 1 μm or less, 1 μm or more and 3 μm or less, 3 μm or more and 6 μm or less, 6 μm or more and 9 μm or less, 9 μm or more and 12 μm or less, or 12 μm or more and 15 μm or less. The thickness T4 is preferably 2 μm or more and 8 μm or less.

[0305] The gate pad electrode 181 is made of a metal material different from that of the first Ni plating layer 183, and includes a first outer surface plating layer 184 that covers the outer surface of the first Ni plating layer 183 within the second gate opening 171. The first outer surface plating layer 184 corresponds to the outer surface plating layer 42 according to the first embodiment.

[0306] The first outer surface plating layer 184 has a thickness T5 (T5 < T4) less than the thickness T4 of the first Ni plating layer 183. The first outer surface plating layer 184 covers the second gate inner wall 168 of the organic insulating layer 31 within the second gate opening 171.

[0307] The first outer surface plating layer 184 has a gate terminal surface 185A that is externally connected via a conductive bonding material (for example, solder). The gate terminal surface 185A is located on the side of the first Ni plating layer 183 with respect to the main surface of the organic insulating layer 31 (the opening end of the second gate opening 171). Thereby, the first outer surface plating layer 184 exposes a part of the second gate inner wall 168 of the organic insulating layer 31.

[0308] Specifically, the first outer surface plating layer 184 has a laminated structure including a first Pd plating layer 185 and a first Au plating layer 186 laminated in this order from the side of the first Ni plating layer 183. The first Pd plating layer 185 and the first Au plating layer 186 respectively correspond to the Pd plating layer 43 and the Au plating layer 44 according to the first embodiment.

[0309] The first Pd plating layer 185 is formed in the form of a film along the outer surface of the first Ni plating layer 183. The first Pd plating layer 185 covers the first Ni plating layer 183 with a gap from the opening end of the second gate opening 171 toward the inorganic insulating layer 30. The first Pd plating layer 185 covers the second gate inner wall 168 of the organic insulating layer 31 within the second gate opening 171.

[0310] The first Pd plating layer 185 has a thickness less than the thickness T4 of the first Ni plating layer 183. The thickness of the first Pd plating layer 185 may be 0.01 μm or more and 1 μm or less. The thickness of the first Pd plating layer 185 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0311] The first Au plating layer 186 is formed in the form of a film along the outer surface of the first Pd plating layer 185. The first Au plating layer 186 covers the first Pd plating layer 185 with a gap from the opening end of the second gate opening 171 toward the inorganic insulating layer 30. The first Au plating layer 186 covers the second gate inner wall 168 of the organic insulating layer 31 within the second gate opening 171.

[0312] The first Au plating layer 186 has a thickness less than the thickness T4 of the first Ni plating layer 183. The thickness of the first Au plating layer 186 may be 0.01 μm or more and 1 μm or less. The thickness of the first Au plating layer 186 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0313] In this embodiment, an example has been described in which first outer surface plating layer 184 has a layered structure including first Pd plating layer 185 and first Au plating layer 186. However, a first outer surface plating layer 184 having a similar structure to any one of outer surface plating layers 42 according to the second to fourth embodiment examples shown in Figures 4A to 4D described above may also be employed.

[0314] The source pad electrode 182 includes a second Ni plating layer 193 formed on the source principal surface electrode 155 in the source pad opening 162. The second Ni plating layer 193 corresponds to the Ni plating layer 41 according to the first embodiment.

[0315] The second Ni plating layer 193 covers the source principal surface electrode 155 in the first source opening 167, and covers the source inner periphery 174 of the inorganic insulating layer 30 in the second source opening 173. The second Ni plating layer 193 has an outer surface formed at a distance from the principal surface of the organic insulating layer 31 (insulating layer 24) toward the source principal surface electrode 155. The second Ni plating layer 193 covers the organic insulating layer 31 in the second source opening 173.

[0316] 14, the second Ni plating layer 193 specifically has a first portion 193A covering the source principal surface electrode 155 and a second portion 193B covering the source inner periphery 174 of the inorganic insulating layer 30. As shown in FIG.

[0317] The first portion 193A of the second Ni plating layer 193 fills the source rough surface region 176 in the first source opening 167 and covers the source principal surface electrode 155. The first portion 193A covers the entire first source inner wall 164 of the inorganic insulating layer 30 and protrudes from the opening end of the first source opening 167 toward the opening end of the second source opening 173. The first portion 193A is connected to the first source inner wall 164 of the inorganic insulating layer 30 and has a first connection portion extending in the thickness direction of the inorganic insulating layer 30.

[0318] The second portion 193B of the second Ni plating layer 193 is drawn out from the first portion 193A toward the organic insulating layer 31 within the second source opening 173. The second portion 193B is formed in an arc shape extending from the opening end of the first source opening 167 toward the organic insulating layer 31.

[0319] The second portion 193B covers the source inner peripheral edge 174 of the inorganic insulating layer 30 within the second source opening 173. As a result, the second portion 193B faces the source main surface electrode 155 with the source inner peripheral edge 174 of the inorganic insulating layer 30 interposed therebetween. The second portion 193B is connected to the main surface of the inorganic insulating layer 30 and has a second connection portion extending in the width direction of the inorganic insulating layer 30.

[0320] In this configuration, the second portion 193B further covers the second source inner wall 169 of the organic insulating layer 31 within the second source opening 173. The second portion 193B covers the region on the inorganic insulating layer 30 side with respect to the middle portion of the second source inner wall 169 of the organic insulating layer 31. In other words, the second portion 193B covers the organic insulating layer 31 such that the exposed area of the second source inner wall 169 (organic insulating layer 31) exceeds the hidden area of the second source inner wall 169 (organic insulating layer 31). Thus, the second Ni plating layer 193 is formed such that the first portion 193A and the second portion 193B engage from different two directions with the opening end of the first source opening 167.

[0321] The second Ni plating layer 193 has a thickness T4 (T2 < T4) that exceeds the thickness T2 of the inorganic insulating layer 30. The thickness T4 is less than the thickness T3 of the organic insulating layer 31 (T3 < T4). The thickness T4 exceeds the value obtained by adding the width WS of the source inner peripheral edge 174 to the thickness T2 of the inorganic insulating layer 30 (T2 + WS < T4). This is the condition for the second Ni plating layer 193 to contact the second source inner wall 169 of the organic insulating layer 31. The thickness T4 is defined by the thickness of the second Ni plating layer 193 with respect to the main surface of the source main surface electrode 155.

[0322] The ratio T4 / T2 of the thickness T4 of the second Ni plating layer 193 to the thickness T2 of the inorganic insulating layer 30 may be greater than 1 and equal to or less than 5. The ratio T4 / T2 may be greater than 1 and equal to or less than 2, equal to or greater than 2 and equal to or less than 3, equal to or greater than 3 and equal to or less than 4, or equal to or greater than 4 and equal to or less than 5.

[0323] The thickness T4 may be equal to or greater than 0.1 μm and equal to or less than 15 μm. The thickness T4 may be equal to or greater than 0.1 μm and equal to or less than 1 μm, equal to or greater than 1 μm and equal to or less than 3 μm, equal to or greater than 3 μm and equal to or less than 6 μm, equal to or greater than 6 μm and equal to or less than 9 μm, equal to or greater than 9 μm and equal to or less than 12 μm, or equal to or greater than 12 μm and equal to or less than 15 μm. The thickness T4 is preferably equal to or greater than 2 μm and equal to or less than 8 μm.

[0324] The source pad electrode 182 is made of a metal material different from that of the second Ni plating layer 193, and includes a second outer surface plating layer 194 that covers the outer surface of the second Ni plating layer 193 within the second source opening 173. The second outer surface plating layer 194 corresponds to the outer surface plating layer 42 according to the first embodiment.

[0325] The second outer surface plating layer 194 has a thickness T5 (T5 < T4) less than the thickness T4 of the second Ni plating layer 193. The second outer surface plating layer 194 covers the second source inner wall 169 of the organic insulating layer 31 within the second source opening 173.

[0326] The second outer surface plating layer 194 has a source terminal surface 194A that is externally connected via a conductive bonding material (for example, solder). The source terminal surface 194A is located on the second Ni plating layer 193 side with respect to the main surface of the organic insulating layer 31 (the opening end of the second source opening 173). Thereby, the second outer surface plating layer 194 exposes a part of the second source inner wall 169 of the organic insulating layer 31.

[0327] Specifically, the second outer surface plating layer 194 has a laminated structure including a second Pd plating layer 195 and a second Au plating layer 196 laminated in this order from the second Ni plating layer 193 side. The second Pd plating layer 195 and the second Au plating layer 196 respectively correspond to the Pd plating layer 43 and the Au plating layer 44 according to the first embodiment.

[0328] The second Pd plating layer 195 is formed in the form of a film along the outer surface of the second Ni plating layer 193. The second Pd plating layer 195 covers the second Ni plating layer 193 with a gap from the opening end of the second source opening 173 toward the inorganic insulating layer 30. The second Pd plating layer 195 covers the second source inner wall 169 of the organic insulating layer 31 within the second source opening 173.

[0329] The second Pd plating layer 195 has a thickness less than the thickness T4 of the second Ni plating layer 193. The thickness of the second Pd plating layer 195 may be 0.01 μm or more and 1 μm or less. The thickness of the second Pd plating layer 195 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0330] The second Au plating layer 196 is formed in the form of a film along the outer surface of the second Pd plating layer 195. The second Au plating layer 196 covers the second Pd plating layer 195 with a gap from the opening end of the second source opening 173 toward the inorganic insulating layer 30. The second Au plating layer 196 covers the second source inner wall 169 of the organic insulating layer 31 within the second source opening 173.

[0331] The second Au plating layer 196 has a thickness less than the thickness T4 of the second Ni plating layer 193. The thickness of the second Au plating layer 196 may be 0.01 μm or more and 1 μm or less. The thickness of the second Au plating layer 196 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0332] In this embodiment, an example has been described in which second outer surface plating layer 194 has a laminated structure including second Pd plating layer 195 and second Au plating layer 196. However, second outer surface plating layer 194 having a similar structure to any one of outer surface plating layers 42 according to the second to fourth embodiment examples shown in Figures 4A to 4D described above may also be employed.

[0333] The second principal surface electrode 46 covers the entire area of ​​the second principal surface 4. The second principal surface electrode 46 forms an ohmic contact with the second principal surface 4. The second principal surface electrode 46 is formed as a drain electrode.

[0334] The second principal surface electrode 46 includes at least one of a Ti layer, a Ni layer, a Pd layer, an Au layer, and an Ag layer. The second principal surface electrode 46 may have a laminated structure in which at least two of a Ti layer, a Ni layer, a Pd layer, an Au layer, and an Ag layer are laminated in any order. The second principal surface electrode 46 may have a single layer structure consisting of a Ti layer, a Ni layer, a Pd layer, an Au layer, and an Ag layer. The second principal surface electrode 46 preferably includes a Ti layer as an ohmic electrode. In this embodiment, the second principal surface electrode 46 has a laminated structure including a Ti layer, a Ni layer, a Pd layer, an Au layer, and an Ag layer laminated in this order from the second principal surface 4 side.

[0335] As described above, the semiconductor device 101 including the MISFET instead of the SBD can achieve the same effects as those described for the semiconductor device 1.

[0336] Fig. 15 is a corresponding view to Fig. 12 and is a cross-sectional view showing a semiconductor device 201 according to a fourth embodiment of the present invention. Fig. 16 is an enlarged view of region XVI shown in Fig. 15. Fig. 17 is an enlarged view of region XVII shown in Fig. 15. In the following, structures corresponding to those described for semiconductor device 101 (see Figs. 9 to 14) are given the same reference symbols and will not be described.

[0337] 15 to 17, organic insulating layer 31 exposes gate inner periphery 172 of inorganic insulating layer 30 in a region between first gate opening 166 and second gate opening 171. Width WG of gate inner periphery 172 preferably exceeds thickness T2 of inorganic insulating layer 30 (T2 <WG)。

[0338] The ratio WG / T2 of the width WG of the gate inner periphery 172 to the thickness T2 of the inorganic insulating layer 30 may be more than 1 and not more than 10. The ratio WG / T2 may be more than 1 and not more than 2, 2 to 4, 4 to 6, 6 to 8, or 8 to 10. The ratio WG / T2 is preferably 2 to 5. The width WG may be more than 0 μm and not more than 10 μm. The width WG may be more than 0 μm and not more than 2 μm, 2 to 4 μm, 4 to 6 μm, 6 to 8 μm, or 8 to 10 μm.

[0339] The first Ni plating layer 183 is formed on the gate principal surface electrode 153 in the gate pad opening 161. The first Ni plating layer 183 covers the gate principal surface electrode 153 in the first gate opening 166, and covers the gate inner periphery 172 of the inorganic insulating layer 30 in the second gate opening 171. The first Ni plating layer 183 has an outer surface formed at a distance from the main surface of the organic insulating layer 31 (insulating layer 24) toward the gate principal surface electrode 153. The first Ni plating layer 183 covers the gate inner periphery 172 of the inorganic insulating layer 30 at a distance from the organic insulating layer 31 in the second gate opening 171.

[0340] 16, the first Ni plating layer 183 specifically has a first portion 183A covering the gate principal surface electrode 153 and a second portion 183B covering the gate inner periphery 172 of the inorganic insulating layer 30. As shown in FIG.

[0341] The first portion 183A of the first Ni plating layer 183 fills the gate rough surface region 175 in the first gate opening 166 and covers the gate main surface electrode 153. The first portion 183A covers the entire first gate inner wall 163 of the inorganic insulating layer 30 in the first gate opening 166 and protrudes from the opening end of the first gate opening 166 toward the opening end of the second gate opening 171. The first portion 183A is connected to the first gate inner wall 163 of the inorganic insulating layer 30 and has a first connection portion extending in the thickness direction of the inorganic insulating layer 30.

[0342] The second portion 183B of the first Ni plating layer 183 is drawn out from the first portion 183A towards the organic insulating layer 31 side within the second gate opening 171. The second portion 183B is formed in an arc shape that starts from the opening end of the first gate opening 166 and faces the second gate inner wall 168 of the organic insulating layer 31.

[0343] The second portion 183B covers the gate inner periphery 172 of the inorganic insulating layer 30 within the second gate opening 171. In this embodiment, the second portion 183B partially covers the gate inner periphery 172 of the inorganic insulating layer 30 within the second gate opening 171 at a distance from the second gate inner wall 168 of the organic insulating layer 31 toward the first gate inner wall 163 of the inorganic insulating layer 30 so that a part of the inner periphery 38 of the inorganic insulating layer 30 is exposed.

[0344] As a result, the first Ni plating layer 183 exposes a part of the gate inner periphery 172 of the inorganic insulating layer 30 and the entire area of ​​the second gate inner wall 168 of the organic insulating layer 31. The second portion 183B faces the gate principal surface electrode 153 across the gate inner periphery 172 of the inorganic insulating layer 30. The second portion 183B is connected to the principal surface of the inorganic insulating layer 30 and has a second connection portion extending in the width direction of the inorganic insulating layer 30.

[0345] The first Ni plating layer 183 has a thickness T4 (T2 < T4) that exceeds the thickness T2 of the inorganic insulating layer 30. The thickness T4 is less than the value (T2 + WG) obtained by adding the width WG of the gate inner periphery 172 to the thickness T2 of the inorganic insulating layer 30 (T4 < T2 + WG). This is the condition for the first Ni plating layer 183 to expose the second gate inner wall 168 of the organic insulating layer 31. The thickness T4 is defined by the thickness of the first Ni plating layer 183 with respect to the main surface of the gate main surface electrode 153.

[0346] The ratio T4 / T2 of the thickness T4 of the first Ni plating layer 183 to the thickness T2 of the inorganic insulating layer 30 may be greater than 1 and less than or equal to 5. The ratio T4 / T2 may be greater than 1 and less than or equal to 2, greater than or equal to 2 and less than or equal to 3, greater than or equal to 3 and less than or equal to 4, or greater than or equal to 4 and less than or equal to 5. The thickness T4 may be 0.1 μm or more and 10 μm or less. The thickness T4 may be 0.1 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less.

[0347] The first outer surface plating layer 184 covers the outer surface of the first Ni plating layer 183 within the second gate opening 171. The first outer surface plating layer 184 has a thickness T5 (T5 < T4) that is less than the thickness T4 of the first Ni plating layer 183. In this form, the first outer surface plating layer 184 partially covers the gate inner periphery 172 of the inorganic insulating layer 30 at a distance from the second gate inner wall 168 of the organic insulating layer 31 toward the first gate inner wall 163 of the inorganic insulating layer 30 within the second gate opening 171 so that a part of the inner periphery 38 of the inorganic insulating layer 30 is exposed.

[0348] The first outer surface plating layer 184 has a gate terminal surface 184A that is externally connected via a conductive bonding material (e.g., solder). The gate terminal surface 184A is located on the first Ni plating layer 183 side with respect to the main surface of the organic insulating layer 31 (the opening end of the second gate opening 171). As a result, the first outer surface plating layer 184 exposes a part of the gate inner periphery 172 of the inorganic insulating layer 30 and the entire second gate inner wall 168 of the organic insulating layer 31 within the second gate opening 171.

[0349] Specifically, the first outer surface plating layer 184 has a laminated structure including a first Pd plating layer 185 and a Pd plating layer 186 laminated in this order from the first Ni plating layer 183 side. The first Pd plating layer 185 is formed in the form of a film along the outer surface of the first Ni plating layer 183. The first Pd plating layer 185 covers the first Ni plating layer 183 with a gap from the opening end of the second gate opening 171 toward the inorganic insulating layer 30.

[0350] The first Pd plating layer 185 partially covers the gate inner periphery 172 of the inorganic insulating layer 30 at a distance from the second gate inner wall 168 of the organic insulating layer 31 toward the first gate inner wall 163 of the inorganic insulating layer 30 within the second gate opening 171 so that a portion of the inner periphery 38 of the inorganic insulating layer 30 is exposed. As a result, the first Pd plating layer 185 exposes a portion of the gate inner periphery 172 of the inorganic insulating layer 30 and the entire area of ​​the second gate inner wall 168 of the organic insulating layer 31 within the second gate opening 171.

[0351] The first Pd plating layer 185 has a thickness less than the thickness T4 of the first Ni plating layer 183. The thickness of the first Pd plating layer 185 may be 0.01 μm or more and 1 μm or less. The thickness of the first Pd plating layer 185 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0352] The Pd plating layer 186 is formed in the form of a film along the outer surface of the first Pd plating layer 185. The Pd plating layer 186 covers the first Pd plating layer 185 with a gap from the opening edge of the second gate opening 171 toward the inorganic insulating layer 30.

[0353] The Pd plating layer 186 partially covers the gate inner periphery 172 of the inorganic insulating layer 30 at a distance from the second gate inner wall 168 of the organic insulating layer 31 toward the first gate inner wall 163 of the inorganic insulating layer 30 within the second gate opening 171 so that a portion of the inner periphery 38 of the inorganic insulating layer 30 is exposed. As a result, the Pd plating layer 186 exposes a portion of the gate inner periphery 172 of the inorganic insulating layer 30 and the entire area of ​​the second gate inner wall 168 of the organic insulating layer 31 within the second gate opening 171.

[0354] The Pd plating layer 186 has a thickness less than the thickness T4 of the first Ni plating layer 183. The thickness of the Pd plating layer 186 may be 0.01 μm or more and 1 μm or less. The thickness of the Pd plating layer 186 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0355] In this embodiment, an example has been described in which first outer surface plating layer 184 has a laminated structure including first Pd plating layer 185 and Pd plating layer 186. However, a first outer surface plating layer 184 having a similar structure to any one of outer surface plating layers 42 according to the second to fourth embodiment examples shown in Figures 8A to 8D described above may also be employed.

[0356] The organic insulating layer 31 exposes a source inner periphery 174 of the inorganic insulating layer 30 in the region between the first source opening 167 and the second source opening 173. The width WS of the source inner periphery 174 exceeds the thickness T2 of the inorganic insulating layer 30 in this embodiment (T2 <WS)。

[0357] The ratio WS / T2 of the width WS of the gate inner periphery 172 to the thickness T2 of the inorganic insulating layer 30 may be more than 1 and not more than 10. The ratio WS / T2 may be more than 1 and not more than 2, 2 to 4, 4 to 6, 6 to 8, or 8 to 10. The ratio WS / T2 is preferably 2 to 5. The width WS may be more than 0 μm and not more than 10 μm. The width WS may be more than 0 μm and not more than 2 μm, 2 to 4 μm, 4 to 6 μm, 6 to 8 μm, or 8 to 10 μm.

[0358] The second Ni plating layer 193 is formed on the source principal surface electrode 155 in the source pad opening 162. The second Ni plating layer 193 covers the source principal surface electrode 155 in the second source opening 173, and covers the source inner periphery 174 of the inorganic insulating layer 30 in the second source opening 173. The second Ni plating layer 193 has an outer surface formed at a distance from the principal surface of the organic insulating layer 31 (insulating layer 24) toward the source principal surface electrode 155. The second Ni plating layer 193 covers the source inner periphery 174 of the inorganic insulating layer 30 at a distance from the organic insulating layer 31 in the second source opening 173.

[0359] 17, the second Ni plating layer 193 specifically has a first portion 193A covering the source principal surface electrode 155 and a second portion 193B covering the source inner periphery 174 of the inorganic insulating layer 30. As shown in FIG.

[0360] The first portion 193A of the second Ni plating layer 193 fills the source rough surface region 176 in the first source opening 167 and covers the source principal surface electrode 155. The first portion 193A covers the entire first source inner wall 164 of the inorganic insulating layer 30 in the first source opening 167 and protrudes from the opening end of the first source opening 167 toward the opening end of the second source opening 173. The first portion 193A is connected to the first source inner wall 164 of the inorganic insulating layer 30 and has a first connection portion extending in the thickness direction of the inorganic insulating layer 30.

[0361] The second part 193B of the second Ni plating layer 193 is drawn out from the first part 193A toward the organic insulating layer 31 within the second source opening 173. The second part 193B is formed in an arc shape extending from the opening end of the first source opening 167 toward the second source inner wall 169 of the organic insulating layer 31.

[0362] The second part 193B covers the source inner periphery 174 of the inorganic insulating layer 30 within the second source opening 173. In this form, the second part 193B partially covers the source inner periphery 174 of the inorganic insulating layer 30 at an interval from the second source inner wall 169 of the organic insulating layer 31 toward the first source inner wall 164 of the inorganic insulating layer 30 within the second source opening 173 so that a part of the inner periphery 38 of the inorganic insulating layer 30 is exposed.

[0363] Thereby, the second Ni plating layer 193 exposes a part of the source inner periphery 174 of the inorganic insulating layer 30 and the entire second source inner wall 169 of the organic insulating layer 31. The second part 193B faces the source main surface electrode 155 with the source inner periphery 174 of the inorganic insulating layer 30 interposed therebetween. The second part 193B is connected to the main surface of the inorganic insulating layer 30 and has a second connection portion extending in the width direction of the inorganic insulating layer 30.

[0364] The second Ni plating layer 193 has a thickness T4 (T2 < T4) that exceeds the thickness T2 of the inorganic insulating layer 30. The thickness T4 is less than the thickness T3 of the organic insulating layer 31 (T3 < T4). The thickness T4 is less than the value obtained by adding the width WS of the source inner periphery 174 to the thickness T2 of the inorganic insulating layer 30 (T4 < T2 + WS). This is the condition for the second Ni plating layer 193 to expose the second source inner wall 169 of the organic insulating layer 31. The thickness T4 is defined by the thickness of the second Ni plating layer 193 with respect to the main surface of the source main surface electrode 155.

[0365] The ratio T4 / T2 of the thickness T4 of the second Ni plating layer 193 to the thickness T2 of the inorganic insulating layer 30 may be greater than 1 and equal to or less than 5. The ratio T4 / T2 may be greater than 1 and equal to or less than 2, equal to or greater than 2 and equal to or less than 3, equal to or greater than 3 and equal to or less than 4, or equal to or greater than 4 and equal to or less than 5. The thickness T4 may be equal to or greater than 0.1 μm and equal to or less than 10 μm. The thickness T4 may be equal to or greater than 0.1 μm and equal to or less than 1 μm, equal to or greater than 1 μm and equal to or less than 2 μm, equal to or greater than 2 μm and equal to or less than 4 μm, equal to or greater than 4 μm and equal to or less than 6 μm, equal to or greater than 6 μm and equal to or less than 8 μm, or equal to or greater than 8 μm and equal to or less than 10 μm.

[0366] The second outer surface plating layer 194 covers the outer surface of the second Ni plating layer 193 within the second source opening 173. The second outer surface plating layer 194 has a thickness T5 (T5 < T4) less than the thickness T4 of the second Ni plating layer 193. In this form, the second outer surface plating layer 194 partially covers the source inner peripheral edge 174 of the inorganic insulating layer 30 at a distance from the second source inner wall 169 of the organic insulating layer 31 toward the first source inner wall 164 of the inorganic insulating layer 30 within the second source opening 173 so that a part of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed.

[0367] The second outer surface plating layer 194 has a source terminal surface 194A that is externally connected via a conductive bonding material (e.g., solder). The source terminal surface 194A is located on the second Ni plating layer 193 side with respect to the main surface of the organic insulating layer 31 (the opening end of the second source opening 173). Thereby, the second outer surface plating layer 194 exposes a part of the source inner peripheral edge 174 of the inorganic insulating layer 30 and the entire second source inner wall 169 of the organic insulating layer 31 within the second source opening 173.

[0368] Specifically, the second outer surface plating layer 194 has a laminated structure including a second Pd plating layer 195 and a second Au plating layer 196 laminated in this order from the second Ni plating layer 193 side. The second Pd plating layer 195 is formed in a film shape along the outer surface of the second Ni plating layer 193. The second Pd plating layer 195 covers the second Ni plating layer 193 at a distance from the opening end of the second source opening 173 toward the inorganic insulating layer 30 side.

[0369] The second Pd plating layer 195 partially covers the source inner periphery 174 of the inorganic insulating layer 30 at a distance from the second source inner wall 169 of the organic insulating layer 31 toward the first source inner wall 164 of the inorganic insulating layer 30 within the second source opening 173 so that a portion of the inner periphery 38 of the inorganic insulating layer 30 is exposed. As a result, the second Pd plating layer 195 exposes a portion of the source inner periphery 174 of the inorganic insulating layer 30 and the entire area of ​​the second source inner wall 169 of the organic insulating layer 31 within the second source opening 173.

[0370] The second Pd plating layer 195 has a thickness less than the thickness T4 of the second Ni plating layer 193. The thickness of the second Pd plating layer 195 may be 0.01 μm or more and 1 μm or less. The thickness of the second Pd plating layer 195 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0371] The second Au plating layer 196 is formed in the form of a film along the outer surface of the second Pd plating layer 195. The second Au plating layer 196 covers the second Pd plating layer 195 with a gap from the opening end of the second source opening 173 toward the inorganic insulating layer 30.

[0372] The second Au plating layer 196 partially covers the source inner periphery 174 of the inorganic insulating layer 30 at a distance from the second source inner wall 169 of the organic insulating layer 31 toward the first source inner wall 164 of the inorganic insulating layer 30 in the second source opening 173 so that a portion of the inner periphery 38 of the inorganic insulating layer 30 is exposed. As a result, the second Au plating layer 196 exposes a portion of the source inner periphery 174 of the inorganic insulating layer 30 and the entire area of ​​the second source inner wall 169 of the organic insulating layer 31 in the second source opening 173.

[0373] The second Au plating layer 196 has a thickness less than the thickness T4 of the second Ni plating layer 193. The thickness of the second Au plating layer 196 may be 0.01 μm or more and 1 μm or less. The thickness of the second Au plating layer 196 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0374] In this embodiment, an example has been described in which second outer surface plating layer 194 has a layered structure including second Pd plating layer 195 and second Au plating layer 196. However, second outer surface plating layer 194 having a similar structure to any one of outer surface plating layers 42 according to the second to fourth embodiment examples shown in Figures 8A to 8D described above may also be employed.

[0375] As described above, the semiconductor device 201 can also provide the same effects as those described for the semiconductor device 101. The semiconductor device 201 can also provide the same effects as those described for the semiconductor device 61.

[0376] Fig. 18 is a plan view from one side of a semiconductor package 301 in which the semiconductor device (reference numbers omitted) according to the first to fourth embodiments is incorporated. Fig. 19 is a plan view from the other side of the semiconductor package 301 shown in Fig. 18. Fig. 20 is a perspective view of the semiconductor package 301 shown in Fig. 18. Fig. 21 is an exploded perspective view of the semiconductor package 301 shown in Fig. 18. Fig. 22 is a cross-sectional view taken along line XXII-XXII shown in Fig. 18. Fig. 23 is a circuit diagram of the semiconductor package 301 shown in Fig. 18.

[0377] 18 to 23, semiconductor package 301 has a configuration called a power guard. Semiconductor package 301 includes a resin package body 302. Package body 302 is made of a mold resin including a filler (e.g., an insulating filler) and a matrix resin. The matrix resin is preferably made of an epoxy resin.

[0378] The package body 302 has a first main surface 303 (first surface) on one side, a second main surface 304 (second surface) on the other side, and side surfaces 305A to 305D connecting the first main surface 303 and the second main surface 304. The first main surface 303 and the second main surface 304 are formed in a quadrangular shape (rectangular in this embodiment) in a plan view seen from their normal direction Z.

[0379] The side surfaces 305A to 305D include a first side surface 305A, a second side surface 305B, a third side surface 305C, and a fourth side surface 305D. The first side surface 305A and the second side surface 305B extend along a first direction X and face a second direction Y intersecting the first direction X. The first side surface 305A and the second side surface 305B form a long side of the package body 302. The third side surface 305C and the fourth side surface 305D extend along the second direction Y and face the first direction X. The third side surface 305C and the fourth side surface 305D form a short side of the package body 302. The second direction Y is specifically perpendicular to the first direction X.

[0380] The semiconductor package 301 includes a first metal plate 310 disposed in a package body 302. The first metal plate 310 is disposed on the first main surface 303 side of the package body 302, and integrally includes a first heat dissipation portion 311 and a first terminal portion 312. The first heat dissipation portion 311 is disposed in the package body 302 so as to be exposed from the first main surface 303. The first heat dissipation portion 311 is formed in a rectangular shape extending along the first direction X in a plan view. The first heat dissipation portion 311 has a plan area less than the plan area of ​​the first main surface 303, and is exposed from the first main surface 303 at a distance inward from the side surfaces 305A to 305D.

[0381] First terminal portion 312 is exposed from first side surface 305A. Specifically, first terminal portion 312 extends in a strip shape from first heat dissipation portion 311 toward first side surface 305A, and penetrates first side surface 305A to be drawn out to the outside of package body 302. When a center line LC is set that crosses the center of first side surface 305A (second side surface 305B) in second direction Y, first heat dissipation portion 311 is located on the fourth side surface 305D side with respect to the center line LC.

[0382] The first terminal portion 312 has a first length L1 in the second direction Y. The width of the first terminal portion 312 in the first direction X is less than the width of the first heat dissipation portion 311 in the first direction X. The first terminal portion 312 is connected to the first heat dissipation portion 311 via a bent portion 313 that is bent from the first main surface 303 side to the second main surface 304 side within the package body 302. As a result, the first terminal portion 312 is exposed from the first side surface 305A with a gap therebetween from the first main surface 303 to the second main surface 304 side.

[0383] The semiconductor package 301 includes a second metal plate 320 disposed in the package body 302. The second metal plate 320 is disposed on the second main surface 304 side of the package body 302 with a gap therebetween from the first metal plate 310, and integrally includes a second heat dissipation section 321 and a second terminal section 322. The second heat dissipation section 321 is disposed in the package body 302 so as to be exposed from the second main surface 304. The second heat dissipation section 321 is formed in a rectangular shape extending along the first direction X in a plan view. The second heat dissipation section 321 has a plan area less than the plan area of ​​the second main surface 304, and is exposed from the second main surface 304 with a gap therebetween inward from the side surfaces 305A to 305D.

[0384] The second terminal portion 322 is exposed from the first side surface 305A. Specifically, the second terminal portion 322 extends in a strip shape from the second heat dissipation portion 321 toward the first side surface 305A, and penetrates the first side surface 305A to be drawn out to the outside of the package body 302. The second terminal portion 322 is located on the third side surface 305C side with respect to the center line LC.

[0385] In this embodiment, the second terminal portion 322 has a second length L2 in the second direction Y that is different from the first length L1 of the first terminal portion 312. The first terminal portion 312 and the second terminal portion 322 are distinguished from each other by their shapes (lengths). The second length L2 of the second terminal portion 322 may be longer than the first length L1 or may be shorter than the first length L1. Of course, the second terminal portion 322 may be formed to have the second length L2 equal to the first length L1.

[0386] The width in the first direction X of second terminal portion 322 is less than the width in the first direction X of second heat dissipation portion 321. Second terminal portion 322 is connected to second heat dissipation portion 321 via bent portion 323 that is bent from second main surface 304 side to first main surface 303 side within package body 302. As a result, second terminal portion 322 is exposed from second side surface 305B with a gap therebetween from second main surface 304 to first main surface 303 side.

[0387] The second terminal portion 322 is drawn out from a different thickness position from the first terminal portion 312 in the normal direction Z. In this embodiment, the second terminal portion 322 is formed at a distance from the first terminal portion 312 toward the second main surface 304. The second terminal portion 322 does not face the first terminal portion 312 in the first direction X.

[0388] The semiconductor package 301 includes one or more (five in this embodiment) control terminals 330 arranged in the package body 302. The multiple control terminals 330 are exposed from a second side surface 305B opposite to a first side surface 305A on which the first terminal portion 312 and the second terminal portion 322 are exposed. The multiple control terminals 330 are located on the third side surface 305C side with respect to a center line LC. The multiple control terminals 330 are located in the same straight line as the second terminal portion 322 of the second metal plate 320 in a plan view. The multiple control terminals 330 may be arranged in any manner.

[0389] The multiple control terminals 330 are each formed in a band shape extending along the second direction Y. Specifically, each of the multiple control terminals 330 includes an internal connection portion 331, an external connection portion 332, and a band-shaped portion 333. The internal connection portion 331 is disposed within the package body 302. The external connection portion 332 is disposed outside the package body 302.

[0390] The strip-shaped portion 333 extends in a strip shape from the internal connection portion 331 through the second side surface 305B toward the external connection portion 332. The strip-shaped portion 333 may have a curved portion 334 that is recessed toward the second main surface 304 in a portion located outside the package body 302. Of course, the strip-shaped portion 333 may be formed without the curved portion 334.

[0391] The multiple control terminals 330 are drawn out from thickness positions different from the first heat dissipation portion 311 and the second heat dissipation portion 321 in relation to the normal direction Z. In this embodiment, the multiple control terminals 330 are disposed in a region between the first heat dissipation portion 311 and the second heat dissipation portion 321 and spaced apart from each other.

[0392] The semiconductor package 301 includes an SBD chip 341 and a MISFET chip 342 disposed in a package body 302. The SBD chip 341 is made of one of the semiconductor devices (reference numbers omitted) according to the first and second embodiments. The MISFET chip 342 is made of one of the semiconductor devices (reference numbers omitted) according to the third and fourth embodiments.

[0393] The SBD chip 341 is disposed in a space sandwiched between the first heat dissipation portion 311 and the second heat dissipation portion 321 within the package body 302. The SBD chip 341 is disposed on the fourth side surface 305D side of the package body 302 with respect to the center line LC. The SBD chip 341 is disposed on the second heat dissipation portion 321 with the second principal surface electrode 46 facing the second heat dissipation portion 321.

[0394] The MISFET chip 342 is disposed in the space between the first heat dissipation portion 311 and the second heat dissipation portion 321 within the package body 302, spaced apart from the SBD chip 341. The MISFET chip 342 is disposed on the third side surface 305C side of the package body 302 with respect to the center line LC. The MISFET chip 342 is disposed on the second heat dissipation portion 321 with the second main surface electrode 46 facing the second heat dissipation portion 321.

[0395] The semiconductor package 301 includes a first conductive bonding material 343 and a second conductive bonding material 344. The first conductive bonding material 343 and the second conductive bonding material 344 each include solder or metal paste. The first conductive bonding material 343 is interposed between the second main surface electrode 46 of the SBD chip 341 and the second heat dissipation portion 321, and thermally, mechanically, and electrically connects the SBD chip 341 and the second heat dissipation portion 321. The second conductive bonding material 344 is interposed between the second main surface electrode 46 of the MISFET chip 342 and the second heat dissipation portion 321, and thermally, mechanically, and electrically connects the MISFET chip 342 and the second heat dissipation portion 321.

[0396] As a result, the cathode of the SBD chip 341 is electrically connected to the drain of the MISFET chip 342. In other words, the second metal plate 320 (second heat dissipation portion 321) functions as cathode and drain terminals for the SBD chip 341 and the MISFET chip 342.

[0397] The semiconductor package 301 includes a first metal spacer 351 and a second metal spacer 352. In this embodiment, the first metal spacer 351 and the second metal spacer (plate-shaped member) 352 are each made of a plate-shaped member containing copper. The second metal spacer 352 has a thickness equal to that of the first metal spacer 351.

[0398] The first metal spacer 351 is interposed between the SBD chip 341 and the first heat dissipation portion 311, and separates the first heat dissipation portion 311 from the SBD chip 341. The second metal spacer 352 is interposed between the MISFET chip 342 and the first heat dissipation portion 311, and separates the first heat dissipation portion 311 from the MISFET chip 342. In this embodiment, the first metal spacer 351 and the second metal spacer 352 are separate bodies, but the first metal spacer 351 and the second metal spacer 352 may be formed integrally.

[0399] The semiconductor package 301 includes a third conductive bonding material 353 and a fourth conductive bonding material 354. The third conductive bonding material 353 and the fourth conductive bonding material 354 each include a solder or a metal paste. The third conductive bonding material 353 and the fourth conductive bonding material 354 each are preferably made of solder.

[0400] The third conductive bonding material 353 is interposed between the pad electrode 40 of the SBD chip 341 and the first metal spacer 351, and thermally, mechanically, and electrically connects the SBD chip 341 and the first metal spacer 351. The fourth conductive bonding material 354 is interposed between the source pad electrode 182 of the MISFET chip 342 and the second metal spacer 352, and thermally, mechanically, and electrically connects the MISFET chip 342 and the second metal spacer 352.

[0401] The semiconductor package 301 includes a fifth conductive bonding material 355 and a sixth conductive bonding material 356. The fifth conductive bonding material 355 and the sixth conductive bonding material 356 each include solder or metal paste. The fifth conductive bonding material 355 is interposed between the first heat dissipation portion 311 and the first metal spacer 351, and thermally, mechanically, and electrically connects the first heat dissipation portion 311 and the first metal spacer 351. The sixth conductive bonding material 356 is interposed between the first heat dissipation portion 311 and the second metal spacer 352, and thermally, mechanically, and electrically connects the first heat dissipation portion 311 and the second metal spacer 352.

[0402] As a result, the anode of the SBD chip 341 is electrically connected to the source of the MISFET chip 342. In other words, the first metal plate 310 (first heat dissipation portion 311) functions as an anode / source terminal for the SBD chip 341 and the MISFET chip 342.

[0403] The semiconductor package 301 includes one or more (five in this embodiment) conductive wires 357. The conductive wires 357 are also called bonding wires. The conductive wires 357 may be made of gold wires, copper wires, or aluminum wires. The multiple conductive wires 357 are connected to the gate pad electrode 181 of the MISFET chip 342 and the internal connection parts 331 of the multiple control terminals 330, respectively.

[0404] As a result, the gate of the MISFET chip 342 is electrically connected to the multiple control terminals 330. That is, the multiple control terminals 330 each function as a gate terminal of the MISFET chip 342. The conductive wire 357 does not need to connect all the control terminals 330 and the gate pad electrode 181. Any of the control terminals 330 may be electrically open.

[0405] As described above, according to the semiconductor package 301, the first conductive bonding material 343 is connected to the pad electrode 40 of the SBD chip 341. As described in the first and second embodiments, the pad electrode 40 of the SBD chip 341 includes the Ni plating layer 41 and the outer surface plating layer 42. This allows the first conductive bonding material 343 to be appropriately connected to the pad electrode 40 of the SBD chip 341. Therefore, the SBD chip 341 can be appropriately connected thermally, mechanically, and electrically to the first heat dissipation section 311 and the second heat dissipation section 321.

[0406] If the SBD chip 341 does not have the organic insulating layer 31, the pad electrodes 40 and the like of the SBD chip 341 may crack or peel off due to the filler contained in the package body 302. This type of problem is called filler attack, and is one of the factors that reduce the reliability of the pad electrodes 40 and the like. Therefore, in the SBD chip 341, the organic insulating layer 31 is formed on the inorganic insulating layer 30. As a result, the organic insulating layer 31 acts as a cushion against the filler, and the pad electrodes 40 and the like can be appropriately protected from the filler attack.

[0407] Furthermore, as described in the first and second embodiments, the SBD chip 341 has a structure including an organic insulating layer 31, in which the Ni plating layer 41 is connected to the inner peripheral edge 38 of the inorganic insulating layer 30. This makes it possible to appropriately suppress cracks, peeling, and the like of the Ni plating layer 41 (outer plating layer 42) caused by filler attack.

[0408] According to the semiconductor package 301, the second conductive bonding material 344 is connected to the source pad electrode 182 of the MISFET chip 342. As described in the third and fourth embodiments, the source pad electrode 182 of the MISFET chip 342 includes the second Ni plating layer 193 and the second outer surface plating layer 194. This allows the second conductive bonding material 344 to be appropriately connected to the source pad electrode 182 of the MISFET chip 342. Therefore, the MISFET chip 342 can be appropriately thermally, mechanically, and electrically connected to the first heat dissipation portion 311 and the second heat dissipation portion 321.

[0409] If the MISFET chip 342 does not include the organic insulating layer 31, the filler contained in the package body 302 may cause cracks, peeling, and the like in the source pad electrode 182 of the MISFET chip 342. This type of problem is called filler attack, and is one factor in reducing the reliability of the source pad electrode 182, etc. Therefore, in the MISFET chip 342, the organic insulating layer 31 is formed on the inorganic insulating layer 30. As a result, the organic insulating layer 31 acts as a cushion against the filler, so that the source pad electrode 182, etc. can be appropriately protected from the filler attack.

[0410] Furthermore, as described in the third and fourth embodiments, the MISFET chip 342 has a structure including an organic insulating layer 31, in which the second Ni plating layer 193 is connected to the first source inner wall 164 of the inorganic insulating layer 30. This makes it possible to appropriately suppress cracks, peeling, and the like of the second Ni plating layer 193 (second outer surface plating layer 194) caused by filler attack. In the MISFET chip 342, the gate pad electrode 181 side can also achieve the same effects as those on the source pad electrode 182 side.

[0411] In this embodiment, an example has been described in which the semiconductor package 301 includes the SBD chip 341 and the MISFET chip 342. However, a semiconductor package 301 including only one of the SBD chip 341 and the MISFET chip 342 may also be used. A semiconductor package 301 including a plurality of SBD chips 341 and / or a plurality of MISFET chips 342 may also be used.

[0412] The present invention can be embodied in other forms.

[0413] In the third and fourth embodiments described above, when increasing the gate threshold voltage Vth is not important, the gate electrode 107 may contain n-type polysilicon doped with n-type impurities instead of p-type polysilicon. In this case, the first low resistance layer 112 made of n-type polycide is formed. With such a structure, the gate resistance can be further reduced.

[0414] In the third and fourth embodiments described above, n-type polysilicon doped with n-type impurities may be included instead of p-type polysilicon. In the third and fourth embodiments described above, a structure in which either or both of the first low-resistance layer 112 and the second low-resistance layer 131 are not formed may be adopted.

[0415] In the third and fourth embodiments described above, a p+ type collector region may be adopted instead of the n+ type drain region. With this structure, an IGBT (Insulated Gate Bipolar Transistor) can be provided instead of the MISFET. In this case, in the third and fourth embodiments described above, the "source" of the MISFET is replaced with the "emitter" of the IGBT, and the "drain" of the MISFET is replaced with the "collector" of the IGBT.

[0416] In each of the above-described embodiments, a Si chip made of a Si single crystal may be used instead of the SiC chip 2. That is, the semiconductor device (reference numbers omitted) according to each of the above-described embodiments may be a Si semiconductor device. In each of the above-described embodiments, a structure in which the conductivity type of each semiconductor portion is inverted may be used. That is, the p-type portion may be made n-type, and the n-type portion may be made p-type.

[0417] Examples of features extracted from this specification and drawings are given below. [A1] to [A20] and [B1] to [B15] below provide a semiconductor device that can improve the reliability of a Ni plating layer in a structure in which a Ni plating layer is formed on an electrode exposed from an opening in an organic insulating layer.

[0418] [A1] A semiconductor device comprising: a chip; an electrode formed on the chip; an inorganic insulating layer covering the electrode and having a first opening exposing the electrode; an organic insulating layer covering the inorganic insulating layer and having a second opening spaced apart from the first opening and surrounding the first opening, exposing an inner periphery of the inorganic insulating layer in a region between the first opening and the second opening; and a Ni plating layer covering the electrode in the first opening and covering the inner periphery of the inorganic insulating layer in the second opening.

[0419] [A2] The semiconductor device according to A1, wherein the Ni plating layer covers the organic insulating layer in the second opening.

[0420] [A3] The semiconductor device according to A2, wherein the Ni plating layer is formed at an interval from the opening end of the second opening toward the inorganic insulating layer.

[0421] [A4] The semiconductor device according to A2 or A3, wherein the Ni plating layer covers the organic insulating layer such that an exposed area of ​​the organic insulating layer in the second opening exceeds a covered area of ​​the organic insulating layer.

[0422] [A5] The semiconductor device according to any one of A2 to A4, wherein the inner periphery of the inorganic insulating layer has a width equal to or smaller than a thickness of the inorganic insulating layer.

[0423] [A6] The semiconductor device according to any one of A2 to A5, further including an outer surface plating layer covering an outer surface of the Ni plating layer in the second opening.

[0424] [A7] The semiconductor device according to A6, wherein the outer surface plating layer covers the organic insulating layer within the second opening.

[0425] [A8] The semiconductor device according to A6 or A7, wherein the outer surface plating layer covers the Ni plating layer with a gap from the opening end of the second opening toward the inorganic insulating layer.

[0426] [A9] The semiconductor device according to any one of A6 to A8, wherein the outer surface plating layer has a thickness less than a thickness of the Ni plating layer.

[0427] [A10] The semiconductor device according to A1, wherein the Ni plating layer covers the inner periphery of the inorganic insulating layer within the second opening and is spaced apart from the organic insulating layer.

[0428] [A11] The semiconductor device according to A10, wherein the Ni plating layer is formed at a distance from the opening end of the second opening toward the inorganic insulating layer.

[0429] [A12] The semiconductor device according to A10 or A11, wherein the inner periphery of the inorganic insulating layer has a width that exceeds a thickness of the inorganic insulating layer.

[0430] [A13] The semiconductor device according to any one of A10 to A12, further including an outer surface plating layer covering an outer surface of the Ni plating layer in the second opening.

[0431] [A14] The semiconductor device according to A13, wherein the outer surface plating layer covers the inner peripheral edge of the inorganic insulating layer.

[0432] [A15] The semiconductor device according to A13 or A14, wherein the outer surface plating layer covers the Ni plating layer at a distance from the organic insulating layer.

[0433] [A16] The semiconductor device according to any one of A13 to A15, wherein the outer surface plating layer covers the Ni plating layer with a gap from the opening end of the second opening toward the inorganic insulating layer.

[0434] [A17] The semiconductor device according to any one of A13 to A16, wherein the outer surface plating layer has a thickness less than a thickness of the Ni plating layer.

[0435] [A18] The semiconductor device according to any one of A1 to A17, wherein the chip is a SiC chip.

[0436] [A19] A semiconductor package comprising: a resin package body having a first surface on one side, a second surface on the other side, and a side surface; a first metal plate disposed within the package body and having a first heat dissipation portion exposed from the first surface and a first terminal portion exposed from the side surface; a second metal plate disposed within the package body at a distance from the first metal plate toward the second surface, and having a second heat dissipation portion exposed from the second surface and a second terminal portion exposed from the side surface; and the semiconductor device according to any one of A1 to A18 disposed in a space sandwiched between the first heat dissipation portion and the second heat dissipation portion within the package body.

[0437] [B1] A semiconductor device comprising: a chip; an electrode formed on the chip; an inorganic insulating layer covering the electrode and having a first opening exposing the electrode; an organic insulating layer covering the inorganic insulating layer and having a second opening spaced apart from the first opening and surrounding the first opening, exposing an inner periphery of the inorganic insulating layer in a region between the first opening and the second opening; and a Ni plating layer covering the electrode in the first opening and covering the inner periphery of the inorganic insulating layer in the second opening; The organic insulating layer has a second outer wall located more inward than a first outer wall of the inorganic insulating layer.

[0438] [B2] The semiconductor device according to B1, wherein the Ni plating layer is formed at a distance from the opening end of the second opening toward the inorganic insulating layer.

[0439] [B3] The semiconductor device according to B1 or B2, further comprising an outer surface plating layer covering an outer surface of the Ni plating layer within the second opening.

[0440] [B4] The semiconductor device according to B3, wherein the outer surface plating layer has a thickness less than a thickness of the Ni plating layer.

[0441] [B5] The semiconductor device according to any one of B1 to B4, wherein the inner periphery of the inorganic insulating layer has a width that exceeds a thickness of the inorganic insulating layer.

[0442] [B6] The semiconductor device according to any one of B1 to B5, wherein the second outer wall of the organic insulating layer is formed in a curved shape recessed toward the inorganic insulating layer.

[0443] [B7] The semiconductor device according to any one of B1 to B6, wherein the chip is a SiC chip.

[0444] [B8] The semiconductor device according to any one of B1 to B7, further comprising a transistor formed on the chip.

[0445] [B9] The semiconductor device according to B8, wherein the transistor includes a plurality of unit cells extending in a stripe shape.

[0446] [B10] The semiconductor device according to B9, wherein the transistor includes a plurality of trench gate structures extending in a stripe shape along the plurality of unit cells.

[0447] [B11] The chip has a rectangular shape in a plan view, The semiconductor device according to B10, wherein the plurality of trench gate structures extend along a short side of the chip.

[0448] [B12] The semiconductor device according to any one of B1 to B10, wherein the chip has a rectangular shape in a plan view.

[0449] [B13] The chip has a second main surface opposite to the first main surface covered by the electrode, further comprising a back electrode covering the second major surface; The semiconductor device according to any one of B1 to B12, wherein the back electrode includes a Ti layer.

[0450] [B14] The chip has a second main surface opposite to the first main surface covered by the electrode, further comprising a back electrode covering the second major surface; The semiconductor device according to any one of B1 to B12, wherein the back electrode includes a Ni layer.

[0451] [B15] A resin package body and a plate-shaped member including copper that is disposed within the package body; and the semiconductor device according to any one of B1 to B14, which is disposed in the package body; the electrodes include a source pad electrode; The plate-like member is electrically connected to the source pad electrode.

[0452] This application corresponds to Japanese Patent Application No. 2019-180861 filed with the Japan Patent Office on September 30, 2019, the entire disclosure of which is incorporated herein by reference. Although the embodiments of the present invention have been described in detail, these are merely specific examples used to clarify the technical content of the present invention, and the present invention should not be interpreted as being limited to these specific examples, and the scope of the present invention is limited only by the scope of the appended claims. [Explanation of symbols]

[0453] 1 Semiconductor device 2. SiC chip (chip) 21 1st main surface electrode (electrode) 30 Inorganic insulating layer 31 Organic insulating layer 34 First Opening 37 Second Opening 38 Inner edge of inorganic insulating layer 41 Ni plating layer 42 Outer plating layer 61 Semiconductor Devices 101 Semiconductor device 153 Gate main surface electrode (electrode) 155 Source main surface electrode (electrode) 166 First Gate Opening (First Opening) 167 First source aperture (first aperture) 171 Second Gate Opening (Second Opening) 172 Inorganic insulating layer on the inner edge of the gate 173 Second source opening (Second opening) 174 Inorganic insulating layer source inner edge 183 First Ni plating layer 184 First outer plating layer 193 Second Ni plating layer 194 Second outer plating layer 201 Semiconductor device 301 Semiconductor Package 302 Package body 303 First main surface (first surface) 304 Second main surface (Second surface) 305A side 305B side 305C side 305D side 310 1st metal plate 311 1st heat dissipation section 312 1st terminal section 320 Second metal plate 321 2nd heat dissipation section 322 2nd terminal section 341 SBD chip (semiconductor device) 342 MISFET chip (semiconductor device) 351 First metal spacer 352 Second metal spacer T2 Inorganic insulating layer thickness T4 Ni plating layer thickness T5 Outer plating thickness W Width of the inner edge of the inorganic insulating layer WG Width of the inner edge of the gate on the inorganic insulating layer WS Width of the inner edge of the inorganic insulating layer

Claims

1. A chip having a side surface; An electrode formed on the chip; an inorganic insulating layer covering the electrode and exposing the electrode through a first opening; an organic insulating layer covering the inorganic insulating layer, the organic insulating layer having a second opening with an opening end spaced apart from an opening end of the first opening, and exposing an inner peripheral edge of the inorganic insulating layer in a region between the first opening and the second opening; a Ni plating layer covering the electrode in the first opening and covering the inner periphery of the inorganic insulating layer in the second opening, the organic insulating layer has a second outer wall located inwardly of the first outer wall of the inorganic insulating layer, The second outer wall is formed along a cutting line at a distance inward from the side surface.

2. A semiconductor device as described in claim 1, wherein the first outer wall of the inorganic insulating layer is formed at a distance inward from the side surface.

3. The semiconductor device according to claim 1 , wherein the Ni plating layer is formed on a side of the inorganic insulating layer from an opening end of the second opening with a gap therebetween.

4. 4. The semiconductor device according to claim 1, further comprising an outer surface plating layer that covers an outer surface of said Ni plating layer within said second opening.

5. The semiconductor device according to claim 4 , wherein the outer surface plating layer has a thickness less than a thickness of the Ni plating layer.

6. 6. The semiconductor device according to claim 1, wherein the inner periphery of the inorganic insulating layer has a width greater than a thickness of the inorganic insulating layer.

7. 7. The semiconductor device according to claim 1, wherein the second outer wall of the organic insulating layer is formed in a curved shape recessed toward the inorganic insulating layer.

8. 8. The semiconductor device according to claim 1, wherein the chip is a SiC chip.

9. 9. The semiconductor device according to claim 1, further comprising a transistor formed on the chip.

10. The semiconductor device according to claim 9 , wherein the transistor includes a plurality of unit cells extending in a stripe shape.

11. The semiconductor device according to claim 10 , wherein the transistor includes a plurality of trench gate structures extending in a stripe shape along the plurality of unit cells.

12. The chip has a rectangular shape in a plan view, The semiconductor device according to claim 11 , wherein the trench gate structures extend along a short side of the chip.

13. 12. The semiconductor device according to claim 1, wherein the chip has a rectangular shape in a plan view.

14. the chip has a second main surface opposite to the first main surface covered by the electrode; further comprising a back electrode covering the second major surface; The semiconductor device according to claim 1, wherein the back electrode includes a Ti layer.

15. the chip has a second main surface opposite to the first main surface covered by the electrode; further comprising a back electrode covering the second major surface; The semiconductor device according to claim 1, wherein the back electrode includes a Ni layer.

16. A resin package body; a plate-shaped member including copper that is disposed within the package body; and a semiconductor device according to any one of claims 1 to 15, disposed in the package body; the electrodes include a source pad electrode; the plate-like member is electrically connected to the source pad electrode.

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