Solid-state imaging device, image reading device, and image forming device

Abstract

To prevent a deterioration in image quality of an image in a solid-state imaging apparatus that executes a rolling shutter operation to a plurality of pixels arranged side by side in a row direction.SOLUTION: A solid-state imaging apparatus has: a pixel line in which pixels are arranged along a first direction, the pixels each having a photoelectric conversion element, a floating diffusion, a transfer element transferring converted electric charges to the floating diffusion, a reset element setting the floating diffusion to a reset voltage, and a first source follower element receiving the voltage of the floating diffusion at a control terminal; an operation control unit that sets a plurality of pixel groups arranged in the first direction and each including a plurality of pixels to an active state and sequentially shifts the pixels set to the active state according to reading of pixel signals from the pixels; and a plurality of power lines that are connected with the pixel line. The pixel groups adjacent to each other are connected with power lines different from each other of the plurality of power lines.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a solid-state imaging device, an image reading device, and an image forming apparatus. [Background technology]

[0002] A solid-state imaging device mounted on a digital camera or the like has a plurality of pixels arranged two-dimensionally in the row and column directions, and captures an image of a subject using, for example, an electronic shutter that operates by a rolling shutter method. This type of solid-state imaging device reduces the number of rows that undergo a reset operation during a readout operation of a specific row, thereby reducing power consumption and reducing the variation in power supply fluctuations between rows (for example, see Patent Document 1). Summary of the Invention [Problem to be solved by the invention]

[0003] For example, a solid-state imaging device performs a rolling shutter operation on a number of pixels arranged in a row direction, sequentially driving a number of consecutive pixels to read out pixel signals from each pixel. In a rolling shutter operation, the more pixels that operate simultaneously, the more likely the power supply current is to fluctuate. If a noise component is added to the pixel signal due to the fluctuation in the power supply current, the quality of the image generated by the solid-state imaging device will deteriorate.

[0004] The disclosed technology has been made in consideration of the above-mentioned problems, and aims to suppress deterioration in image quality in a solid-state imaging device that performs a rolling shutter operation on multiple pixels arranged in a row direction. [Means for solving the problem]

[0005] In order to solve the above technical problems, a solid-state imaging device according to one aspect of the present invention includes a pixel line in which pixels are arranged along a first direction, each pixel having a photoelectric conversion element that converts received light into an electric charge, a floating diffusion, a transfer element that transfers the converted electric charge to the floating diffusion, a reset element that sets the floating diffusion to a reset voltage, and a first source follower element that receives the voltage of the floating diffusion at a control terminal; an operation control unit that sets a plurality of pixel groups obtained by dividing the pixel line into a plurality of pixel groups to an active state and sequentially shifts pixels that are set to the active state in response to reading out pixel signals from the pixels; and a plurality of power supply lines connected to the pixel line, wherein adjacent pixel groups are connected to different ones of the plurality of power supply lines. the operation control unit performs a reset read operation in which the reset voltage is read from the floating diffusion in the pixel, and in each of the plurality of pixel groups, sets the pixel group to the active state before the reset read operation of a first pixel, and the power supply line connected to the pixel group set to the active state is different from the power supply line connected to the pixel group for which the reset read is performed. It is characterized by: Effect of the Invention

[0006] In a solid-state imaging device that performs a rolling shutter operation on a plurality of pixels aligned in a row direction, degradation of image quality can be suppressed. [Brief description of the drawings]

[0007] [Figure 1] 1 is a block diagram showing an example of a solid-state imaging device according to a first embodiment of the present invention. [Diagram 2] 2 is a circuit diagram showing an example of a main part of the solid-state imaging device of FIG. 1. [Diagram 3] 2 is a timing chart showing an example of the operation of the solid-state imaging device of FIG. [Figure 4] 2 is a diagram showing an example of a transition of an active period of each pixel in the solid-state imaging device of FIG. 1. [Diagram 5] FIG. 13 is a block diagram showing an example of another solid-state imaging device. [Figure 6] 6 is a diagram illustrating an example of the influence of voltage fluctuations on the power supply lines of the solid-state imaging devices of FIGS. 1 and 5. FIG. [Figure 7] 6 is a diagram illustrating an example of the influence of voltage fluctuations in the ground lines of the solid-state imaging devices of FIGS. 1 and 5. FIG. [Figure 8] FIG. 11 is a block diagram showing an example of a solid-state imaging device according to a second embodiment of the present invention. [Figure 9] 9 is a circuit diagram showing an example of a main part of the solid-state imaging device of FIG. 8. [Figure 10] 9 is a diagram showing an example of a transition of an active period of each pixel in the solid-state imaging device of FIG. 8. FIG. [Figure 11] FIG. 11 is a block diagram showing an example of a solid-state imaging device according to a third embodiment of the present invention. [Figure 12] FIG. 13 is a block diagram showing an example of a solid-state imaging device according to a fourth embodiment of the present invention. [Figure 13] FIG. 13 is a block diagram showing an example of a solid-state imaging device according to a fifth embodiment of the present invention. [Figure 14] 14 is a block diagram showing an example of an image forming apparatus including a scanner unit in which any one of the solid-state imaging devices shown in FIGS. 1, 8, 11, 12, and 13 is mounted. FIG. [Figure 15] 10A and 10B are diagrams illustrating examples of combinations of connection specifications of power supply voltage lines and ground voltage lines in the above-described embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, the embodiments will be described with reference to the drawings. In the following, the same reference numerals as the signal names and power supply names are used for the signal lines and power supply lines, respectively. Note that in each drawing, the same components are given the same reference numerals, and duplicated explanations may be omitted.

[0009] (First embodiment) Fig. 1 is a block diagram showing an example of a solid-state imaging device according to a first embodiment of the present invention. The solid-state imaging device 10 shown in Fig. 1 has a line sensor LSNS including four pixel lines PL, each including a plurality of pixels PX (PXr, PXg, PXb, PXn) arranged along the horizontal direction of the figure. The horizontal direction (row direction) of the figure is an example of a first direction, and the vertical direction (column direction) of the figure is an example of a second direction.

[0010] Pixel PXr in the top pixel line PL in FIG. 1 senses red light, pixel PXg in the second pixel line PL senses green light, pixel PXb in the third pixel line PL senses blue light, and pixel PXn in the bottom pixel line PL senses near-infrared light. That is, pixels PXr, PXg, PXb, and Pxn detect different wavelength ranges of light. Note that in FIG. 1 and subsequent figures, if there is not enough space to indicate them, pixels PXr, PXg, PXb, and PXn are also indicated by the symbols R, G, B, and N, respectively.

[0011] Although not limited to this, the line sensor LSNS has 31 blocks BLK (BLK1-BLK31) arranged horizontally in FIG. 1. Each block BLK includes four sub-blocks SB. Therefore, the line sensor LSNS has 124 (31 blocks BLK x 4) sub-blocks SB (SB1-SB124). The blocks BLK and sub-blocks SB are arranged from left to right in FIG. 1 in ascending order of numbers. A block BLK is an example of a pixel group including a plurality of pixels PX.

[0012] Each sub-block SB has 16 pixels PXr, PXg, PXb, and PXn arranged in the horizontal direction of Fig. 1. Therefore, each block BLK has 64 pixels PXr, 64 PXg, 64 PXb, and 64 PXn. And the line sensor LSNS has 1984 pixels PXr, PXg, PXb, and PXn arranged in the horizontal direction of Fig. 1.

[0013] The solid-state imaging device 10 also has four power supply voltage lines VDD (VDD1-VDD4) connected to the power supply pad VPAD and four ground voltage lines GND (GND1-GND4) connected to the ground pad GPAD. The power supply voltage lines VDD are an example of a power supply line and a first power supply line. The ground voltage line GND is an example of a power supply line and a second power supply line.

[0014] Each block BLKm indicated by the number m is connected to a power supply voltage line VDD (m mod 4) and a ground voltage line GND (m mod 4). Here, the number m indicates any one of 1 to 31, and the symbol mod indicates a modulus operator. For example, the block BLK1 is connected to the first power supply voltage line VDD1 and the first ground voltage line GND1, which are the remainder "1" (=1 mod 4) obtained by dividing the block number "1" by "4". The block BLK30 is connected to the second power supply voltage line VDD2 and the second ground voltage line GND2, which are the remainder "2" (=30 mod 4) obtained by dividing the block number "30" by "4". Note that the number of the power supply voltage lines VDD and the ground voltage lines GND may be two or more. In the following description, when the power supply voltage line VDD and the ground voltage line GND are not distinguished from each other, the ground voltage line GND may be referred to as the power supply voltage line GND.

[0015] For example, all pixels PXr, PXg, PXb, and PXn in block BLK1 are connected to a common power supply voltage line VDD1 and a common ground voltage line GND1. All pixels PXr, PXg, PXb, and PXn in block BLK2 are connected to a common power supply voltage line VDD2 and a common ground voltage line GND2. All pixels PXr, PXg, PXb, and PXn in block BLK30 are connected to a common power supply voltage line VDD2 and a common ground voltage line GND2.

[0016] The number of power supply voltage lines VDD and the number of ground voltage lines GND are not limited to four. Even when the number of power supply voltage lines VDD is increased or decreased, the number of pixels PX to which the power supply voltage VDD is supplied from the power supply pad VPAD does not change. Also, even when the number of ground voltage lines GND is increased or decreased, the number of pixels PX to which the ground voltage line GND is supplied from the ground pad GPAD does not change.

[0017] For example, when the number of power supply voltage lines VDD is increased, the number of pixels assigned to each power supply voltage line VDD is reduced, so the power supply current flowing through each power supply voltage line VDD is reduced. This reduces the voltage drop of each power supply voltage line VDD, so the wiring width of each power supply voltage line VDD can be narrowed. Similarly, when the number of ground voltage lines GND is increased, the number of pixels assigned to each ground voltage line GND is reduced, so the ground current flowing through each ground voltage line GND is reduced. This reduces the voltage float of each ground voltage line GND, so the wiring width of each ground voltage line GND can be narrowed. Therefore, even when the number of power supply voltage lines VDD is increased, it is possible to suppress an increase in the total wiring width of the power supply voltage lines VDD. Similarly, even when the number of ground voltage lines GND is increased, it is possible to suppress an increase in the total wiring width of the ground voltage lines GND. As a result, even when the number of power supply voltage lines VDD and the number of ground voltage lines GND are increased, it is possible to suppress an increase in the circuit area of ​​the solid-state imaging device 10.

[0018] Fig. 2 is a circuit diagram showing an example of a main part of the solid-state imaging device 10 of Fig. 1. For ease of understanding, Fig. 2 shows sub-blocks SB1 and SB2 and red pixels PXr (PXr1-PXr17) included in the sub-blocks SB1 and SB2.

[0019] The configuration of the pixels PXg, PXb, PXn and the signal lines connected to the pixels PXg, PXb, PXn are the same as the configuration of the pixel PXr and the signal lines connected to the pixel PXr. That is, the line sensor LSNS has the same circuit configuration as that shown in Fig. 2 for each pixel line PL of the pixels PXg, PXb, PXn. In addition, each pixel PXr, PXg, PXb, PXn is connected to a transfer control signal line TX, a reset signal line RST, an output line OUT, and an active signal line ACT1 that are independent of each other.

[0020] The pixel PXr1 has a photodiode PD, a transfer transistor TRT, a reset transistor TRR, a floating diffusion FD, a source follower SF1, and a current source CS1. For example, the transfer transistor TRT, the reset transistor TRR, and the source follower SF1 are n-channel Metal Oxide Semiconductor (MOS) transistors.

[0021] The photodiode PD is an example of a photoelectric conversion element that converts received light into an electric charge. The transfer transistor TRT is an example of a transfer element. The reset transistor TRR is an example of a reset element. The source follower SF1 is an example of a first source follower element.

[0022] The photodiode PD has an anode connected to a ground voltage line GND1 and a cathode connected to the source of the transfer transistor TRT. The gate of the transfer transistor TRT is connected to a transfer control signal line TX and the drain of the transfer transistor TRT is connected to a floating diffusion FD. The gate of the reset transistor TRR is connected to a reset signal line RST and the drain of the transfer transistor TRT is connected to a reset voltage line VRST. The source of the reset transistor TRR is connected to the floating diffusion FD.

[0023] The gate, which is the control terminal of the source follower SF1, is connected to the floating diffusion FD, the drain of the source follower SF1 is connected to the power supply voltage line VDD1, and the source of the source follower SF1 is connected to the output line OUT. The current source CS1 is connected between the output line OUT and the ground voltage line GND1. The current source CS1 operates when the active signal ACT1 is at an active level, and stops operating when the active signal ACT1 is at an inactive level. Each pixel PXr generates a voltage corresponding to the gate voltage of the source follower SF1 on the output line OUT while the current source CS1 is operating.

[0024] The photodiode PD and the current source CS1 may be connected to different ground voltage lines GND. In this case, for example, two ground voltage lines GND11 and GND12 are wired instead of the ground voltage line GND1 in Fig. 1, and two ground voltage lines GND21 and GND22 are wired instead of the ground voltage line GND2 in Fig. 8. The same applies to the ground voltage lines GND3 and GND4.

[0025] Furthermore, the number or width of the ground voltage lines GND connected to the photodiode PD and the current source CS1 may be different from each other. When the ground voltage lines GND are separated for each of the photodiode PD and the current source CS1, the separated ground voltage lines GND may be connected to different ground pads GPAD.

[0026] The output line OUT of pixel PXr1 is connected to selection switches SWR1 and SWS1 via a selection switch SSW1 whose on / off is controlled by a selection signal SEL1. The selection switch SWR1 is turned on / off in response to a reset selection signal RSEL, and connects the selection switch SSW1 to the input of the amplifier RAMP1. The selection switch SWS1 is turned on / off in response to a signal selection signal SSEL, and connects the selection switch SSW1 to the input of the amplifier SAMP1.

[0027] The selection signal SEL1 controls the on / off of the selection switches SSW1-SSW16 connected to the output lines OUT of the 16 pixels PXr1-PXr16 in the sub-block SB1. The selection signal SEL2 controls the on / off of the 16 selection switches SSW corresponding to the sub-block SB2. And each selection signal SEL (SEL1, SEL2, ..., SEL248) controls the on / off of the 16 selection switches SSW connected to each of the corresponding 124 sub-blocks SB.

[0028] The reset selection signal RSEL controls the on / off of the selection switches SWR corresponding to all pixels PXr1-PXr1984. The signal selection signal SSEL controls the on / off of the selection switches SWS corresponding to all pixels PXr1-PXr1984. Then, for each sub-block SB, 16 reset voltages appearing on the 16 output lines OUT are transmitted to the inputs of the amplifiers RAMP (RAMP1-RAMP16). Also, for each sub-block SB, 16 signal voltages appearing on the 16 output lines OUT are transmitted to the inputs of the amplifiers SAMP (SAMP1-SAMP16).

[0029] Each amplifier RAMP (RAMP1-RAMP16) amplifies the received voltage and outputs it as a reset voltage R (R1-R16). Each amplifier SAMP amplifies the received voltage and outputs it as a signal voltage S (S1-S16). The reset voltages R1-R16 and signal voltages S1-S16 amplified by the amplifiers RAMP and SAMP, respectively, are converted to digital values ​​RD1-RD16 and SD1-SD16 by an AD conversion circuit (not shown), and then output to the operation control unit 12.

[0030] The solid-state imaging device 10 has an operation control unit 12 that controls the operation of the line sensor LSNS. The operation control unit 12 sets a predetermined number of sub-blocks SB to an active state in an overlapping manner. The operation control unit 12 receives, for each sub-block SB, the reset voltages R1-R16 and the signal voltages S1-S16 output from the pixels PXr, PXg, PXb, and PXn as digital values ​​RD1-RD16 and SD1-SD16. As illustrated in FIG. 4, for example, the number of sub-blocks SB that are overlappingly set to an active state is 16.

[0031] The operation of the line sensor LSNS will be described below. The operation described below is performed for each sub-block SB. The operation control unit 12 asserts an active signal ACT1 to be supplied to the predetermined number of sub-blocks SB in advance, and operates the current source CS1. The operation control unit 12 asserts a reset signal RST for each sub-block SB, and sets each floating diffusion FD to the voltage of the reset voltage line VRST.

[0032] Next, the operation control unit 12 turns on the selection switches SSW1-SSW16 and SWR1-SWR16 corresponding to each sub-block SB. Then, the operation control unit 12 receives the digital values ​​of the reset voltages R1-R16 output from the amplifiers RAMP1-RAMP16 via an AD converter (not shown).

[0033] Next, the operation control unit 12 asserts a transfer control signal TX for each sub-block SB, and sets each floating diffusion FD to a voltage corresponding to the photoelectric conversion by each photodiode PD. Next, the operation control unit 12 turns on the selection switches SSW1-SSW16 and SWS1-SWS16 corresponding to each sub-block SB. Then, the operation control unit 12 receives the digital values ​​of the signal voltages S1-S16 output from the amplifiers SAMP1-SAMP16 via an AD converter (not shown). The operation control unit 12 calculates the difference between the digital value of the reset voltage R and the digital value of the signal voltage S for each pixel PX, and obtains pixel data. The reset voltage R and the signal voltage S are examples of pixel signals read out from each pixel PX.

[0034] Fig. 3 is a timing diagram showing an example of the operation of the solid-state imaging device 10 of Fig. 1. The operation shown in Fig. 3 is performed based on the control by the operation control unit 12 of Fig. 2. The operation of each sub-block SB is similar to the operation described in Fig. 2. The dashed lines extending vertically in Fig. 3 indicate divisions of cycles. For example, the cycles are clock cycles of a clock used in the solid-state imaging device 10.

[0035] Although not limited to this, in the example shown in FIG. 3, the operation control unit 12 sets the reset signal RST and the transfer control signal TX to a high level for three cycles at non-overlapping timings. The high level periods of the reset signal RST and the transfer control signal TX are the on periods of the reset transistor TRR and the transfer transistor TRT, respectively. The operation control unit 12 changes the reset signal RST to a low level and then sets the selection signal SEL to a high level for one cycle. Also, the operation control unit 12 changes the transfer control signal TX to a low level and then sets the selection signal SEL to a high level for one cycle. For example, the operation control unit 12 sets the transfer control signal TX to a high level five cycles after setting the reset signal RST to a high level. Hereinafter, the changes of the reset signal RST, the transfer control signal TX, and the selection signal SEL from a low level to a high level are also referred to as assertion. The changes of the reset signal RST, the transfer control signal TX, and the selection signal SEL from a high level to a low level are also referred to as negation.

[0036] The operation control unit 12 performs a reset read operation to read a reset voltage R from the floating diffusion FD by asserting the selection signal SEL after negating the reset signal RST. The operation control unit 12 performs a signal read operation to read a signal S from the floating diffusion FD by asserting the selection signal SEL after negating the transfer control signal TX.

[0037] The operation control unit 12 starts the operation of the sub-blocks SB one cycle apart in sequence. This allows the operation control unit 12 to receive digital values ​​RD1-RD16 of the reset voltages R1-R16 and digital values ​​SD1-SD16 of the signal voltages S1-S16 of the sub-blocks SB in sequence without interruption. In addition, the operation control unit 12 amplifies the reset voltage R and the signal voltage S with different amplifiers RAMP and SAMP, so that the generation interval of the selection signal SEL for the reset voltage R and the selection signal SEL for the signal voltage S can be set to any interval.

[0038] 3, the reset selection signal RSEL in FIG. 2 is asserted together with the selection signal SEL that reads out the reset voltage R. The signal selection signal SSEL in FIG. 2 is asserted together with the selection signal SEL that reads out the signal voltage S.

[0039] 4 is a diagram showing an example of the transition of the active period of each pixel PX (PXr, PXg, PXb, PXn) of the solid-state imaging device 10 of FIG. 1. In each cycle CYC, the shaded sub-blocks SB indicate that they are in an active state. That is, the shaded sub-blocks SB indicate that the active signal ACT1 of FIG. 2 is asserted, and that the source follower SF1 of FIG. 2 is operating. As shown in FIG. 4, the solid-state imaging device 10 performs a rolling shutter operation in which the reset voltage R and the signal voltage S are read out from the pixels PX while sequentially shifting the sub-blocks SB set to the active state.

[0040] In each cycle CYC, the sub-blocks SB not shaded are in an inactive state. That is, the sub-blocks SB not shaded are in an inactive state. That is, the active signal ACT1 is negated, and the source follower SF1 is not operating. In FIG. 4, the symbol R indicates the sub-block SB that reads the reset voltage R, and the symbol S indicates the sub-block SB that reads the signal voltage S.

[0041] In this embodiment, the operation control unit 12 in FIG. 2 simultaneously sets 16 sub-blocks SB (four blocks BLK) to the active state. That is, the operation control unit 12 sets a predetermined number, 256 pixels PX, to the active state in an overlapping manner. Then, the operation control unit 12 shifts the sub-blocks SB to be set to the active state by one every cycle CYC.

[0042] Furthermore, the operation control unit 12 sets the interval between the sub-block SB that reads out the reset voltage R from the pixel PX and the sub-block SB that reads out the signal voltage S from the pixel PX to 4 blocks BLK. For example, in cycle CYC1, the operation control unit 12 reads out the reset voltage R from the sub-block SB11 and reads out the signal voltage S from the sub-block SB6. Note that the interval between the sub-block SB that reads out the reset voltage R and the sub-block SB that reads out the signal voltage S may be equal to or greater than the number of sub-blocks SB included in one block BLK minus 1.

[0043] In this way, the operation control unit 12 can differentiate the block BLK in which the reset read operation is performed from the block BLK in which the signal read operation is performed. The operation control unit 12 can read out the reset voltage R and the signal voltage S from each of the sub-blocks SB connected to different power supply voltage lines VDD and different ground voltage lines GND.

[0044] Therefore, it is possible to prevent fluctuations in the power supply voltage VDD and the ground voltage GND when the reset voltage R is read from affecting the reading of the signal voltage S. Similarly, it is possible to prevent fluctuations in the power supply voltage VDD and the ground voltage GND when the signal voltage S is read from affecting the reading of the reset voltage R. In other words, it is possible to prevent the reset voltage R and the signal voltage S from fluctuating due to power supply noise.

[0045] Furthermore, the operation control unit 12 operates the current sources CS1 up to the sub-blocks SB five blocks ahead of the sub-block SB from which the reset voltage R is being read out. The sub-block SB five blocks ahead is the sub-block SB with the larger number. Therefore, the operation control unit 12 can set each block BLK to the active state before the reset readout operation of the first pixel PX in the block BLK.

[0046] Therefore, the operation control unit 12 can separate the block BLK for performing the reset read operation from the block BLK for setting to the active state. Also, the operation control unit 12 can ensure a sufficient settling time before reading the reset voltage R from the active state of the sub-block SB. As a result, it is possible to prevent the fluctuation of the power supply voltage line VDD and the fluctuation of the ground voltage line GND that occur when the operation of the current source CS1 starts from affecting the reading of the reset voltage R. In other words, it is possible to prevent the reset voltage R from fluctuating due to power supply noise.

[0047] Furthermore, the operation control unit 12 operates the current source CS1 for the sub-blocks SB five blocks behind the sub-block SB from which the signal voltage S is being read out. The fifth sub-block SB behind is the sub-block SB with the smaller number. Therefore, after the signal readout operation of the last pixel PX in each block BLK, the operation control unit 12 can set the block BLK from the active state to the inactive state.

[0048] Therefore, the operation control unit 12 can separate the block BLK that performs the signal read operation from the block BLK that is set to the inactive state. As a result, it is possible to prevent the fluctuation of the power supply voltage line VDD and the fluctuation of the ground voltage line GND that occur when the operation of the current source CS1 is stopped from affecting the reading of the signal voltage S. In other words, it is possible to prevent the signal voltage S from fluctuating due to power supply noise.

[0049] Assume that the operation control unit 12 sets the interval between the sub-block SB that reads out the reset voltage R and the sub-block SB that reads out the signal voltage S to 2 blocks BLK. In this case, the sub-block SB that reads out the reset voltage R and the sub-block SB that reads out the signal voltage S are in the same block BLK every 4 cycles. However, compared to the case where the power supply voltage line VDD and the ground voltage line GND are not separated for each block BLK, it is possible to reduce fluctuations in the reset voltage R and the signal voltage S due to power supply noise.

[0050] Furthermore, when each block BLK has eight sub-blocks SB, the sub-block SB that reads out the reset voltage R and the sub-block SB that reads out the signal voltage S can be separated by eight blocks BLK or more to obtain the same effect as described above. Furthermore, when each block BLK has eight sub-blocks SB, the current source CS1 can be operated up to the sub-block SB that is eight blocks ahead of the sub-block SB that reads out the reset voltage R to obtain the same effect as described above. Furthermore, when each block BLK has eight sub-blocks SB, the current source CS1 can be operated up to the sub-block SB that is eight blocks behind the sub-block SB that reads out the signal voltage S to obtain the same effect as described above.

[0051] Fig. 5 is a block diagram showing an example of another solid-state imaging device. The solid-state imaging device 20 shown in Fig. 5 has the same line sensor LSNS as that in Fig. 1. However, four power supply voltage lines VDD1-VDD4 are connected to pixels R, G, B, and N of different colors, respectively. In addition, four ground voltage lines GND1-GND4 are connected to pixels R, G, B, and N of different colors, respectively. The operation of the solid-state imaging device 20 is similar to that in Figs. 3 and 4.

[0052] Fig. 6 is a diagram showing an example of the influence of voltage fluctuations of the power supply voltage line VDD of the solid-state imaging devices 10 and 20 of Fig. 1 and Fig. 5. The simulation results shown in Fig. 6 focus only on the power supply fluctuations of the power supply voltage line VDD, so for example, the wiring resistance of the ground voltage line GND is set to zero. The horizontal axis indicates the position of the pixel PX, and the vertical axis indicates the difference RS between the reset voltage R and the signal voltage S. The difference RS is the substantial signal voltage from each pixel PX.

[0053] Fig. 6 shows the change in the substantial signal voltage accompanying the fluctuation of the power supply voltage VDD when an image of a subject with zero luminance (darkness) is captured. In the simulation result of the solid-state imaging device 10 shown in Fig. 6, the substantial fluctuation of the signal voltage is 0 mV, which indicates that there is almost no voltage fluctuation of the power supply voltage line VDD.

[0054] In this way, in the solid-state imaging device 10 in which the power supply voltage line VDD is separated for each block BLK, the substantial signal voltage indicates 0 mV, which is equal to the brightness of the subject in the dark. On the other hand, in the simulation result of the solid-state imaging device 20 in which the power supply voltage line VDD is separated for each color of the pixel PX, the substantial signal voltage varies depending on the position of the pixel PX. In other words, at least one of the signal voltage S and the reset voltage R changes due to the fluctuation of the power supply voltage VDD.

[0055] Fig. 7 is a diagram showing an example of the influence of voltage fluctuations of the ground voltage line GND of the solid-state imaging devices 10 and 20 of Fig. 1 and Fig. 5. Detailed description of the same elements as in Fig. 6 is omitted. The simulation results shown in Fig. 7 focus only on the power supply fluctuations of the ground voltage line GND, so for example, the wiring resistance of the power supply voltage line VDD is set to zero.

[0056] Fig. 7 shows the change in the substantial signal voltage accompanying the fluctuation of the ground voltage GND when an image of a subject with zero luminance (darkness) is captured. The simulation result of the solid-state imaging device 10 shown in Fig. 7 shows that the substantial signal voltage fluctuation is 0 mV, and there is almost no voltage fluctuation in the ground voltage line GND.

[0057] In this way, in the solid-state imaging device 10 in which the ground voltage line GND is separated for each block BLK, the substantial signal voltage indicates 0 mV, which is equal to the brightness of the subject in the dark. On the other hand, in the simulation result of the solid-state imaging device 20 in which the ground voltage line GND is separated for each color of the pixel PX, the substantial signal voltage varies depending on the position of the pixel PX. That is, at least one of the signal voltage S and the reset voltage R varies with the fluctuation of the ground voltage GND.

[0058] As described above, in the first embodiment, adjacent blocks BLK are connected to different power supply voltage lines VDD and different ground voltage lines GND, thereby preventing fluctuations in the reset voltage R and the signal voltage S due to power supply noise. As a result, in a solid-state imaging device 10 that performs a rolling shutter operation on a plurality of pixels PX arranged in a row direction, deterioration of image quality can be suppressed. Even in a solid-state imaging device 10 in which pixels PXr, PXg, PXb, and PXn of different colors are arranged in a column direction, fluctuations in the reset voltage R and the signal voltage S due to power supply noise can be prevented.

[0059] By separating the sub-blocks SB that read out the reset voltage R and the signal voltage S by a predetermined number of blocks BLK or more, it is possible to prevent fluctuations in the power supply voltage VDD and the ground voltage GND when the reset voltage R is read out from affecting the reading of the signal voltage S. Similarly, it is possible to prevent fluctuations in the power supply voltage VDD and the ground voltage GND when the signal voltage S is read out from affecting the reading of the reset voltage R.

[0060] By operating the current source CS1 up to the sub-block SB a predetermined number ahead of the sub-block SB from which the reset voltage R is being read, the block BLK in which the reset read operation is performed can be separated from the block BLK set to the active state. Also, a sufficient settling time can be ensured from the active state of the sub-block SB until the reset voltage R is read out. As a result, it is possible to prevent the fluctuations in the power supply voltage line VDD and the ground voltage line GND that occur when the operation of the current source CS1 starts from affecting the reading of the reset voltage R.

[0061] By operating the current source CS1 up to the sub-block SB that is a predetermined number behind the sub-block SB from which the signal voltage S is being read, the block BLK that performs the signal read operation can be separated from the block BLK that is set to the inactive state. As a result, it is possible to prevent the fluctuations in the power supply voltage line VDD and the ground voltage line GND that occur when the operation of the current source CS1 is stopped from affecting the reading of the signal voltage S. In other words, it is possible to prevent the signal voltage S from fluctuating due to power supply noise.

[0062] Even when the number of power supply voltage lines VDD increases, the total wiring width of the power supply voltage lines VDD can be prevented from increasing. Similarly, even when the number of ground voltage lines GND increases, the total wiring width of the ground voltage lines GND can be prevented from increasing. As a result, even when the number of power supply voltage lines VDD and the number of ground voltage lines GND increase, the increase in the circuit area of ​​the solid-state imaging device 10 can be prevented.

[0063] Second Embodiment FIG. 8 is a block diagram showing an example of a solid-state imaging device according to a second embodiment of the present invention. The same elements as those in FIG. 1 are given the same reference numerals, and detailed description thereof will be omitted. In the solid-state imaging device 10A shown in FIG. 8, two ground voltage lines GND (GND1, GND2) are connected to a ground pad GPAD. A plurality of block pairs each consisting of an odd-numbered block BLK and an even-numbered block BLK adjacent to each other are alternately connected to the ground voltage line GND1 and the ground voltage line GND2. Each block BLK is an example of a first pixel group each including a plurality of pixels PX. A block pair consisting of two adjacent blocks BLK is an example of a second pixel group including pixels PX equal to or greater than the number of pixels in the first pixel group.

[0064] The block BLK31 is connected to the ground voltage line GND2. In the solid-state imaging device 10A, the configuration other than the wiring structure of the ground voltage lines GND1 and GND2 is the same as that in FIG. 1, except that the structure of the pixels PX of the line sensor LSNS is different. Note that the number of the power supply voltage lines VDD and the ground voltage lines GND may be two or more.

[0065] Fig. 9 is a circuit diagram showing an example of a main part of the solid-state imaging device of Fig. 8. The same elements as those in Fig. 2 are given the same reference numerals, and detailed description will be omitted. In each pixel PX of the line sensor LSNS shown in Fig. 9, a source follower SF2 and a current source CS2 are added to the pixel PX shown in Fig. 2. The source follower SF2 is an example of a second source follower element.

[0066] Furthermore, the solid-state imaging device 10A has an operation control unit 12A instead of the operation control unit 12 of FIG. 2. The operation control unit 12A has the same functions as the operation control unit 12 of FIG. 2, except for the addition of a function of generating an active signal ACT2. The circuit connected to the output line OUT is the same as that of FIG. 2. The operation timing of the solid-state imaging device 10A is the same as that of FIG. 3. Note that the solid-state imaging device 10A may have a pixel PX having a circuit configuration having one source follower SF1 the same as that of FIG. 2.

[0067] In the sub-block SB1, the source of the source follower SF1 is connected to the current source CS1 and the gate of the source follower SF2. The drain of the source follower SF2 is connected to the power supply voltage line VDD1, and the source of the source follower SF2 is connected to the current source CS2 and the output line OUT. The current source CS2 is connected between the output line OUT and the ground voltage line GND1, and operates according to the active signal ACT2. Note that the selection switch SSW (SSW1-SSW17) may be disposed in each pixel PXr (PXr1-PXr17). In this case, the selection switch SSW is disposed between the source of the source follower SF1 and the gate of the source follower SF2.

[0068] In this embodiment, the source followers SF1 and SF2 of each block BLK are connected to the same power supply voltage line VDD (e.g., VDD1) and to the same ground voltage line GND (e.g., GND1). Also, the source followers SF1 and SF2 of different blocks BLK are connected to different power supply voltage lines VDD (e.g., VDD1 and VDD2) and to different ground voltage lines GND (e.g., GND1 and GND2).

[0069] However, in each block BLK, the source followers SF1 and SF2 may be connected to different power supply voltage lines VDD. In this case, for example, two power supply voltage lines VDD11 and VDD12 are wired in place of the power supply voltage line VDD1 in FIG. 8, and two power supply voltage lines VDD21 and VDD22 are wired in place of the power supply voltage line VDD2 in FIG. 8. The same applies to the power supply voltage lines VDD3 and VDD4. Furthermore, the number or wiring width of the power supply voltage lines VDD connected to each of the source followers SF1 and SF2 may be different.

[0070] Also, the source followers SF1 and SF2 may be connected to different ground voltage lines GND. In this case, for example, two ground voltage lines GND11 and GND12 are wired instead of the ground voltage line GND1 in Fig. 8, and two ground voltage lines GND21 and GND22 are wired instead of the ground voltage line GND2 in Fig. 8. Furthermore, the number or wiring width of the ground voltage lines GND connected to the source followers SF1 and SF2 may be different.

[0071] Furthermore, in each block BLK, the source followers SF1, SF2 and the photodiode PD may be connected to different ground voltage lines GND (for example, GND11, GND12, and GND13, not shown).

[0072] Furthermore, when the power supply voltage line VDD is separated for each element such as the source followers SF1, SF2, the separated power supply voltage lines VDD may be connected to different power supply pads VPAD. Similarly, when the ground voltage line GND is separated for each element such as the source followers SF1, SF2, the separated ground voltage lines GND may be connected to different ground pads GPAD.

[0073] 8 are connected to a mutually independent transfer control signal line TX, reset signal line RST, output line OUT, and active signal lines ACT1 and ACT2. The operation control unit 12A operates the current sources CS1 and CS2 for each pixel PX using the active signals ACT1 and ACT2, thereby operating the source followers SF1 and SF2. The source follower SF2 receives an output signal from the source follower SF1 at its gate, and generates a voltage in the output line OUT according to a change in the gate voltage.

[0074] Fig. 10 is a diagram showing an example of the transition of the active period of each pixel of the solid-state imaging device of Fig. 8. Detailed description of the same operations as in Fig. 4 will be omitted. The transition of the active range of the source follower SF1 is the same as in Fig. 4. The transition of the active range of the source follower SF2 is irregular compared to the transition of the active range of the source follower SF1.

[0075] The operation control unit 12A does not change the active range of the source follower SF2 until the pixel PX from which the signal voltage S is read out moves out of the next block BLK. In other words, the operation control unit 12A maintains the active state up to the block BLK immediately preceding the block BLK including the pixel PX from which the signal voltage S is read out.

[0076] For example, in cycles CYC1, CYC2, and CYC3, the operation control unit 12A does not change the active range of the source follower SF2 because it reads out the signal voltage S from block BLK2. The operation control unit 12A shifts the active range of the source follower SF2 by two sub-blocks SB in each of cycles CYC4 and CYC5 after changing the pixel PX from which the signal voltage S is read out to block BLK3. In this way, the operation control unit 12A shifts the active range of the source follower SF1 by 16 pixels, while shifting the active range of the source follower SF2 by 32 pixels.

[0077] In cycles CYC5, CYC6, and CYC7, the operation control unit 12A does not change the active range of the source follower SF2 because the signal voltage S is read from the next block BLK3. In each of cycles CYC8 and CYC9 after the pixel PX from which the signal voltage S is read is changed to block BLK4, the operation control unit 12A shifts the active range of the source follower SF2 by two sub-blocks SB. In subsequent operations, the operation control unit 12A performs the same operations as those described above in FIG. 10. The voltage fluctuation characteristics of the power supply voltage lines VDD and GND of the solid-state imaging device 10A are the same as those in FIG. 6 and FIG. 7.

[0078] As described above, the second embodiment can also provide the same effects as the first embodiment. Furthermore, in the second embodiment, in the solid-state imaging device 10A that performs the rolling shutter operation on a plurality of pixels PX having two source followers SF1 and SF2, degradation of image quality can be suppressed.

[0079] (Third embodiment) Fig. 11 is a block diagram showing an example of a solid-state imaging device according to a third embodiment of the present invention. The same elements as those in Fig. 1 are given the same reference numerals, and detailed description thereof will be omitted. The solid-state imaging device 10B shown in Fig. 11 has a line sensor LSNS including 31 blocks BLK, similar to Fig. 1. Note that the line sensor LSNS may have a source follower SF2 and a current source CS2, as shown in Fig. 9.

[0080] In the solid-state imaging device 10B in Fig. 11, the power supply pad VPAD and the four power supply voltage lines VDD1-VDD4 are connected by three relay power supply voltage lines extending in the vertical direction in Fig. 11. For example, the relay power supply voltage lines are formed using a first wiring layer, and the power supply voltage lines VDD1-VDD4 are formed using a second wiring layer different from the first wiring layer. The power supply voltage lines connecting the power supply voltage lines VDD1-VDD4 to each block BLK of the line sensor LSNS are formed using the first wiring layer.

[0081] The ground pad GPAD and the four ground voltage lines GND1-GND4 are connected by three relay ground voltage lines extending in the vertical direction of Fig. 11. For example, the relay ground voltage lines are formed using a first wiring layer, and the ground voltage lines GND1-GND4 are formed using a second wiring layer different from the first wiring layer. The ground voltage lines connecting the ground voltage lines GND1-GND4 to each block BLK of the line sensor LSNS are formed using the first wiring layer.

[0082] The black square marks on the power supply voltage lines VDD1-VDD4 and the ground voltage lines GND1-GND4 indicate contacts provided between the first wiring layer and the second wiring layer. The number of power supply voltage lines VDD and ground voltage lines GND may be two or more. The voltage fluctuation characteristics of the power supply voltage lines VDD and GND of the solid-state imaging device 10B are the same as those in FIGS. 6 and 7.

[0083] As described above, the third embodiment can also provide the same effects as the first and second embodiments. Furthermore, in the third embodiment, the power supply pad VPAD and the power supply voltage lines VDD1-VDD4 are connected by a plurality of relay power supply voltage lines. Also, the ground pad GPAD and the ground voltage lines GND1-GND4 are connected by a plurality of relay ground voltage lines. This can improve the degree of freedom of wiring of the power supply voltage lines VDD1-VDD4 and the ground voltage lines GND1-GND4.

[0084] (Fourth embodiment) Fig. 12 is a block diagram showing an example of a solid-state imaging device according to a fourth embodiment of the present invention. The same elements as those in Fig. 1 are given the same reference numerals, and detailed description thereof will be omitted. The solid-state imaging device 10C shown in Fig. 12 has a line sensor LSNS including 31 blocks BLK, similar to Fig. 1. Note that the line sensor LSNS may have a source follower SF2 and a current source CS2, as shown in Fig. 9.

[0085] In the solid-state imaging device 10C of FIG. 12, the power supply voltage lines VDD1-VDD4 and the ground voltage lines GND1-GND4 extending in the horizontal direction of the figure are formed using multiple wiring layers. The power supply voltage lines VDD1-VDD4 of the multiple layers extending in the horizontal direction of the figure are connected to each other via contacts. The ground voltage lines GND1-GND4 of the multiple layers extending in the horizontal direction of the figure are connected to each other via contacts. The number of the power supply voltage lines VDD and the ground voltage lines GND may be two or more. The characteristics of the voltage fluctuations of the power supply voltage lines VDD and the ground voltage lines GND of the solid-state imaging device 10C are similar to those of FIG. 6 and FIG. 7.

[0086] As described above, the fourth embodiment can also provide the same effects as the first to third embodiments. Furthermore, in the fourth embodiment, the power supply voltage lines VDD1-VDD4 and the ground voltage lines GND1-GND4 are formed using a plurality of wiring layers, so that the power supply resistance can be reduced and power supply noise can be reduced. This can reliably prevent fluctuations in the reset voltage R and the signal voltage S due to power supply noise.

[0087] Fifth embodiment Fig. 13 is a block diagram showing an example of a solid-state imaging device according to a fifth embodiment of the present invention. The same elements as those in Fig. 1 are given the same reference numerals, and detailed description thereof will be omitted. The solid-state imaging device 10D shown in Fig. 13 has a line sensor LSNS including 31 blocks BLK, similar to Fig. 1. Note that the line sensor LSNS may have a source follower SF2 and a current source CS2, as shown in Fig. 9.

[0088] The power supply voltage lines VDD1-VDD4 of the solid-state imaging device 10D in FIG. 13 are connected to different power supply pads VPAD. The ground voltage lines GND1-GND4 of the solid-state imaging device 10D are connected to different ground pads GPAD. The power supply voltage lines VDD1-VDD4 and the ground voltage lines GND1-GND4 extending in the horizontal direction of the figure may be formed using multiple wiring layers and connected via contacts, as in FIG. 12. The number of the power supply voltage lines VDD1 and the ground voltage lines GND may be two or more. The voltage fluctuation characteristics of the power supply voltage lines VDD and the ground voltage lines GND of the solid-state imaging device 10D are the same as those of FIG. 6 and FIG. 7.

[0089] As described above, the fifth embodiment can also provide the same effects as the first embodiment. Furthermore, in the fifth embodiment, by connecting the power supply voltage lines VDD1-VDD4 to different power supply pads VPAD, it is possible to prevent the power supply noise of each power supply voltage line VDD from sneaking into the other power supply voltage lines VDD. Furthermore, by connecting the ground voltage lines GND1-GND to different ground pads GPAD, it is possible to prevent the power supply noise of each ground voltage line GND from sneaking into the other ground voltage lines GND.

[0090] Fig. 14 is a block diagram showing an example of an image forming apparatus including a scanner unit in which any of the solid-state imaging devices shown in Fig. 1, Fig. 8, Fig. 11, Fig. 12, and Fig. 13 is mounted. The image forming apparatus 100 shown in Fig. 14 is an MFP (Multi-Function Peripheral) having a copy function, a printer function, a scanner function, a fax function, etc., and is a so-called multifunction machine. Hereinafter, the image forming apparatus 100 will be referred to as MFP 100.

[0091] The MFP 100 has a controller 110, a short-range communication circuit 120, an engine control unit 130, an operation panel 140, and a network I / F 150. The controller 110 has a CPU 101, which is the main part of the computer, a system memory (MEM-P) 102, a north bridge (NB) 103, a south bridge (SB) 104, and an ASIC (Application Specific Integrated Circuit) 106.

[0092] The controller 110 also includes a local memory (MEM-C) 107, a hard disk drive (HDD) controller 108, and a hard disk (HD) 109. The controller 110 includes an accelerated graphics port (AGP) bus 121 that interconnects the NB 103 and the ASIC 106. The configuration of the controller 110 is not limited to the configuration shown in FIG. 14. For example, the CPU 101, the NB 103, and the SB 104 may be realized by a system on chip (SoC). In this case, the controller 110 may include a PCI-express (registered trademark) bus that interconnects the SoC and the ASIC 106.

[0093] The CPU 101 performs overall control of the MFP 100. The NB 103 is a bridge that connects the CPU 101 with the MEM-P 102, the SB 104, and the AGP bus 121. The NB 103 may include a memory controller that controls reading and writing from and to the MEM-P 102, a PCI (Peripheral Component Interconnect) master, and an AGP target.

[0094] The MEM-P102 has a ROM 102a in which programs and data for implementing the various functions of the controller 110 are stored. The MEM-P102 also has a RAM 102b in which the programs and data are expanded and which is used as a drawing memory during memory printing. The programs stored in the RAM 102b may be read from a computer-readable recording medium such as a CD-ROM, CD-R, or DVD. In this case, the programs stored in the recording medium are files in a format that can be installed in the MEM-P102 or files in an executable format.

[0095] The SB 104 is a bridge for connecting the NB 103 to a PCI device or a peripheral device. The ASIC 106 is an IC for image processing that has hardware elements for image processing. The ASIC 106 has a bridge function for connecting the AGP bus 121, the PCI bus 122, the HDD controller 108, and the MEM-C 107.

[0096] For example, the ASIC 106 has a PCI target, an AGP master, and an arbiter (ARB) which is the core of the ASIC 106. The ASIC 106 has a memory controller which controls the MEM-C 107, and a plurality of DMACs (Direct Memory Access Controllers) which rotate image data by hardware logic or the like. The ASIC 106 also has a PCI unit which transfers data between the scanner unit 131 and the printer unit 132 via the PCI bus 122. The ASIC 106 may be connected to a Universal Serial Bus (USB) interface or an Institute of Electrical and Electronics Engineers 1394 (IEEE1394) interface.

[0097] The MEM-C 107 is a local memory used as a copy image buffer and a code buffer. The HD 109 stores image data, font data used during printing, and forms. The CPU 101 controls the HD 109 to read data from or write data to the HD 109.

[0098] The AGP bus 121 is a bus interface for a graphics accelerator card proposed to speed up graphic processing. The AGP bus 121 can access the graphics accelerator card at high speed by directly accessing the MEM-P 102 at high throughput. The short-range communication circuit 120 is a communication circuit such as NFC or Bluetooth (registered trademark), and is connected to the short-range communication circuit 120a.

[0099] The engine control unit 130 has a scanner unit 131 including the line sensor LSNS shown in FIG. 2 or FIG. 9, and a printer unit 132. The controller 110 performs overall control of the MFP 100. The scanner unit 131 is an example of an image reading device. For example, the controller 110 controls drawing of images, communication, input of information from an operation panel 140, and the like. The scanner unit 131 or the printer unit 132 has an image processing function such as error diffusion or gamma conversion.

[0100] MFP 100 can sequentially switch among document box function, copy function, printer function, and facsimile function using the application switching key on operation panel 140. When the document box function is selected, the mode becomes document box mode. When the copy function is selected, the mode becomes copy mode. When the printer function is selected, the mode becomes printer mode. When the facsimile mode is selected, the mode becomes facsimile mode.

[0101] Operation panel 140 has display unit 104a including an LCD (Liquid Crystal Display) that displays various information and LEDs (Light Emitting Diodes) that display operating states by turning them on and off. Operation panel 140 also has input unit 140b having a touch panel and hard key switches. Operation panel 140 having a touch panel does not necessarily have to have hard key switches. Although operation panel 140 is connected to ASIC 106 in FIG. 14, it may be connected to SB 104.

[0102] The network I / F 150 is an interface that performs data communication using a communication network (not shown). The short-range communication circuit 120 and the network I / F 150 are connected to the ASIC 106 via a PCI bus 122.

[0103] It should be noted that the device in which the line sensor LSNS is mounted is not limited to the MFP 100. For example, the line sensor LSNS may be mounted in a copy machine having only a copy function, a scanner device having only a scanner function, or a facsimile. The line sensor LSNS shown in Fig. 1 and Fig. 8 has pixels PX of multiple colors, but may be a monochrome line sensor having only single-color pixels PX in a horizontal row.

[0104] Fig. 15 is a diagram showing an example of a combination of connection specifications of the power supply voltage line VDD and the ground voltage line GND in the above-mentioned embodiment. The VDD wiring shown in Fig. 15 indicates the power supply voltage line VDD wired in the horizontal direction in Figs. 1, 8, 11, 12, and 13. The GND wiring indicates the ground voltage line GND wired in the horizontal direction in Figs. 1, 8, 11, 12, and 13.

[0105] 15, the VDD1 line indicates the power supply voltage line VDD connected to the source follower SF1, and the VDD2 line indicates the power supply voltage line VDD connected to the source follower SF2. The GND1 line indicates the ground voltage line GND connected to the source follower SF1, and the GND2 line indicates the ground voltage line GND connected to the source follower SF2.

[0106] In FIG. 15, the individual wiring shown for the VDD wiring indicates that any one of multiple power supply voltage lines VDD is individually connected to multiple blocks BLK. The common wiring shown for the VDD wiring indicates that one power supply voltage line VDD is commonly connected to multiple blocks BLK. The individual wiring shown for the GND wiring indicates that any one of multiple ground voltage lines GND is individually connected to multiple blocks BLK. The common wiring shown for the GND wiring indicates that one ground voltage line GND is commonly connected to multiple blocks BLK.

[0107] The individual wiring shown in the VDD1 wiring indicates that one of the multiple power supply voltage lines VDD1 is individually connected to multiple blocks BLK, and the power supply voltage line VDD1 is connected to the source follower SF1. The common wiring shown in the VDD1 wiring indicates that the power supply voltage line VDD1 is commonly connected to multiple blocks BLK, and the power supply voltage line VDD1 is commonly connected to the source follower SF1.

[0108] The individual wiring shown in the VDD2 wiring indicates that one of the multiple power supply voltage lines VDD2 is individually connected to multiple blocks BLK, and the power supply voltage line VDD2 is connected to the source follower SF2. The common wiring shown in the VDD2 wiring indicates that the power supply voltage line VDD2 is commonly connected to multiple blocks BLK, and the power supply voltage line VDD2 is commonly connected to the source follower SF2.

[0109] The individual wiring shown in the GND1 wiring indicates that any one of the multiple ground voltage lines GND1 is individually connected to the multiple blocks BLK and the ground voltage line GND1 is connected to the source follower SF1. The common wiring shown in the GND1 wiring indicates that the ground voltage line GND1 is commonly connected to the multiple blocks BLK and commonly connected to the source follower SF1.

[0110] The individual wiring shown in the GND2 wiring indicates that any of the multiple ground voltage lines GND2 are individually connected to the multiple blocks BLK and the ground voltage line GND2 is connected to the source follower SF2. The common wiring shown in the GND2 wiring indicates that the ground voltage line GND2 is commonly connected to the multiple blocks BLK and commonly connected to the source follower SF2.

[0111] Although the present invention has been described above based on the embodiments, the present invention is not limited to the requirements shown in the above embodiments. These points can be changed without departing from the spirit of the present invention, and can be appropriately determined according to the application form. [Explanation of symbols]

[0112] 10, 10A, 10B, 10C, 10D Solid-state imaging device 12 Motion control section 20 Solid-state imaging device 100 Image forming device 110 Controller 120 Near field communication circuit 130 Engine control unit 131 Scanner section 132 Printer section 140 Operation Panel ACT1, ACT2 active signal lines BLK Block CS1, CS2 current source FD Floating Diffusion GND, GND1-GND4 Ground voltage lines GPAD Grounding Pad LSNS Line Sensor OUT Output line PD Photodiode PL pixel line PX, PXb, PXg, PXn, PXr pixels R Reset voltage RAMP Amplifier RSEL Reset selection signal RST Reset signal S Signal Voltage SAMP Amplifier SB Sub-block SEL1, SEL2 selection signals SF1, SF2 Source Follower SSEL signal selection signal SSW, SWR, SWS selection switch TRR Reset Transistor TRT Transfer transistor TX Transfer control signal VDD, VDD1-VDD4 power supply voltage lines VPAD Power Pad VRST Reset voltage line [Prior art documents] [Patent documents]

[0113] [Patent Document 1] JP 2016-029757 A

Claims

1. a pixel line in which pixels are arranged along a first direction, each pixel having a photoelectric conversion element that converts received light into an electric charge, a floating diffusion, a transfer element that transfers the converted electric charge to the floating diffusion, a reset element that sets the floating diffusion to a reset voltage, and a first source follower element that receives the voltage of the floating diffusion at a control terminal; an operation control unit that sets a plurality of pixel groups arranged in the first direction, each of which includes a plurality of the pixels, to an active state, and sequentially shifts the pixels that are set to the active state in response to readout of pixel signals from the pixels; a plurality of power lines connected to the pixel lines; adjacent pixel groups are connected to different power supply lines among the plurality of power supply lines; The operation control unit performs a reset read operation in which the reset voltage is read from the floating diffusion in the pixel, and sets the pixel group to the active state in each of the plurality of pixel groups before the reset read operation of a first pixel; The power supply line connected to the pixel group set to the active state is different from the power supply line connected to the pixel group for which the reset readout is performed. A solid-state imaging device comprising:

2. a plurality of pixel lines each having a different wavelength range for detecting light and arranged in a second direction intersecting the first direction; In the plurality of pixel lines, the pixel groups arranged in the second direction are connected to a common power supply line.

2. The solid-state imaging device according to claim 1,

3. the operation control unit performs, at a time interval, the reset readout operation and a signal readout operation of reading out a signal voltage from the floating diffusion to which the converted electric charge has been transferred, in the pixel; The pixel group for which the reset readout operation is performed and the pixel group for which the signal readout operation is performed are different from each other.

3. The solid-state imaging device according to claim 1, wherein:

4. The operation control unit sets each of the plurality of pixel groups from the active state to an inactive state after the signal readout operation of the last pixel in the plurality of pixel groups.

4. The solid-state imaging device according to claim 3,

5. a second source follower element that operates in response to an output signal from the first source follower element; the operation control unit sets the plurality of pixel groups arranged in the pixel line in the first direction to an active state, and sequentially shifts the pixels to be set to the active state in response to readout of the pixel signals from the second source follower elements; In each of the plurality of pixel groups, the first source follower element and the second source follower element are connected to the same power supply line; The first source follower element and the second source follower element of any one of the plurality of pixel groups and the first source follower element and the second source follower element of a pixel group adjacent to any one of the plurality of pixel groups are connected to different power supply lines.

3. The solid-state imaging device according to claim 1, wherein:

6. the plurality of power supply lines include a plurality of first power supply lines and a plurality of second power supply lines; the pixels of the pixel line are included in a plurality of first pixel groups each including a plurality of pixels, and a plurality of second pixel groups each including a number of pixels equal to or greater than the number of pixels of the first pixel groups; the first pixel groups adjacent to each other are connected to different first power lines; The second pixel groups adjacent to each other are connected to different second power lines.

6. The solid-state imaging device according to claim 1, wherein:

7. the first power supply lines are power supply voltage lines, The plurality of second power supply lines are ground voltage lines.

7. The solid-state imaging device according to claim 6,

8. The solid-state imaging device according to any one of claims 1 to 7 is provided. An image reading device comprising:

9. The solid-state imaging device according to any one of claims 1 to 7 is provided. An image forming apparatus comprising:

Images