Quantum bit, quantum computing device, and method for manufacturing quantum bit

Abstract

This quantum bit has: an s-wave superconductor layer; a higher-order topological insulator layer provided on the s-wave superconductor layer; a first ferromagnetic insulator layer provided on the higher-order topological insulator layer; and, a first gate electrode provided on the first ferromagnetic insulator layer. The higher-order topological insulator layer has: a first region provided with a first hinge helical channel; and, a second region provided with a second hinge helical channel that is separated from the first hinge helical channel. The first ferromagnetic insulator layer covers the first hinge helical channel and the second hinge helical channel.

Description

[Technical field]

[0001] The present disclosure relates to quantum bits, quantum processing devices, and methods for making quantum bits. [Background technology]

[0002] Research is being conducted on quantum computing devices using Majorana particles. A structure combining a two-dimensional topological insulator and an s-wave superconductor has been proposed as a structure that generates Majorana particles. A single layer of WTe2, a layered material of transition metal dichalcogenide, is used as the two-dimensional topological insulator. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-96107 A [Patent Document 2] US Patent Application Publication No. 2013 / 0299783 [Patent Document 3] US Patent Application Publication No. 2016 / 0035674 [Patent Document 4] JP 2013-247267 A [Non-patent literature]

[0004] [Non-Patent Document 1] N. Read and D. Green, Phys. Rev. B 61, 10267 (2000) [Non-Patent Document 2] V. Mourik et al., Science 336, 25 (2012) [Non-Patent Document 3] J. Alicea, Rep. Prog. Phys. 75, 076501 (2012) [Non-Patent Document 4] S. Wu et al., Science 359, 76 (2018) [Non-Patent Document 5] Y.-B. Choi et al., Nat. Mater 19, 974 (2020) Summary of the Invention [Problem to be solved by the invention]

[0005] Although theoretical proposals have been made, it is not easy to obtain a monolayer of WTe2 stably. Therefore, it is not possible to stably produce Majorana particles using conventional techniques.

[0006] An object of the present disclosure is to provide a quantum bit, a quantum computing device, and a method for manufacturing the quantum bit, which are capable of stably expressing Majorana particles. [Means for solving the problem]

[0007] According to one embodiment of the present disclosure, a quantum bit is provided, comprising: an s-wave superconductor layer; a higher-order topological insulator layer provided on the s-wave superconductor layer; a first ferromagnetic insulator layer provided on the higher-order topological insulator layer; and a first gate electrode provided on the first ferromagnetic insulator layer, wherein the higher-order topological insulator layer has a first region having a first hinge helical channel and a second region having a second hinge helical channel spaced from the first hinge helical channel, and the first ferromagnetic insulator layer is provided with a quantum bit covering the first hinge helical channel and the second hinge helical channel. Effect of the Invention

[0008] According to the present disclosure, Majorana particles can be stably expressed. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a top view showing a quantum bit according to the first embodiment. [Diagram 2]FIG. 2 is a cross-sectional view (part 1) showing the quantum bit according to the first embodiment. [Diagram 3] FIG. 3 is a second cross-sectional view showing the quantum bit according to the first embodiment. [Figure 4] FIG. 4 is a perspective view showing a layer of a higher-order topological insulator. [Diagram 5] FIG. 5 is a top view (part 1) illustrating the method for manufacturing a quantum bit according to the first embodiment. [Figure 6] FIG. 6 is a top view (part 2) illustrating the method for manufacturing a quantum bit according to the first embodiment. [Figure 7] FIG. 7 is a top view (part 3) illustrating the method for manufacturing a quantum bit according to the first embodiment. [Figure 8] FIG. 8 is a top view (part 4) illustrating the method for manufacturing a quantum bit according to the first embodiment. [Figure 9] FIG. 9 is a top view (part 5) illustrating the method for manufacturing a quantum bit according to the first embodiment. [Figure 10] FIG. 10 is a top view (part 6) illustrating the method for manufacturing a quantum bit according to the first embodiment. [Figure 11] FIG. 11 is a cross-sectional view (part 1) showing the method for manufacturing a quantum bit according to the first embodiment. [Figure 12] FIG. 12 is a cross-sectional view (part 2) showing the method for manufacturing a quantum bit according to the first embodiment. [Figure 13] FIG. 13 is a cross-sectional view (part 3) illustrating the method for manufacturing a quantum bit according to the first embodiment. [Figure 14] FIG. 14 is a cross-sectional view (part 4) illustrating the method for manufacturing a quantum bit according to the first embodiment. [Figure 15] FIG. 15 is a cross-sectional view (part 5) illustrating the method for manufacturing a quantum bit according to the first embodiment. [Figure 16] FIG. 16 is a cross-sectional view (part 6) illustrating the method for manufacturing a quantum bit according to the first embodiment. [Figure 17] FIG. 17 is a diagram illustrating a quantum processing device according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In this specification and drawings, components having substantially the same functional configuration may be denoted by the same reference numerals to avoid redundant description. In this disclosure, the X1-X2 direction, the Y1-Y2 direction, and the Z1-Z2 direction are defined as mutually orthogonal directions. A plane including the X1-X2 direction and the Y1-Y2 direction is described as an XY plane, a plane including the Y1-Y2 direction and the Z1-Z2 direction is described as a YZ plane, and a plane including the Z1-Z2 direction and the X1-X2 direction is described as a ZX plane. For convenience, the Z1-Z2 direction is defined as a vertical direction, the Z1 side is defined as the upper side, and the Z2 side is defined as the lower side. In addition, a planar view refers to viewing an object from the Z1 side, and a planar shape refers to a shape of an object viewed from the Z1 side.

[0011] (First embodiment) First, a first embodiment will be described. The first embodiment relates to a quantum bit. The quantum bit according to the first embodiment is used in a quantum computing device such as a quantum computer. FIG. 1 is a top view showing the quantum bit according to the first embodiment. FIGS. 2 and 3 are cross-sectional views showing the quantum bit according to the first embodiment. FIG. 2 corresponds to a cross-sectional view taken along line II-II in FIG. 1. FIG. 3 corresponds to a cross-sectional view taken along line III-III in FIG. 1.

[0012] The quantum bit 1 according to the first embodiment includes a substrate 90, an s-wave superconductor layer 10, a higher-order topological insulator layer 20, a first ferromagnetic insulator layer 31, a second ferromagnetic insulator layer 32, and a third ferromagnetic insulator layer 33. The quantum bit 1 further includes a first gate electrode 41, a second gate electrode 42, a third gate electrode 43, a first superconducting quantum interference device (SQUID) 61, a second SQUID 62, and a third SQUID 63.

[0013] The substrate 90 is, for example, a single crystal substrate with a surface having Miller indices of (100). Materials for the substrate 90 include MgO, mica, sapphire, and SiC.

[0014] The s-wave superconductor layer 10 is provided on a part of the surface of the substrate 90. The s-wave superconductor layer 10 is, for example, an Nb layer with a surface Miller index of (110). The thickness of the s-wave superconductor layer 10 is, for example, about 100 nm to 200 nm. The planar shape of the s-wave superconductor layer 10 is a rectangle with two sides parallel to the X1-X2 direction and two sides parallel to the Y1-Y2 direction.

[0015] The high-order topological insulator layer 20 is provided on the s-wave superconductor layer 10. The high-order topological insulator layer 20 is, for example, a multi-layer WTe2. For example, the multi-layer WTe2 has 5 to 100 layers, preferably 10 to 50 layers, of WTe2, which is a two-dimensional material. Since the thickness of a single layer of WTe2 is 0.7 nm, when the high-order topological insulator layer 20 includes 14 layers of WTe2, the thickness of the high-order topological insulator layer 20 is about 10 nm.

[0016] 4 is a perspective view showing the high-order topological insulator layer 20. The shape of the high-order topological insulator layer 20 is a substantially rectangular parallelepiped. The a-axis direction of the high-order topological insulator layer 20 is parallel to the Y1-Y2 direction, the b-axis direction is parallel to the X1-X2 direction, and the c-axis direction is parallel to the Z1-Z2 direction. The Miller indices of the top surface of the high-order topological insulator layer 20 are (001), the Miller indices of the side surface on the Y2 side are (100), and the Miller indices of the side surface on the X2 side are (010).

[0017] A groove 50 having a T-shape in plan view is formed on the surface of the high-order topological insulator layer 20. The groove 50 has a first groove 51, a second groove 52, and a third groove 53. For example, the width of the first groove 51, the second groove 52, and the third groove 53 is 20 nm, and the depth is 5 nm. The first groove 51 and the third groove 53 extend parallel to the X1-X2 direction, and the second groove 52 extends parallel to the Y1-Y2 direction. The first groove 51 is provided near the center of the high-order topological insulator layer 20 in the Y1-Y2 direction, and extends from the end of the high-order topological insulator layer 20 on the X2 side to the center in the X1-X2 direction. The third groove 53 is provided near the center of the high-order topological insulator layer 20 in the Y1-Y2 direction, and extends from the end of the high-order topological insulator layer 20 on the X1 side to the center in the X1-X2 direction. Therefore, the first groove 51 and the third groove 53 are formed in a straight line. The second groove 52 is provided near the center of the high-order topological insulator layer 20 in the X1-X2 direction, and extends from the Y1 side end of the high-order topological insulator layer 20 to the center in the Y1-Y2 direction. Therefore, the second groove 52 is perpendicular to the first groove 51 and the third groove 53.

[0018] The high-order topological insulator layer 20 has a first region 21 on the Y2 side of the first groove 51 and the third groove 53. The high-order topological insulator layer 20 has a second region 22 on the Y1 side of the first groove 51 and the X2 side of the second groove 52. The high-order topological insulator layer 20 has a third region 23 on the Y1 side of the third groove 53 and the X1 side of the second groove 52.

[0019] The first region 21, the second region 22, and the third region 23 each have a hinge helical channel on one of two intersecting lines between a plane perpendicular to the a-axis direction and a plane perpendicular to the c-axis direction. The hinge helical channel is parallel to the b-axis direction. Specifically, the first region 21 has a first hinge helical channel 11 on an intersecting line (ridge line) between the top surface and the side surface on the Y1 side. The second region 22 has a second hinge helical channel 12 on an intersecting line between the side surface on the Y2 side and the bottom surface of the first groove 51. The third region 23 has a third hinge helical channel 13 on an intersecting line between the side surface on the Y2 side and the bottom surface of the third groove 53. The first hinge helical channel 11 may be located at the intersection of the Y1 side surface of the first region 21 and the bottom surface of the groove 50, the second hinge helical channel 12 may be located at the intersection of the top surface of the second region 22 and the Y2 side surface, and the third hinge helical channel 13 may be located at the intersection of the top surface of the third region 23 and the Y2 side surface.

[0020] The first ferromagnetic insulating layer 31 is provided on a part of the first region 21, the second region 22, and the groove 50, and covers a part of the first hinge helical channel 11 and the second hinge helical channel 12. The second ferromagnetic insulating layer 32 is provided on a part of the second region 22, the third region 23, and the groove 50, and covers a part of the second hinge helical channel 12 and the third hinge helical channel 13. The third ferromagnetic insulating layer 33 is provided on a part of the third region 23, the first region 21, and the groove 50, and covers a part of the third hinge helical channel 13 and the first hinge helical channel 11. The material of the first ferromagnetic insulating layer 31, the second ferromagnetic insulating layer 32, and the third ferromagnetic insulating layer 33 may be Cr2Ga2Te6. The material of the first ferromagnetic insulating layer 31, the second ferromagnetic insulating layer 32, and the third ferromagnetic insulating layer 33 may be another diluted magnetic semiconductor. The first ferromagnetic insulating layer 31, the second ferromagnetic insulating layer 32 and the third ferromagnetic insulating layer 33 each have a thickness of, for example, about 30 nm.

[0021] The second ferromagnetic insulating layer 32 is separated from the first ferromagnetic insulating layer 31 on the second hinge helical channel 12 on the X1 side in the X1-X2 direction. The third ferromagnetic insulating layer 33 is separated from the second ferromagnetic insulating layer 32 on the third hinge helical channel 13 on the X1 side in the X1-X2 direction. The third ferromagnetic insulating layer 33 is separated from the first ferromagnetic insulating layer 31 on the X1 side on the first hinge helical channel 11 in the X1-X2 direction.

[0022] The first gate electrode 41 is provided on the first ferromagnetic insulator layer 31. The second gate electrode 42 is provided on the second ferromagnetic insulator layer 32. The third gate electrode 43 is provided on the third ferromagnetic insulator layer 33. An example of a material for the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43 is Au. The thickness of the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43 is, for example, about 100 nm.

[0023] The first SQUID 61 has a lower superconductor layer 61A, a lower superconductor layer 61B, a tunnel barrier layer 61C, and an upper superconductor layer 61D.

[0024] The lower superconductor layer 61A and the lower superconductor layer 61B protrude from the X2 side surface of the s-wave superconductor layer 10 toward the X2 side. The lower superconductor layer 61A is located on the Y2 side of the lower superconductor layer 61B. In a plan view, the lower superconductor layer 61A protrudes from the first region 21 toward the X2 side, and the lower superconductor layer 61B protrudes from the second region 22 toward the X2 side. The lower superconductor layer 61A and the lower superconductor layer 61B are formed integrally with the s-wave superconductor layer 10 from the same material as the s-wave superconductor layer 10. The lower superconductor layer 61A and the lower superconductor layer 61B are connected to the s-wave superconductor layer 10. The lower superconductor layer 61A and the lower superconductor layer 61B are, for example, Nb layers having a thickness of about 100 nm to 200 nm.

[0025] The tunnel barrier layer 61C and the upper superconductor layer 61D have a U-shaped planar shape. The material of the tunnel barrier layer 61C is NbO xand the material of the upper superconductor layer 61D is Nb. The thickness of the tunnel barrier layer 61C is, for example, about 1 nm to 5 nm, and the thickness of the upper superconductor layer 61D is, for example, about 100 nm to 200 nm. One end of the tunnel barrier layer 61C contacts the lower superconductor layer 61A, and the other end of the tunnel barrier layer 61C contacts the lower superconductor layer 61B. The upper superconductor layer 61D is provided on the tunnel barrier layer 61C.

[0026] A tunnel barrier layer 61C is sandwiched between the lower superconductor layer 61A and the upper superconductor layer 61D, and between the lower superconductor layer 61B and the upper superconductor layer 61D. The first SQUID 61 is composed of such Josephson junctions. The first SQUID 61 detects a change in magnetic flux between the first hinge helical channel 11 and the second hinge helical channel 12.

[0027] The second SQUID 62 has a lower superconductor layer 62A, a lower superconductor layer 62B, a tunnel barrier layer 62C, and an upper superconductor layer 62D.

[0028] The lower superconductor layer 62A and the lower superconductor layer 62B protrude from the Y1 side surface of the s-wave superconductor layer 10 toward the Y1 side. The lower superconductor layer 62A is located on the X2 side of the lower superconductor layer 62B. In a plan view, the lower superconductor layer 62A protrudes from the second region 22 toward the Y1 side, and the lower superconductor layer 62B protrudes from the third region 23 toward the Y1 side. The lower superconductor layer 62A and the lower superconductor layer 62B are formed integrally with the s-wave superconductor layer 10 from the same material as the s-wave superconductor layer 10. The lower superconductor layer 62A and the lower superconductor layer 62B are connected to the s-wave superconductor layer 10. The lower superconductor layer 62A and the lower superconductor layer 62B are, for example, Nb layers having a thickness of about 100 nm to 200 nm.

[0029] The tunnel barrier layer 62C and the upper superconductor layer 62D have a U-shaped planar shape. The material of the tunnel barrier layer 62C is NbO xand the material of the upper superconductor layer 62D is Nb. The thickness of the tunnel barrier layer 62C is, for example, about 1 nm to 5 nm, and the thickness of the upper superconductor layer 62D is, for example, about 100 nm to 200 nm. One end of the tunnel barrier layer 62C contacts the lower superconductor layer 62A, and the other end of the tunnel barrier layer 62C contacts the lower superconductor layer 62B. The upper superconductor layer 62D is provided on the tunnel barrier layer 62C.

[0030] A tunnel barrier layer 62C is sandwiched between the lower superconductor layer 62A and the upper superconductor layer 62D, and between the lower superconductor layer 62B and the upper superconductor layer 62D. The second SQUID 62 is composed of such a Josephson junction. The second SQUID 62 detects a change in the magnetic flux between the second hinge helical channel 12 and the third hinge helical channel 13.

[0031] The third SQUID 63 has a lower superconductor layer 63A, a lower superconductor layer 63B, a tunnel barrier layer 63C, and an upper superconductor layer 63D.

[0032] The lower superconductor layer 63A and the lower superconductor layer 63B protrude from the X1 side surface of the s-wave superconductor layer 10 toward the X1 side. The lower superconductor layer 63A is located on the Y1 side of the lower superconductor layer 63B. In a plan view, the lower superconductor layer 63A protrudes from the third region 23 toward the X1 side, and the lower superconductor layer 63B protrudes from the first region 21 toward the X1 side. The lower superconductor layer 63A and the lower superconductor layer 63B are formed integrally with the s-wave superconductor layer 10 from the same material as the s-wave superconductor layer 10. The lower superconductor layer 63A and the lower superconductor layer 63B are connected to the s-wave superconductor layer 10. The lower superconductor layer 63A and the lower superconductor layer 63B are, for example, Nb layers having a thickness of about 100 nm to 200 nm.

[0033] The tunnel barrier layer 63C and the upper superconductor layer 63D have a U-shaped planar shape. The material of the tunnel barrier layer 63C is NbO xand the material of the upper superconductor layer 63D is Nb. The thickness of the tunnel barrier layer 63C is, for example, about 1 nm to 5 nm, and the thickness of the upper superconductor layer 63D is, for example, about 100 nm to 200 nm. One end of the tunnel barrier layer 63C contacts the lower superconductor layer 63A, and the other end of the tunnel barrier layer 63C contacts the lower superconductor layer 63B. The upper superconductor layer 63D is provided on the tunnel barrier layer 63C.

[0034] A tunnel barrier layer 63C is sandwiched between the lower superconductor layer 63A and the upper superconductor layer 63D, and between the lower superconductor layer 63B and the upper superconductor layer 63D. The third SQUID 63 is composed of such Josephson junctions. The third SQUID 63 detects a change in the magnetic flux between the third hinge helical channel 13 and the first hinge helical channel 11.

[0035] In the quantum bit 1 configured in this manner, four Majorana particles γ1, γ2, γ3, and γ4 are expressed. For example, the Majorana particle γ1 is stably expressed in the vicinity of the first gate electrode 41 of the first hinge helical channel 11, and the Majorana particle γ4 is stably expressed in the vicinity of the third gate electrode 43 of the first hinge helical channel 11. Furthermore, for example, the Majorana particle γ2 is stably expressed between the first gate electrode 41 and the second gate electrode 42 of the second hinge helical channel 12, and the Majorana particle γ3 is stably expressed between the second gate electrode 42 and the third gate electrode 43 of the third hinge helical channel 13. The Majorana particles γ1 to γ4 are exchanged by a change in electrostatic potential accompanying the application of gate voltages to the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43.

[0036] For example, in the exchange between Majorana particle γ1 and Majorana particle γ2, an electric field is applied from the first gate electrode 41, and a minute change in magnetic flux during the exchange between Majorana particles γ1 and γ2 is detected as a minute change in a voltage signal by the first SQUID 61. In the exchange between Majorana particle γ2 and Majorana particle γ3, an electric field is applied from the second gate electrode 42, and a minute change in magnetic flux during the exchange between Majorana particles γ2 and γ3 is detected as a minute change in a voltage signal by the second SQUID 62. In addition, in the exchange between Majorana particle γ3 and Majorana particle γ4, an electric field is applied from the third gate electrode 43, and a minute change in magnetic flux during the exchange between Majorana particles γ3 and γ4 is detected as a minute change in a voltage signal by the third SQUID 63.

[0037] A single layer of WTe2, which is a layered material of transition metal dichalcogenide, is easily oxidized, and its properties change when exposed to the air. It is possible to suppress oxidation by sandwiching the single layer of WTe2 between chemically stable materials such as hexagonal boron nitride (h-BN) and graphene, but in that case, the manufacturing process of the quantum bit becomes complicated. In addition, it is difficult to adjust the size of the single layer of WTe2. In contrast, in this embodiment, a higher-order topological insulator layer 20 such as multi-layer WTe2 is used, so a configuration for suppressing oxidation is not required. In addition, it is easier to adjust the size of the higher-order topological insulator layer 20 than to adjust the size of the single layer of WTe2.

[0038] It is also possible to provide a plurality of quantum bits 1 on the substrate 90 to achieve multi-qubit configuration, or to implement a semiconductor integrated circuit on the substrate 90. Therefore, according to this embodiment, it is possible to accelerate research and development toward realizing a practical error-tolerant quantum computer.

[0039] Next, a method for manufacturing the quantum bit 1 according to the first embodiment will be described. Figures 5 to 10 are top views showing the method for manufacturing the quantum bit 1 according to the first embodiment. Figures 11 to 16 are cross-sectional views showing the method for manufacturing the quantum bit 1 according to the first embodiment.

[0040] First, as shown in Fig. 5 and Fig. 11, a substrate 90 is prepared and annealed at about 1200°C for 3 to 4 hours in an oxygen atmosphere at atmospheric pressure. Next, the substrate 90 is immersed in methanol for 20 minutes and rinsed with ultrapure water. These processes can improve the flatness of the surface of the substrate 90. Fig. 11 corresponds to a cross-sectional view taken along line XI-XI in Fig. 5.

[0041] Thereafter, an s-wave superconductor layer 19 is formed on the substrate 90, and a high-order topological insulator layer 29 is formed on the s-wave superconductor layer 19. In the following, a description will be given assuming that an Nb layer is formed as the s-wave superconductor layer 19, and a multi-layer WTe2 is formed as the high-order topological insulator layer 29. The s-wave superconductor layer 19 and the high-order topological insulator layer 29 can be epitaxially grown in situ in the same vacuum chamber by, for example, a pulsed laser deposition (PLD) method. The basic degree of vacuum during the formation of the s-wave superconductor layer 19 and the high-order topological insulator layer 29 is, for example, 5×10 -6 Pa or less. When forming the s-wave superconductor layer 19 and the high-order topological insulator layer 29 by the PLD method, a KrF excimer laser (λ=248 nm) light source can be used as the laser light source. The s-wave superconductor layer 19 and the high-order topological insulator layer 29 may be formed by, for example, a molecular beam epitaxy method, a sputtering method, a co-evaporation method, or the like.

[0042] When forming an Nb layer as the s-wave superconductor layer 19 by the PLD method, for example, a Nb pure metal target can be used as the target. When forming the s-wave superconductor layer 19, for example, the temperature of the substrate 90 is kept at about 400° C., and the laser energy density is set to 2.0 J / cm 2 . 2 ~5.0J / cm 2 The irradiation frequency is 10 Hz, the distance between the substrate 90 and the target is about 5 cm, and the film formation rate is 0.5 nm / min to 1.0 nm / min. On the substrate 90 maintained at about 400° C., the Nb layer grows epitaxially while being oriented in the

[0110] direction.

[0043] When forming a multi-layer WTe2 as the highly-ordered topological insulator layer 29 by the PLD method, for example, a WTe2 sintered compact target can be used as the target. When forming the highly-ordered topological insulator layer 29, for example, the temperature of the substrate 90 is kept at 250°C to 350°C, and the laser energy density is 1.0 J / cm 2 ~2.0J / cm 2 The irradiation frequency is 1 Hz, the distance between the substrate 90 and the target is about 5 cm, and the deposition rate is 0.1 nm / min to 0.5 nm / min. The high-order topological insulator layer 29 (multilayer WTe2) is oriented in the c-axis direction on the s-wave superconductor layer 19 (Nb layer), and the crystal structure of the high-order topological insulator layer 29 is T d The structure (space group: Pmm21) is shown.

[0044] After the multilayer WTe2 is formed, it is preferable to perform post-annealing at about 300° C. for 30 minutes to 1 hour, in order to improve the crystallinity of the multilayer WTe2.

[0045] After the high-order topological insulator layer 29 is formed, the s-wave superconductor layer 19 and the high-order topological insulator layer 29 are processed to form the s-wave superconductor layer 10, the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, the lower superconductor layer 62B, the lower superconductor layer 63A, and the lower superconductor layer 63B from the s-wave superconductor layer 19, as shown in Fig. 6 and Fig. 12. Fig. 12 corresponds to a cross-sectional view taken along the line XII-XII in Fig. 6.

[0046] When processing the s-wave superconductor layer 19 and the high-order topological insulator layer 29, first, a first electron beam resist is spin-coated on the high-order topological insulator layer 29. Then, a first mask pattern is formed from the first electron beam resist by electron beam lithography. The first mask pattern covers the portions of the s-wave superconductor layer 19 where the s-wave superconductor layer 10, the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, the lower superconductor layer 62B, the lower superconductor layer 63A, and the lower superconductor layer 63B are to be formed, from above the high-order topological insulator layer 29, and exposes the other portions. As the first electron beam resist, for example, a resist obtained by diluting ZEP 520A (manufactured by Nippon Zeon Co., Ltd.) with ZEP-A (manufactured by Nippon Zeon Co., Ltd.) at a ratio of 1:1 can be used. After the first mask pattern is formed, Ar ion milling is used to process the s-wave superconductor layer 19 and the high-order topological insulator layer 29. In the Ar ion milling, for example, the beam acceleration voltage is 280 V and the beam current is 150 mA.

[0047] After processing the s-wave superconductor layer 19 and the high-order topological insulator layer 29, the first mask pattern is removed, and the high-order topological insulator layer 29 is processed to form a high-order topological insulator layer 29A having a rectangular planar shape and a flat upper surface from the high-order topological insulator layer 29, as shown in Fig. 7 and Fig. 13. Fig. 13 corresponds to a cross-sectional view taken along line XIII-XIII in Fig. 7.

[0048] When processing the high-order topological insulator layer 29, first, a second electron beam resist is spin-coated on the high-order topological insulator layer 29 and the substrate 90. Then, a second mask pattern is formed from the second electron beam resist by electron beam lithography. The second mask pattern covers the portion of the high-order topological insulator layer 29 on the s-wave superconductor layer 10 and exposes the portions on the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, the lower superconductor layer 62B, the lower superconductor layer 63A, and the lower superconductor layer 63B. As the second electron beam resist, for example, a resist obtained by diluting ZEP 520A (manufactured by Nippon Zeon Co., Ltd.) with ZEP-A (manufactured by Nippon Zeon Co., Ltd.) at a ratio of 1:1 can be used. After forming the second mask pattern, the high-order topological insulator layer 29 is processed by Ar ion milling. As a result, the high-order topological insulator layer 29A is formed, and the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, the lower superconductor layer 62B, the lower superconductor layer 63A, and the lower superconductor layer 63B are exposed from the high-order topological insulator layer 29A. In the Ar ion milling, for example, the beam acceleration voltage is set to 280 V and the beam current is set to 150 mA.

[0049] After the formation of the high-order topological insulator layer 29A, the second mask pattern is removed, and the high-order topological insulator layer 29A is processed to form a high-order topological insulator layer 20 having a first region 21, a second region 22, and a third region 23 from the high-order topological insulator layer 29A, as shown in Fig. 8 and Fig. 14. Fig. 14 corresponds to a cross-sectional view taken along line XIV-XIV in Fig. 8.

[0050] When processing the high-order topological insulator layer 29A, first, a third electron beam resist is spin-coated on the high-order topological insulator layer 29A, the substrate 90, the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, the lower superconductor layer 62B, the lower superconductor layer 63A, and the lower superconductor layer 63B. Next, a third mask pattern is formed from the third electron beam resist by electron beam lithography. The third mask pattern exposes the portion of the high-order topological insulator layer 29A where the groove 50 is to be formed, and covers the other portions. As the third electron beam resist, for example, a resist obtained by diluting ZEP 520A (manufactured by Nippon Zeon Co., Ltd.) with ZEP-A (manufactured by Nippon Zeon Co., Ltd.) at a ratio of 1:1 can be used. After forming the third mask pattern, the high-order topological insulator layer 29A is processed by Ar ion milling. As a result, a groove 50 including a first groove 51, a second groove 52, and a third groove 53 is formed, and a highly-ordered topological insulator layer 20 including a first region 21, a second region 22, and a third region 23 is obtained. The first region 21 includes a first hinge helical channel 11, the second region 22 includes a second hinge helical channel 12, and the third region 23 includes a third hinge helical channel 13 (see FIG. 4). In the Ar ion milling, for example, the beam acceleration voltage is set to 280 V and the beam current is set to 150 mA.

[0051] After the formation of the highly-ordered topological insulator layer 20, the third mask pattern is removed, and the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, the third ferromagnetic insulator layer 33, the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43 are formed as shown in Fig. 9 and Fig. 15. Fig. 15 corresponds to a cross-sectional view taken along the line XV-XV in Fig. 9.

[0052] When forming the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, the third ferromagnetic insulator layer 33, the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43, a fourth electron beam resist is first spin-coated on the high-order topological insulator layer 20, the substrate 90, the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, the lower superconductor layer 62B, the lower superconductor layer 63A, and the lower superconductor layer 63B. Then, a fourth mask pattern is formed from the fourth electron beam resist by electron beam lithography. The fourth mask pattern exposes the portions where the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, the third ferromagnetic insulator layer 33, the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43 are to be formed, and covers the other portions. As the fourth electron beam resist, for example, a resist obtained by diluting ZEP 520A (manufactured by Zeon Corporation) with ZEP-A (manufactured by Zeon Corporation) at a ratio of 1:1 can be used. After forming the fourth mask pattern, a Cr2Ga2Te6 layer and an Au layer are formed by the PLD method.

[0053] When the Cr2Ga2Te6 layer is formed by the PLD method, for example, the temperature of the substrate 90 is kept at 150° C. to 250° C., and the laser energy density is set to 1.0 J / cm 2 ~2.0J / cm 2 The irradiation frequency is 1 Hz, the distance between the substrate 90 and the target is about 5 cm, and the film formation rate is 1.0 nm / min to 2.0 nm / min.

[0054] When the Au layer is formed by the PLD method, for example, the temperature of the substrate 90 is kept at room temperature, and the laser energy density is set to 1.0 J / cm 2 ~2.0J / cm 2 The irradiation frequency is set to 5 Hz, the distance between the substrate 90 and the target is set to about 5 cm, and the film formation rate is set to 5.0 nm / min to 10.0 nm / min.

[0055] After the Cr2Ga2Te6 layer and the Au layer are formed, the fourth mask pattern is removed together with the Cr2Ga2Te6 layer and the Au layer deposited thereon. That is, lift-off is performed. As a result, the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, the third ferromagnetic insulator layer 33, the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43 are obtained. In addition, four Majorana particles γ1, γ2, γ3, and γ4 are expressed.

[0056] Next, tunnel barrier layers 61C to 63C and upper superconductor layers 61D to 63D are formed as shown in Fig. 10 and Fig. 16. Fig. 16 corresponds to a cross-sectional view taken along line XVI-XVI in Fig. 10.

[0057] When forming the tunnel barrier layers 61C to 63C and the upper superconductor layers 61D to 63D, first, a fifth electron beam resist is spin-coated on the high-order topological insulator layer 20, the substrate 90, the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, the lower superconductor layer 62B, the lower superconductor layer 63A, the lower superconductor layer 63B, the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43. Next, a fifth mask pattern is formed from the fifth electron beam resist by electron beam lithography. The fifth mask pattern exposes the portions where the tunnel barrier layers 61C to 63C and the upper superconductor layers 61D to 63D are to be formed, and covers the other portions. As the fifth electron beam resist, for example, a resist obtained by diluting ZEP 520A (manufactured by Nippon Zeon Co., Ltd.) with ZEP-A (manufactured by Nippon Zeon Co., Ltd.) at a ratio of 1:1 can be used. After forming the fifth mask pattern, NbO x A layer and a Nb layer are formed.

[0058] NbO x When forming the layer by the PLD method, for example, a Nb metal target is used, the temperature of the substrate 90 is kept at room temperature, and the oxygen partial pressure in the vacuum chamber is adjusted to about 50 Pa to 55 Pa. The Nb layer can be formed under the same conditions as those for the s-wave superconductor layer 19.

[0059] NbO xAfter the formation of the Nb layer and the Nb layer, a fifth mask pattern is formed on the NbO x The Nb layer and the Nb layer are then removed together. In other words, lift-off is performed. As a result, tunnel barrier layers 61C to 63C and upper superconductor layers 61D to 63D are obtained, and the first SQUID 61, the second SQUID 62 and the third SQUID 63 are formed.

[0060] In this manner, the quantum bit 1 according to the first embodiment can be manufactured.

[0061] The material of the high-order topological insulator layer 20 is not limited to multi-layer WTe2, but may be, for example, multi-layer Bi4Br4. Also, the material of the s-wave superconductor layer 10 is not limited to Nb, but may be, for example, Al or Pd.

[0062] Second embodiment Next, a second embodiment will be described. The second embodiment relates to a quantum processing device including the quantum bit 1 according to the first embodiment. Fig. 17 is a diagram showing the quantum processing device according to the second embodiment.

[0063] As shown in FIG. 17, the quantum computing device 2 according to the second embodiment includes a quantum bit chip 81, a signal generator 82, a signal demodulator 83, and a cryogenic dilution refrigerator 84. The quantum bit chip 81 includes a plurality of quantum bits 1 according to the first embodiment. The quantum bit chip 81 is accommodated in the cryogenic dilution refrigerator 84 and cooled to a temperature of 10 mK or less. The signal generator 82 generates a microwave pulse signal, and the microwave pulse signal is input to the quantum bit chip 81. The quantum bit chip 81 outputs a signal corresponding to the microwave pulse signal, and the signal demodulator 83 demodulates the signal output from the quantum bit chip 81. The signal generator 82 and the signal demodulator 83 are used at a temperature of, for example, about room temperature.

[0064] Since the quantum computing device 2 according to the second embodiment includes the quantum bit 1 according to the first embodiment, it is possible to stably manifest Majorana particles and perform stable computation.

[0065] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims. [Explanation of symbols]

[0066] 1: Quantum bits 2: Quantum computing device 10: s-wave superconductor layer 11: First hinge helical channel 12: Second hinge helical channel 13: 3rd hinge helical channel 20: High-order topological insulator layers 21:First area 22:Second area 23: Third area 31: First ferromagnetic insulator layer 32: Second ferromagnetic insulator layer 33: Third ferromagnetic insulator layer 41: First gate electrode 42: second gate electrode 43: Third gate electrode 50: Groove 51: 1st groove 52:Second groove 53: Third groove 61: First SQUID 62:2nd SQUID 63: The Third SQUID

Claims

1. an s-wave superconductor layer; a high-order topological insulator layer provided on the s-wave superconductor layer; a first ferromagnetic insulator layer disposed on the highly ordered topological insulator layer; a first gate electrode provided on the first ferromagnetic insulator layer; having The high-order topological insulator layer is a first region having a first hinge helical channel; a second region having a second hinged helical channel spaced from the first hinged helical channel; having The first ferromagnetic insulator layer covers the first hinged helical channel and the second hinged helical channel.

2. 10. The quantum bit of claim 1 further comprising a first superconducting quantum interferometer that detects changes in magnetic flux between the first hinged helical channel and the second hinged helical channel.

3. the higher-order topological insulator layer has a third region with a third hinged helical channel spaced from the first hinged helical channel and the second hinged helical channel; a second ferromagnetic insulator layer covering the second hinge helical channel and the third hinge helical channel; a second gate electrode provided on the second ferromagnetic insulator layer; a third ferromagnetic insulator layer covering the third hinge helical channel and the first hinge helical channel; a third gate electrode provided on the third ferromagnetic insulator layer; 3. The quantum bit according to claim 1, further comprising:

4. A second superconducting quantum interference detector; a third superconducting quantum interference detector; having a second superconducting quantum interferometer for detecting a change in magnetic flux between the second hinged helical channel and the third hinged helical channel; 4. The quantum bit of claim 3, wherein a third superconducting quantum interferometer detects changes in magnetic flux between the third hinged helical channel and the first hinged helical channel.

5. The high-order topological insulator layer is a first groove defining the first region and the second region; a second groove defining the second region and the third region; a third groove defining the third region and the first region; 5. The quantum bit according to claim 3, wherein:

6. The first groove and the third groove extend in a common first direction, The second groove extends in a second direction perpendicular to the first direction, The quantum bit according to claim 5 , wherein the first groove, the second groove, and the third groove are connected to each other.

7. The high-order topological insulator layer is a multilayer WTe ２ Or multi-layer Bi ４ B ４ 7. The quantum bit of claim 1, further comprising:

8. A quantum computing device comprising the quantum bit according to any one of claims 1 to 7.

9. forming a high-order topological insulator layer on an s-wave superconductor layer; forming a first ferromagnetic insulator layer on the highly ordered topological insulator layer; forming a first gate electrode on the first ferromagnetic insulator layer; having The high-order topological insulator layer is a first region having a first hinge helical channel; a second region having a second hinged helical channel spaced from the first hinged helical channel; having The first ferromagnetic insulator layer covers the first hinged helical channel and the second hinged helical channel.

10. the higher-order topological insulator layer has a third region with a third hinged helical channel spaced from the first hinged helical channel and the second hinged helical channel; forming a second ferromagnetic insulator layer covering the second hinge helical channel and the third hinge helical channel; forming a third ferromagnetic insulator layer covering the third hinge helical channel and the first hinge helical channel; forming a second gate electrode on the second ferromagnetic insulator layer; forming a third gate electrode on the third ferromagnetic insulator layer; 10. The method of claim 9, further comprising:

11. 11. The method for manufacturing a quantum bit according to claim 10, further comprising forming, in the higher-order topological insulator layer, a first groove that defines the first region and the second region, a second groove that defines the second region and the third region, and a third groove that defines the third region and the first region.

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