Semiconductor Device

Abstract

Provided is a semiconductor device provided with a gate trench portion, and a first trench portion adjacent to the gate trench portion, the semiconductor device comprising: a first conductive-type drift region provided in a semiconductor substrate; a second conductive-type base region provided above the drift region; a first conductive-type emitter region provided above the base region and having a higher doping concentration than the drift region; and a second conductive-type contact region provided above the base region and having a higher doping concentration than the base region. The contact region may have a first contact portion and a second contact portion provided extending from the first trench portion to below the lower end of the emitter region in a mesa portion between the gate trench portion and the first trench portion. The first contact portion may be provided extending from the first trench portion rather than the second contact portion in a trench arrangement direction.

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 states that "the characteristics such as saturation current of a semiconductor device are improved." [Prior art document] [Patent documents] [Patent Document 1] JP 2018-195798 A [Patent Document 2] International Publication No. 2018 / 052098 Pamphlet

[0003] To provide a semiconductor device having improved latch-up resistance during switching.

[0004] In a first aspect of the present invention, there is provided a semiconductor device including a gate trench portion and a first trench portion adjacent to the gate trench portion, the semiconductor device including a first conductivity type drift region provided in a semiconductor substrate, a second conductivity type base region provided above the drift region, an emitter region of the first conductivity type provided above the base region and having a doping concentration higher than that of the drift region, and a second conductivity type contact region provided above the base region and having a doping concentration higher than that of the base region. The contact region may have a first contact portion and a second contact portion provided in a mesa portion between the gate trench portion and the first trench portion, the first contact portion extending from the first trench portion to below a lower end of the emitter region. The first contact portion may extend from the first trench portion further than the second contact portion in the trench arrangement direction.

[0005] The second contact portion may be located below the emitter region and closer to the center of the emitter region in the trench extension direction than the first contact portion.

[0006] The first contact portion and the second contact portion may be in contact with a lower end of the emitter region.

[0007] At the center of the emitter region in the extension direction of the trench, a lower end of the emitter region may be in contact with the base region.

[0008] The first contact portion may be in contact with the gate trench portion below the emitter region, and the second contact portion may be spaced apart from the gate trench portion below the emitter region.

[0009] The second contact portion may be spaced apart from the gate trench portion by 0.6 μm or more in the trench arrangement direction.

[0010] The size of the step between the first contact portion and the second contact portion in the trench arrangement direction may be 10% or more and 50% or less of the mesa width of the mesa portion.

[0011] The first contact portion and the second contact portion may be provided on the front surface of the semiconductor substrate, on a sidewall of the first trench portion.

[0012] The semiconductor device may include an interlayer insulating film provided above a semiconductor substrate, and the emitter region may be connected to an emitter electrode via a contact hole provided through the interlayer insulating film.

[0013] The emitter region may extend from the gate trench portion beyond the contact hole in the trench arrangement direction.

[0014] The emitter region may extend from the gate trench portion in the trench arrangement direction and terminate without reaching the first trench portion.

[0015] The second contact portion may extend from the first trench portion beyond the contact hole in the trench arrangement direction.

[0016] The contact region may have third contact portions provided alternately with the emitter regions along the trench extension direction on the front surface of the semiconductor substrate.

[0017] The first trench portion may be a dummy trench portion set to an emitter potential.

[0018] The first trench portion may include a dummy gate trench portion that is set to a gate potential and is not in contact with the emitter region.

[0019] The first trench portion may be a gate trench portion set to a gate potential.

[0020] The emitter region may have a first emitter region in contact with the gate trench portion and spaced apart from the first trench portion in the mesa portion, and the contact region may be provided below a lower end of the first emitter region on a side of the first trench portion in the mesa portion.

[0021] The emitter region may have a second emitter region in contact with the first trench portion and spaced apart from the gate trench portion in the mesa portion. The contact region may also be provided below a lower end of the second emitter region on the gate trench portion side in the mesa portion.

[0022] The first emitter regions and the second emitter regions may be provided alternately in the extension direction of the gate trench portion.

[0023] The above summary of the invention does not list all of the features of the present invention. Also, subcombinations of these features may also be inventions. [Brief description of the drawings]

[0024] [Figure 1A] 1 shows an example of a top view of a semiconductor device 100. FIG. [Figure 1B] FIG. 1B is an example of a cross-sectional view taken along line aa' in FIG. 1A. [Figure 1C] FIG. 1B is an example of a cross-sectional view taken along line bb' in FIG. 1A. [Figure 1D] 1 shows an example of an enlarged view of a front surface 21 of a semiconductor device 100. FIG. [Figure 1E]An example of an enlarged view of the lower end of the emitter region 12 is shown. [Figure 1F] FIG. 1E is an example of a cross-sectional view taken along line cc' in FIG. 1D. [Figure 1G] FIG. 1E is an example of a cross-sectional view taken along line dd' in FIG. [Diagram 2] 2A to 2C are diagrams for explaining an example of a method for manufacturing the semiconductor device 100. [Diagram 3] 1 shows an example of a top view of a semiconductor device 100 in which a contact hole 54 has not yet been opened. [Figure 4A] 1 shows an example of a top view of a semiconductor device 100. FIG. [Figure 4B] FIG. 4B is an example of a cross-sectional view taken along line ee' in FIG. 4A. [Figure 5A] 1 shows an example of a top view of a semiconductor device 100 according to a modified example. [Figure 5B] FIG. 5B is an example of a cross-sectional view taken along line ff' in FIG. 5A. [Figure 6A] 1 shows an example of a top view of a semiconductor device 100 according to a modified example. [Figure 6B] FIG. 6B is an example of a cross-sectional view taken along line g-g' in FIG. 6A. [Figure 7A] 1 shows an example of a top view of a semiconductor device 100 according to a modified example. [Figure 7B] FIG. 7B is an example of a cross-sectional view taken along line hh' in FIG. 7A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0026] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the front surface and the other surface is referred to as the back surface. The directions of "upper," "lower," "front," and "back" are not limited to the direction of gravity or the direction of attachment to a substrate or the like when mounting a semiconductor device.

[0027] In this specification, technical matters may be explained using orthogonal coordinate axes of X, Y, and Z. In this specification, a plane parallel to the front surface of the semiconductor substrate is defined as the XY plane, and a direction that forms a right-handed system with the X and Y axes and is parallel to the depth direction of the semiconductor substrate is defined as the Z axis.

[0028] In each embodiment, an example is shown in which the first conductivity type is N type and the second conductivity type is P type, but the first conductivity type may be P type and the second conductivity type may be N type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment are opposite polarities.

[0029] As used herein, layers or regions marked with an N or P indicate that electrons or holes are the majority carriers, respectively, and + and - following an N or P indicate a higher or lower doping concentration, respectively, than layers or regions not marked with that symbol.

[0030] 1A shows an example of a top view of a semiconductor device 100. The semiconductor device 100 of this example is a semiconductor chip including a transistor section 70 and a diode section 80. For example, the semiconductor device 100 is a trench-gate type RC-IGBT (Reverse Conducting Insulated Gate Bipolar Transistor) in which a plurality of trench sections are arranged. In this example, the plurality of trench sections are arranged in the X-axis direction in a stripe pattern extending in the Y-axis direction.

[0031] The transistor section 70 is a region obtained by projecting a collector region 22 provided on the back side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10, which will be described later in FIG. 1B. The collector region 22 has a second conductivity type. In this example, the collector region 22 is a P+ type, for example. The transistor section 70 includes a transistor such as an IGBT.

[0032] The diode section 80 is a region obtained by projecting a cathode region 82 provided on the back side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10, which will be described later in FIG. 1B. The cathode region 82 has a first conductivity type. In this example, the cathode region 82 is an N+ type, for example. The diode section 80 includes a diode such as a free wheel diode (FWD) provided adjacent to the transistor section 70 on the upper surface of the semiconductor substrate 10.

[0033] FIG. 1A shows the region around the chip end portion, which is the edge side of the semiconductor device 100, and omits other regions. For example, an edge termination structure is provided in the region on the negative side in the Y-axis direction of the semiconductor device 100 in this example. The edge termination structure relieves electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure has, for example, a guard ring, a field plate, a resurf, or a structure combining these. Note that, for convenience, in this example, the edge on the negative side in the Y-axis direction will be described, but the same applies to other edges of the semiconductor device 100.

[0034] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, etc. The semiconductor substrate 10 in this example is a silicon substrate.

[0035] The semiconductor device 100 of this example includes, on the front surface of the semiconductor substrate 10, a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17. The semiconductor device 100 of this example also includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface of the semiconductor substrate 10.

[0036] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the emitter region 12, the base region 14, the contact region 15, and the well region 17. In addition, the gate metal layer 50 is provided above the gate trench portion 40 and the well region 17.

[0037] The emitter electrode 52 and the gate metal layer 50 are formed of a material containing a metal. For example, at least a portion of the emitter electrode 52 is formed of aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. At least a portion of the gate metal layer 50 may be formed of aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. The emitter electrode 52 and the gate metal layer 50 may have a barrier metal made of titanium, a titanium compound, or the like under the region made of aluminum or the like. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.

[0038] The emitter electrode 52 and the gate metal layer 50 are provided above the semiconductor substrate 10 with an interlayer insulating film 38 therebetween. The interlayer insulating film 38 is omitted in Fig. 1A. A contact hole 54, a contact hole 55, and a contact hole 56 are provided penetrating the interlayer insulating film 38.

[0039] The contact hole 55 connects the gate metal layer 50 and the gate conductive portion in the gate trench portion 40 of the transistor section 70. Inside the contact hole 55, a plug made of tungsten or the like may be formed.

[0040] The contact hole 56 connects the emitter electrode 52 and the dummy conductive portion in the dummy trench portion 30. Inside the contact hole 56, a plug made of tungsten or the like may be formed.

[0041] The connection portion 25 electrically connects a front surface electrode, such as the emitter electrode 52 or the gate metal layer 50, to the semiconductor substrate 10. In one example, the connection portion 25 is provided between the gate metal layer 50 and the gate conductive portion. The connection portion 25 is also provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is a conductive material, such as polysilicon doped with impurities. Here, the connection portion 25 is polysilicon (N+) doped with N-type impurities. The connection portion 25 is provided above the front surface of the semiconductor substrate 10 via an insulating film, such as an oxide film, or the like.

[0042] The gate trench portions 40 are arranged at predetermined intervals along a predetermined trench arrangement direction (the X-axis direction in this example). As an example, the gate trench portions 40 are arranged with a trench interval of 1.5 μm between adjacent trench portions, but the trench interval is not limited to this interval. The gate trench portion 40 in this example may have two extension portions 41 extending along a trench extension direction (the Y-axis direction in this example) parallel to the front surface of the semiconductor substrate 10 and perpendicular to the trench arrangement direction, and a connection portion 43 connecting the two extension portions 41.

[0043] It is preferable that at least a portion of the connection portion 43 is formed in a curved shape. By connecting the ends of the two extension portions 41 in the gate trench portion 40, it is possible to alleviate electric field concentration at the ends of the extension portions 41. At the connection portion 43 of the gate trench portion 40, the gate metal layer 50 may be connected to the gate conductive portion.

[0044] The dummy trench portion 30 in this example is a trench portion electrically connected to the emitter electrode 52 and set to the emitter potential. The dummy trench portion 30 is arranged at a predetermined interval along a predetermined trench arrangement direction (X-axis direction in this example) similar to the gate trench portion 40. As an example, the dummy trench portion 30 is arranged with a trench interval of 1.5 μm between adjacent trench portions, but the trench interval is not limited to this interval. In particular, the trench interval of the dummy trench portion 30 may be set to be different from the trench interval of the gate trench portion 40. The dummy trench portion 30 in this example may have a U-shape on the front surface of the semiconductor substrate 10 similar to the gate trench portion 40. That is, the dummy trench portion 30 may have two extension portions 31 extending along the trench extension direction and a connection portion 33 connecting the two extension portions 31. The dummy trench portion 30 may be set to a floating potential that is not set to a predetermined potential. The dummy trench portion 30 is an example of a first trench portion adjacent to the gate trench portion 40.

[0045] In this manner, the first trench portion adjacent to the gate trench portion 40 may be the dummy trench portion 30 set to the emitter potential. The first trench portion adjacent to the gate trench portion 40 may be the gate trench portion 40 set to the gate potential. Also, the first trench portion adjacent to the gate trench portion 40 may be a dummy gate trench portion 130 that is set to the gate potential and does not contact the emitter region 12. The dummy gate trench portion 130 will be described later.

[0046] The transistor section 70 of this example has a structure in which two gate trench sections 40 having a connection portion 43 and two dummy trench sections 30 having no connection portion are repeatedly arranged. That is, the arrangement ratio of the gate trench sections 40 and the dummy trench sections 30 may be set to a predetermined desired arrangement ratio. In the transistor section 70 of this example, the ratio of the number of the gate trench sections 40 to the number of the dummy trench sections 30 is 1:1. The transistor section 70 of this example has a dummy trench section 30 between two extension sections 41 connected by the connection portion 43. The number of the gate trench sections 40 may be the number of the extension sections 41. The number of the dummy trench sections 30 may be the number of the extension sections 31.

[0047] However, the ratio of the gate trench portions 40 to the dummy trench portions 30 is not limited to this example. The ratio of the gate trench portions 40 to the dummy trench portions 30 may be 2:3 or 2:4. By increasing the number of dummy trench portions 30 relative to the gate trench portions 40, the electric field concentration in the mesa portion 71 can be alleviated, and the voltage and current withstand capability of the semiconductor device 100 can be increased. In addition, by adjusting the ratio of the gate trench portions 40 to the dummy trench portions 30, the gate capacitance for driving the semiconductor device 100 can be adjusted. By increasing the number of dummy trench portions 30 relative to the gate trench portions 40, Number of Increasing the gate capacitance increases and the saturation current decreases. Also, the transistor section 70 may have a so-called full gate structure in which the dummy trench section 30 is not provided and the entire section is made up of the gate trench section 40. The ratio of the gate trench section 40 to the dummy trench section 30 disclosed in this specification may be interpreted as the ratio of the gate trench section 40 to the dummy trench. The dummy trench includes a trench in which no channel is formed on the sidewall, such as the dummy trench section 30 or the dummy gate trench section 130 described later.

[0048] The well region 17 is a second conductive type region provided on the front surface side of the semiconductor substrate 10 relative to a drift region 18 described later. The well region 17 is an example of a well region provided on the edge side of the semiconductor device 100. The well region 17 is, for example, a P+ type. The well region 17 is formed in a predetermined range from the end of the active region on the side where the gate metal layer 50 is provided. The diffusion depth of the well region 17 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. Part of the regions of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side are formed in the well region 17. The bottoms of the ends of the gate trench portion 40 and the dummy trench portion 30 in the trench extension direction may be covered by the well region 17.

[0049] The contact hole 54 is formed above the emitter region 12 and the contact region 15 in the transistor section 70. The emitter region 12 and the contact region 15 are exposed in the contact hole 54. The contact hole 54 is not provided above the well regions 17 provided at both ends in the Y-axis direction. In this manner, one or more contact holes 54 are formed in the interlayer insulating film. The one or more contact holes 54 may be provided extending in the trench extension direction. Note that a plug region 11 (not shown) may be provided below the contact hole 54.

[0050] The plug region 11 may be provided below the contact hole 54. The plug region 11 may be provided below the contact hole 54 and above the contact region 15. The plug region 11 may be provided below the contact hole 54 and above the base region 14. The plug region 11 may be provided in the mesa portion 71 or in the mesa portion 81. The plug region 11 may be provided below the contact hole 54 and not above the emitter region 12. In this case, the plug region 11 may be provided discretely along the contact hole 54 in correspondence with the repeated structure of the emitter region 12 and the contact region 15. However, the plug region 11 may be provided below the contact hole 54 and above the emitter region 12. The plug region 11 may be provided in the mesa portion 81 so as to extend in the Y-axis direction along the contact hole 54.

[0051] The mesa portion 71 and the mesa portion 81 are mesa portions provided adjacent to the trench portion in a plane parallel to the front surface of the semiconductor substrate 10. The mesa portion is a portion of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and may be a portion from the front surface of the semiconductor substrate 10 to the deepest bottom of each trench portion. The extension portion of each trench portion may be one trench portion. In other words, the region sandwiched between the two extension portions may be the mesa portion.

[0052] The mesa portion 71 is provided in the transistor portion 70 adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40. The mesa portion 71 has a well region 17, an emitter region 12, a base region 14, and a contact region 15 on the front surface of the semiconductor substrate 10.

[0053] On the other hand, the mesa portion 81 is provided adjacent to the dummy trench portion 30 in the diode portion 80. The trench portion in the mesa portion 81 may be electrically connected to the emitter electrode 52 through the contact hole 56 and set to the emitter potential. That is, the trench portion provided in the diode portion 80 may be the dummy trench portion 30.

[0054] The mesa portion 81 has a well region 17 and a base region 14 on the front surface of the semiconductor substrate 10. The emitter electrode 52 is also disposed on the upper surface of the mesa portion 81. That is, the metal layer of the emitter electrode 52 may function as an anode electrode in the diode portion 80.

[0055] The base region 14 is a second conductivity type region provided on the front surface side of the semiconductor substrate 10 in the transistor portion 70. The base region 14 is, for example, a P-type. The base region 14 may be provided on both ends in the Y-axis direction of the mesa portion 71 on the front surface 21 of the semiconductor substrate 10. Note that FIG. 1A shows only one end of the base region 14 in the Y-axis direction.

[0056] The emitter region 12 is a region of a first conductivity type having a higher doping concentration than the drift region 18 described later in FIG. 1B. In this example, the emitter region 12 is, for example, an N+ type. For example, the dopant of the emitter region 12 is phosphorus (P) or arsenic (As). The emitter region 12 is provided in contact with the gate trench portion 40 on the front surface of the mesa portion 71. The emitter region 12 may be provided extending in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 to the other. The emitter region 12 is also provided below the contact hole 54. The emitter region 12 is connected to the emitter electrode 52 via the contact hole 54 provided penetrating the interlayer insulating film 38.

[0057] The emitter region 12 may extend to the dummy trench portion 30 and be in contact with the dummy trench portion 30. However, the emitter region 12 may terminate without reaching the dummy trench portion 30 and not be in contact with the dummy trench portion 30. The emitter region 12 in this example is not in contact with the dummy trench portion 30.

[0058] The contact region 15 is a region of a second conductivity type having a higher doping concentration than the base region 14. In this example, the contact region 15 is of P+ type, for example. An example of a dopant for the contact region 15 is boron (B). In this example, the contact region 15 is provided on the front surface 21 of the mesa portion 71. The contact region 15 may be provided in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 to the other. However, the contact region 15 may be separated from the gate trench portion 40 below the emitter region 12 in a portion where the emitter region 12 contacts the gate trench portion 40.

[0059] The contact region 15 may or may not be in contact with the gate trench portion 40. In addition, the contact region 15 may or may not be in contact with the dummy trench portion 30. In this example, the contact region 15 is in contact with the dummy trench portion 30 and the gate trench portion 40. The contact region 15 is also provided below the contact hole 54. The contact region 15 may also be provided in the mesa portion 81.

[0060] Fig. 1B is an example of an a-a' cross-sectional view in Fig. 1A. The a-a' cross-section is an XZ plane that extends from the transistor section 70 to the diode section 80 and passes through the emitter region 12 in the transistor section 70. In the a-a' cross-section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24. The emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.

[0061] The drift region 18 is a region of a first conductivity type provided in the semiconductor substrate 10. In this example, the drift region 18 is, for example, an N-type. The drift region 18 may be a region remaining in the semiconductor substrate 10 without other doped regions being formed therein. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.

[0062] The buffer region 20 is a region of a first conductivity type provided below the drift region 18. In this example, the buffer region 20 is, for example, an N-type. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer extending from the lower surface side of the base region 14 from reaching the collector region 22 of the second conductivity type and the cathode region 82 of the first conductivity type.

[0063] The collector region 22 is provided below the buffer region 20 in the transistor section 70. The collector electrode 24 is formed on the rear surface 23 of the semiconductor substrate 10. The collector electrode 24 is made of a conductive material such as a metal.

[0064] The base region 14 is a second conductivity type region provided above the drift region 18 in the mesa portion 71 and the mesa portion 81. The base region 14 is provided in contact with the gate trench portion 40. The base region 14 may be provided in contact with the dummy trench portion 30.

[0065] The emitter region 12 is provided in the mesa portion 71 between the base region 14 and the front surface 21. The emitter region 12 is provided in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30.

[0066] The plug region 11 is a region of a second conductivity type having a higher doping concentration than the contact region 15. In this example, the plug region 11 is of P++ type, for example. In this example, the plug region 11 is provided on the front surface 21. In the mesa portion 81, the plug region 11 is provided above the base region 14. The lower end of the plug region 11 may be shallower than the lower end of the emitter region 12. In the mesa portion 81, the plug region 11 may be provided extending in the Y-axis direction along the contact hole 54.

[0067] One or more gate trench portions 40 and one or more dummy trench portions 30 are provided on the front surface 21. Each trench portion is provided from the front surface 21 to the drift region 18. In a region where at least one of the emitter region 12, the base region 14, and the contact region 15 is provided, each trench portion also penetrates these regions to reach the drift region 18. The trench portion penetrating the doped region is not limited to a case where the trench portion is formed in the order of forming the doped region and then the trench portion. A case where the trench portion is formed and then the doped region is formed between the trench portions is also included in the case where the trench portion penetrates the doped region.

[0068] The gate trench portion 40 has a gate trench, a gate insulating film 42, and a gate conductive portion 44 formed on the front surface 21. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate insulating film 42 inside the gate trench. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front surface 21 by an interlayer insulating film 38. The potential of a gate electrode of an IGBT or the like is applied to the gate conductive portion 44.

[0069] The gate conductive portion 44 includes a region facing the adjacent base region 14 on the mesa portion 71 side, across the gate insulating film 42, in the depth direction of the semiconductor substrate 10. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel due to an electron inversion layer is formed in the surface layer of the interface of the base region 14 that contacts the gate trench.

[0070] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and is formed on the inner side of the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 is covered by an interlayer insulating film 38 on the front surface 21. The potential of an emitter electrode of an IGBT or the like is applied to the dummy conductive portion 34. The dummy conductive portion 34 may be at a floating potential.

[0071] The interlayer insulating film 38 is provided above the semiconductor substrate 10. An emitter electrode 52 is provided above the interlayer insulating film 38. The interlayer insulating film 38 is provided with one or more contact holes 54 for electrically connecting the emitter electrode 52 to the semiconductor substrate 10. Contact holes 55 and 56 may also be provided penetrating the interlayer insulating film 38.

[0072] The lower end portion 13 is the lower end of the emitter region 12 in the mesa portion 71, and is the lower end on the dummy trench portion 30 side. When the emitter region 12 reaches the dummy trench portion 30, the lower end portion 13 contacts the dummy trench portion 30.

[0073] At least a part of the contact region 15 is provided below the lower end 13 of the mesa portion 71. That is, the contact region 15 is provided deeper than the emitter region 12 and is provided so as to partially overlap with the emitter region 12. The contact region 15 in this example is provided extending from the dummy trench portion 30 to below the lower end 13 of the emitter region 12 in the trench arrangement direction. This makes it difficult for holes below the emitter region 12 to be directly extracted through the emitter region 12. This makes it difficult for an NPNP type parasitic thyristor from the emitter region 12 to the collector region 22 to be turned on, and latch-up of the semiconductor device 100 can be suppressed.

[0074] In the cross section of this example, the contact region 15 is separated from the gate trench portion 40 at the mesa portion 71. This allows the contact region 15 to avoid impeding the formation of an inversion layer on the side surface of the gate trench portion 40, making it easier for the semiconductor device 100 to operate stably.

[0075] The contact region 15 of this example is provided across both sides of the dummy trench portion 30 in the X-axis direction. In the manufacturing process of the contact region 15 of this example, a mask is provided on the semiconductor substrate 10, and the trench portion but The contact regions 15 may be ion implanted across the region to be provided. The dummy trenches 30 may be provided by etching the semiconductor substrate 10 after the contact regions 15 are provided.

[0076] For the purpose of miniaturizing the semiconductor device 100, the interval between the mesa portions 71 is shortened, that is, the process pitch is made finer. For example, when a diffusion region is provided in a silicon semiconductor substrate 10 by ion implantation, the dopant is likely to diffuse within a certain range. Due to the structure of the contact region 15 in this example, even if the process pitch is made finer, it is easy to manufacture the contact region 15 that extends to below the lower end portion 13 of the emitter region 12 and is separated from the gate trench portion 40. This makes it possible to provide a semiconductor device 100 that has high latch-up resistance without significantly affecting the electrical characteristics. However, the contact region 15 is arranged in the trench extension direction. The lower end of the emitter region 12 The effect of suppressing latch-up can be achieved as long as the contact region 15 is provided so as to be connected, and the embodiment is not limited to the embodiment in which the contact region 15 is in contact with the dummy trench portion 30 .

[0077] In the diode section 80, the buffer region 20 is laminated above the cathode region 82, and the drift region 18 is laminated above the buffer region 20. In the mesa section 81, the base region 14 is laminated above the drift region 18, and a PN junction is formed between the base region 14 and the drift region 18. The base region 14 is electrically connected to the emitter electrode 52 via a contact hole 54.

[0078] FIG. 1C is an example of a b-b' cross section in FIG. 1A. The b-b' cross section is an XZ plane that passes through the contact region 15 in the transistor section 70 without passing through the emitter region 12. In this example, the mesa section 71 in the transistor section 70 has the base region 14, the contact region 15, and the plug region 11 above the drift region 18. By providing the plug region 11, the RBSOA (reverse bias safe operating area) tolerance is improved. In the diode section 80, the mesa section 81 may have a structure similar to that in the example in FIG. 1B.

[0079] The contact region 15 extends from the gate trench portion 40 to the dummy trench portion 30. A contact hole 54 is provided above the contact region 15. Holes are extracted from the contact region 15 and the plug region 11 through the contact hole 54. The bottom end of the contact region 15 may be deeper than the bottom end of the plug region 11.

[0080] When the contact region 15 provided below the emitter region 12 and the contact region 15 in the cross section of this example are provided by the same process, the contact regions 15 are provided to the same depth. In this case, the contact region 15 is deeper than the emitter region 12. However, the contact region 15 may be provided to a different depth below the emitter region 12 than in other regions.

[0081] 1D shows an example of an enlarged view of the front surface 21 of the semiconductor device 100. The c-c' cross section shows the XZ plane passing through a first contact portion 151 described later. The d-d' cross section shows the XZ plane passing through a second contact portion 152 described later. The dashed line in the emitter region 12 indicates the boundary B between the second contact portion 152 and the base region 14 below the emitter region 12. The contact region 15 of this example has a first contact portion 151, a second contact portion 152, and a third contact portion 153.

[0082] The first contact portion 151 and the second contact portion 152 are provided in the mesa portion 71, extending from the first trench portion to below the lower end of the emitter region 12. The first trench portion in this example is a dummy trench portion 30, but may be a gate trench portion 40 or a dummy gate trench portion 130. Similarly, in other examples, even if the first trench portion is described as a dummy trench portion 30, it may be changed to a gate trench portion 40 or a dummy gate trench portion 130 as appropriate.

[0083] 1D, the first contact portion 151 and the second contact portion 152 have a step at the end on the gate trench portion 40 side. In this example, the step between the first contact portion 151 and the second contact portion 152 is formed to describe an arc like boundary B, but the shape of boundary B is not limited to this.

[0084] The first contact portion 151 is provided to extend further from the dummy trench portion 30 than the second contact portion 152 in the trench arrangement direction. The first contact portion 151 is located closer to the end of the emitter region 12 than the second contact portion 152 in the trench extension direction. The first contact portion 151 in this example contacts the gate trench portion 40 in the trench arrangement direction, but may be separated from the gate trench portion 40. The first contact portion 151 may be provided on the front surface 21 of the semiconductor substrate 10 on the side wall of the dummy trench portion 30.

[0085] The second contact portion 152 is located closer to the center of the emitter region 12 than the first contact portion 151 in the trench extension direction. The center of the emitter region 12 in the trench extension direction corresponds to the position of the dd' cross section. The second contact portion 152 may be provided on the front surface 21 of the semiconductor substrate 10, on the side wall of the dummy trench portion 30.

[0086] The third contact portion 153 is provided in a region where the emitter region 12 is not formed when viewed from above. The third contact portion 153 may be provided on the front surface 21, extending from the dummy trench portion 30 to the gate trench portion 40. The third contact portion 153 in this example is provided on the front surface 21 alternately with the emitter regions 12 along the trench extension direction.

[0087] The first contact portion 151, the second contact portion 152, and the third contact portion 153 may have the same doping concentration. That is, the first contact portion 151, the second contact portion 152, and the third contact portion 153 may be formed simultaneously by the same ion implantation process.

[0088] Figure 1E shows an example of an enlarged view of the bottom end of emitter region 12. This view corresponds to an XY plane at a deeper position than the XY plane shown in Figure 1D.

[0089] The first contact portion 151 is in contact with the gate trench portion 40 below the emitter region 12. The first contact portion 151 is in contact with the base region 14, the second contact portion 152, and the third contact portion 153.

[0090] The second contact portion 152 is spaced apart from the gate trench portion 40 below the emitter region 12. The second contact portion 152 is located below the emitter region 12 closer to the center of the emitter region 12 in the trench extension direction than the first contact portion 151. The second contact portion 152 of this example is arc-shaped with the base region 14 at the boundary B in top view. Condition It is adjacent to.

[0091] The base region 14 is provided below the emitter region 12 and in contact with the second contact portion 152 and the third contact portion 153. Furthermore, the lower end of the emitter region 12 is in contact with the base region 14 at the center of the emitter region 12 in the trench extension direction.

[0092] Fig. 1F is an example of a cc' cross section in Fig. 1D. The cc' cross section is an XZ plane passing through the first contact portion 151 in the transistor portion 70.

[0093] The emitter region 12 extends from the gate trench portion 40 to the dummy trench portion 30 side, over the contact hole 54, in the trench arrangement direction. This makes it easier for a current to flow from the emitter region 12 through the contact hole 54. The emitter region 12 in this example extends from the gate trench portion 40 to the dummy trench portion 30 side in the trench arrangement direction, and terminates without reaching the dummy trench portion 30. However, the emitter region 12 may be provided by extending from the gate trench portion 40 to the dummy trench portion 30 in the trench arrangement direction.

[0094] The first contact portion 151 extends in the trench arrangement direction from the dummy trench portion 30, which is the first trench portion, beyond the contact hole 54. The first contact portion 151 is provided on the front surface 21 of the semiconductor substrate 10, on the side wall of the dummy trench portion 30. The first contact portion 151 has an upper region 92 and a lower region 94.

[0095] The upper region 92 is a region in the semiconductor substrate 10 that has the same depth as the emitter region 12. As an example, the depth of the upper region 92 is 0.5 μm. However, the depth of the upper region 92 is not limited to this. When the emitter region 12 extends from the gate trench portion 40 to the dummy trench portion 30 and reaches the dummy trench portion 30, the upper region 92 is not provided in the cross section where the emitter region 12 is exposed on the front surface 21 of the semiconductor substrate 10. For example, the doping concentration of the upper region 92 is 5E19 / cm3 Above, 2E20 / cm 3 Here, E stands for a power of 10, for example, 5E19 / cm 3 is 5 x 10 19 / cm 3 means...

[0096] The lower region 94 is provided in a region of the semiconductor substrate 10 that is deeper than the emitter region 12. The lower region 94 extends beyond the lower end portion 13 of the emitter region 12 from the dummy trench portion 30 toward the gate trench portion 40. For example, the doping concentration of the lower region 94 is 1E19 / cm 3 Above, 1E20 / cm 3 The following is the result.

[0097] The first contact portion 151 is in contact with the lower end of the emitter region 12. That is, the upper end of the lower region 94 is in contact with the lower end of the emitter region 12. The first contact portion 151 is also in contact with the lower end portion 13.

[0098] The width Wc is the width of the contact region 15 in the trench arrangement direction. The width Wc is the width measured from the center of the dummy trench portion 30 to the end of the contact region 15 on the gate trench portion 40 side. In other words, the width Wc corresponds to the maximum reach position of the lower region 94 on the gate trench portion 40 side, measured from the center of the dummy trench portion 30. The width Wc may be 1.2 μm or less, or may be 1.1 μm or less.

[0099] Here, the width of the upper region 92 in the trench arrangement direction may be in the range of 15% to 40% of the mesa width Wm. The width of the lower region 94 in the trench arrangement direction may be in the range of 30% to 70% of the mesa width Wm. Furthermore, the width of the portion where the lower region 94 overlaps with the emitter region 12 in the trench arrangement direction may be in the range of 0% to 30% of the mesa width Wm, and more preferably in the range of 10% to 20%.

[0100] The thickness Dc is the thickness of the contact region 15 in the depth direction of the semiconductor substrate 10. The thickness Dc is greater than the depth of the lower end of the emitter region 12 and less than the depth Db of the base region 14. For example, the thickness Dc is 0.5 μm or more and 2.0 μm or less. The thickness of the upper region 92 may be in the range of 0.3 μm or more and 0.8 μm or less. The thickness of the lower region 94 may be in the range of 0.3 μm or more and 1.1 μm or less.

[0101] Fig. 1G is an example of a d-d' cross-sectional view in Fig. 1D. The d-d' cross-section is an XZ plane passing through the second contact portion 152 in the transistor portion 70. In this example, differences from the c-c' cross-section in Fig. 1F will be particularly described. Other points may be the same as the c-c' cross-section in Fig. 1F.

[0102] The second contact portion 152 extends in the trench arrangement direction from the dummy trench portion 30, which is the first trench portion, beyond the contact hole 54. The second contact portion 152 is provided on the front surface 21 of the semiconductor substrate 10, on the side wall of the dummy trench portion 30. The second contact portion 152 has an upper region 96 and a lower region 98.

[0103] The upper region 96 is a region in the semiconductor substrate 10 that has the same depth as the emitter region 12. As an example, the depth of the upper region 96 is 0.5 μm. However, the depth of the upper region 96 is not limited to this. When the emitter region 12 extends from the gate trench portion 40 to the dummy trench portion 30 and reaches the dummy trench portion 30, the upper region 96 is not provided in the cross section where the emitter region 12 is exposed on the front surface 21 of the semiconductor substrate 10. For example, the doping concentration of the upper region 96 is 5E19 / cm 3 Above, 2E20 / cm 3 The following is the result.

[0104] The lower region 98 is provided in a region of the semiconductor substrate 10 that is deeper than the emitter region 12. The lower region 98 extends beyond the lower end 13 of the emitter region 12 from the dummy trench portion 30 toward the gate trench portion 40. The lower end 13 is the end of the lower end of the emitter region 12 on the dummy trench portion 30 side. For example, the doping concentration of the lower region 98 is 1E19 / cm 3 Above, 1E20 / cm 3 The following is the result.

[0105] The second contact portion 152 is in contact with the lower end of the emitter region 12. That is, the upper end of the lower region 98 is in contact with the lower end of the emitter region 12. The second contact portion 152 is also in contact with the lower end portion 13.

[0106] The width Ws is the distance between the contact region 15 and the gate trench portion 40 in the trench arrangement direction. The width Ws may be provided so that a channel can be formed at the end of the gate trench portion 40. The width Ws in this example indicates the distance between the second contact portion 152 and the gate trench portion 40 in the trench arrangement direction. In one example, the width Ws is 0.6 μm or more. The width Ws may be in the range of 10% to 50% of the mesa width Wm.

[0107] The size of the step on the gate trench portion 40 side of the first contact portion 151 and the second contact portion 152 in the trench extension direction may be 10% or more and 50% or less of the mesa width Wm of the mesa portion 71. When the first contact portion 151 contacts the gate trench portion 40 as in this example, the size of the step in the trench arrangement direction of the first contact portion 151 and the second contact portion 152 is equal to the width Ws.

[0108] 2 is a diagram for explaining an example of a manufacturing method of the semiconductor device 100. In this diagram, a mask 155 for forming the contact region 15 is shown by a dashed line in an enlarged view of the front surface 21 of the semiconductor device 100 shown in FIG. 1D. The mask 155 has a thinning region 156.

[0109] The thinned-out region 156 is formed by thinning out the emitter region 12 at the center in the trench extension direction. protruding outwards By providing the thinning region 156, a step can be formed between the first contact portion 151 and the second contact portion 152 on the gate trench portion 40 side when the dopant is diffused by annealing after the ion implantation.

[0110] FIG. 3 shows an example of a top view of the semiconductor device 100 in which the contact hole 54 is not yet opened.

[0111] The non-connection region 59 is a region where the contact hole 54 is not opened and the emitter electrode 52 is not electrically connected to the contact region 15 on the front surface 21. For example, the non-connection region 59 is an unopened region where the contact hole 54 is not formed in the interlayer insulating film 38 due to oxide film etching failure caused by particles, foreign matter, etc. The non-connection region 59 may also be a region where the contact region 15 on the front surface 21 is not formed due to resist residue, etc.

[0112] In this example, the hole current that would have been drawn out in the non-connection region 59 flows through the contact region 15 and is drawn out via the contact hole 54 above another neighboring contact region 15. That is, the hole current does not flow through the base region 14 below the emitter region 12, but flows through the contact region 15 that has a lower resistance to holes than the base region 14, so that latch-up can be suppressed. This suppresses switching breakdown caused by process defects. Therefore, it is possible to provide a semiconductor device 100 having a redundant element structure that is resistant to process defects.

[0113] Furthermore, the semiconductor device 100 of this example can extract holes via the first contact portion 151 and the second contact portion 152 provided below the emitter region 12, which further facilitates suppression of latch-up. Since the semiconductor device 100 of this example is provided with the first contact portion 151 and the second contact portion 152 below the emitter region 12, the emitter region 12 may be extended to the dummy trench portion 30, which is the first trench portion.

[0114] Fig. 4A shows an example of a top view of the semiconductor device 100. This example differs from Fig. 1A in that the emitter region 12 is provided in contact with the dummy trench portion 30. This example will be described in particular with respect to the differences from Fig. 1A.

[0115] In this example, the emitter region 12 extends in the trench arrangement direction from the gate trench portion 40 to the dummy trench portion 30. The emitter region 12 and the contact region 15 are provided on the front surface 21 of the semiconductor substrate 10 so as to be alternately in contact with the gate trench portion 40 and the dummy trench portion 30 in the trench extension direction.

[0116] The plug region 11 may be provided in a region sandwiched between the contact regions 15 of the mesa portion 71 in the trench arrangement direction. The plug region 11 does not have to be provided in a region sandwiched between the emitter regions 12 of the mesa portion 71 in the trench arrangement direction. However, the plug region 11 may be provided in a region sandwiched between the emitter regions 12 of the mesa portion 71 in the trench arrangement direction. The plug region 11 may be provided in the mesa portion 81, extending in the trench extension direction.

[0117] Fig. 4B is an example of an e-e' cross section in Fig. 4A. The e-e' cross section is an XZ plane that extends from the transistor portion 70 to the diode portion 80 and passes through the emitter region 12 in the transistor portion 70. Note that the XZ cross section that extends from the transistor portion 70 to the diode portion 80 and passes through the second contact portion 152 in the transistor portion 70 is the same as Fig. 1C.

[0118] In this example, the second contact portion 152 is provided below the emitter region 12 in the mesa portion 71. Similarly, in another cross section, the first contact portion 151 is provided below the emitter region 12. This allows holes below the emitter region 12 to be extracted through the first contact portion 151 and the second contact portion 152, thereby suppressing latch-up.

[0119] 5A shows an example of a top view of a modified semiconductor device 100. In this example, differences from FIG. 1A will be particularly described. The semiconductor device 100 of this example includes a dummy gate trench portion 130 that does not contact the emitter region 12 as a first trench portion.

[0120] The dummy gate trench portion 130 is a trench portion that is set to the gate potential and does not contact the emitter region 12. That is, although the dummy gate trench portion 130 is set to the gate potential, it does not form a channel near the sidewall. In order to set the dummy gate trench portion 130 to the gate potential, the dummy gate trench portion 130 extends in the Y-axis direction to a region where the gate metal layer 50 is provided. The dummy gate trench portion 130 is connected to the gate metal layer 50 via a contact hole 58 and is set to the gate potential.

[0121] Although the dummy gate trench portion 130 is set to the gate potential, it is not in contact with the emitter region 12, so that a channel due to an inversion layer of the first conductivity type is not formed on the sidewall of the dummy gate trench portion 130. The dummy gate trench portion 130 makes it easier to attract carriers to the mesa portion 71, Dummy trench section 30 The dummy gate trench portion 130 and the dummy trench portion 30 have different properties such as gate capacitance. Therefore, by using the dummy gate trench portion 130 and the dummy trench portion 30 in combination, it is possible to adjust the threshold voltage, saturation current, electric field concentration, gate capacitance, and the like in the semiconductor device 100.

[0122] On the front surface 21 of the semiconductor substrate 10, the gate trench portion 40 in this example has a U-shaped structure, and the dummy gate trench portion 130 has an I-shaped structure. However, the structures of the gate trench portion 40 and the dummy gate trench portion 130 are not limited to these structures as long as the desired arrangement ratio can be achieved.

[0123] In this example, in the diode section 80 Dummy trench section 30 is similar to the structure in FIG. 1A. That is, Dummy trench section 30 is connected to the emitter electrode 52 via a contact hole 56 and is set to the emitter potential.

[0124] Fig. 5B is an example of an f-f' cross section in Fig. 5A. The f-f' cross section is an XZ plane that extends from the transistor section 70 to the diode section 80 and passes through the emitter region 12 in the transistor section 70. The dummy gate trench section 130 has a second gate insulating film 132 and a second gate conductive section 134. The semiconductor device 100 of this example has an accumulation region 16 between the drift region 18 and the base region 14.

[0125] The accumulation region 16 is a region of a first conductivity type provided between the base region 14 and the drift region 18. In this embodiment, the accumulation region 16 is, for example, an N+ type. The accumulation region 16 is provided in the transistor section 70 and the diode section 80. This allows the semiconductor device 100 to avoid mask misalignment of the accumulation region 16. The accumulation region 16 is provided in contact with the gate trench section 40. The accumulation region 16 may or may not be in contact with the dummy trench section 30.

[0126] The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18. The dose of the ion implantation of the accumulation region 16 is 1E12 cm -2 Above, 1E13cm -2 The ion implantation dose of the accumulation region 16 may be 3E12 cm -2 Above, 6E12cm -2By providing the accumulation region 16, the carrier injection enhancement effect can be improved, and the on-voltage of the transistor section 70 can be reduced.

[0127] 1B in that the dummy gate trench portion 130 of the semiconductor device 100 is set to the emitter potential. The lower end of the emitter region 12 Therefore, the semiconductor device 100 can suppress latch-up due to the structure of the contact region 15, regardless of the potential of the dummy gate trench portion 130.

[0128] 6A shows an example of a top view of a modified semiconductor device 100. The semiconductor device 100 of this example includes a contact trench portion 60.

[0129] The contact trench portion 60 is provided extending from the front surface 21 in the depth direction of the semiconductor substrate 10. The contact trench portion 60 electrically connects the emitter electrode 52 and the semiconductor substrate 10. The contact trench portion 60 is provided extending in the trench extension direction. The contact trench portion 60 in this example is arranged in a stripe shape along the gate trench portion 40 and the dummy trench portion 30.

[0130] The contact trench portion 60 is formed above the emitter region 12 and the contact region 15 in the transistor portion 70. The contact trench portion 60 is formed above the base region 14 in the diode portion 80. The contact trench portion 60 is not provided above the well regions 17 provided at both ends in the Y-axis direction. One or more contact trench portions 60 may be provided extending in the trench extension direction.

[0131] The emitter region 12 is provided in contact with the gate trench portion 40. The emitter region 12 is provided extending from the gate trench portion 40 to the side wall of the contact trench portion 60 in the trench arrangement direction. The emitter region 12 does not have to be provided between the dummy trench portion 30 and the contact trench portion 60.

[0132] The emitter regions 12 and the contact regions 15 may be alternately arranged in the trench extension direction between the gate trench portion 40 and the contact trench portion 60. In the trench extension direction, the width of the contact regions 15 may be larger than the width of the emitter regions 12. In the trench extension direction, the width of the emitter regions 12 may be 0.6 μm or more and 1.6 μm or less. By appropriately controlling the ratio of the emitter regions 12 to the contact regions 15, latch-up can be easily suppressed.

[0133] The plug region 11 may be provided in a region adjacent to the contact region 15 of the mesa portion 71 in the trench arrangement direction. The plug region 11 does not have to be provided in a region adjacent to the emitter region 12 of the mesa portion 71 in the trench arrangement direction. However, the plug region 11 may be provided in a region adjacent to the emitter region 12 of the mesa portion 71 in the trench arrangement direction. The plug region 11 may be provided in the mesa portion 81, extending along the contact trench portion 60 in the trench extension direction.

[0134] 6B is an example of a cross-sectional view taken along line g-g' in FIG.

[0135] The contact trench portion 60 is provided so as to extend toward the back surface 23 of the semiconductor substrate 10 further than the front surface 21. The contact trench portion 60 of this example is provided so as to extend toward the back surface 23 of the semiconductor substrate 10 further than the emitter region 12. That is, the lower end of the contact trench portion 60 of this example is deeper than the lower end of the emitter region 12. The lower end of the contact trench portion 60 of this example is shallower than the lower end of the second contact portion 152. The contact trench portion 60 of this example has a plug 62 and a barrier metal layer 64.

[0136] The plug 62 is a conductive material provided inside the contact trench portion 60. The plug 62 may be made of the same material as the emitter electrode 52 or a different material. The plug 62 may include a material such as tungsten.

[0137] A barrier metal layer 64 is provided below the plug 62. In this example, the barrier metal layer 64 is provided between the plug 62 and the emitter region 12. The barrier metal layer 64 may include a material such as titanium nitride.

[0138] The emitter region 12 is provided in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30. The emitter region 12 is provided extending from the gate trench portion 40 to the side wall of the contact trench portion 60 in the trench arrangement direction. Therefore, the lower end portion 13 is located on the side wall of the contact trench portion 60 between the gate trench portion 40 and the contact trench portion 60 in the trench arrangement direction.

[0139] At least a portion of the second contact portion 152 is provided below the lower end portion 13 of the mesa portion 71. The second contact portion 152 of this example is provided extending from the dummy trench portion 30 to below the lower end portion 13 of the emitter region 12 in the trench arrangement direction. The second contact portion 152 may or may not extend from the dummy trench portion 30 beyond the contact trench portion 60 in the trench arrangement direction.

[0140] The trench bottom region 19 is a second conductive type region provided below the dummy trench portion 30 and the gate trench portion 40. In this example, the trench bottom region 19 covers the lower ends of the dummy trench portion 30 and the gate trench portion 40. The doping concentration of the trench bottom region 19 may be lower than that of the base region 14. The trench bottom region 19 is provided between the drift region 18a and the drift region 18b. The provision of the trench bottom region 19 improves the avalanche resistance. Note that although an embodiment in which the semiconductor device 100 includes the trench bottom region 19 may be described, the trench bottom region 19 may be omitted.

[0141] The drift region 18a is provided between the base region 14 and the trench bottom region 19 in the mesa portion 71 and the mesa portion 81. The drift region 18b is provided below the trench bottom region 19. The doping concentrations of the drift region 18a and the drift region 18b may be the same.

[0142] The plug region 11 may be provided in contact with the lower end of the contact trench portion 60. The plug region 11 may be provided on the side wall of the contact trench portion 60. In this example, the plug region 11 covers the lower end of the contact trench portion 60 and a part of the side wall of the contact trench portion 60. The lower end of the plug region 11 may be shallower than the lower end of the base region 14. The plug region 11 may be formed by ion implantation into the lower end of a groove for forming the contact trench portion 60.

[0143] FIG. 7A shows an example of a top view of a semiconductor device 100 according to a modified example. The semiconductor device 100 of this example is a case where a first trench portion adjacent to a gate trench portion 40 is the gate trench portion 40, and has a staggered structure. The semiconductor device 100 of this example does not include a diode portion 80, but may include a diode portion 80. The semiconductor device 100 has multiple adjacently provided diode portions 80. Number The gate trench portion 40 is provided adjacent to each other. The gate trench portions 40 may be connected to each other by a connection portion 43.

[0144] Adjacent gate trench portions 40 are in contact with the emitter region 12 at different positions in the trench extension direction. That is, the semiconductor device 100 has a staggered structure and includes emitter regions 12 arranged alternately. In this case, each of adjacent gate trench portions 40 has both a portion that becomes a gate trench portion and a portion that becomes a first trench portion. That is, in the mesa portion between adjacent gate trench portions 40, there is an emitter region 12 (first emitter region) that contacts one gate trench portion 40 and is spaced from the other gate trench portion 40, and an emitter region 12 (second emitter region) that is spaced from one gate trench portion 40 and contacts the other gate trench portion 40.

[0145] The contact region 15 is provided in a region including below the lower end 13 of the first emitter region on the other gate trench portion 40 side and below the lower end 13 of the second emitter region on one gate trench portion 40 side. In the trench extension direction of the gate trench portion 40, the first emitter region and the second emitter region are provided alternately with the contact region 15 therebetween.

[0146] 7B is an example of a cross-sectional view taken along line h-h' in FIG. 7A. The semiconductor device 100 of this example includes a contact trench portion 60 shallower than the emitter region 12, and the emitter region 12 provided at both ends of the contact trench portion 60 in the trench arrangement direction, but is not limited thereto. That is, the semiconductor device 100 may include a contact trench portion 60 deeper than the emitter region 12, or may include an emitter region 12 provided on one side of the contact trench portion 60. The semiconductor device 100 may or may not include a trench bottom region 19.

[0147] The plug region 11 may be provided in a region adjacent to the contact region 15. The plug region 11 may be provided between the contact trench portion 60 and the contact region 15. The plug region 11 may be sandwiched between the contact regions 15 in the trench arrangement direction. The plug region 11 in this example is not provided in a region adjacent to the emitter region 12. However, the plug region 11 may be provided in a region adjacent to the emitter region 12. In this case, the plug region 11 may or may not penetrate the emitter region 12. When the plug region 11 does not penetrate the emitter region 12, the plug region 11 may be in contact with the contact region 15 in another XZ cross section.

[0148] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included in the technical scope of the present invention.

[0149] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically indicated as "before," "prior to," etc., and may be realized in any order unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is explained using "first," "next," etc. for convenience, it does not mean that it is essential to perform the process in this order. [Explanation of symbols]

[0150] 10 semiconductor substrate, 11 plug region, 12 emitter region, 13 bottom end, 14 base region, 15 contact region, 16 accumulation region, 17 well region, 18 drift region, 19 trench bottom region, 20 buffer region, 21 front surface, 22 collector region, 23 back surface, 24 contact region a gate insulating film, a gate conductive portion, a gate metal layer, and an emitter electrode, a gate insulating film, and a gate insulating layer, and a gate insulating layer formed on the gate electrode, the gate insulating film and the gate insulating layer being electrically connected to each other; pole, 54 contact hole, 55 contact hole, 56 contact hole, 58 contact hole, 59 non-connection region, 60 contact trench portion, 62 plug, 64 barrier metal layer, 70 transistor portion, 71 mesa portion, 80 diode portion, 81 mesa portion, 82 cathode region, 92 upper region, 94 lower region, 96 upper region, 98 lower region, 100 semiconductor device, 130 dummy gate trench portion, 132 second gate insulating film, 134 second gate conductive portion, 151 first contact portion, 152 second contact portion, 153 third contact portion, 155 mask, 156 thinning region

Claims

1. A semiconductor device including a gate trench portion and a first trench portion adjacent to the gate trench portion, a drift region of a first conductivity type provided in a semiconductor substrate; a second conductivity type base region provided above the drift region; an emitter region of a first conductivity type provided above the base region and having a doping concentration higher than that of the drift region; a contact region of a second conductivity type provided above the base region and having a doping concentration higher than that of the base region; Equipped with the contact region has a first contact portion and a second contact portion extending from the first trench portion to below a lower end of the emitter region in a mesa portion between the gate trench portion and the first trench portion, the first contact portion is provided so as to extend from the first trench portion further than the second contact portion in a trench arrangement direction; A sidewall of the gate trench portion contacts the emitter region and the contact region on the front surface of the semiconductor substrate. Semiconductor device.

2. A semiconductor device comprising a gate trench portion and a first trench portion adjacent to the gate trench portion, a drift region of a first conductivity type provided in a semiconductor substrate; a second conductivity type base region provided above the drift region; an emitter region of a first conductivity type provided above the base region and having a doping concentration higher than that of the drift region; a contact region of a second conductivity type provided above the base region and having a doping concentration higher than that of the base region; Equipped with the contact region has a first contact portion and a second contact portion extending from the first trench portion to below a lower end of the emitter region in a mesa portion between the gate trench portion and the first trench portion, the first contact portion is provided so as to extend from the first trench portion further than the second contact portion in a trench arrangement direction; The first contact portion and the second contact portion are provided below the emitter region and below a contact hole for connecting the front surface of the semiconductor substrate to an emitter electrode. Semiconductor device.

3. A semiconductor device comprising a gate trench portion and a first trench portion adjacent to the gate trench portion, a drift region of a first conductivity type provided in a semiconductor substrate; a second conductivity type base region provided above the drift region; an emitter region of a first conductivity type provided above the base region and having a doping concentration higher than that of the drift region; a contact region of a second conductivity type provided above the base region and having a doping concentration higher than that of the base region; Equipped with the contact region has a first contact portion and a second contact portion extending from the first trench portion to below a lower end of the emitter region in a mesa portion between the gate trench portion and the first trench portion, the first contact portion is provided so as to extend from the first trench portion further than the second contact portion in a trench arrangement direction; The second contact portion is located below the emitter region and closer to a center portion of the emitter region in a trench extension direction than the first contact portion. Semiconductor device.

4. The first contact portion and the second contact portion are in contact with a lower end of the emitter region. The semiconductor device according to claim 1 .

5. At a center portion of the emitter region in the trench extension direction, a lower end of the emitter region is in contact with the base region. The semiconductor device according to claim 1 .

6. A semiconductor device comprising a gate trench portion and a first trench portion adjacent to the gate trench portion, a drift region of a first conductivity type provided in a semiconductor substrate; a second conductivity type base region provided above the drift region; an emitter region of a first conductivity type provided above the base region and having a doping concentration higher than that of the drift region; a contact region of a second conductivity type provided above the base region and having a doping concentration higher than that of the base region; Equipped with the contact region has a first contact portion and a second contact portion extending from the first trench portion to below a lower end of the emitter region in a mesa portion between the gate trench portion and the first trench portion, the first contact portion is provided so as to extend from the first trench portion further than the second contact portion in a trench arrangement direction; the first contact portion is in contact with the gate trench portion below the emitter region, The second contact portion is located below the emitter region and is spaced apart from the gate trench portion. Semiconductor device.

7. the second contact portion is spaced from the gate trench portion by 0.6 μm or more in the trench arrangement direction; The semiconductor device according to claim 6.

8. A semiconductor device comprising a gate trench portion and a first trench portion adjacent to the gate trench portion, a drift region of a first conductivity type provided in a semiconductor substrate; a second conductivity type base region provided above the drift region; an emitter region of a first conductivity type provided above the base region and having a doping concentration higher than that of the drift region; a contact region of a second conductivity type provided above the base region and having a doping concentration higher than that of the base region; Equipped with the contact region has a first contact portion and a second contact portion extending from the first trench portion to below a lower end of the emitter region in a mesa portion between the gate trench portion and the first trench portion, the first contact portion is provided so as to extend from the first trench portion further than the second contact portion in a trench arrangement direction; The size of a step between the first contact portion and the second contact portion in the trench arrangement direction is 10% or more and 50% or less of a mesa width of the mesa portion. Semiconductor device.

9. The first contact portion and the second contact portion are provided on a sidewall of the first trench portion on the front surface of the semiconductor substrate. The semiconductor device according to claim 1 .

10. an interlayer insulating film provided above the semiconductor substrate; The emitter region is connected to an emitter electrode via a contact hole provided through the interlayer insulating film. The semiconductor device according to claim 1 .

11. The emitter region extends from the gate trench portion beyond the contact hole in the trench arrangement direction. The semiconductor device according to claim 10.

12. The emitter region extends from the gate trench portion in the trench arrangement direction and terminates without reaching the first trench portion. The semiconductor device according to claim 11.

13. A semiconductor device comprising: a gate trench portion; and a first trench portion adjacent to the gate trench portion, a drift region of a first conductivity type provided in a semiconductor substrate; a second conductivity type base region provided above the drift region; an emitter region of a first conductivity type provided above the base region and having a doping concentration higher than that of the drift region; a contact region of a second conductivity type provided above the base region and having a doping concentration higher than that of the base region; Equipped with the contact region has a first contact portion and a second contact portion extending from the first trench portion to below a lower end of the emitter region in a mesa portion between the gate trench portion and the first trench portion, the first contact portion is provided so as to extend from the first trench portion further than the second contact portion in a trench arrangement direction; an interlayer insulating film provided above the semiconductor substrate; the emitter region is connected to an emitter electrode via a contact hole provided through the interlayer insulating film; the emitter region extends from the gate trench portion beyond the contact hole in the trench arrangement direction, The second contact portion extends from the first trench portion beyond the contact hole in the trench arrangement direction. Semiconductor device.

14. A semiconductor device comprising: a gate trench portion; and a first trench portion adjacent to the gate trench portion, a drift region of a first conductivity type provided in a semiconductor substrate; a second conductivity type base region provided above the drift region; an emitter region of a first conductivity type provided above the base region and having a doping concentration higher than that of the drift region; a contact region of a second conductivity type provided above the base region and having a doping concentration higher than that of the base region; Equipped with the contact region has a first contact portion and a second contact portion extending from the first trench portion to below a lower end of the emitter region in a mesa portion between the gate trench portion and the first trench portion, the first contact portion is provided so as to extend from the first trench portion further than the second contact portion in a trench arrangement direction; The contact region has third contact portions provided alternately with the emitter regions along a trench extension direction on the front surface of the semiconductor substrate. Semiconductor device.

15. A semiconductor device comprising: a gate trench portion; and a first trench portion adjacent to the gate trench portion, a drift region of a first conductivity type provided in a semiconductor substrate; a second conductivity type base region provided above the drift region; an emitter region of a first conductivity type provided above the base region and having a doping concentration higher than that of the drift region; a contact region of a second conductivity type provided above the base region and having a doping concentration higher than that of the base region; Equipped with the contact region has a first contact portion and a second contact portion extending from the first trench portion to below a lower end of the emitter region in a mesa portion between the gate trench portion and the first trench portion, the first contact portion is provided so as to extend from the first trench portion further than the second contact portion in a trench arrangement direction; The first trench portion is a dummy trench portion set to an emitter potential. Semiconductor device.

16. A semiconductor device comprising: a gate trench portion; and a first trench portion adjacent to the gate trench portion, a drift region of a first conductivity type provided in a semiconductor substrate; a second conductivity type base region provided above the drift region; an emitter region of a first conductivity type provided above the base region and having a doping concentration higher than that of the drift region; a contact region of a second conductivity type provided above the base region and having a doping concentration higher than that of the base region; Equipped with the contact region has a first contact portion and a second contact portion extending from the first trench portion to below a lower end of the emitter region in a mesa portion between the gate trench portion and the first trench portion, the first contact portion is provided so as to extend from the first trench portion further than the second contact portion in a trench arrangement direction; the first trench portion includes a dummy gate trench portion that is set to a gate potential and does not contact the emitter region; Semiconductor device.

17. The first trench portion is a gate trench portion set to a gate potential. The semiconductor device according to claim 1 .

18. the emitter region has a first emitter region in the mesa portion, the first emitter region being in contact with the gate trench portion and spaced apart from the first trench portion; The contact region is provided in the mesa portion below a lower end of the first emitter region on the first trench portion side. The semiconductor device according to claim 17.

19. A semiconductor device comprising: a gate trench portion; and a first trench portion adjacent to the gate trench portion, a drift region of a first conductivity type provided in a semiconductor substrate; a second conductivity type base region provided above the drift region; an emitter region of a first conductivity type provided above the base region and having a doping concentration higher than that of the drift region; a contact region of a second conductivity type provided above the base region and having a doping concentration higher than that of the base region; Equipped with the contact region has a first contact portion and a second contact portion extending from the first trench portion to below a lower end of the emitter region in a mesa portion between the gate trench portion and the first trench portion, the first contact portion is provided so as to extend from the first trench portion further than the second contact portion in a trench arrangement direction; the first trench portion is a gate trench portion set to a gate potential, the emitter region has a first emitter region in the mesa portion, the first emitter region being in contact with the gate trench portion and spaced apart from the first trench portion; the contact region is provided in the mesa portion below a lower end of the first emitter region on the first trench portion side, the emitter region has a second emitter region in the mesa portion, the second emitter region being in contact with the first trench portion and spaced apart from the gate trench portion; The contact region is also provided below a lower end of the second emitter region on the gate trench portion side in the mesa portion. Semiconductor device.

20. The first emitter region and the second emitter region are provided alternately in the trench extension direction of the gate trench portion.

20. The semiconductor device according to claim 19.

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