Image sensor

Abstract

To provide an imaging element capable of achieving local high-frame rate photographing or local high-resolution photographing for each imaging region, so as to improve the image quality of the whole screen.SOLUTION: An imaging element comprises: a pixel array divided into pixel blocks and controlled; and a signal reading circuit consisting of column reading circuits. The column reading circuit comprises: an input changeover switch that selects any one pixel signal or sequentially selects all pixel signals regarding pixel signals output from respective pixels of the pixel block during one frame according to a mode selection signal given for each pixel block; an analog integrator that samples and integrates the pixel signal which is input via the input changeover switch at a number of times corresponding to the number of pixels of the pixel block; and an ADC that converts an output of the analog integrator into a digital signal.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an imaging device for acquiring a video signal. [Background technology]

[0002] Conventionally, it has been proposed to provide an image sensor with an operation mode specialized for a particular imaging performance such as frame rate or resolution (for example, Patent Document 1). There is a shooting technique that uses such an image sensor to select an optimum operation mode according to the characteristics of the shooting scene, thereby improving the image quality of the acquired video signal. For example, by selecting a mode adapted to the shooting scene, such as shooting in a high frame rate / low resolution mode when shooting a fast-moving subject, or shooting in a low frame rate / high resolution mode when shooting a high-definition subject with little movement, it is possible to substantially improve image quality. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-141405 A Summary of the Invention [Problem to be solved by the invention]

[0004] When capturing wide-field images such as 360° video, it is expected that multiple scenes with different characteristics will be captured simultaneously on the same captured screen. In this case, for example, if capturing in high frame rate mode is selected to match a fast-moving subject on the screen, the definition of a stationary high-definition subject captured simultaneously on the same screen will decrease. Conversely, if capturing in high resolution mode is selected to match a high-definition subject on the screen, the fast-moving subject will be blurred, making it difficult to capture its movement.

[0005] Therefore, in consideration of the above-mentioned problems, an object of the present invention is to provide an imaging element that realizes local high frame rate shooting or high resolution shooting for each imaging area, thereby improving image quality across the entire screen. [Means for solving the problem]

[0006] In order to solve the above problems, an image sensor according to the present invention is an image sensor comprising a pixel array which is divided into pixel blocks each consisting of a plurality of adjacent pixels and controlled, and a signal readout circuit which is made up of a column readout circuit corresponding to a pixel block column of the pixel block, wherein the column readout circuit is provided for each of the pixel blocks. , choose between high resolution readout or high frame rate readout The device is characterized by having an input selector switch that selects one of the pixel signals output from each pixel of the pixel block during one frame or selects all of the pixel signals in sequence in response to a mode selection signal, an analog integrator that samples and integrates the pixel signals input via the input selector switch a number of times corresponding to the number of pixels in the pixel block, and an ADC (analog-to-digital converter) that converts the output of the analog integrator into a digital signal.

[0007] It is also preferable that the column readout circuit of the imaging device further performs correlated double sampling, which subtracts a reset level output of a pixel from a signal level output of the pixel.

[0008] It is also desirable that the image sensor has an input selector switch that selects all pixel signals in sequence when the mode selection signal indicates high frame rate shooting, and that selects one of the pixel signals when the mode selection signal indicates high resolution shooting.

[0009] It is also desirable that when the mode selection signal indicates high frame rate shooting, the imaging element outputs a signal obtained by accumulating all pixel signals of the pixel block for each frame as the video output of the pixel block, and when the mode selection signal indicates high resolution shooting, the imaging element outputs one pixel signal of the pixel block in sequence for each frame.

[0010] It is also preferable that the imaging element updates the mode selection signal every period of a number of frames corresponding to the number of pixels in the pixel block.

[0011] It is also preferable that in the imaging device, the column readout circuits are arranged above and below a column of pixel blocks in the pixel array, one controlling the pixel blocks in odd-numbered rows and the other controlling the pixel blocks in even-numbered rows. Effect of the Invention

[0012] According to the imaging element of the present invention, local high frame rate shooting or high resolution shooting can be realized for each imaging region, and image quality of the entire screen can be improved. [Brief description of the drawings]

[0013] [Figure 1] 1 is a diagram showing an example of a circuit configuration of an image sensor according to an embodiment of the present invention; [Diagram 2] FIG. 2 is a diagram showing an example of a circuit configuration of one pixel. [Diagram 3] FIG. 1 is a diagram illustrating an example of the configuration of a switched capacitor (SC) integrator. [Figure 4] 4 is an example of a timing diagram of a drive signal for an image sensor. [Diagram 5] FIG. 11 is a diagram showing the relationship between a pixel drive signal and an FD signal of each pixel. [Figure 6] FIG. 2 is a diagram for explaining the integrating operation of an SC integrator. [Figure 7] 11A and 11B are diagrams illustrating examples of mode selection signals and corresponding output signal formats. [Figure 8] FIG. 13 is a diagram showing an example of a circuit configuration of an image sensor according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0015] (Embodiment) 1 shows an example of a circuit configuration of an image sensor according to an embodiment of the present invention. The image sensor includes a pixel array 100, a row selection / pixel drive circuit 110, a signal readout circuit 200, and a drive signal generation circuit 210.

[0016] The pixel array 100 is configured and controlled by blocking adjacent k×l pixel regions (k pixels horizontally and l pixels vertically, where k and l are integers of 2 or more) 10 as one block unit. Here, the pixel array 100 will be described as being configured of 2×2 pixel regions as pixel blocks 10, and being configured as H horizontal blocks×V vertical blocks (2H horizontal pixels×2V vertical pixels). The size (number of pixels) of the pixel blocks 10 can be freely set based on the image resolution during high frame rate shooting, etc. Four signal read lines 17 (k×l lines, i.e., one line for each pixel in the pixel block 10) are wired in the vertical direction for each column of pixel blocks (V pixel blocks 10 arranged vertically), and each is connected in parallel to a column read circuit 201 described later.

[0017] Each pixel (Pixel A to Pixel D in this embodiment) of the pixel block 10 is composed of, for example, a 4Tr (transistor) type pixel. An example of the circuit configuration of one pixel is shown in Fig. 2. The pixel includes a photodiode (PD) 11, a transfer gate 12, a floating diffusion (FD) 13, an output transistor (source follower circuit) 14, a selection transistor 15, and a reset transistor 16.

[0018] A photodiode (PD) 11 performs photoelectric conversion in response to incident light and generates a signal charge based on the amount of exposure.

[0019] The transfer gate 12 is controlled by a charge transfer signal TX. When the signal TX goes high, the transfer gate 12 becomes conductive and transfers the signal charge generated in the photodiode (PD) 11 to the floating diffusion (FD) 13 .

[0020] The floating diffusion (FD) 13 essentially functions as a capacitor and accumulates the transferred signal charge. The potential of the floating diffusion (FD) 13 based on the signal charge is applied to the gate electrode of the output transistor 14.

[0021] The output transistor 14 constitutes a source follower circuit, and outputs an output signal (output voltage) to the source side in response to a voltage applied to the gate electrode.

[0022] The selection transistor 15 is controlled by a row selection signal SL, and is turned on when the signal SL goes High, and outputs an output signal from the output transistor (source follower circuit) 14 to a signal read line 17.

[0023] The reset transistor 16 is controlled by an FD reset signal RT, and when the signal RT goes high, it becomes conductive, drains the signal charge accumulated in the floating diffusion (FD) 13, and resets the output of the pixel.

[0024] In this way, output signals from the pixels (Pixel A to Pixel D) of each pixel block 10 are output to the signal read lines (A to D) 17. Note that the pixel structure is not limited to the above-mentioned 4Tr type pixel, and any structure may be used as long as the pixel has a configuration for outputting an output signal based on incident light to the signal read line 17.

[0025] Returning to FIG. 1, the row selection and pixel drive circuit 110 selects and drives rows of the pixel array 100. Row selection selects and drives pixels for each pixel block row (H pixel blocks 10 arranged in the horizontal direction). A signal for selecting the mth pixel block row is denoted as SL(m). The row selection and pixel drive circuit 110 simultaneously drives the pixel blocks 10 in the same pixel block row (m rows) with the same control signal, but supplies different pixel drive signals (XT, RT) to each pixel (Pixel A to Pixel D) in the pixel block 10 to control each pixel. In this embodiment, the pixel drive signals for each pixel (Pixel A to Pixel D) in the mth pixel block 10 are respectively TX A (m)~TXD (m), R.T. A (m)~RT D (m).

[0026] The signal readout circuit 200 is made up of H column readout circuits 201 (column readout circuits (1) to (H)) corresponding to H horizontal blocks of the pixel array 100. The column readout circuit 201 includes an input changeover switch 20 (switch φ A ~φ D ), a switched capacitor integrator (hereinafter, SC integrator) 30, and an ADC (analog-to-digital converter) 40. Each column readout circuit (1)-(H) integrates and AD (analog-to-digital) converts the output signal of a selected and driven pixel block row, and outputs the result as image sensor output signals D(1), D(2), ..., D(H).

[0027] The drive signal generation circuit 210 supplies the same control signal P, control signal Q, SC integrator control signal, and ADC control signal to each of the column readout circuits (1) to (H). Each column readout circuit 201 operates simultaneously by the drive signals supplied from the drive signal generation circuit 210.

[0028] The diagram on the left side of Fig. 1 shows an enlarged view of the structure of the nth column (n = 1, 2, ..., H) of the image sensor. In the nth column, pixel blocks 10 of 2 x 2 pixels (k x l pixels) are arranged in a V-block array in the column direction (vertical direction). Output signals of each pixel (Pixel A to Pixel D) of pixel block 10 are connected to signal read lines A to D, respectively.

[0029] The configuration of the column readout circuit 201 will be described. The input changeover switch 20 connects the signal readout lines A to D and the SC integrator 30 through a switch φ A ~φ D. Therefore, one of the output signals of the signal readout lines A to D (pixel signals output from each pixel of the pixel block) is input to the SC integrator 30. Note that the operation of the input changeover switch 20 differs depending on the control signal, as described below. When a control signal P is given, the signal readout lines A to D are connected in order, and when a control signal Q is given, a specific one of the signal readout lines A to D is connected.

[0030] 3 is an example of the configuration of a switched capacitor (SC) integrator 30. The SC integrator 30 includes a sampling capacitor 31 (capacitor C1), an integrating capacitor 32 (capacitor C2), an OP amplifier 33, and a switch φ SMP ,φ AMP ,φ RT It is composed of switch φ RT When the switch φ is turned ON (conducting), the charge accumulated in the integrating capacitor 32 is initialized. SMP , is ON, φ AMP When the input voltage V in The sampling capacitor 31 is charged by the switch φ SMP is OFF, φ AMP When the output voltage V out The switch φ SMP ,φ AMP By repeatedly turning on and off the input voltage V in The charge due to the sampling capacitance 31 is accumulated in the integrating capacitance 32. That is, the SC integrator 30 functions as an analog integrator. out can be given a gain (C1 / C2).

[0031] The SC integrator 30 performs the above sampling and charge transfer operations multiple times to calculate the input voltage V in The input signal to the SC integrator 30 is input through the input changeover switch 20 (switch φ A ~φ D) allows the pixel signal of one of Pixel A to Pixel D to be selected. Mode selection signals F(1) to F(H) are input from the outside to the image sensor, and a mode selection signal F(n) is input to the column readout circuit (n) of the nth column. Both a control signal P and a control signal Q are supplied to the input changeover switch 20 uniformly for all columns, but which control signal will be used for control is selected according to the mode selection signal F(n) supplied for each column.

[0032] The mode selection signal F(n) is a signal expressed as follows: F(n)=(F 1n ,F 2n ,···,F Vn ) (n=1,2,…,H) F mn =0 or 1

[0033] Here, F mn indicates a mode selection signal for the pixel block 10 in the mth row and nth column (given to each pixel block 10). That is, F mn When reading out the pixel block in the mth row and nth column, high frame rate readout (F mn =0) or high resolution readout (F mn F = 1) is specified. mn When =0, control signals P and F mn When =1, the control signal Q switches the switch φ of the input changeover switch 20. A ~φ D are driven respectively.

[0034] Mode selection signal F mn Although the method of generating the signal is not limited in the present invention, it is preferable to use the signal as a feedback signal of the captured image. For example, the time-space frequency components and noise components of the image signal captured by this imaging device or another imaging device are analyzed, and based on the results, the area with high time frequency is converted into the mode selection signal F. mn = 0, and the high spatial frequency region is the mode selection signal F mn A possible method is to generate the mode selection signal F = 1 so that the image characteristics are fed back to the mode selection signal F. mnis desirably updated once every k×l frames, or once every four frames in this embodiment, for the number of frames corresponding to the number of pixels included in one pixel block 10.

[0035] The ADC 40 converts the integration result of the SC integrator 30 into a digital signal, and outputs it from the image sensor as an output signal D(n) (n=1, 2, ..., H). Note that the output signal may be further subjected to digital correlated double sampling (DCDS) to subtract the ADC output of the pixel reset level from the ADC output of the pixel signal level, thereby outputting a signal from which fixed pattern noise has been removed.

[0036] 4 shows an example of a timing diagram of a drive signal for the image sensor. f =1 / f f (f f is the frame frequency), scanning is performed from the 1st row to the Vth row of the pixel block. FIG. 4 shows an enlarged view of each drive signal and control signal when processing the mth row in each frame period. In this embodiment, the readout circuit performs a different readout operation for each frame in a four-frame cycle (Frames A to D) corresponding to the number of pixels (k×l pixels, 4 pixels in this embodiment) included in one pixel block. Note that the switch φ A ~φ D During one frame, when the control signal is P (high frame rate shooting), it operates to select all pixel signals of the pixel block in sequence, and when the control signal is Q (high definition shooting), it operates to select one of the pixel signals of the pixel block.

[0037] The details of the readout operation will be described with reference to Fig. 5 and Fig. 6. Fig. 5 is a diagram showing the relationship between the pixel drive signal and the FD signal of each pixel, and Fig. 6 is a diagram explaining the integration operation of the SC integrator 30.

[0038] First, the pixel drive signals and pixel output signals will be described in detail with reference to Fig. 5. Fig. 5 illustrates the transition of signal charges accumulated in the floating diffusion (FD) 13 of each pixel in an arbitrary pixel block (for example, the mth row and the nth column) by the pixel drive signals of Frames A to D.

[0039] In the readout operation in Frame A, the charge transfer signal TX A ~TX D TX A →TX B →TX C →TX D The photoelectric conversion signal of each pixel is then transferred to the FD 13. For example, as shown in the pixel FD signal diagram on the left, the FD of Pixel A at this point is 4 / f f When the exposure signal is accumulated, the FD of Pixel B is 3 / f f When the exposure signal is accumulated, the FD of Pixel C is 2 / f f When the exposure signal is accumulated, the FD of Pixel D is 1 / f f The exposure signal is stored.

[0040] Then, for Pixel A, the FD reset signal RT A is sent to reset the charge in the FD. As a result, the FD of Pixel A goes to the reset level, but the charges in the FD of the other pixels Pixels B to D are maintained.

[0041] In the following Frame B, the charge transfer signal is TX B →TX C →TX D →TX A Then, the 1 / f f When an exposure signal is added (the FD of Pixel A is 1 / f f Exposure signal, FD of Pixel B is 4 / f f Exposure signal, FD of Pixel C is 3 / f f Exposure signal, FD of Pixel D is 2 / f fAfter that, the FD reset signal RT B The charge in the FD of Pixel B is reset, but the charges in the FD of the other pixels, Pixels A, C, and D, are maintained.

[0042] In the following Frame C, the charge transfer signal is TX C →TX D →TX A →TX B Then, the 1 / f f The exposure signal is added. Then, the FD reset signal RT C This resets only the FD capacitance (charge) of Pixel C.

[0043] In the following Frame D, the charge transfer signal is TX D →TX A →TX B →TX C Then, the 1 / f f The exposure signal is added. Then, the FD reset signal RT D This resets only the FD capacitance (charge) of Pixel D. After that, the process returns to the operation procedure of Frame A and the same operation is repeated every four frames. Note that when a pixel block consists of k×l pixels, the above charge transfer process is performed every k×l frames.

[0044] The signal charge generated during one frame period is 1 / f f Assuming that this is an exposure signal, the signal charge of the FD 13 of each pixel in Pixels A to D will be 1 / f every frame from the FD reset level (shown as 0 / 4 in FIG. 5). f →2 / f f →3 / f f →4 / f f The exposure signal accumulates, and the 4 / f f When the exposure signal reaches 4 / 4 (shown as 4 / 4 in Fig. 5), the FD reset level is restored and the operation is repeated for a four-frame cycle. Also, each pixel operates with a phase shift of one frame.

[0045] Next, the operation of integrating the FD signal by the SC integrator 30 will be described in detail with reference to Fig. 6. Fig. 6 illustrates the pixel drive signal in the readout operation of Frame A and the integration operation by the SC integrator 30, comparing the control signal P (high frame rate shooting) and the control signal Q (high resolution shooting). A ~TX D and reset signal RT A The figure shows the amount of signal accumulated in the FD 13 of Pixels A to D over time. The display showing the accumulation state of signal charge is the same as in FIG.

[0046] The SC integrator 30 is first turned on by the switch φ RT When the charge of the integrating capacitance 32 is reset by turning ON, the switch φ of the input changeover switch 20 is turned ON. A ~φ D The FD output of Pixel A to Pixel D corresponding to the operation of is integrated. Input switch φ A ~φ D As mentioned above, the mode selection signal F mn The control signal P or the control signal Q is selected by the signal P or Q. The SC integrator 30 performs an integration process each time by sampling and integrating a number of times (k×l times, 4 times in this embodiment) corresponding to the number of pixels in the pixel block.

[0047] First, the integration operation will be described when the control signal P is used. When the control signal P is used (when reading out at a high frame rate), first, the input changeover switch φ A ~φ D is φ A →φ B →φ C →φ D By turning on in this order, Pixel A(3 / f f Exposure signal) → Pixel B(2 / f f Exposure signal) → Pixel C(1 / f fThe FD output of each pixel is sampled in the order of Pixel D (exposure signal) → Pixel D (FD reset level signal) and integrated by the SC integrator 30. That is, the output of k×l pixels is sampled once each and integrated. After the integration operation is completed, the output of the SC integrator 30 is sampled by the downstream ADC 40 as shown in FIG. mn,A1 Immediately after sampling, each pixel receives a charge transfer signal TX A (m)~TX D (m) is the signal charge for one frame (1 / f f The exposure signal is transferred from the photodiode and stored.

[0048] When the sampling of the ADC 40 is completed, the SC integrator 30 switches the switch φ RT Reset the charge of the integrated capacitance 32 by f Exposure signal) → Pixel B(3 / f f Exposure signal) → Pixel C(2 / f f Exposure signal) → Pixel D(1 / f f The FD output of each pixel is sampled in the order of the exposure signal and integrated by the SC integrator 30. The integrated output is sampled by the ADC 40 and similarly converted into a digital signal D mn,A2 D mn,A1 and D mn,A2 Difference of |D mn,A1 -D mn,A2 | is 1 / f of Pixel A to D f Since this signal is equal to the sum of the exposure signals, it is calculated as 1 / f f It can be treated as an exposure signal. That is, when the control signal P (mode selection signal F mn = 0), an additive signal of k × l pixels is obtained for each frame, and the pixel block is photographed at a high frame rate.

[0049] Next, the integration operation by the control signal Q will be described. When the control signal Q is used (in the case of high resolution readout), the switch φ RTAfter the charge of the integrating capacitance 32 of the SC integrator 30 is reset when the charge transfer signal TX A (m) is the signal charge for one frame (1 / f f The exposure signal) is transferred from the photodiode to FD13 of Pixel A, and the accumulated signal amount of Pixel A is 4 / f f Then, the switch φ of the input changeover switch 20 is turned on. A Only switch φ B ~φ D Since remains OFF, the SC integrator 30 is Pixel A(4 / f f Only the exposure signal) is multisampled four times (k x l times). The integration result is converted to D mn,A1 Note that TX B (m)~TX D Although the FD signals of Pixels B to D are also accumulated by (m), in Frame A, Pixels B to D are not connected to the SC integrator 30.

[0050] Next, switch φ RT The charge of the integrating capacitance 32 of the SC integrator 30 is reset by the FD reset signal RT A Then, the charge of FD13 of Pixel A is reset. Then, the switch φ A Only Pixel A is continuously ON, and the SC integrator 30 multi-samples and integrates Pixel A (FD reset level) four times (k×l times). The integration result is output by the ADC 40 as mn,A2 D mn,A1 and D mn,A2 Difference of |D mn,A1 -D mn,A2 | is 4 / f for Pixel A f Since this signal is equal to the exposure signal, it is 4 / f f It can be treated as an exposure signal. That is, when the control signal Q (mode selection signal F mn = 1), an exposure signal for one pixel is obtained in one frame, and high-resolution photography is performed for that pixel block.

[0051] The readout operation procedure and operation principle of Frame A have been explained based on FIG. 6, but the same readout operation procedure and operation principle can be applied to Frames B to D by the operation timing shown in FIG. 4. In other words, exposure signals of k×l pixels can be obtained individually in k×l frame periods, achieving high resolution. |D mn,A1 -D mn,A2 The calculation method of | is not limited, and may be performed by a digital circuit within the element, or a calculation method outside the imaging element may be used.

[0052] FIG. 7 shows an example of the input mode selection signal and the corresponding output signal format. As shown in FIG. 7(a), F(n)=(F 1n ,F 2n ,…,F Vn ) (n=1,2,…,H) is input, F mn The image sensor is divided into two regions by taking the value of 0 or 1.

[0053] As shown in FIG. 7(b), the mode selection signal F mn In the region where is 0, 1 / f f Since the 4-pixel sum signal is obtained as the video output, localized high frame rate imaging can be achieved. mn The area where is 1 is 4 / f f Since exposure subframe readout signals (Pixel A to D) can be acquired, localized high-resolution imaging can be realized. mn In the region where the pixel number is 1, the pixel signals of each pixel (Pixel A to D) are acquired sequentially for each frame, and each pixel signal is held for four frame periods (period during which all pixels in the pixel block 10 are read out) by processing on the circuit. In this way, a video output of the pixel block for high-resolution imaging is obtained.

[0054] According to the imaging element of this embodiment, it is possible to specify which of the resolution and frame rate is to be prioritized for each pixel block (k×l pixel region) by a mode selection signal input from the outside. Therefore, even in an imaging scene in which a fast-moving subject and a high-definition subject are simultaneously captured in the same screen as described above, it is possible to improve the image quality of the entire screen by realizing local high frame rate shooting or high resolution shooting.

[0055] (Other embodiments) FIG. 8 shows an example of the circuit configuration of an image sensor according to another embodiment of the present invention.

[0056] In the above embodiment, H column readout circuits 201 are provided below the pixel array 100, and the readout circuits are connected in parallel to the pixel block columns, but the number of column readout circuits 201 in parallel to the pixel block columns is arbitrary. For example, as shown in Fig. 8, signal readout circuits (column readout circuits 201) may be provided above and below (the pixel block columns) the pixel array 100, and the total number of column readout circuits 201 may be increased to 2H. In this case, for example, by using a wiring structure in which odd-numbered rows of pixel blocks are connected to signal lines to the upper circuits and even-numbered rows of pixel blocks are connected to signal lines to the lower circuits, the number of parallel readout circuits can be doubled while maintaining the column pitch.

[0057] Furthermore, in the above embodiment, the SC integrator 30 is used as an analog integrator, but the method of realizing the integration function may be arbitrary as long as the circuit is capable of sequentially performing analog addition of a plurality of signals from pixels.

[0058] Although the above-mentioned embodiment has been described as a representative example, it is clear to those skilled in the art that many modifications and substitutions can be made within the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited by the above-mentioned embodiment, and various modifications or changes can be made without departing from the scope of the claims. For example, the functions included in each block, each step, etc. described in the embodiment can be rearranged so as not to be logically inconsistent, and multiple configuration blocks, steps, etc. can be combined into one or divided. [Explanation of symbols]

[0059] 10 pixel blocks 11 Photodiode (PD) 12 Transfer Gate 13 Floating Diffusion (FD) 14 Output transistor 15 Select transistor 16 Reset transistor 17 Signal readout line 20 Input selector switch 30 Switched Capacitor (SC) Multiplier 31 Sampling Capacity 32 Accumulated capacity 33 OP amp 40 ADC (Analog / Digital Converter) 100 pixel array 110 Row selection and pixel driving circuit 200 Signal readout circuit 201 Column readout circuit 210 Drive signal generating circuit

Claims

1. a pixel array which is divided into pixel blocks each including a plurality of adjacent pixels and controlled; an image sensor comprising a signal readout circuit including a column readout circuit corresponding to a pixel block column of the pixel block, The column readout circuit includes: an input changeover switch which selects one of the pixel signals output from each pixel of the pixel block during one frame or selects all of the pixel signals in sequence in response to a mode selection signal which is provided for each pixel block and selects whether to perform high resolution readout or high frame rate readout; an analog integrator that samples and integrates a pixel signal input via the input changeover switch a number of times corresponding to the number of pixels in the pixel block; an ADC (analog / digital converter) for converting the output of the analog integrator into a digital signal; An imaging element comprising:

2. 2. The imaging device according to claim 1, The image pickup device, wherein the column readout circuit further performs correlated double sampling for subtracting a reset level output of the pixel from a signal level output of the pixel.

3. 3. The imaging device according to claim 1, an input switching switch that selects all pixel signals in sequence when the mode selection signal indicates high frame rate shooting, and that selects any one of the pixel signals when the mode selection signal indicates high resolution shooting.

4. 4. The imaging device according to claim 1, an imaging element, characterized in that when the mode selection signal is for high frame rate shooting, a signal obtained by integrating all pixel signals of the pixel block for each frame is output as a video output of the pixel block, and when the mode selection signal is for high resolution shooting, any one of the pixel signals of the pixel block is output in sequence for each frame.

5. 5. The imaging device according to claim 1, 2. An imaging device according to claim 1, wherein the mode selection signal is updated for each period of a number of frames corresponding to the number of pixels in the pixel block.

6. 6. The imaging device according to claim 1, the column readout circuits are arranged above and below a column of pixel blocks in the pixel array, one of which controls the pixel blocks in odd-numbered rows and the other of which controls the pixel blocks in even-numbered rows.

Images