Resistive memory device having ultra-thin barrier layer and method for forming same

Abstract

To provide a resistive memory device.SOLUTION: A resistive memory devices include an ultra-thin barrier layer provided between a bottom electrode and a bottom electrical contact to a memory device. The ultra-thin barrier layer can reduce the total step height of the resistive memory elements by 15% or more, including as much as about 20% or more. The use of the ultra-thin barrier layer can further improve the thickness uniformity of a dielectric etch stop layer partially underlying and extending between the memory elements by at least about 15%. The use of the ultra-thin barrier layers can improve manufacturability, provide lower costs and higher yields for the resistive memory device, and facilitate the integration of the resistive memory device at an advanced technology node.SELECTED DRAWING: Figure 27

Description

[Technical field]

[0001] The present disclosure relates to resistive memory devices and methods for manufacturing resistive memory devices. [Background technology]

[0002] Resistive memory devices use memory elements that can provide at least two resistance states. Different resistance states can provide different resistance levels. Resistive random access memory (RRAM or ReRAM) is a novel resistive memory device technology. ReRAM devices are non-volatile memory devices that operate by modifying the resistance of a solid dielectric material. As the resistance increases and current is prevented from flowing to a node, the memory state can indicate an "off" or "0" state. Conversely, as the resistance decreases and current is allowed to flow, the memory state can indicate an "on" or "1" state. Other novel non-volatile memory technologies that utilize similar resistive switch principles include phase-change memory (PCM), magnetoresistive random-access memory (MRAM), conductive-bridging RAM (CBRAM), and carbon nanotube memory. These novel technologies are usually recognized as potential replacements for flash memory. However, to date, these technologies have not yet been widely adopted. Resistive memory technology still needs to be improved. Summary of the Invention

[0003] According to various embodiments of the present disclosure, a resistive memory device includes a metal portion, a barrier layer having a thickness of 6 nm or less above the metal portion, a bottom electrode above the barrier layer, a switch layer above the bottom electrode, an top electrode above the switch layer, and a conductive via in contact with the top electrode.

[0004] In another embodiment, a resistive memory device is proposed comprising a dielectric material layer and a stack above a first portion of the dielectric material layer, the stack including a barrier layer, a bottom electrode above the barrier layer, a switch layer above the bottom electrode, and a top electrode above the switch layer, wherein a second portion of the dielectric material layer laterally surrounds the stack, and wherein a maximum step between a top surface of the second portion of the dielectric material layer and a top surface of the top electrode of the stack is less than 80 nm.

[0005] In another embodiment, a method for manufacturing a resistive memory device is proposed, the method including the steps of forming a dielectric material layer over a metal portion, etching the dielectric material layer to form an opening through the dielectric material layer to expose a surface of the metal portion at a bottom of the opening, forming a barrier layer having a thickness of 6 nm or less over the surface of the metal portion exposed at the bottom of the opening, forming a bottom electrode over the barrier layer, forming a switch layer over the bottom electrode, forming an top electrode over the switch layer, and forming a conductive via in contact with the top electrode. [Brief description of the drawings]

[0006] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings, in which: It should be noted that, in accordance with standard industry practice, various features have not been drawn to scale, and in fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of illustration. [Figure 1A] FIG. 2 is a vertical cross-sectional view of a first exemplary structure prior to formation of a memory device array in accordance with an embodiment of the present disclosure. [Figure 1B] 3A-3C are vertical cross-sectional views of a first exemplary structure during formation of a memory device array according to embodiments of the present disclosure. [Figure 1C] FIG. 2 is a vertical cross-sectional view of a first exemplary intermediate structure after forming an upper level metal interconnect structure according to an embodiment of the present disclosure. [Diagram 2] 2 is a vertical cross-sectional view of a first exemplary intermediate structure during a process of forming a resistive memory device including a first dielectric material layer and a metal portion embedded in the first dielectric material layer, according to one embodiment of the present disclosure. FIG. [Diagram 3] 2A-2C are vertical cross-sectional views of an example intermediate structure during a process of forming a resistive memory device including a second dielectric material layer and a metal portion deposited above a top surface of a first dielectric material layer, according to an embodiment of the present disclosure. [Figure 4] 4A-4C are vertical cross-sectional views of an example intermediate structure during a process of forming a resistive memory device including a patterned mask formed over a top surface of a second dielectric material layer according to an embodiment of the present disclosure. [Diagram 5] 4A-4C are vertical cross-sectional views of an example intermediate structure during a process of forming a resistive memory device illustrating the formation of an opening through a second dielectric material layer to expose a top surface of a metal portion, according to an embodiment of the present disclosure. [Figure 6] A vertical cross-sectional view of an exemplary intermediate structure during the process of forming a resistive memory device, showing a continuous barrier layer deposited over the top and side surfaces of the second dielectric material layer and over the exposed top surface of a metal portion deposited on the bottom surface of the opening. [Figure 7] 2A-2C are vertical cross-sectional views of an example intermediate structure during a process of forming a resistive memory device, showing a continuous bottom electrode layer being deposited above an upper surface of the continuous barrier layer, according to an embodiment of the present disclosure. [Figure 8] 2A-2C are vertical cross-sectional views of an example intermediate structure during a process of forming a resistive memory device showing a continuous switch layer being deposited above a continuous bottom electrode layer, according to an embodiment of the present disclosure. [Figure 9] 4A-4C are vertical cross-sectional views of an example intermediate structure during a process of forming a resistive memory device showing an optional continuous cap layer being deposited over a continuous switch layer, according to an embodiment of the present disclosure. [Figure 10] 2A-2C are vertical cross-sectional views of an example intermediate structure during a process of forming a resistive memory device showing a continuous top electrode layer being deposited over an optional continuous cap layer, according to an embodiment of the present disclosure. [Figure 11] 2A-2C are vertical cross-sectional views of an example intermediate structure during a process of forming a resistive memory device, showing a successive hardmask layer being deposited over a successive top electrode layer, according to an embodiment of the present disclosure. [Figure 12]3A-3C are vertical cross-sectional views of example intermediate structures during a process of forming a resistive memory device including a patterned mask overlying a continuous hardmask layer, according to embodiments of the present disclosure. [Figure 13] 1A-1C are vertical cross-sectional views of example intermediate structures during a process of forming a resistive memory device after an etching process removes portions of the continuous hard mask layer, the continuous top electrode layer, and the optional continuous cap layer to provide a first stack above the continuous switch layer, according to an embodiment of the present disclosure. [Figure 14] 1A-1C are vertical cross-sectional views of an example intermediate structure during a process of forming a resistive memory device, showing a continuous spacing material layer being deposited over the exposed top surface of the continuous switch layer and over the top and side surfaces of the first stack, according to an embodiment of the present disclosure. [Figure 15] FIG. 2 is a vertical cross-sectional view of an example intermediate structure during a process of forming a resistive memory device after an etching process removes portions of the continuous spacing material layer to form at least one spacer above a side of a first stack, according to an embodiment of the present disclosure. [Figure 16] 4A-4C are vertical cross-sectional views of an example intermediate structure during a process of forming a resistive memory device including a patterned mask positioned above a top surface of a hard mask and at least one spacer, according to an embodiment of the present disclosure. [Figure 17] 1A-1C are vertical cross-sectional views of an example intermediate structure during a process of forming a resistive memory device after an etching process removes portions of the continuous switch layer, the continuous bottom electrode layer, and the continuous barrier layer to provide a second stack, according to an embodiment of the present disclosure. [Figure 18] A vertical cross-sectional view of an exemplary intermediate structure during a process of forming a resistive memory device, including a third dielectric material layer over an exposed top surface of the second dielectric material layer and a third dielectric material layer over the sides and top surface of the second stack, in accordance with an embodiment of the present disclosure. [Figure 19] 3A-3C are vertical cross-sectional views of example intermediate structures during a process of forming a resistive memory device including a buffer layer above a third dielectric material layer, according to various embodiments of the present disclosure. [Figure 20]4A-4C are vertical cross-sectional views of an example intermediate structure during a process of forming a resistive memory device including a fourth dielectric material layer above a buffer layer, according to various embodiments of the present disclosure. [Figure 21] 1A-1C are vertical cross-sectional views of a resistive memory device including a metal interconnect and a conductive via extending from the metal interconnect through a fourth dielectric material layer, a buffer layer, a third dielectric material layer, and a hard mask and contacting a top surface of a top electrode according to various embodiments of the present disclosure. [Figure 22] 2 is a vertical cross-sectional view of a resistive memory device according to another embodiment of the present disclosure. [Diagram 23] 2 is a vertical cross-sectional view of a resistive memory device according to another embodiment of the present disclosure. [Figure 24] 2 is a vertical cross-sectional view of a resistive memory device according to another embodiment of the present disclosure. [Diagram 25] 2 is a vertical cross-sectional view of a resistive memory device according to another embodiment of the present disclosure. [Figure 26] 2 is a vertical cross-sectional view of a resistive memory device according to another embodiment of the present disclosure. [Figure 27] 1 is a flow chart illustrating a method for manufacturing a resistive memory device according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] The following disclosure provides many different embodiments or examples of different features for implementing the provided subject matter. Below, specific examples of components and arrangements are described to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, a first feature formed above or on a second feature may include an embodiment in which the first feature and the second feature are formed such that they are in direct contact, and may include an embodiment in which another feature is formed between the first feature and the second feature to allow the first feature and the second feature to not be in direct contact. Also, in the various examples of the disclosure, numerals and / or letters may be repeatedly referenced. This repetition is for simplicity and clarity, and does not in itself dictate a relationship between the various embodiments and / or configurations being described.

[0008] Also, for ease of description, spatially relative terminology such as "below," "below," "lower," "above," "top," and the like may be used herein to describe the relationship of one element or feature to another element or feature illustrated in each drawing. The spatially relative terminology is intended to encompass different orientations during use or operation of the device other than the orientation depicted in each drawing. The device may be otherwise oriented (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0009] Generally, various embodiments disclosed herein may include a resistive memory device, such as a resistive random-access memory (ReRAM) device, and a method of forming a resistive memory device having an ultra-thin barrier layer between a bottom electrode and an electrical contact to the resistive memory device.

[0010] As used herein, a "resistive memory device" includes a memory device in which data can be stored in a memory element by changing the resistance of the memory element. The change in resistance of the memory element can occur quickly (e.g., in less than 10 minutes, such as less than 1 minute, including less than 1 second), can be non-volatile (i.e., the memory element maintains its resistance state when no power is applied for an extended period of time, such as more than 24 hours), and can be reversible. A resistive memory device typically comprises a large number of independently operating memory cells (e.g., 103 or more, 105 or more, 106 or more, or 109 or more memory cells) organized into a memory array, and each memory cell of the memory array can include a memory element capable of providing at least two resistance states (providing different levels of resistance).

[0011] Applying electrical stress to the memory element (e.g., via a voltage or current pulse) can change the resistance state of a single memory element of a resistive memory device. For example, in the case of a ReRAM memory device, the memory element may have a first initial state of resistance. In an embodiment, the memory element may include a dielectric material, and the initial state of resistance may be a relatively high resistance state. An initial bulk "form" step (also called an "electroforming" step) may be performed by applying one or more voltage pulses at a sufficiently high voltage to induce soft breakdown in the material of the memory element. After the "form" step, the memory element may have a significant drop in resistance and is in a stable low resistance state (LRS).

[0012] To reverse this process, a "reset" process may be performed by applying one or more additional voltage pulses, which may have a polarity opposite to that of the voltage pulses used during the "form" step, causing the memory element to increase in resistance and transition to a stable high resistance state (HRS). The "reset" process may destroy the conductive path, or "filament," through the memory element, making the memory element relatively highly resistive again. The resistivity of the memory element after "reset" may be close to the initial resistance state before the "form" step. A "set" process may be performed by applying one or more additional voltage pulses, which may have the same polarity as the voltage pulses used during the initial "form" step, causing the conductive path to be re-established and converting the memory element to a low resistance state.

[0013] Thus, a single memory cell of a memory array can be programmed by changing the memory element of the cell from a high resistance state (HRS) to a low resistance state (LRS), or vice versa. During a read operation, a low voltage can be applied to the memory element, and the logic state of each memory cell can be determined based on the current flowing through the memory cell. A relatively high current flow indicates that the memory element in the cell has a low resistance state (LRS), and a relatively low current flow indicates that the memory element has a high resistance state (HRS). The current difference detected between memory elements having a high resistance state (HRS) and a low resistance state (LRS) may be referred to as the "memory window" of the resistive memory device. In some embodiments, a high current flow (i.e., LRS) may indicate a stored data value of "1" and a low current flow (i.e., HRS) may indicate a stored data value of "0".

[0014] One type of resistive memory device may comprise a single memory element (i.e., memory cell) made of a stack including a switch layer (which may be referred to as a "storage layer") formed of a dielectric material, a first conductive layer (which may be referred to as a "bottom electrode") located on one side of the switch layer, and a second conductive layer (which may be referred to as a "top electrode") located on the other side of the switch layer. Electrical contacts may electrically contact the top electrode and the bottom electrode on opposite sides of the stack. In embodiments in which the switch layer and the top electrode and the bottom electrode extend horizontally (i.e., parallel to the surface of the supporting substrate), the electrical contacts to the stack may include metal features embedded in the dielectric material, such as metal traces or metal vias. Because of the ease of fabricating the single memory element, a resistive memory device having this configuration may be an attractive option for back-end-of-line (BEOL) integration.

[0015] When forming a resistive memory element as described above, a barrier layer is typically deposited before depositing the bottom electrode layer. The barrier layer is to prevent material from diffusing from the bottom electrical contact (e.g., metal line or via) into the bottom electrode of the memory element, potentially contaminating the bottom electrode and degrading the performance of the memory element. The barrier layer is typically formed by a physical deposition technique such as physical vapor deposition (PVD). The barrier layer may have a thickness of 18 nm or more.

[0016] The presence of a relatively thick barrier layer tends to cause resistive memory elements to have a relatively large vertical height (also referred to as a large "step"), which can increase processing time, lead to higher manufacturing costs, lower yields, and inhibit integration of resistive memory devices at advanced technology nodes.

[0017] Also, forming resistive memory elements may require an etching process to remove material, including portions of the barrier layer, from between each of the stacked layers forming the individual memory elements. Etching processes to remove portions of the relatively thick barrier layer may increase processing time and may result in thickness non-uniformity and damage to the dielectric etch stop layer that partially underlies and extends between the memory elements, which may adversely affect device yield.

[0018] To address the above problems in resistive memory devices, such as resistive random-access memory (ReRAM), various embodiments disclosed herein include a resistive memory device with an ultra-thin barrier layer disposed between a bottom electrode and a bottom electrical contact to the memory device. In various embodiments, the barrier layer may have a thickness of 6 nm or less, such as between about 0.3 nm and about 6 nm, including between about 1 nm and about 4.5 nm. The ultra-thin barrier layer can reduce the total step height of the resistive memory element by 15% or more, including as much as about 20% or more. According to various embodiments, the use of the ultra-thin barrier layer can further improve the thickness uniformity of a dielectric etch stop layer that partially underlies and extends between the memory elements by at least about 15%. In various embodiments, the ultra-thin barrier layer can be formed by a conformal deposition process, such as atomic layer deposition (ALD). Various embodiments of the ultra-thin barrier layer can improve manufacturability, provide lower costs and higher yields for resistive memory devices, and facilitate integration of resistive memory devices in advanced technology nodes.

[0019] Referring to FIG. 1A, a vertical cross-sectional view of a first exemplary structure according to embodiments of the present disclosure is shown prior to the formation of a memory device array according to embodiments of the present disclosure. The first exemplary structure may include a substrate 8 containing a semiconductor material layer 10. The substrate 8 may include a bulk semiconductor substrate, such as a silicon substrate, in which the semiconductor material layer extends continuously from a top surface of the substrate 8 to a bottom surface of the substrate 8, or a semiconductor-on-insulator layer including the semiconductor material layer 10 as a top semiconductor layer above a buried insulator layer (e.g., a silicon oxide layer). The exemplary structure may include various device regions, which may include a memory array region 50 in which at least one non-volatile memory cell array may be subsequently formed.

[0020] The exemplary structure may also include a peripheral logic region 52 in which electrical connections may later be formed between each non-volatile memory cell array and peripheral circuitry including field effect transistors. Areas of the memory array region 50 and logic region 52 may be used to form various elements of the peripheral circuitry.

[0021] During front-end-of-line (FEOL) operations, semiconductor devices such as field effect transistors (FETs) may be formed on and / or in the semiconductor material layer 10. For example, shallow trench isolation structures 12 may be formed in the upper portion of the semiconductor material layer 10 by forming shallow trenches and later filling the shallow trenches with a dielectric material such as silicon oxide. Other suitable dielectric materials are within the contemplation of the present disclosure. A masked ion implantation process may be performed to form various doping wells (not explicitly shown) in various regions of the upper portion of the semiconductor material layer 10.

[0022] The gate structures 20 may be formed above the top surface of the substrate 8 by depositing and patterning a gate dielectric layer, a gate electrode layer, and a gate cap dielectric layer. Each gate structure 20 may include a vertical stack of a gate dielectric 22, a gate electrode 24, and a gate cap dielectric 28, referred to herein as a gate stack (gate dielectric 22, gate electrode 24, gate cap dielectric 28). An ion implantation process may be performed to form extended implant regions, which may include source extension regions and drain extension regions. A dielectric gate spacer 26 may be formed around the gate stack (gate dielectric 22, gate electrode 24, gate cap dielectric 28). The components of the gate stack (gate dielectric 22, gate electrode 24, gate cap dielectric 28) and the dielectric gate spacer 26 constitute the gate structure 20. A further ion implantation process may be performed to form deep active regions using the gate structures 20 as a self-aligned implantation mask. Such deep active regions may include deep source regions and deep drain regions. An upper portion of the deep active region may overlap a portion of the extended implant region. Each combination of the extended implant region and the deep active region may constitute an active region 14, which may be a source region or a drain region, depending on an electrical bias. A semiconductor channel 15 may be formed beneath each gate stack (gate dielectric 22, gate electrode 24, gate cap dielectric 28) between a pair of adjacent active regions 14. A metal semiconductor alloy region 18 may be formed on the top surface of each active region 14. Field effect transistors may be formed on the semiconductor material layer 10. Each field effect transistor may include a gate structure 20, a semiconductor channel 15, a pair of active regions 14 (one of which is used as a source region and the other is used as a drain region), and an optional metal semiconductor alloy region 18. Complementary metal-oxide-semiconductor (CMOS) circuitry 75 may be provided on the semiconductor material layer 10 and may include thin film transistors (TFTs) and peripheral circuitry for use in, for example, a transistor array(s) of a memory device to be formed later.

[0023] Thereafter, various interconnect hierarchies may be formed, which are formed prior to forming the memory device array and are referred to herein as lower interconnect hierarchies (L0, L1, L2). In an embodiment of a two-dimensional array of memory devices that is subsequently formed above two levels of interconnect level metal wiring, the lower interconnect hierarchies (L0, L1, L2) may include a contact hierarchy L0, a first interconnect hierarchy L1, and a second interconnect hierarchy L2. The contact hierarchy L0 may include a planarizing dielectric layer 31A (comprising a planarizable dielectric material such as silicon oxide) and various contact via structures 41V (contacting respective ones of the active regions 14 or gate electrodes 24 and formed within the planarizing dielectric layer 31A). The first interconnect hierarchy L1 includes a first interconnect level dielectric (ILD) layer 31B and a first metal wiring 41L formed within the first ILD layer 31B. The first ILD layer 31B is also referred to as the first wiring level dielectric layer. The first metal wiring 41L may contact an individual one of the contact via structures 41V. The second interconnect level structure L2 includes a second ILD layer 32 that may include a first via level dielectric material layer and a second wiring level dielectric material layer or a stack of wiring and via level dielectric material layers. The second ILD layer 32 may be formed into a second interconnect level metal interconnect structure (42V, 42L) that includes the first metal via structure 42V and the second metal wiring 42L. The top surface of the second metal wiring 42L may be flush with the top surface of the second ILD layer 32.

[0024] 1B is a vertical cross-sectional view of the first exemplary structure during the formation of a memory device array according to an embodiment of the present disclosure. Referring to FIG. 1B, a non-volatile memory cell array 95, such as resistive memory devices, may be formed in the memory array region 50 above the second interconnect hierarchy L2. Details of the structure and processing steps of the non-volatile memory cell array 95 are detailed below. A third ILD layer 33 may be formed during the formation of the non-volatile memory cell array 95. The collection of all structures formed in the hierarchy of the non-volatile memory cell array 95 is referred to herein as the third interconnect hierarchy L3.

[0025] FIG. 1C is a vertical cross-sectional view of the first exemplary structure after forming an upper level metal interconnect structure according to an embodiment of the present disclosure. Referring to FIG. 1C, a third interconnect level metal interconnect structure (43V, 43L) may be formed in the third ILD layer 33. The third interconnect level metal interconnect structure (second metal via structure 43V, third metal wiring 43L) may include a second metal via structure 43V and a third metal wiring 43L. Thereafter, further interconnect levels, referred to herein as upper interconnect levels (L4, L5, L6, L7), may be formed. For example, the upper interconnect level (L4, L5, L6, L7) may include a fourth interconnect level L4, a fifth interconnect level L5, a sixth interconnect level L6, and a seventh interconnect level L7. The fourth interconnect hierarchy L4 may include a fourth ILD layer 34 in which the fourth interconnect hierarchical metal interconnect structure (44V, 44L) (which may include the third metal via structure 44V and the fourth metal wiring 44L) is formed. The fifth interconnect hierarchy L5 may include a fifth ILD layer 35 in which the fifth interconnect hierarchical metal interconnect structure (45V, 45L) (which may include the fourth metal via structure 45V and the fifth metal wiring 45L) is formed. The sixth interconnect hierarchy L6 may include a sixth ILD layer 36 in which the sixth interconnect hierarchical metal interconnect structure (46V, 46L) (which may include the fifth metal via structure 46V and the sixth metal wiring 46L) is formed. The seventh interconnect hierarchy L7 may include a seventh ILD layer 37 in which the sixth metal via structure 47V (which is a seventh interconnect hierarchical metal interconnect structure) and the metal bond pad 47B are formed. Metal bond pad 47B can be configured for use with a weld bond (C4 ball bonds or wire bonds can be used) or can be configured for use with a metal-to-metal bond (eg, copper-to-copper bond).

[0026] Each ILD layer may be referred to as an ILD layer 30. Each of the interconnect hierarchical metal interconnect structures may be referred to as a metal interconnect structure 40. Each successive combination of metal via structures and metal wiring located within the same interconnect hierarchy (L2-L7) may be formed as two different structures by two single damascene process steps, or may be formed simultaneously as a single structure by a dual damascene process. Each of the metal interconnect structures 40 may include a separate metal liner (e.g., a TiN, TaN, or WN layer having a thickness in the range of 2 nanometers (nm) to 20 nm) and a separate metal fill material (e.g., W, Cu, Co, Mo, Ru, other elemental metals, or alloys or combinations thereof). Other suitable materials used as the metal liner and metal fill material are within the contemplation of the present disclosure. Various etch-stop dielectric layers and dielectric capping layers may be interposed between pairs of vertically adjacent ILD layers 30 or may be incorporated within one or more of the ILD layers 30.

[0027] Although this disclosure has been described using examples in which a non-volatile memory cell array 95, such as a resistive memory device, can be formed as a component of a third interconnect hierarchy L3, it is expressly contemplated herein that the non-volatile memory cell array 95 can be formed as a component of any other interconnect hierarchy (e.g., L1-L7). Also, while this disclosure has been described using examples in which a set of eight interconnect hierarchy structures is formed, it is expressly contemplated herein that an embodiment using a different number of interconnect hierarchy structures is used. Also, it is expressly contemplated herein that an embodiment in which more than one non-volatile memory cell array 95 can be provided within a plurality of interconnect hierarchy structures in the memory array region 50. Although this disclosure has been described using examples in which a non-volatile memory cell array 95 can be formed in a single interconnect hierarchy structure, it is expressly contemplated herein that the non-volatile memory cell array 95 can be formed above two vertically adjacent interconnect hierarchy structures. Also, it is expressly contemplated herein that the non-volatile memory cell array 95 can be formed on or within the semiconductor material layer 10 (e.g., during front-end-of-line (FEOL) operations).

[0028] 2-21 are sequential vertical cross-sectional views of an example structure during the formation process of a resistive memory device according to various embodiments of the present disclosure. The resistive memory device may have memory cells formed therein that are part of a memory cell array 95, as shown in FIGS. 1B and 1C. Referring to FIG. 2, a first dielectric material layer 101 may be deposited above a substrate, such as a substrate 8 containing a semiconductor material layer 10 as shown in FIGS. 1A-1C. The substrate 8 may include a control element formed during a FEOL process. In some embodiments, one or more additional dielectric material layers, such as an ILD layer, may be deposited between the substrate 8 and the first dielectric material layer 101. In such embodiments, the first dielectric material layer 101 may be omitted. For example, the ILD layer 32 discussed above with respect to FIGS. 1B and 1C may be substituted for the first dielectric material layer 101.

[0029] The first dielectric material layer 101 may be any of a variety of materials, including silicon oxide (SiO2), silicon nitride (SiN4), hafnium oxide (HfO2), hafnium silicate (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titanate (HfTiO), hafnium zirconium oxide (Hf 0.5 Zr 0.5 The first dielectric material layer 101 may be formed of any suitable dielectric material, such as tantalum oxide (Ta2O5), aluminum oxide (Al2O3), hafnium oxide-aluminum oxide (HfO2-Al2O3), zirconium oxide (ZrO2), silicon carbide (SiC), or the like. In some embodiments, the first dielectric material layer 101 may be formed of a low-k dielectric material, such as fluorosilicate glass (FSG), hydrogen silsesquioxane (HSQ), benzocyclobutene (BCB), organic polymer dielectric materials, carbon-doped silicon oxide, porous silicon dioxide, polymer foams, and the like. In some embodiments, the first dielectric material layer 101 may be an intrinsic oxide layer formed on the substrate 8. Other suitable dielectric materials are within the contemplation of the present disclosure.

[0030] The first dielectric material layer 101 may be deposited by any suitable deposition process, which may include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), metalorganic CVD (MOCVD), plasma enhanced CVD (PECVD), sputtering, laser ablation, or the like.

[0031] 2, metal portion 103, such as a metal line or via, may be embedded in first dielectric material layer 101. In some embodiments, one or more additional metal interconnect structures, such as metal via structures and metal lines, may be deposited between substrate 8 and metal portion 103. In these embodiments, metal portion 103 may be omitted. For example, metal line 42L or via 42V discussed above with respect to FIGS. 1B and 1C may be substituted for metal portion 103.

[0032] In various embodiments, metal portion 103 is laterally surrounded by first dielectric material layer 101. In various embodiments, a top surface of metal portion 103 may be substantially flush with a top surface of first dielectric material layer 101. At least one resistive memory device may be subsequently formed above the top surface of metal portion 103, as described in more detail below. Thus, metal portion 103 may be referred to as bottom metal portion 103.

[0033] Metal portion 103 may include any suitable conductive material, such as copper (Cu), aluminum (Al), zirconium (Zr), titanium (Ti), titanium nitride (TiN), tungsten (W), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), iridium (Ir), iron (Fe), beryllium (Be), chromium (Cr), antimony (Sb), osmium (Os), thorium (Th), vanadium (V), alloys thereof, and combinations thereof. In some embodiments, metal portion 103 may include a metal liner (e.g., TiN, TaN, or WN) in contact with first dielectric material layer 101, and a metal fill material (e.g., W, Cu, Co, Mo, Ru, other elemental metals, or alloys or combinations thereof) located above the metal liner. Other suitable conductive materials for use in metal portion 103 are within the contemplation of this disclosure.

[0034] The metal portion 103 may be formed by selectively etching the first dielectric material layer 101 through a photolithographically patterned mask to form one or more grooves or openings in the first dielectric material layer 101, depositing one or more metal materials (e.g., a metal liner layer and a metal fill material) over a top surface of the first dielectric material layer 101 and into the one or more grooves or openings, and performing a planarization process, such as a chemical mechanical planarization (CMP) process, to remove the metal material(s) from above the top surface of the first dielectric material layer 101 and provide the one or more metal portions 103 inlaid in the first dielectric material layer 101. The metal material(s) of the metal portion 103 may be deposited by any suitable deposition process. For example, suitable deposition processes may include physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), electrochemical deposition, or combinations thereof.

[0035] In some embodiments, a plurality of metal portions 103 may be formed in the first dielectric material layer 101, and each metal portion 103 may be embedded in and laterally surrounded by the first dielectric material layer 101. The plurality of metal portions 103 may be spaced apart from one another at least along a first horizontal direction hd1.

[0036] FIG. 3 is a vertical cross-sectional view of an exemplary intermediate structure during the formation process of a resistive memory device including a second dielectric material layer 105 and a metal portion 103 deposited above a top surface of a first dielectric material layer 101 according to an embodiment of the present disclosure. Referring to FIG. 3, the second dielectric material layer 105 may be made of a suitable dielectric material as described above and may be deposited by a suitable deposition process as described above. In various embodiments, the second dielectric material layer 105 may be made of a different dielectric material than the first dielectric material layer 101. In some embodiments, the second dielectric material layer 105 may be an etch stop layer having different etching characteristics (i.e., high etch resistance) than the etching chemistry used in the subsequent etching step. In one non-limiting embodiment, the second dielectric material layer 105 may include silicon carbide. The second dielectric material layer 105 may have a thickness less than the thickness of the first dielectric material layer 101. In some embodiments, the second dielectric material layer 105 may have a thickness between about 5 nm and about 30 nm, although larger and smaller thicknesses of the second dielectric material layer 105 are within the contemplation of the present disclosure.

[0037] 4 is a vertical cross-sectional view of an example intermediate structure during a process of forming a resistive memory device according to an embodiment of the present disclosure, including a patterned mask 107 formed over a top surface of the second dielectric material layer 105. With reference to FIG. 4, the mask 107, which may include a photoresist layer and / or a hard mask, may be patterned by photolithography to form one or more openings therethrough.

[0038] 5 is a vertical cross-sectional view of an example intermediate structure during a process of forming a resistive memory device illustrating forming an opening 108 through the second dielectric material layer 105 to expose a top surface of the metal portion 103, according to an embodiment of the present disclosure. Referring to FIG. 5, the example intermediate structure may be etched through a patterned mask 107 to remove portions of the second dielectric material layer 105 and expose a top surface of the metal portion 103. After the etching process, the patterned mask 107 may be removed by an appropriate process (e.g., by ashing or dissolving using a solvent).

[0039] In some embodiments, an etching process may form a plurality of openings 108 through the second dielectric material layer 105. Each of the openings 108 may expose a portion of a top surface of the metal portion 103. Each of the openings 108 may correspond to a location of a resistive memory element in a subsequently formed resistive memory element array.

[0040] 6 is a vertical cross-sectional view of an example intermediate structure during the formation process of a resistive memory device showing a continuous barrier layer 109L deposited over the top and sides of the second dielectric material layer 105 and over the exposed top surface of the metal portion 103 above the bottom surface of the opening 108. Referring to FIG. 6, the continuous barrier layer 109L may be deposited by a deposition process. In various embodiments, the continuous barrier layer 109L may be deposited by atomic layer deposition (ALD). An ALD deposition process is a thin film deposition process in which a surface is exposed to an alternating sequence of gas species (which may be referred to as precursor pulses) to grow a thin film on the surface. Other suitable deposition processes capable of producing thin films are within the contemplation of the present disclosure.

[0041] The continuous barrier layer 109L may be made of a conductive material, which serves as a diffusion barrier layer to prevent or essentially inhibit the material(s) of the metal portion 103 from diffusing into the bottom electrode of the resistive memory device that is subsequently formed on the continuous barrier layer 109L. In various embodiments, the continuous barrier layer 109L may include a conductive oxide, nitride, and / or oxynitride material. In some embodiments, the conductive oxide, nitride, and / or oxynitride material of the continuous barrier layer 109L may include at least one metal selected from aluminum (Al), manganese (Mn), cobalt (Co), titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), tin (Sn), and magnesium (Mg). In one non-limiting embodiment, the continuous barrier layer 109L may include tantalum nitride (TaN).

[0042] Referring again to FIG. 6, the continuous barrier layer 109L may have a thickness T1 that is 6 nm or less, for example, between about 0.3 nm and about 6 nm, including between about 1 nm and about 4.5 nm. Larger and smaller thicknesses T1 of the continuous barrier layer 109L are within the contemplation of the present disclosure. The thickness T1 of the continuous barrier layer 109L is sufficient to provide an effective diffusion barrier, but not so large that the resistance of the continuous barrier layer 109L becomes too large. In one non-limiting example, the thickness T1 of the continuous barrier layer 109L may be between about 2 nm and about 3 nm.

[0043] In embodiments where the continuous barrier layer 109L is formed by ALD, the deposition process may include a thermal ALD process and / or a plasma-enhanced ALD process. In various embodiments, the ALD deposition process may be performed at a temperature between 150° C. and 300° C. Suitable precursors used during the ALD process to form the continuous barrier layer 109L including TaN may include, for example, the tantalum precursor pentakis(dimethylamino)tantalum(V) (PDMAT) and / or tantalum chloride (TaCl5), and the nitrogen precursor ammonia (NH3). Other suitable precursor materials are within the contemplation of the present disclosure.

[0044] In various embodiments, the density of the continuous barrier layer 109L formed by ALD can be greater than that of an equivalent barrier layer formed by physical vapor deposition (PVD). Thus, according to various embodiments, the continuous barrier layer 109L formed by ALD can be made significantly thinner (e.g., ≦6 nm, whereas a layer formed by PVD is about 18 nm) while still providing an effective diffusion barrier. The relatively thin barrier layer according to various embodiments can reduce the total step height of the subsequently formed resistive memory element(s). In addition, the use of a conformal deposition process such as ALD can more effectively control the thickness T1 of the continuous barrier layer 109L, and the thickness T1 varies minimally or not at all in the exemplary intermediate structure.

[0045] 7 is a vertical cross-sectional view of an example intermediate structure during the formation process of a resistive memory device showing a continuous bottom electrode layer 111L deposited above an upper surface of the continuous barrier layer 109L according to an embodiment of the present disclosure. The continuous bottom electrode layer 111L may include any suitable conductive material, such as titanium (Ti), titanium nitride (TiN), gold (Au), ruthenium (Ru), tungsten (W), tungsten nitride (WN), aluminum copper (AlCu), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), iridium (Ir), iron (Fe), beryllium (Be), chromium (Cr), antimony (Sb), osmium (Os), thorium (Th), vanadium (V), copper (Cu), aluminum (Al), zirconium (Zr), alloys thereof, and combinations thereof. Other suitable conductive materials for use in the continuous bottom electrode layer 111L are within the contemplation of the present disclosure. The continuous bottom electrode layer 111L may include a single layer of conductive material or multiple layers of conductive materials that may have the same or different compositions. The continuous bottom electrode layer 111L may be deposited by any suitable deposition method as described above.

[0046] 8 is a vertical cross-sectional view of an example intermediate structure during the formation process of a resistive memory device showing a continuous switch layer 113L deposited above the continuous bottom electrode layer 111L, according to an embodiment of the present disclosure. In various embodiments, the continuous switch layer 113L may be conformally deposited above the top surface of the continuous bottom electrode layer 111L. The continuous switch layer 113L may be deposited by any suitable deposition process as described above.

[0047] The continuous switch layer 113L may include a solid dielectric material switchable between a high resistance state (HRS) and a low resistance state (LRS). Suitable materials for use in the continuous switch layer 113L include, for example, titanium oxide (TiO2), hafnium oxide (HfO2), hafnium aluminum oxide (HFO2), and the like. x Al 1-xO2), Tantalum oxide (Ta2O5), Tungsten oxide (WO2), Zirconium oxide (ZrO2), Hafnium zirconium oxide (Hf x Zr 1-x The continuous switch layer 113L may include dielectric materials, metal oxides, and / or high-k materials, such as SiO2, 0.1≦x≦0.9), aluminum oxide (Al2O3), nickel oxide (NiO), zinc oxide (ZnO), and silicon oxide (SiO2). Other suitable materials having resistive switching properties are within the contemplation of the present disclosure. The continuous switch layer 113L may include a single layer of material or multiple layers of materials having the same or different compositions.

[0048] 9 is a vertical cross-sectional view of an example intermediate structure during the formation process of a resistive memory device showing an optional continuous cap layer 115L deposited over the continuous switch layer 113L, according to an embodiment of the present disclosure. In various embodiments, the optional continuous cap layer 115L may be conformally deposited over the top surface of the continuous switch layer 113L. The optional continuous cap layer 115L may be deposited by any suitable deposition process as described above.

[0049] The optional continuous cap layer 115L may include a material that provides an oxygen storage function, which contributes to a phase change in the dielectric material of the continuous switch layer 113L. In some embodiments, the continuous cap layer 115L may be a metal or metal oxide having a relatively low oxygen concentration. Suitable metal materials for use in the optional continuous cap layer 115L may include, for example, titanium (Ti), hafnium (Hf), platinum (Pt), tantalum (Ta), and aluminum (Al), as well as combinations and alloys thereof. Suitable metal oxide materials for use in the optional continuous cap layer 115L may include, for example, titanium oxide (TiO x ), hafnium oxide (HfO x ), zirconium oxide (ZrO x ), germanium oxide (GeO x ), cerium oxide (CeO x ) and tantalum oxide (TaO x ), and combinations thereof. Other suitable cap layer materials having oxygen storage functionality are within the contemplation of the present disclosure.

[0050] 10 is a vertical cross-sectional view of an example intermediate structure during the formation process of a resistive memory device showing a continuous top electrode layer 117L deposited over an optional continuous cap layer 115L, according to an embodiment of the present disclosure. In an embodiment where the optional cap layer 115L is not present, the continuous top electrode layer 117L may be deposited over the top surface of the continuous switch layer 113L. The continuous top electrode layer 117L may be deposited by a suitable deposition process as described above.

[0051] The continuous top electrode layer 117L may comprise any suitable conductive material, such as titanium (Ti), titanium nitride (TiN), gold (Au), tungsten (W), tungsten nitride (WN), aluminum copper (AlCu), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), iridium (Ir), iron (Fe), beryllium (Be), chromium (Cr), antimony (Sb), osmium (Os), thorium (Th), vanadium (V), copper (Cu), aluminum (Al), zirconium (Zr), alloys thereof, and combinations thereof. Other suitable materials for use in the continuous top electrode layer 117L are within the contemplation of the present disclosure. In some embodiments, the continuous top electrode layer 117L may be made of the same material(s) as the continuous bottom electrode layer 111L. Alternatively, the continuous top electrode layer 117L and the continuous bottom electrode layer 111L may be made of different materials. The continuous top electrode layer 117L may include a single layer of conductive material or multiple layers of conductive material that may have the same or different compositions.

[0052] FIG. 11 is a vertical cross-sectional view of an example intermediate structure during the formation process of a resistive memory device, showing a continuous hard mask layer 119L deposited above the continuous top electrode layer 117L, according to an embodiment of the present disclosure. The continuous hard mask layer 119L may be made of a suitable dielectric material, such as silicon carbide (SiC), silicon oxynitride (SiON), silicon nitride (SiN), and the like. Other suitable materials for the continuous hard mask layer 119L are within the contemplation of the present disclosure. The continuous hard mask layer 119L may be deposited by a suitable deposition process as described above. In an embodiment, a planarization process, such as a chemical mechanical planarization (CMP) process, may be performed to provide a flat upper surface 120 of the continuous hard mask layer 119L, as shown in FIG. 11.

[0053] 12 is a vertical cross-sectional view of an example intermediate structure during a resistive memory device formation process including a patterned mask 121 located above a continuous hard mask layer 119L according to an embodiment of the present disclosure. Referring to FIG. 12, the patterned mask 121 may include a photolithographically patterned photoresist layer, where a first region 122 of the example structure is covered by the patterned mask 121 and a second region 124 of the example structure is exposed by the patterned mask 121. The first region 122 may be on the metal portion 103 and may correspond to the location of a resistive memory element to be formed later. In various embodiments, the example intermediate structure may include a plurality of first regions 122 on which the patterned mask 121 is located, where each of the first regions 122 is on the metal portion 103 and corresponds to the location of a resistive memory element to be formed later. The second regions 124 exposed by the patterned mask 121 can extend continuously between the individual first regions 122 .

[0054] FIG. 13 is a vertical cross-sectional view of an example intermediate structure in a process of forming a resistive memory device after an etching process to remove portions of the continuous hard mask layer 119L, the continuous top electrode layer 117L, and the optional continuous cap layer 115L to provide a first stack 126 above the continuous switch layer 113L, according to an embodiment of the present disclosure. With reference to FIG. 13, an etching process, such as an anisotropic etching process, may be utilized to remove portions of the continuous hard mask layer 119L, the continuous top electrode layer 117L, and the optional continuous cap layer 115L from the second region 124 of the example intermediate structure exposed by the patterned mask 121. In some embodiments, the etching process may include multiple etching steps. For example, an initial etching step may be performed to remove portions of the continuous hard mask layer 119L and provide discrete hard masks 119 in the first region 122. The patterned mask 121 may be selectively removed by a suitable process, such as ashing or dissolving using a solvent. One or more subsequent etching steps may then be performed to remove portions of the continuous top electrode layer 117L and the optional continuous cap layer 115L to provide a first stack 126 including the discrete hard mask 119, the discrete top electrodes 117 and the optional discrete cap layer 115 above the continuous switch layer 113L. The subsequent etching steps may use different etching chemistries than the initial etching step, such that the hard mask 119 may protect the top electrodes 117 and the optional cap layer 115 from being etched in the first region 122 of the exemplary intermediate structure.

[0055] In various embodiments, after the etching process, the exemplary intermediate structure can include a plurality of first stacked layers 126 above the continuous switch layer 113L, and each of the first stacked layers 126 can be above a metal portion 103 and can correspond to the location of a resistive memory element to be formed later.

[0056] 14 is a vertical cross-sectional view of an example intermediate structure during the process of forming a resistive memory device, showing a continuous spacing material layer 123L deposited over the exposed top surface of the continuous switch layer 113L and over the top and side surfaces of the first stack 126, according to an embodiment of the present disclosure. With reference to FIG. 14, the continuous spacing material layer 123L may be comprised of any suitable dielectric material as described above, including oxide and / or nitride materials (e.g., SiN), and may be deposited by any suitable deposition process as described above.

[0057] FIG. 15 is a vertical cross-sectional view of an example intermediate structure during a process of forming a resistive memory device after an etching process to remove a portion of the continuous spacing material layer 123L to form at least one spacer 123 above a side of the first stacked layer 126 according to an embodiment of the present disclosure. With reference to FIG. 15, an etching process may be performed to remove the continuous spacing material layer 123L from above a top surface of the hard mask 119 and above a portion of the continuous switch layer 113L. After the etching process, the remaining portion of the continuous spacing material layer 123L may form at least one spacer 123. In some embodiments, a single spacer 123 may extend continuously around the periphery of the first stacked layer 126. Or, multiple spacers 123 may be located on different sides of the first stacked layer 126. At least one spacer 123 may be located above the continuous switch layer 113L and may extend along a side of the first stacked layer 126.

[0058] 16 is a vertical cross-sectional view of an example intermediate structure during a process of forming a resistive memory device including a patterned mask 125 and at least one spacer 123 located above a top surface of the hard mask 119 according to an embodiment of the present disclosure. Referring to FIG. 16, the patterned mask 125 may include a photoresist layer patterned by photolithography such that the patterned mask 125 covers the first stacked layer 126 and at least one spacer 123 extending above a side of the first stacked layer 126. The top surface of the continuous switch layer 113L can be exposed by the patterned mask 125. In an embodiment in which the example structure includes a plurality of first stacked layers 126, the patterned mask 125 may cover each of the first stacked layers 126 and the spacers 123 extending above a side of the stacked layers 126.

[0059] FIG. 17 is a vertical cross-sectional view of an example intermediate structure in a process of forming a resistive memory device after an etching process to remove portions of the continuous switch layer 113L, the continuous bottom electrode layer 111L, and the continuous barrier layer 109L to provide a second stack 127, according to an embodiment of the present disclosure. With reference to FIG. 17, an etching process, such as an anisotropic etching process, may be used to remove portions of the continuous switch layer 113L, the continuous bottom electrode layer 111L, and the continuous barrier layer 109L exposed by the patterned mask 125. The etching process may stop at the second dielectric material layer 105. The patterned mask 125 may protect the hard mask 119, the top electrode 117, the optional cap layer 115, and the at least one spacer 123 from being etched during the etching process. In various embodiments, the second dielectric material layer 105 may be an etch stop layer, which has a higher etch resistance to the etching chemistry to remove portions of the continuous barrier layer 109L than the material of the continuous barrier layer 109L. After the etching process, the patterned mask 125 may be removed by an appropriate process (eg, by ashing or dissolving using a solvent).

[0060] The etching process can form a second stack 127 including discrete barrier layers 109, discrete bottom electrodes 111 above the barrier layers 109, discrete switch layers 113 above the bottom electrodes 111, optional cap layers 115 above the switch layers 113, top electrodes 117 above the optional cap layers 115, and a hard mask 119 above the top electrodes 117. The second stack 127 can include at least one spacer 123 above a top surface of the switch layers 113 and above sides of the optional cap layers 115, top electrodes 117, and hard mask 119. The second stack 127 can be located in a third region 128 of the exemplary intermediate structure. The third region 128 can have a lateral extent greater than the first region 122 described above with reference to FIG. 12 along at least one horizontal direction (e.g., a first horizontal direction hd1 in FIG. 17). An upper surface of the second dielectric material layer 105 may be exposed in a fourth region 130 of the exemplary intermediate structure. The fourth region 130 may laterally surround the second stack 127.

[0061] In various embodiments, the exemplary intermediate structure may include a plurality of third regions 128, and each third region 128 may include a second stack 127, as shown in Figure 17. A fourth region 130 exposing a top surface of the second dielectric material layer 105 may extend continuously between the second stack 127 in each of the third regions 128.

[0062] 17, the barrier layer 109 of the second stack 127 may have a thickness T1 that is 6 nm or less, for example, between about 0.3 nm and about 6 nm, including between about 1 nm and about 4.5 nm. In various embodiments, the barrier layer 109 may include an outer portion 134 extending horizontally above an upper surface of the second dielectric material layer 105, and a central portion 136 recessed perpendicularly to the outer portion 134 and extending horizontally above an upper surface of the metal portion 103. The recessed central portion 136 may be located between the metal portion 103 and the bottom electrode 111. In various embodiments, the recessed central portion 136 of the barrier layer 109 may be in direct contact with an upper surface of the metal portion 103 and in direct contact with a lower surface of the bottom electrode 111.

[0063] In various embodiments, the bottom surface of the recessed central portion 136 of the barrier layer 109 may be flush with the bottom surface of the second dielectric material layer 105. In various embodiments, the top surface 138 of the second dielectric material layer 105 in the fourth region 130 of the exemplary intermediate structure may be flush with or vertically below the bottom surface of the outer portion 134 of the barrier layer 109. In the exemplary intermediate structure shown in FIG. 17, each of the bottom electrode 111, the switch layer 113, the optional cap layer 115, and the top electrode 117 may all have a shape similar to the barrier layer 109 and may include an outer portion that extends horizontally above the outer portion 134 of the barrier layer 109, and a central portion that is vertically recessed relative to the outer portion that is above the recessed central portion 136 of the barrier layer 109.

[0064] The second dielectric material layer 105 may have a thickness T2 in the fourth region 130 of the exemplary intermediate structure. In some embodiments, after an etching process that forms the second stack 127 in the third region 128 of the exemplary intermediate structure, the thickness T2 of the second dielectric material layer 105 in the fourth region 130 may be less than the thickness of the second dielectric material layer 105 in the third region 128. In some embodiments, the thickness T2 of the second dielectric material layer 105 in the fourth region 130 may be at least about 1 nm less than the thickness of the second dielectric material layer 105 in the third region 128. In the fourth region 130 of the exemplary intermediate structure, the uniformity of the thickness T2 of the second dielectric material layer 105 may be characterized by a half uniformity percentage, which is equal to half the range between the maximum and minimum thicknesses of the dielectric material layer 105 divided by the average thickness of the dielectric material layer 105, multiplied by 100. In various embodiments, when measured using a suitable thickness metrology technique (e.g., a spectroscopic reflectance metrology technique typically used to measure nanometer-scale thin film thicknesses), the half uniformity percentage of the thickness T2 may be less than 9%, including less than 8%. In some embodiments, the thickness T2 may have a 3-sigma uniformity metric of less than 14%, such as less than 12%.

[0065] In various embodiments, the thickness T2 of the second dielectric material layer 105 can have improved uniformity relative to an equivalent structure having a barrier layer 109 of a given thickness (e.g., ≧18 nm). According to various embodiments, providing an ultra-thin (e.g., ≦6 nm) barrier layer 109 allows greater control over the etching process for removing portions of the continuous barrier layer 109L to expose the top surface 138 of the second dielectric material layer 105. As the barrier layer 109 becomes relatively thicker, non-uniformities during the etching process can cause portions of the second dielectric material layer 105 to be over-etched. This can lead to damage to the second dielectric material layer 105 and can adversely affect device yields. Conversely, various embodiments of the present disclosure can provide at least about a 15% improvement in the uniformity of the thickness T2 of the second dielectric material layer 105. Thus, damage to the second dielectric material layer 105 can be reduced and device yields can be improved.

[0066] 17, the step H of each of the second stacks 127 may be defined as the maximum vertical distance between the top surface 138 of the second dielectric material layer 105 and the top surface of the top electrode 117 in the second stack 127. In various embodiments, the step(s) H in the exemplary intermediate structure may be less than 80 nm, including less than 70 nm, such as about 67 nm. By utilizing an ultra-thin (e.g., ≦6 nm) barrier layer 109, the step H may be reduced by at least about 15%, including as much as about 20%, compared to an equivalent structure having a barrier layer 109 of a given thickness (e.g., ≧18 nm) that may have a step H of at least about 82 nanometers. The reduction in step H may reduce processing time, lower manufacturing costs, improve yields, and facilitate integration of resistive memory devices according to various embodiments with advanced technology nodes.

[0067] 18 is a vertical cross-sectional view of an example intermediate structure during the formation process of a resistive memory device including a third dielectric material layer 129 above the exposed top surface 138 of the second dielectric material layer 105 and above the side and top surfaces of the second stack 127, according to an embodiment of the present disclosure. With reference to FIG. 18, the third dielectric material layer 129 may be conformally deposited above the top surface 138 of the second dielectric material layer 105 and above the side and top surfaces of the second stack 127 by a suitable deposition process as described above. The third dielectric material layer 129 may be comprised of a suitable dielectric material as described above. In various embodiments, the third dielectric material layer 129 may be an etch stop layer having different etching characteristics (i.e., high etch resistance) than the etching chemistry used in the subsequent etching step.

[0068] FIG. 19 is a vertical cross-sectional view of an example intermediate structure during the formation process of a resistive memory device including an optional buffer layer 131 above a third dielectric material layer 129 according to various embodiments of the present disclosure. With reference to FIG. 19, the optional buffer layer 131 may be deposited above an upper surface of the third dielectric material layer 129 by a suitable deposition process as described above. In some embodiments, the buffer layer 131 may be conformally deposited above the third dielectric material layer 129 to reduce stress between the third dielectric material layer 129 and a fourth dielectric layer (e.g., a low-k dielectric material layer) that may be later deposited above the example intermediate structure. The optional buffer layer may include silicon oxide, including silicon oxide formed using, for example, tetraethyl orthosilicate (TEOS) precursor. Other suitable materials for use in the optional buffer layer 131 are within the contemplation of the present disclosure.

[0069] FIG. 20 is a vertical cross-sectional view of an example intermediate structure during the formation process of a resistive memory device including a fourth dielectric material layer 133 above a buffer layer 131 according to various embodiments of the present disclosure. With reference to FIG. 20, the fourth dielectric material layer 133 may be deposited above the top surface of the buffer layer 131 by a suitable deposition process as described above. A planarization process, such as a chemical mechanical planarization (CMP) process, may optionally be used to provide a planar top surface of the fourth dielectric material layer 133. The fourth dielectric material layer 133 may include a suitable dielectric material as described above. In some embodiments, the fourth dielectric material layer 133 may include a low-k dielectric material, such as fluorosilicate glass (FSG), hydrogen silsesquioxane (HSQ), benzocyclobutene (BCB), organic polymer dielectric materials, carbon-doped silicon oxide, porous silicon dioxide, polymer foams, and the like. Other suitable dielectric materials are within the contemplation of the present disclosure. In some embodiments, the fourth dielectric material layer 133 may be made of the same material as the first dielectric material layer 101. Or, the fourth dielectric material layer 133 may have a different composition than the first dielectric material layer 101.

[0070] 21 is a vertical cross-sectional view of a resistive memory device 100 including a metal line 135 and a conductive via 137 extending from the metal line 135 through the fourth dielectric material layer 133, the buffer layer 131, the third dielectric material layer 129, and the hard mask 119 and contacting a top surface of the top electrode 117, according to various embodiments of the present disclosure. Referring to FIG. 21, the metal line 135 and the conductive via 137 may be formed by selectively etching the exemplary intermediate structure through a photolithographically patterned mask to form a via opening extending through the fourth dielectric material layer 133, the buffer layer 131, the third dielectric material layer 129, and the hard mask 119, and selectively etching the fourth dielectric material layer 133 through a photolithographically patterned mask to form a groove opening for the metal line 135. One or more metal materials (e.g., a metal liner layer and a metal fill material) as described above may be deposited over the top surface of the fourth dielectric material layer 133 and into the via and groove openings. The metal material(s) may be deposited by a suitable deposition process as described above. A planarization process, such as a chemical mechanical planarization (CMP) process, may be used to remove excess metal material(s) to provide metal traces 135 and conductive vias 137, as shown in FIG. 21 . In some embodiments, the metal traces 135 and conductive vias 137 may be formed simultaneously (e.g., using a dual damascene process). Alternatively, the metal traces 135 and conductive vias 137 may be formed using separate etching, deposition, and planarization steps (e.g., using separate single damascene processes).

[0071] In some embodiments, the etching process for forming the via opening may include an initial etch to form an opening through the fourth dielectric material layer 133 and the buffer layer 131. The initial etch may stop at the third dielectric material layer 129, which may be an etch stop layer as described above. One or more further etches may be used in the via opening that extends through the third dielectric layer 129 and the hard mask 119 to expose the top surface of the top electrode 117. The one or more further etches may use different etching chemistries than the initial etch.

[0072] 21, the memory device 100 in this embodiment includes a second stack 127 including a barrier layer 109 above the bottom metal portion 103, a bottom electrode 111 above the barrier layer 109, a switch layer 113 above the bottom electrode 111, an optional cap layer 115 above the switch layer 113, a top electrode 117 above the optional cap layer 115, and a hard mask 119 above the top electrode 117. The second stack 127 may include at least one spacer 123 above the top surface of the switch layer 113 and above the sides of the optional cap layer 115, the top electrode 117, and the hard mask 119. The second dielectric material layer 105 may extend under a portion of the second stack 127. A conductive via 137 may extend through the hard mask 119 and contact the top surface of the top electrode 117.

[0073] 21, the resistive memory device 100 may include a barrier layer 109 located between the bottom metal portion 103 and the bottom electrode 111. The barrier layer 109 may have a thickness of 6 nm or less, for example between about 0.3 nm and about 6 nm, including between about 1 nm and about 4.5 nm. The barrier layer 109 may include an outer portion 134 extending horizontally above an upper surface of the second dielectric material layer 105, and a central portion 136 recessed vertically relative to the outer portion 134 and extending horizontally above an upper surface of the bottom metal portion 103.

[0074] The bottom metal 103 and conductive vias 137 may be used to change the switch layer 113 from a high resistance state (HRS) to a low resistance state (LRS) or vice versa by applying a voltage to the second stack 127. In an exemplary structure, a plurality of memory devices 100 as shown in FIG. 21 may be formed. Each memory device 100 may form a single memory element (e.g., memory cell) of a resistive memory device array 95, as described above with reference to FIGS. 1B and 1C.

[0075] FIG. 22 is a vertical cross-sectional view of a resistive memory device 200 according to another embodiment of the present disclosure. The resistive memory device 200 shown in FIG. 22 may be similar to the resistive memory device 100 described above with reference to FIG. 21 and may include a second stack 127 having a barrier layer 109 above the bottom metal portion 103, a bottom electrode 111 above the barrier layer 109, a switch layer 113 above the bottom electrode 111, a top electrode 117 above the switch layer 113, and a hard mask 119 above the top electrode 117. The second stack 127 may include at least one spacer 123 above the top surface of the switch layer 113, the top electrode 117, and the hard mask 119. The second dielectric material layer 105 may extend below a portion of the second stack 127. The conductive via 137 may extend through the fourth dielectric material layer 133 , the buffer layer 131 , the third dielectric material layer 123 and the hard mask 119 , and may contact the top surface of the top electrode 117 .

[0076] The resistive memory device 200 shown in Fig. 22 may differ from the resistive memory device 100 in Fig. 21 because the optional cap layer 115 may be omitted from the second stack 127. The resistive memory device 200 shown in Fig. 22 may differ from the resistive memory device 100 in Fig. 21 because the bottom electrode 111 may have a planar top surface. Thus, the switch layer 113, the top electrode 117 and the hard mask 119 located above the bottom electrode 111 in the second stack 127 may also have planar top surfaces and may not include a recessed central portion.

[0077] The resistive memory device 200 in the embodiment of FIG. 22 may include a barrier layer 109 located between the bottom metal portion 103 and the bottom electrode 111. The barrier layer 109 may have a thickness of 6 nm or less, for example between about 0.3 nm and about 6 nm, including between about 1 nm and about 4.5 nm. The barrier layer 109 may include an outer portion 134 extending horizontally above an upper surface of the second dielectric material layer 105, and a central portion 136 recessed vertically relative to the outer portion 134 and extending horizontally above an upper surface of the bottom metal portion 103. The barrier layer 109 may further include at least one vertical portion 139 extending vertically between the outer portion 134 and the recessed central portion 136 of the barrier layer 109. At least one vertical portion 139 may laterally surround the bottom portion of the bottom electrode 111 and may be located between the bottom portion of the bottom electrode 111 and the second dielectric material layer 105 .

[0078] FIG. 23 is a vertical cross-sectional view of a resistive memory device 300 according to another embodiment of the present disclosure. The resistive memory device 300 shown in FIG. 23 may be similar to the resistive memory device 100 described above with reference to FIG. 21 and may include a second stack 127 including a barrier layer 109, a bottom electrode 111 above the barrier layer 109, a switch layer 113 above the bottom electrode 111, a top electrode 117 above the switch layer 113, and a hard mask 119 above the top electrode 117. The second dielectric material layer 105 may extend under a portion of the second stack 127. A conductive via 137 may extend through the fourth dielectric material layer 133, the buffer layer 131, the third dielectric material layer 123, and the hard mask 119, and may contact a top surface of the top electrode 117.

[0079] The resistive memory device 300 shown in Fig. 23 may differ from the resistive memory device 100 in Fig. 21 because the optional cap layer 115 may be omitted from the second stack 127. The resistive memory device 300 shown in Fig. 23 may differ from the resistive memory device 100 in Fig. 21 because the second stack 127 may include at least one spacer 123 above the top surface of the second dielectric material layer 105 and above the sides of the bottom electrode 111, the switch layer 113, the top electrode 117 and the hard mask 119.

[0080] The resistive memory device 300 of Figure 23 may differ from the resistive memory device 100 of Figure 21 because the barrier layer 109 may include a central portion 136 that extends horizontally above the bottom metal portion 103 and at least one vertical portion 139 that extends vertically between the central portion 136 of the barrier layer and the bottom surface of the bottom electrode 111. The barrier layer 109 in the embodiment of Figure 23 may not include an outer portion that extends horizontally above the top surface of the second dielectric material layer 105. The barrier layer 109 may have a thickness of 6 nm or less, for example, between about 0.3 nm and about 6 nm, including between about 1 nm and about 4.5 nm.

[0081] The resistive memory device 300 in the embodiment of FIG. 23 may also include an extended electrode 140, which may be located above a central portion 136 of the barrier layer 109 and may be laterally surrounded by at least one vertical portion 139 of the barrier layer 109. The central portion 136 of the barrier layer 109 may extend horizontally between a lower surface of the extended electrode 140 and an upper surface of the bottom metal portion 103. The at least one vertical portion 139 of the barrier layer 109 may extend between a side(s) of the extended electrode 140 and the second dielectric material layer 105. The upper surface of the extended electrode 140 may be in electrical contact with a lower surface of the bottom electrode 111. The extended electrode 140 may include any suitable metal material as described above. In some embodiments, the extended electrode 140 may be made of the same metal material as the bottom electrode 111. Alternatively, the extension electrode 140 may be made of a different metal material than the bottom electrode 111 .

[0082] FIG. 24 is a vertical cross-sectional view of a resistive memory device 400 according to another embodiment of the present disclosure. Referring to FIG. 24, the resistive memory device 400 may include a stack 142 including a barrier layer 109, a bottom electrode 111 above the barrier layer 109, a switch layer 113 above the bottom electrode 111, and a top electrode 117 above the switch layer 113. In the resistive memory device 400 shown in FIG. 24, when viewed in cross section along a plane parallel to the first horizontal direction hd1, the bottom electrode 111 may have a shape similar to the letter "U". Specifically, the bottom electrode 111 may have a central portion 144 extending horizontally above the bottom metal portion 103 and a pair of vertical portions 143, 145 extending vertically upward from either one side of the central portion 144 of the bottom electrode 111. The pair of vertical portions 143, 145 may extend above a plane containing the top surface of the second dielectric material layer 105. The switch layer 113 may extend horizontally above the top surface of the second dielectric material layer 105 and conformally extend above the "U" shaped bottom electrode 111, so that the switch layer 113 extends above the sides and top surface of the vertical portions 143, 145 of the bottom electrode 111 and horizontally above the central portion 144 of the bottom electrode 111. The top electrode 117 may conformally extend above the switch layer 113. The stacked layer 142 in the embodiment shown in FIG. 24 does not include the cap layer 115, the hard mask 119 or the spacer 129. Also, the embodiment shown in FIG. 24 does not include the third dielectric material layer 123 or the buffer layer 131 above the stacked layer 142.

[0083] 24 comprises a barrier layer 109 having a central portion 136 extending horizontally above the bottom metal portion 103 and at least one vertical portion 139 extending vertically between the central portion 136 of the barrier layer and a bottom surface of the bottom electrode 111. The central portion 136 of the barrier layer 109 may be located between the bottom metal portion 103 and a central portion 144 of the bottom electrode 111, and the vertical portion of the barrier layer 109 may be located between the respective vertical portions 143, 145 of the bottom electrode 111 and a side of the second dielectric material layer 105. The barrier layer 109 may have a thickness of 6 nm or less, for example between about 0.3 nm and about 6 nm, including between about 1 nm and about 4.5 nm.

[0084] The barrier layer 109 and the bottom electrode 111 may be located in an opening through the second dielectric material layer 105 and may not extend horizontally above a top surface of the second dielectric material layer 105. Thus, the stack 142 above the top surface of the second dielectric material layer 105 may include the switch layer 113 above the second dielectric material layer 105 and the top electrode 117 above the switch layer 113.

[0085] 24, the resistive memory device 400 may further include a metal line 135 and a conductive via 137 extending from the metal line 135 through the fourth dielectric material layer 133 and contacting a top surface of the top electrode 117. However, in the embodiment of the resistive memory device 400 shown in FIG. 24, the metal line 135 and the conductive via 137 may be laterally shifted relative to the bottom metal portion 103, the bottom electrode 111, and the barrier layer 109.

[0086] FIG. 25 is a vertical cross-sectional view of a resistive memory device 500 according to another embodiment of the present disclosure. The resistive memory device 500 shown in FIG. 25 may be similar to the resistive memory device 100 described above with reference to FIG. 21 and may include a second stack 127 having a barrier layer 109 above the bottom metal portion 103, a bottom electrode 111 above the barrier layer 109, a switch layer 113 above the bottom electrode 111, a top electrode 117 above the switch layer 113, and a hard mask 119 above the top electrode 117. At least one spacer 123 may be located above a top surface of the second dielectric material layer 105 and above the sides of the barrier layer 109, the bottom electrode 111, the switch layer 113, the top electrode 117, and the hard mask 119. The optional cap layer 115 is not present in the second stack 127 of the resistive memory device 500.

[0087] The resistive memory device 500 in the embodiment of FIG. 25 may include a barrier layer 109 located between the bottom metal portion 103 and the bottom electrode 111. The barrier layer 109 may have a thickness of 6 nm or less, for example between about 0.3 nm and about 6 nm, including between about 1 nm and about 4.5 nm. The barrier layer 109 may include an outer portion 134 extending horizontally above an upper surface of the second dielectric material layer 105, and a central portion 136 recessed vertically relative to the outer portion 134 and extending horizontally above an upper surface of the bottom metal portion 103. The barrier layer 109 may further include at least one vertical portion 139 extending vertically between the outer portion 134 and the recessed central portion 136 of the barrier layer 109. At least one vertical portion 139 may laterally surround the lower portion of the bottom electrode 111 and may be located between the lower portion of the bottom electrode 111 and the second dielectric material layer 105. The bottom electrode 111, the switch layer 113 and the top electrode 117 may have a shape similar to the barrier layer 109 and may each include outer portions extending horizontally above the outer portions 134 of the barrier layer 109 and central portions that are recessed vertically relative to the outer portions located above the recessed central portion 136 of the barrier layer 109.

[0088] 25, the resistive memory device 500 may further include a metal line 135 and a conductive via 137 extending from the metal line 135 through the fourth dielectric material layer 133, the buffer layer 131, the third dielectric material layer 129 and the hard mask 119 and contacting a top surface of the top electrode 117. In the embodiment of the resistive memory device 500 shown in FIG. 25, the metal line 135 and the conductive via 137 may be shifted laterally relative to the bottom metal portion 103. The conductive via 137 may contact the top electrode 117 at an outer portion of the top electrode 117 that extends in the horizontal direction.

[0089] 26 is a vertical cross-sectional view of a resistive memory device 100 and an access transistor 102 on a substrate 8 according to various embodiments of the present disclosure. With reference to FIG. 26, the resistive memory devices 100 described above may be arranged in a one transistor-one resistor (1T1R) configuration, with each resistive memory device 100 (which may also be referred to as a resistive memory element or cell) connected to an access transistor 102. In various embodiments, a two-dimensional array of memory cells 100 and corresponding access transistors 102 may be located on a substrate 8, such as the semiconductor substrate described above with reference to FIGS. 1A-1C.

[0090] The access transistor 102 can provide functions required to operate the resistive memory cell 100. In particular, the access transistor 102 can be used to control programming, erasing and sensing (reading) operations of the resistive memory cell 100. In some embodiments, the sensing circuitry and / or the top electrode bias circuitry system can be located on the substrate 8. In some embodiments, the access transistor 102 can be a field effect transistor (FET) and can include a complementary metal-oxide-semiconductor (CMOS) transistor. Although the embodiment shown in FIG. 26 illustrates a CMOS transistor 102, other transistors such as fin FETs, thin film transistors (TFTs), etc. can be used.

[0091] Metal interconnect structures (e.g., 41V, 41L, 42V, 42L, 43V, 103, 135, 137, 153, 155) may be used to connect each resistive memory cell 100 to the access transistor 102 and to connect the access transistor 102 to a corresponding signal line. For example, a first active region 14 (e.g., drain region) of the access transistor 102 may be electrically connected to a bottom electrode of the memory cell 100, for example, via a subset of the metal interconnect structures. A gate structure 20 of the access transistor 102 may be electrically connected to a word line, which may be embodied as a metal interconnect structure (e.g., metal wiring 155). A top electrode of the memory cell 100 may be electrically connected to a bit line, which may be embodied as a metal interconnect structure (e.g., metal wiring 135). A second active region 14 (e.g., source region) of the access transistor 102 may be electrically connected to a source line, which may be embodied as a metal interconnect structure (e.g., metal wiring 153). Although only four levels of metal wiring are shown in Figure 26, it will be understood that more metal wiring levels may be formed above the levels shown in Figure 26. It will also be understood that the level in which the source lines, word lines and bit lines are located, and the relative placement of these lines, may be selected based on design parameters.

[0092] FIG. 27 is a flow chart illustrating a method 301 for fabricating a resistive memory device 100, 200, 300, 400, 500 according to an embodiment of the present disclosure. With reference to FIG. 3 and FIG. 27, in step 302 of the method 301, a dielectric material layer 105 may be formed above the metal portion 103. With reference to FIG. 4, FIG. 5, and FIG. 27, in step 304 of the method 301, the dielectric material layer 105 may be etched to form an opening 108 through the dielectric material layer 105 to expose a surface of the metal portion 103 at a bottom of the opening 108. With reference to FIG. 6 and FIG. 27, in step 306 of the method 301, a barrier layer 109 having a thickness T1 of 6 nm or less may be formed above a surface of the metal portion 103 exposed at a bottom of the opening 108. In some embodiments, the barrier layer 109 may be formed by atomic layer deposition (ALD).

[0093] 7 and 27, in a step 308 of the method 301, a bottom electrode 111 may be formed above the barrier layer 109. In a step 310 of the method 301, a switch layer 113 may be formed above the bottom electrode 111. In a step 312 of the method 301, a top electrode 117 may be formed above the switch layer 113. In a step 314 of the method 301, a conductive via 137 may be formed in contact with the top electrode 117. In a step 314 of the method 301, a conductive via 137 may be formed in contact with the top electrode 117.

[0094] Referring to all drawings, in accordance with various embodiments of the present disclosure, a resistive memory device 100, 200, 300, 400, 500 comprises a metal portion 103, a barrier layer 109 having a thickness T1 of 6 nm or less above the metal portion 103, a bottom electrode 111 above the barrier layer 109, a switch layer 113 above the bottom electrode 111, an top electrode 117 above the switch layer 113, and a conductive via 137 in contact with the top electrode 117.

[0095] In one embodiment, the barrier layer 109 comprises a conductive oxide, nitride and / or oxynitride material to prevent diffusion of the metal portion 103 material into the bottom electrode 111 .

[0096] In another embodiment, the switch layer 113 comprises a solid dielectric material switchable between a high resistance state (HRS) and a low resistance state (LRS).

[0097] In another embodiment, the resistive memory device further comprises a first dielectric material layer 101 laterally surrounding the metal portion 103, a second dielectric material layer 105 above the first dielectric material layer 101 and having an opening 108 passing through the second dielectric material layer 105, and a barrier layer 109 including a portion 136 extending through the second dielectric material layer 105 above the metal portion 103 at the bottom of the opening 108.

[0098] In another embodiment, the barrier layer 109 further includes at least one vertical portion 139 extending along a sidewall of the opening 108 through the second dielectric material layer 105 .

[0099] In another embodiment, the bottom electrode 111 has a U-shaped cross-sectional shape including a central portion 144 extending horizontally through the second dielectric material layer 105 and within the opening 108, a pair of vertical portions 143, 145 extending vertically upward from opposite sides of the central portion 144 of the bottom electrode 111 and extending above a plane containing the top surface of the second dielectric material layer 105, a switch layer 113 extending conformally over each side and top surface of the vertical portion 143 and above the central portion 145 of the bottom electrode 111, and a top electrode 117 extending conformally above the switch layer 113.

[0100] In another embodiment, the resistive memory device further comprises an extended electrode 140 located within an opening 108 passing through the second dielectric material layer 105 and surrounded by a barrier layer 109 at the bottom and sides, and a lower electrode 111 located above an upper surface of the extended electrode 140.

[0101] In another embodiment, the barrier layer 109 further includes an outer portion 134 extending above the upper surface of the second dielectric material layer 105, and the portion 136 of the barrier layer 109 that extends through the second dielectric material layer 105 and above the metal portion 103 at the bottom of the opening 108 is a central portion 136 of the barrier layer 109 that is recessed vertically relative to the outer portion 134 of the barrier layer 109.

[0102] In another embodiment, a resistive memory device comprises a stack 127 over a first portion of the second dielectric material layer 105 and an opening 108 through the second dielectric material layer 105, and including a barrier layer 109, a bottom electrode 111, a switch layer 113, a top electrode 117, a hard mask 119 over the top electrode 117, and a conductive via 137 extending through the hard mask 119 and contacting the top electrode 117.

[0103] In another embodiment, the stack 127 further includes a cap layer 115 between the switch layer 113 and the top electrode 117 to provide an oxygen storage function contributing to the phase change in the switch layer 113, and at least one spacer 123 positioned above the sides of the cap layer 115, the top electrode 117 and the hard mask 119.

[0104] In another embodiment, the resistive memory device further comprises a third dielectric material layer 129 over the top surface of the second dielectric material layer 105 and the sides and top surface of the stack 127, a buffer layer 131 over the third dielectric material layer 129, and a fourth dielectric material layer 133 over the buffer layer 131, wherein the conductive via 137 extends through the fourth dielectric material layer 133, the buffer layer 131, the third dielectric material layer 129 and the hard mask 119 and contacts the upper electrode 117.

[0105] In another embodiment, the second portion of the second dielectric material layer 105 laterally surrounds the stack 127 and the thickness T2 of the second portion of the second dielectric material layer 105 has a half uniformity percentage less than 9%.

[0106] In another embodiment, conductive via 137 is shifted laterally relative to metal portion 103 .

[0107] In another embodiment, a resistive memory device 100, 200, 300, 400, 500 is proposed, comprising a dielectric material layer 105 and a stack 127 above a first portion of the dielectric material layer 105 and including a barrier layer 109, a bottom electrode 111 above the barrier layer 109, a switch layer 113 above the bottom electrode 111, and a top electrode 117 above the switch layer 113, wherein a second portion of the dielectric material layer 105 laterally surrounds the stack 127 and the maximum step height H between a top surface 138 of the second portion of the dielectric material layer 105 and a top surface of the top electrode 117 of the stack 127 is less than 80 nm.

[0108] In one embodiment, the dielectric material layer 105 is an etch stop layer, at least a portion of the barrier layer 109 passes through the etch stop layer 105 and is located in the opening 108 and is in electrical contact with the metal portion 103 underlying the stack 127, and the resistive memory device further comprises a conductive via 137 in contact with the top electrode 117.

[0109] In another embodiment, the resistive memory device comprises a plurality of stacked layers 127 each including a barrier layer 109, a bottom electrode 111 above the barrier layer 109, a switch layer 113 above the bottom electrode 111, and a top electrode 117 above the switch layer 113, and each forming a single resistive memory element of the resistive memory element array, the etch stop layer 105 extends continuously between each stacked layer 127, and the maximum step between a top surface of the etch stop layer 105 and a top surface of the top electrode 117 in each of the stacked layers 127 is less than 80 nm. In another embodiment, the etch stop layer comprises silicon carbide.

[0110] In another embodiment, a method for manufacturing a resistive memory device 100, 200, 300, 400, 500 is proposed, the method including the steps of forming a dielectric material layer 105 above the metal portion 103, etching the dielectric material layer 105 through the dielectric material layer 105 to form an opening 108 to expose a surface of the metal portion 103 at a bottom of the opening 108, forming a barrier layer 109 having a thickness T1 of 6 nm or less above the surface of the metal portion 103 exposed at the bottom of the opening 108, forming a bottom electrode 111 above the barrier layer 109, forming a switch layer 113 above the bottom electrode 111, forming a top electrode 117 above the switch layer 113, and forming a conductive via 137 in contact with the top electrode 117.

[0111] In one embodiment, the barrier layer 109 is formed by atomic layer deposition (ALD).

[0112] In another embodiment, forming the barrier layer 109 includes forming a continuous barrier layer 109L above an upper surface 138 of the dielectric material layer 105 and in an opening 108 passing through the dielectric material layer 105, and etching the continuous barrier layer 109L through a patterned mask 125 to remove a portion of the continuous barrier layer 109L to expose the upper surface 138 of the dielectric material layer 105, wherein after etching the continuous barrier layer 109L, a thickness T2 of the second dielectric material layer 105 has a half uniformity percentage of less than 9%.

[0113] The foregoing has outlined features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should readily appreciate that this disclosure may be used as a basis for designing or modifying other processes and structures which carry out the same purposes and / or achieve the same advantages as the embodiments incorporated herein. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions and alterations may be made herein without departing from the spirit and scope of the present disclosure. [Explanation of symbols]

[0114] 8 Substrate 10 Semiconductor material layer 12 Shallow trench isolation structure 14 Active area 15 Semiconductor Channels 18 Alloy area 20 Gate Structure 22 Gate Dielectric 24 Gate electrode 26 Dielectric Gate Spacer 28 Gate Cap Dielectric 31A Planarizing Dielectric Layer 31B, 32, 33, 34, 35, 36, 37 ILD layer 41L, 42L, 43L, 44L, 45L, 46L, 153, 155 Metal wiring 41V Contact Via Structure 42V Metal Via Structures / Vias 43V, 44V, 45V, 46V, 47V Metal via structures 47B Metal Bonding Pad 50 Memory Array Area 52 Peripheral Logic Area 75 CMOS Circuits 95 Memory Cell Array 100 Memory device / memory cell 101, 105 Dielectric material layer 103 Metal Parts 107 Mask 108 Aperture 109 Barrier Layer 109L Continuous barrier layer 111 Lower electrode 111L Continuous bottom electrode (layer) 113 Switch Layer 113L Continuous Switch Layer 115 Cap Layer 115L continuous cap layer 117 Upper electrode 117L Continuous top electrode layer 119, 121 Mask 119L Successive hardmask layers 120 flat top surface 122 First Area 123 Spacer 123L Continuously spaced material layers 124 Second Area 125 Patterned Mask 126, 127, 142 Lamination 128 The Third Region 129 Third dielectric material layer 130 The Fourth Region 131 Buffer Layer 133 Fourth dielectric material layer 134 External part 135 Metal wiring 136 (center) part 137 Conductive Vias 138 Top surface 139, 143, 145 Vertical section 140 Stretched electrode 144 Central part 200, 300, 400, 500 Resistive memory devices 301 Method 302 - 314 Processes L0, L1, L2, L3, L4, L5, L6, L7 Hierarchical structures

Claims

1. Metal parts and a barrier layer having a thickness of 6 nm or less above the metal portion; a bottom electrode above the barrier layer; a switch layer above the bottom electrode; a top electrode above the switch layer; a conductive via in contact with the upper electrode; a first layer of dielectric material laterally surrounding the metal portion; a second dielectric layer overlying the first dielectric layer and including an opening through the second dielectric layer; Equipped with the barrier layer includes a portion that extends above the metal portion at the bottom of the opening through the second dielectric material layer; the thickness of the second dielectric material layer is less in an area beyond the bottom electrode than in an area directly beneath the bottom electrode, and the thickness half uniformity percentage is less than 9%, the half uniformity percentage being half the range between the maximum and minimum thicknesses of the second dielectric material layer divided by the average thickness of the second dielectric material layer multiplied by 100; an elongated electrode located within the opening through the second dielectric layer and surrounded on a bottom and on a plurality of lateral sides by the barrier layer; The resistive memory device according to claim 1, wherein the lower electrode is located above an upper surface of the extended electrode.

2. 2. The resistive memory device of claim 1, wherein the barrier layer comprises a conductive oxide, nitride and / or oxynitride material for preventing diffusion of material of the metal portion into the bottom electrode.

3. 3. A resistive memory device according to claim 1 or 2, wherein the switch layer comprises a solid dielectric material switchable between a high resistance state and a low resistance state.

4. 2. The resistive memory device of claim 1, wherein said barrier layer further comprises at least one vertical portion extending along a sidewall of said opening through said second layer of dielectric material.

5. a dielectric material layer including an opening therethrough; a stack including a barrier layer over a first portion of the dielectric material layer, the barrier layer having a thickness of 6 nm or less, a bottom electrode over the barrier layer, a switch layer over the bottom electrode, and a top electrode over the switch layer; Equipped with the second portion of the dielectric material layer laterally surrounds the stack and the maximum step between a top surface of the dielectric material layer and a top surface of the upper electrode of the stack is less than 80 nm; the thickness of the dielectric material layer is less in an area beyond the bottom electrode than in an area directly beneath the bottom electrode, and the thickness half uniformity percentage is less than 9%, the half uniformity percentage being half the range between a maximum thickness and a minimum thickness of the dielectric material layer divided by an average thickness of the dielectric material layer multiplied by 100; an elongated electrode located within the opening through the dielectric layer and surrounded on a bottom and on a plurality of lateral sides by the barrier layer; The resistive memory device according to claim 1, wherein the lower electrode is located above an upper surface of the extended electrode.

6. forming a layer of dielectric material over the metal portion; etching the dielectric layer to form an opening through the dielectric layer exposing a surface of the metal portion at a bottom of the opening; forming a barrier layer having a thickness of 6 nm or less over the surface of the metal portion exposed at the bottom of the opening; forming an elongated electrode in the opening through the dielectric layer, the elongated electrode being surrounded on a bottom and on a plurality of lateral sides by the barrier layer; forming a lower electrode above the barrier layer and above a top surface of the extended electrode; forming a switch layer above the bottom electrode; forming a top electrode above the switch layer; forming a conductive via in contact with the top electrode; Including, 13. A method for manufacturing a resistive memory device, comprising: a thickness of the dielectric material layer that is thinner in an area beyond the bottom electrode than in an area directly beneath the bottom electrode; and a half uniformity percentage of the thickness that is less than 9%, the half uniformity percentage being equal to half the range between the maximum and minimum thicknesses of the dielectric material layer divided by the average thickness of the dielectric material layer and then multiplied by 100.

7. The method of claim 6 , wherein the barrier layer is formed by atomic layer deposition.

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