Imaging device

Abstract

An imaging device according to an embodiment of the present disclosure comprises a pixel. The pixel includes a photoelectric conversion unit, a charge accumulating unit of a first conductivity type, a first transistor, and a second transistor. The photoelectric conversion unit converts light into electric charges. The charge accumulating unit accumulates the electric charges generated by the photoelectric conversion unit. The first transistor includes a first gate electrode and a first diffusion region which includes an impurity of the first conductivity type and which functions as a source or a drain. The second transistor includes a second gate electrode and a second diffusion region which includes an impurity of a second conductivity type and which functions as a source or a drain. The second conductivity type is different from the first conductivity type. In a plan view, a distance D2 between the charge accumulating unit and the second transistor is greater than a distance between the charge accumulating unit and the first transistor.

Description

Imaging device

[0001] The present disclosure relates to an imaging device.

[0002] Image sensors are used in digital cameras, etc. Examples of image sensors include a charge coupled device (CCD) image sensor and a complementary metal oxide semiconductor (CMOS) image sensor.

[0003] In one example of an image sensor, a photodiode is provided on a semiconductor substrate.

[0004] In another example of an image sensor, a photoelectric conversion layer is provided above a semiconductor substrate. An imaging device having such a structure is sometimes called a stacked-type imaging device.

[0005] In one specific example of a stacked-type imaging device, signal charges are generated by photoelectric conversion. The generated charges are temporarily stored in a diffusion region provided on a semiconductor substrate. A signal corresponding to the amount of stored charge is read out via a CCD circuit or a CMOS circuit provided on the semiconductor substrate.

[0006] Patent Documents 1 to 3 and Non-Patent Document 1 describe imaging devices.

[0007] International Publication No. 2014 / 002330 International Publication No. 2012 / 147302 Patent No. 6323813

[0008] M. Goto et al.: “Pixel-Parallel 3-D Integrated CMOS Image Sensors with Pulse Frequency Modulation A / D Converters Developed by Direct Bonding of SOI Layers”, IEEE Trans. on Electron Devices, 62, 11, p. 3530.

[0009] There is a demand for techniques suitable for obtaining high quality images.

[0010] An imaging device according to an aspect of the present disclosure includes at least one pixel, the at least one pixel including: a photoelectric conversion unit that converts light into electric charges; a charge accumulation unit of a first conductivity type that accumulates the electric charges generated by the photoelectric conversion unit; a first transistor including a first gate electrode and a first diffusion region containing impurities of the first conductivity type and functioning as a source or drain; and a second transistor including a second gate electrode and a second diffusion region containing impurities of a second conductivity type different from the first conductivity type and functioning as a source or drain. In a plan view, a distance between the charge accumulation unit and the second transistor is longer than a distance between the charge accumulation unit and the first transistor.

[0011] The technology according to the present disclosure is suitable for obtaining high-quality images.

[0012] FIG. 1 is a schematic diagram showing an exemplary configuration of an imaging device according to a first embodiment. FIG. 2 is a schematic diagram showing an exemplary circuit configuration of a pixel of the imaging device according to the first embodiment. FIG. 3A is a schematic diagram showing an example of a photoelectric conversion unit. FIG. 3B is a schematic diagram showing an example of a photoelectric conversion unit. FIG. 4 is a schematic diagram showing an exemplary circuit configuration of a pixel and a readout circuit according to the first embodiment. FIG. 5 is a schematic diagram showing an exemplary circuit configuration of a pixel and a readout circuit according to a second embodiment. FIG. 6 is a schematic plan view showing an example of a layout of each element in a pixel according to the second embodiment. FIG. 7 is a cross-sectional view showing a pixel according to the second embodiment. FIG. 8 is a schematic plan view showing an example of a layout of each element in a pixel according to the first embodiment. FIG. 9 is a cross-sectional view showing a pixel according to a third embodiment. FIG. 10 is a cross-sectional view showing a schematic configuration example applicable to a pixel according to the third embodiment. FIG. 11 is a cross-sectional view showing a pixel according to a fourth embodiment. FIG. 12 is a cross-sectional view showing a pixel according to a fifth embodiment. FIG. 13 is a cross-sectional view schematically showing a pixel according to a sixth embodiment. FIG. 14 is a plan view schematically showing an example of the layout of each element in a pixel according to a seventh embodiment. FIG. 15 is a cross-sectional view schematically showing a pixel according to the seventh embodiment. FIG. 16 is a plan view schematically showing an example of the layout of a pixel array. FIG. 17 is a plan view schematically showing an example of the layout of a pixel region and a peripheral region. FIG. 18 is a cross-sectional view schematically showing the pixel shown in FIG. 17. FIG. 19 is a cross-sectional view schematically showing the pixel shown in FIG. 17. FIG. 20 is a schematic diagram showing a circuit configuration of a pixel in an embodiment using a photodiode. FIG. 21 is a plan view schematically showing an example of the layout of each element in a pixel in an embodiment using a photodiode.

[0013] (Summary of One Aspect of the Present Disclosure) An imaging device according to a first aspect of the present disclosure includes at least one pixel. The at least one pixel includes: a photoelectric conversion unit that converts light into electric charges; a charge accumulation unit of a first conductivity type that accumulates the electric charges generated by the photoelectric conversion unit; a first transistor including a first gate electrode and a first diffusion region that contains impurities of the first conductivity type and functions as a source or drain; and a second transistor including a second gate electrode and a second diffusion region that contains impurities of a second conductivity type different from the first conductivity type and functions as a source or drain. In a plan view, a distance between the charge accumulation unit and the second transistor is longer than a distance between the charge accumulation unit and the first transistor.

[0014] The technique according to the first aspect is suitable for obtaining high-quality images.

[0015] In a second aspect of the present disclosure, for example, in the imaging device according to the first aspect, the at least one pixel may include an isolation region that isolates the second transistor, and in a planar view, the distance between the charge accumulation portion and the isolation region may be longer than the distance between the charge accumulation portion and the first transistor.

[0016] The technique according to the second aspect is suitable for obtaining high-quality images.

[0017] In a third aspect of the present disclosure, for example, in the imaging device according to the first or second aspect, the first transistor may be an amplifying transistor that generates a signal according to the charge stored in the charge storage section.

[0018] The amplifier transistor is a specific example of the first transistor.

[0019] In a fourth aspect of the present disclosure, for example, in the imaging device according to any one of the first to third aspects, the first transistor may be located in a central region of the at least one pixel in a plan view.

[0020] According to the fourth aspect, it is easy to realize the magnitude relationship of the distances of the first aspect.

[0021] In a fifth aspect of the present disclosure, for example, in the imaging device according to any one of the first to fourth aspects, the charge accumulation section, the first transistor, and the second transistor may be arranged in this order along a certain direction in a planar view.

[0022] According to the fifth aspect, it is easy to realize the magnitude relationship of the distances of the first aspect.

[0023] In a sixth aspect of the present disclosure, for example, in the imaging device according to any one of the first to fifth aspects, the first conductivity type may be N-type, and the second conductivity type may be P-type.

[0024] The N-type is a specific example of the first conductivity type, and the P-type is a specific example of the second conductivity type.

[0025] In a seventh aspect of the present disclosure, for example, in an imaging device according to any one of the first to sixth aspects, the at least one pixel may include a first well region containing impurities of the second conductivity type, and a second well region containing impurities of the first conductivity type, and in a planar view, the first transistor may be located in the first well region and the second transistor may be located in the second well region, and in a planar view, the area of ​​the first well region may be larger than the area of ​​the second well region.

[0026] The configuration of the seventh aspect is a specific example of the pixel configuration.

[0027] In an eighth aspect of the present disclosure, for example, in an imaging device according to any one of the first to seventh aspects, the at least one pixel may include a plurality of pixels including a first pixel and a second pixel adjacent to each other, and in a planar view, the charge storage portion of the first pixel, the second transistor of the first pixel, the second transistor of the second pixel, and the charge storage portion of the second pixel may be arranged in this order along a certain direction.

[0028] The technique according to the eighth aspect is suitable for obtaining high-quality images.

[0029] In a ninth aspect of the present disclosure, for example, in the imaging device according to the seventh aspect, the at least one pixel may include a plurality of pixels including a first pixel and a second pixel adjacent to each other, and the first pixel and the second pixel may share one of the first well regions.

[0030] The ninth aspect is advantageous from the viewpoint of miniaturization of the imaging device.

[0031] In a tenth aspect of the present disclosure, for example, in an imaging device according to any one of the first to ninth aspects, the photoelectric conversion unit may include a photoelectric conversion layer that converts light into electric charges, and a pixel electrode that collects the electric charges generated in the photoelectric conversion layer, and the charge accumulation unit may accumulate the electric charges collected by the pixel electrode.

[0032] The tenth aspect is suitable for forming a stacked-type imaging device.

[0033] In an eleventh aspect of the present disclosure, for example, in the imaging device according to the tenth aspect, the at least one pixel may have a conductive structure that connects the pixel electrode and the charge accumulation portion.

[0034] The eleventh aspect is suitable for sending charges from a photoelectric conversion section to a charge accumulation section.

[0035] In a twelfth aspect of the present disclosure, for example, in the imaging device according to any one of the first to ninth aspects, the photoelectric conversion unit may be a photodiode.

[0036] The photodiode is a specific example of a photoelectric conversion unit.

[0037] In a thirteenth aspect of the present disclosure, for example, in an imaging device according to any one of the first to twelfth aspects, the imaging device may further include a semiconductor substrate, and the first diffusion region of the first transistor and the second diffusion region of the second transistor may be present in a cross section perpendicular to a main surface of the semiconductor substrate.

[0038] The configuration of the thirteenth aspect is a specific example of a pixel configuration. In a fourteenth aspect of the present disclosure, for example, in the imaging device according to any one of the first to thirteenth aspects, the first diffusion region of the first transistor may be different from the charge accumulation portion. In a fifteenth aspect of the present disclosure, for example, in the imaging device according to any one of the first to fourteenth aspects, the distance between the charge accumulation portion and the second gate electrode of the second transistor may be longer than the distance between the charge accumulation portion and the first gate electrode of the first transistor in a plan view.

[0039] An imaging device according to a sixteenth aspect of the present disclosure includes a pixel, wherein the pixel includes: a first transistor including a first diffusion region that is a source or drain and a first gate electrode that contains impurities of a first conductivity type; a second transistor including a second diffusion region that is a source or drain and a second gate electrode that contains impurities of a second conductivity type different from the first conductivity type; a first contact plug connected to the first diffusion region and containing impurities of the first conductivity type; and a second contact plug connected to the second diffusion region and containing impurities of the second conductivity type.

[0040] The technique according to the sixteenth aspect is suitable for obtaining high-quality images.

[0041] In a seventeenth aspect of the present disclosure, for example, in the imaging device according to the sixteenth aspect, the first diffusion region may contain impurities of the first conductivity type, and the second diffusion region may contain impurities of the second conductivity type.

[0042] The first conductivity type is a specific example of the conductivity type of the impurity contained in the first diffusion region, and the second conductivity type is a specific example of the conductivity type of the impurity contained in the second diffusion region.

[0043] In an eighteenth aspect of the present disclosure, for example, in the imaging device according to the sixteenth or seventeenth aspect, the first diffusion region may be a charge accumulation section that accumulates charge, and the first transistor may be a reset transistor that resets the potential of the first diffusion region.

[0044] The reset transistor is a specific example of the first transistor.

[0045] An imaging device according to a nineteenth aspect of the present disclosure includes a pixel, wherein the pixel includes: a first transistor including a source or a drain containing an impurity of the first conductivity type; and a second transistor including a source or a drain containing an impurity of a second conductivity type different from the first conductivity type.

[0046] A pixel according to a nineteenth aspect has transistors of mutually inverted polarities. The nineteenth aspect is suitable for realizing a small-sized, highly functional imaging device. One example of the first transistor according to the nineteenth aspect is an amplification transistor, and another example is a reset transistor.

[0047] An imaging device according to a twentieth aspect of the present disclosure includes a pixel, wherein the pixel includes: a first transistor including a first diffusion region that is a source or a drain and a first gate electrode that contains impurities of a first conductivity type; and a first plug that is connected to the first diffusion region and contains impurities of the first conductivity type.

[0048] The technique according to the twentieth aspect is suitable for obtaining a high-quality image. An example of the first transistor according to the twentieth aspect is a reset transistor.

[0049] In this specification, ordinal numbers such as first, second, third, etc. may be used. When an element is assigned an ordinal number, it is not necessary that there is an element of the same type with a lower number. The number of the ordinal number can be changed as needed.

[0050] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component arrangements and connection forms, steps, step orders, and the like shown in the following embodiments are merely examples and are not intended to limit the present disclosure. The various aspects described in this specification can be combined with each other unless a contradiction occurs. In the following description, components having substantially the same functions are denoted by the same reference numerals, and their descriptions may be omitted. Furthermore, to avoid overly complicated drawings, illustration of some elements may be omitted.

[0051] The various elements shown in the drawings are merely shown schematically to facilitate understanding of the present disclosure, and the dimensional ratios and appearances may differ from the actual objects. In other words, each drawing is a schematic diagram and is not necessarily an accurate illustration. Therefore, for example, the scales and the like do not necessarily match in each drawing.

[0052] A generic or specific aspect may be realized as an element, a device, a module, a system, or a method, or may be realized as any combination of an element, a device, a module, a system, and a method.

[0053] Additional benefits and advantages of the disclosed embodiments will become apparent from the specification and drawings. The benefits and / or advantages are provided individually by the various embodiments or features disclosed in the specification and drawings, and not all are required to obtain one or more of them.

[0054] The polarity of the transistors and the conductivity type of the diffusion regions in the following embodiments are merely examples, and unless otherwise inconsistent, the polarity of the transistors and the conductivity type of the diffusion regions may be reversed.

[0055] First Embodiment An imaging device 100 according to a first embodiment will be described below. The imaging device 100 includes a readout circuit 50A including a plurality of transistors.

[0056] 1 shows the circuit configuration of the imaging device 100. The imaging device 100 includes a plurality of pixels 110A and peripheral circuits. The plurality of pixels 110A and peripheral circuits are provided on a semiconductor substrate 60.

[0057] In this embodiment, the plurality of pixels 110A and the peripheral circuits are provided on a single semiconductor substrate 60. However, the plurality of pixels 110A and the peripheral circuits may be provided on separate semiconductor substrates.

[0058] In the imaging device 100, a plurality of pixels 110A are arranged two-dimensionally, thereby forming a pixel array.

[0059] In this embodiment, the multiple pixels 110A are arranged in a row direction and a column direction. The row direction and column direction refer to the directions in which the rows and columns extend, respectively. In FIG. 1 , the vertical direction, i.e., the up-down direction, is the column direction. The horizontal direction, i.e., the left-right direction, is the row direction. Specifically, the center of each pixel 110A is located on a lattice point of a square lattice.

[0060] The pixels 110A may be arranged in other patterns, for example, the center of each pixel 110A may be located on a lattice point of a triangular lattice, a hexagonal lattice, or the like.

[0061] The plurality of pixels 110A may be arranged one-dimensionally, in which case the imaging device 100 may be a line sensor.

[0062] The number of pixels 110A included in the imaging device 100 may be one.

[0063] Each of the pixels 110A is connected to a power supply line 120. A predetermined power supply voltage is supplied to each pixel 110A via the power supply line 120.

[0064] The imaging device 100 includes a photoelectric conversion unit 17. The photoelectric conversion unit 17 performs photoelectric conversion on incident light, thereby generating electric charges. In a typical example, each pixel 110A includes the photoelectric conversion unit 17.

[0065] In this embodiment, the photoelectric conversion section 17 is in the form of a film. The photoelectric conversion section 17 is stacked on the semiconductor substrate 60. In this way, the imaging device 100 constitutes a stacked-type imaging device.

[0066] In this embodiment, the photoelectric conversion units 17 of the multiple pixels 110A are continuously arranged without any gaps between them on the semiconductor substrate 60. The same voltage is supplied to all of the continuously arranged photoelectric conversion units 17.

[0067] In another example, the photoelectric conversion units 17 of the plurality of pixels 110A are arranged at intervals from one another on the semiconductor substrate 60. Different voltages can be supplied to the respective photoelectric conversion units 17.

[0068] The peripheral circuits include a control circuit 146, a voltage supply circuit 148, a vertical scanning circuit 141, a column signal processing circuit 142, a horizontal signal readout circuit 143, and a constant current source 144. The peripheral circuits may further include other signal processing circuits, output circuits, etc.

[0069] The voltage supply circuit 148 supplies a voltage to each pixel 110A via the accumulation control line 130. Specifically, the voltage supply circuit 148 supplies a voltage to the photoelectric conversion unit 17 via the accumulation control line 130.

[0070] The voltage supply circuit 148 may be a circuit that converts a voltage supplied from a power source such as a battery into a predetermined voltage. The voltage supply circuit 148 may be a circuit that generates a predetermined voltage. The voltage supply circuit 148 may be a part of the vertical scanning circuit 141.

[0071] In this embodiment, the column signal processing circuit 142 is arranged for each column of the pixel array of the pixels 110A. The constant current source 144 is arranged for each column of the pixel array of the pixels 110A.

[0072] The vertical scanning circuit 141 is connected to the band control signal line CON1 and the selection control signal line CON3.

[0073] The vertical scanning circuit 141 applies a predetermined voltage to the band control signal line CON1, thereby adjusting the feedback of the signal charge.

[0074] The vertical scanning circuit 141 applies a predetermined voltage to the selection control signal line CON3. This selects a row of the pixel array, and selects multiple pixels 110A belonging to that row. In this embodiment, the pixels 110A are selected row by row in this manner. Then, the signal voltage of the selected pixels 110A is read out, and the pixel electrodes are reset.

[0075] The column signal processing circuit 142 may also be referred to as a row signal storage circuit. The vertical scanning circuit 141 may also be referred to as a row scanning circuit. The selection control signal line CON3 may also be referred to as an address signal line.

[0076] The control circuit 146 controls the entire image pickup apparatus 100. During this control, the control circuit 146 receives command data, a clock, and the like. These are provided from outside the image pickup apparatus 100, for example.

[0077] Typically, the control circuit 146 has a timing generator. The control circuit 146 supplies drive signals to the vertical scanning circuit 141, the horizontal signal readout circuit 143, the voltage supply circuit 148, etc. In FIG. 1 , arrows extending from the control circuit 146 schematically represent the flow of output signals from the control circuit 146.

[0078] The control circuit 146 may be realized, for example, by a microcontroller including one or more processors. The functions of the control circuit 146 may be realized by a combination of a general-purpose processing circuit and software. The functions of the control circuit 146 may also be realized by hardware specialized for such processing.

[0079] The pixels 110A arranged in each column are electrically connected to a column signal processing circuit 142 via a vertical signal line 170 corresponding to each column. The column signal processing circuit 142 performs noise suppression signal processing, analog-to-digital conversion (A / D conversion), etc. The noise suppression signal processing is, for example, correlated double sampling.

[0080] The plurality of column signal processing circuits 142 are connected to a horizontal signal read circuit 143. The horizontal signal read circuit 143 reads out signals from the plurality of column signal processing circuits 142 and outputs the signals to a horizontal common signal line 180.

[0081] Next, the structure of the pixel 110A according to this embodiment will be described with reference to FIGS.

[0082] 2 shows the circuit configuration of the pixel 110 A. The pixel 110 A includes a photoelectric conversion unit 17 and a readout circuit 50 A.

[0083] The photoelectric conversion unit 17 receives incident light and generates signal charges. Hereinafter, the signal charges may be simply referred to as charges.

[0084] Specifically, the photoelectric conversion unit 17 generates positive and negative charges in response to incident light. In this embodiment, the positive charges are used as signal charges. Typically, the positive and negative charges are hole-electron pairs.

[0085] The readout circuit 50A reads out the signal charge generated by the photoelectric conversion unit 17. The readout circuit 50A includes an amplifier 2, a band control unit 3, a charge storage unit FD, and an output selection unit 5.

[0086] The charge storage unit FD stores the signal charge generated by the photoelectric conversion unit 17. The charge storage unit FD is a diffusion region provided in the semiconductor substrate 60.

[0087] The input of the amplifier 2 is connected to the charge storage unit FD. The amplifier 2 amplifies a signal corresponding to the signal charge stored in the charge storage unit FD and outputs the amplified signal to the band control unit 3 and the output selection unit 5.

[0088] The band control unit 3 includes a band control circuit 3A and a reset circuit 4A.

[0089] At least three different voltages are supplied to the band control circuit 3A from the voltage control circuit 99. The band control circuit 3A performs a band control function according to the supplied voltages. The band control circuit 3A applies band limitation to the output signal of the amplifier 2 and outputs the result to the charge storage unit FD.

[0090] The reset circuit 4A resets the charge storage unit FD, specifically, the reset circuit 4A resets the signal charge stored in the charge storage unit FD.

[0091] In the imaging device 100, a feedback circuit 30 is formed, which is a feedback loop that passes through the amplifier 2, the band control section 3, and the charge storage section FD.

[0092] In the feedback circuit 30, the signal read out from the charge storage unit FD is amplified by the amplifier 2, band-limited by the band control circuit 3A, and fed back to the charge storage unit FD.

[0093] The output selection unit 5 is connected to a signal readout line 7. The signal readout line 7 corresponds to the vertical signal line 170 shown in Fig. 1. The signal readout line 7 is shared by at least two pixels.

[0094] The output selection unit 5 has a function of outputting the signal amplified by the amplifier 2 to a signal read line 7. The output selection unit 5 has a function of supplying a current to the amplifier 2. These functions can be switched between each other.

[0095] 3A shows a photoelectric conversion unit 17A, which is a specific example of the photoelectric conversion unit 17 of this embodiment. FIG. 3B shows a photoelectric conversion unit 17B, which is another specific example of the photoelectric conversion unit 17.

[0096] 3A includes a photoelectric conversion layer 17b, a counter electrode 17c, and a pixel electrode 17a. The photoelectric conversion layer 17b is sandwiched between the counter electrode 17c and the pixel electrode 17a. The photoelectric conversion unit 17A is stacked on a semiconductor substrate 60.

[0097] The photoelectric conversion layer 17b is formed of an organic material or an inorganic material such as amorphous silicon. The photoelectric conversion layer 17b may include a layer made of an organic material and a layer made of an inorganic material. The photoelectric conversion layer 17b has a film shape. Typically, the photoelectric conversion layer 17b is provided continuously across the plurality of pixels 110A.

[0098] The pixel electrode 17a is formed from a metal such as aluminum or copper, a metal nitride, or polysilicon doped with impurities to provide conductivity. The pixel electrode 17a is spatially separated from the pixel electrodes 17a of other adjacent pixels 110A. This electrically separates the pixel electrode 17a from the pixel electrodes 17a of other pixels 110A.

[0099] The counter electrode 17c is formed of a transparent conductive material such as ITO (Indium Tin Oxide). Therefore, the counter electrode 17c is translucent. "Translucent" refers to the property of transmitting at least a portion of light having a wavelength that can be absorbed by the photoelectric conversion layer 17b, and it is not essential that the counter electrode 17c transmits light over the entire wavelength range of visible light. Typically, the counter electrode 17c is provided continuously across multiple pixels 110A, similar to the photoelectric conversion layer 17b.

[0100] A reference voltage Vp is applied to the counter electrode 17c. The pixel electrode 17a is connected to the charge storage unit FD. The photoelectric conversion layer 17b converts light into electric charges. The pixel electrode 17a collects the electric charges generated by the photoelectric conversion layer 17b. The charge storage unit FD stores the electric charges collected by the pixel electrode 17a.

[0101] Specifically, the pixel 110A has a conductive structure that connects the pixel electrode 17a and the charge storage portion FD. The conductive structure may include a wiring layer, a plug, etc. The conductive structure is not shown in FIG. 3A.

[0102] 3B is a photodiode. Specifically, the photoelectric conversion unit 17B is provided on a semiconductor substrate 60.

[0103] A reference voltage Vp is applied to one end of the photodiode, which is the photoelectric conversion unit 17B. When positive charges are read out as signal charges, the reference voltage Vp is typically a positive reference voltage. A charge accumulation unit FD is connected to the other end of the photodiode. The photodiode generates charges. The charge accumulation unit FD accumulates the charges generated by the photodiode.

[0104] The photoelectric conversion unit 17 may be an element having other photoelectric conversion functions.

[0105] Pixel 110A and readout circuit 50A will be further described with reference to FIG.

[0106] The read circuit 50A includes an amplifier transistor 200, a feedback transistor 301, a reset transistor 400, and a select transistor 502. The amplifier transistor 200, the feedback transistor 301, and the reset transistor 400 are N-type metal oxide semiconductor field effect transistors (MOSFETs). The select transistor 502 is a P-type MOSFET.

[0107] Hereinafter, an N-type MOSFET may be referred to as an NMOS, and a P-type MOSFET may be referred to as a PMOS.

[0108] In this embodiment, which of the two diffusion regions of the MOSFET corresponds to the source and which corresponds to the drain is determined by the polarity of the MOSFET and the level of the potential at that time, and therefore which corresponds to the source and which corresponds to the drain may vary depending on the operating state of the MOSFET.

[0109] However, it is also possible to configure an imaging device such that the two diffusion regions of a MOSFET are fixed as to which of them corresponds to the source and which to the drain, and some MOSFETs may have floating source and drain configurations, while others may have fixed source and drain configurations.

[0110] The amplifier 2 includes an amplifying transistor 200 and a switching circuit 20. The amplifying transistor 200 and the switching circuit 20 are connected to each other.

[0111] The gate of the amplifying transistor 200 is connected to the charge storage unit FD.

[0112] One of the source and drain of the amplifier transistor 200 is connected to one of the source and drain of the feedback transistor 301. One of the source and drain of the amplifier transistor 200 is connected to one of the source and drain of the selection transistor 502.

[0113] The switching circuit 20 includes a first switch element 11 and a second switch element 12. The switching circuit 20 is connected to the other of the source and the drain of the amplifying transistor 200.

[0114] Specifically, the other of the source and drain of the amplifying transistor 200 can be connected to a first voltage source VA1 via a first switch element 11. The other of the source and drain of the amplifying transistor 200 can also be connected to a second voltage source VA2 via a second switch element 12. By controlling the switching circuit 20 with control signals V1 and V2, the voltage applied to the other of the source and drain of the amplifying transistor 200 can be switched between voltage Va1 and voltage Va2.

[0115] The voltage Va1 of the first voltage source VA1 is, for example, the ground voltage GND, and the voltage Va2 of the second voltage source VA2 is, for example, the power supply voltage VDD.

[0116] The switching circuit 20 may be provided for each pixel, or may be shared by a plurality of pixels. Sharing the switching circuit 20 is advantageous from the viewpoint of reducing the number of elements per pixel.

[0117] The band control circuit 3A includes a feedback transistor 301, a first capacitance element 9, and a second capacitance element 10.

[0118] The term "capacitor element" refers to a structure in which a dielectric such as an insulating film is sandwiched between electrodes. The term "electrode" is not limited to an electrode made of metal, but is broadly interpreted to include a polysilicon layer and the like. The electrode may be a part of the semiconductor substrate 60.

[0119] The first capacitance element 9 and the second capacitance element 10 may be MIM (Metal Insulator Metal) capacitances or MIS (Metal Insulator Semiconductor) capacitances.

[0120] One of the source and drain of the feedback transistor 301 is connected to one of the source and drain of the amplification transistor 200. One of the source and drain of the feedback transistor 301 is connected to one of the source and drain of the selection transistor 502.

[0121] The other of the source and drain of the feedback transistor 301 is connected to one end of the first capacitance element 9. A reference voltage VR1 is applied to the other end of the first capacitance element 9. The feedback transistor 301 and the first capacitance element 9 form an RC filter circuit.

[0122] The other of the source and drain of the feedback transistor 301 is also connected to one end of the second capacitance element 10. The other end of the second capacitance element 10 is connected to the charge storage section FD.

[0123] Hereinafter, the node formed between the feedback transistor 301, the first capacitive element 9, and the second capacitive element 10 may be referred to as a "node RD." Here, the node refers to an electrical connection between multiple elements in an electric circuit, and is a concept that includes wiring and the like that provides the electrical connection between the elements.

[0124] The gate of the feedback transistor 301 is connected to a band control signal line CON1.

[0125] The reset circuit 4A includes a reset transistor 400 .

[0126] The reset transistor 400 includes a charge storage portion FD as one of the source and the drain. A node RD is connected to the other of the source and the drain of the reset transistor 400. The gate of the reset transistor 400 is connected to a reset control signal line CON2.

[0127] The voltage of the reset control signal line CON2 determines the state of the reset transistor 400. For example, when the voltage of the reset control signal line CON2 is at a high level, the reset transistor 400 is in an on state. In this state, the charge storage unit FD is reset to the reference voltage VR2.

[0128] 4, the voltage of node RD is applied to the reset transistor 400. In this way, it is possible to reduce the change in voltage of the charge storage section FD before and after turning off the reset transistor 400. This enables high-speed noise suppression.

[0129] The output selection unit 5 includes a selection transistor 502 .

[0130] In this embodiment, the select transistor 502 has a polarity opposite to that of the amplifying transistor 200. Specifically, the amplifying transistor 200 is an NMOS, and the select transistor 502 is a PMOS.

[0131] One of the source and drain of the selection transistor 502 is connected to one of the source and drain of the amplification transistor 200. The other of the source and drain of the selection transistor 502 is connected to the signal read line 7.

[0132] The gate of the selection transistor 502 is connected to a selection control signal line CON3. The state of the selection transistor 502 is determined by the voltage of the selection control signal line CON3.

[0133] For example, when the voltage of the selection control signal line CON3 is at a low level, the selection transistor 502 is in an on state. In this state, the amplification transistor 200 and the signal read line 7 are electrically connected.

[0134] When the voltage of the selection control signal line CON3 is at a high level, the selection transistor 502 is in an off state, in which the amplification transistor 200 and the signal read line 7 are electrically isolated from each other.

[0135] When the voltage of the selection control signal line CON3 is between low and high levels, the selection transistor 502 operates as a current source. This causes a current to be supplied to the amplification transistor 200. The amount of current is determined by the voltage of the selection control signal line CON3. The designer can design the read circuit 50A to obtain a desired amount of current. The voltage between low and high levels is, for example, an intermediate voltage between these two levels.

[0136] The switching circuit 40 is connected to the signal read line 7. The switching circuit 40 includes a third switch element 13, a fourth switch element 14, voltage sources VB1 and VB2, and a constant current source 6. The constant current source 6 corresponds to the constant current source 144 shown in FIG.

[0137] One terminal of a constant current source 6 can be connected to the signal readout line 7 via a third switch element 13. A voltage source VB2 can be connected to the signal readout line 7 via a fourth switch element 14. The other terminal of the constant current source 6 is connected to a voltage source VB1.

[0138] A control signal V3 can be supplied to the third switch element 13. A control signal V4 can be supplied to the fourth switch element 14. The control signals V3 and V4 can switch between connecting the voltage source VB2 or the constant current source 6 to the signal read line 7.

[0139] The voltage Vb1 of the voltage source VB1 is, for example, the ground voltage GND, and the voltage Vb2 of the voltage source VB2 is, for example, the power supply voltage VDD.

[0140] When the voltage source VB2 is connected to the signal read line 7 and the voltage of the selection control signal line CON3 is between a low level and a high level, the selection transistor 502 operates as a current source. In this case, the selection transistor 502 and the amplification transistor 200 form an inverting amplifier circuit. The voltage between the low level and the high level is, for example, an intermediate voltage between these levels.

[0141] When the constant current source 6 is connected to the signal read line 7 and the voltage of the selection control signal line CON3 is at a low level, the amplifying transistor 200 and the constant current source 6 form a source follower circuit. In this case, a signal corresponding to the signal charge accumulated in the charge accumulation unit FD is output to the signal read line 7 and read out to the outside.

[0142] The constant current source 6 may be provided for each pixel, or may be shared by a plurality of pixels. Sharing the constant current source 6 is advantageous from the viewpoint of reducing the number of elements per pixel.

[0143] The imaging device 100 includes a feedback circuit 30. The feedback circuit 30 negatively feeds back the signal from the photoelectric conversion unit 17 to the charge storage unit FD via the amplification transistor 200.

[0144] The state of the feedback transistor 301 is determined by the voltage of the band control signal line CON1.

[0145] For example, when the voltage of the band control signal line CON1 is at a high level, the feedback transistor 301 is in an on state. In this case, the charge storage unit FD, the amplification transistor 200, the feedback transistor 301, and the second capacitive element 10 form a feedback circuit 30.

[0146] When the voltage of the band control signal line CON1 decreases, the resistance component of the feedback transistor 301 increases, thereby narrowing the band of the feedback transistor 301 and narrowing the frequency range of the feedback signal.

[0147] When the feedback circuit 30 is formed, the signal output from the feedback transistor 301 is attenuated by an attenuation circuit including the second capacitive element 10 and the parasitic capacitance of the charge storage unit FD, and is fed back to the charge storage unit FD.

[0148] When the voltage of the band control signal line CON1 further drops to a low level, the feedback transistor 301 is turned off. In the off state, the feedback circuit 30 is not formed.

[0149] For details of the operation and control of the imaging device 100 according to the first embodiment, please refer to Patent Document 3, etc. The same applies to the second embodiment.

[0150] Several other embodiments will be described below. In the following, elements common to the embodiments already described and the embodiments to be described thereafter will be given the same reference numerals, and their description may be omitted. The descriptions of the respective embodiments may be mutually applied unless technically inconsistent. The respective embodiments may be combined with each other unless technically inconsistent.

[0151] Second Embodiment A second embodiment will now be described. Fig. 5 shows the circuit configuration of a pixel 110B and a readout circuit 50B according to the second embodiment.

[0152] 5, the switching circuit 40 has constant current sources 6A and 6B. The output selection unit 5 has a selection transistor 503 instead of the selection transistor 502. The polarity of the selection transistor 503 is the same as the polarity of the amplification transistor 200, etc. In this example, the selection transistor 503 is an NMOS.

[0153] The constant current source 6A corresponds to the constant current source 6 in Fig. 4 etc. In other words, the constant current source 6A corresponds to the constant current source 144 in Fig. 1 .

[0154] The gate of the selection transistor 503 is connected to a selection control signal line CON3. The state of the selection transistor 503 is determined by the voltage of the selection control signal line CON3.

[0155] For example, when the voltage of the selection control signal line CON3 is at a high level, the selection transistor 503 is in an on state. In this state, the amplification transistor 200 and the signal read line 7 are electrically connected.

[0156] When the voltage of the selection control signal line CON3 is at a low level, the selection transistor 503 is in an off state, in which the amplification transistor 200 and the signal read line 7 are electrically isolated from each other.

[0157] In the second embodiment, a current is supplied from the constant current source 6B to the amplifying transistor 200 by turning on the fourth switch element 14 and the selection transistor 503 .

[0158] In the imaging device 100 according to the second embodiment, the pixel 110B includes an inverting transistor 600 in addition to the amplifying transistor 200, the feedback transistor 301, the reset transistor 400, and the selecting transistor 503. The inverting transistor 600 has an inverted polarity relative to the amplifying transistor 200, the feedback transistor 301, the reset transistor 400, and the selecting transistor 503. In this example, the inverting transistor 600 is a PMOS. The amplifying transistor 200, the feedback transistor 301, the reset transistor 400, and the selecting transistor 503 are NMOS.

[0159] The inverting transistor 600 can cooperate with another transistor having an inverted polarity to that of the inverting transistor 600 to form a CMOS. By using CMOS, it is possible to realize a circuit having a specific function. For example, by using CMOS, it is possible to realize an inverter that performs A / D conversion.

[0160] In a so-called stacked-type imaging device in which the photoelectric conversion unit 17 is stacked on the semiconductor substrate 60, it is easy to secure space for forming a CMOS on the semiconductor substrate 60. However, even in an imaging device using a photodiode, a CMOS can be formed using an inversion transistor 600.

[0161] The inversion transistor 600 may or may not be included in the readout circuit. The other transistor that cooperates with the inversion transistor 600 to form the CMOS may be a transistor shown in the figure or a transistor not shown in the figure.

[0162] (Plane Layout and Cross-Sectional View) Fig. 6 is a schematic plan view of a pixel 110B according to the second embodiment, and Fig. 7 is a schematic cross-sectional view of the pixel 110B.

[0163] Fig. 6 schematically shows the arrangement of each element provided on the semiconductor substrate 60 when the pixel 110B shown in Fig. 7 is viewed along the normal direction of the semiconductor substrate 60. The cross section shown in Fig. 7 is obtained by cutting the pixel 110B along the dashed line VII-VII in Fig. 6 and developing it. Some elements are omitted from Fig. 6.

[0164] The pixel 110B includes a semiconductor substrate 60, a photoelectric conversion unit 17, a conductive structure 89, and an interlayer insulating layer 90. The conductive structure 89 is disposed above the semiconductor substrate 60. Specifically, the conductive structure 89 is disposed on the light incident side as viewed from the semiconductor substrate 60.

[0165] The semiconductor substrate 60 includes a support substrate 61, a P-type semiconductor region 61p, a P-well 65p, an N-well 65n, a diffusion region 67n, a diffusion region 68an, a diffusion region 68bn, a diffusion region 72ap, a diffusion region 72bp, an element isolation region 69a, and an element isolation region 69b.

[0166] The support substrate 61 is a P-type substrate. Specifically, the support substrate 61 is a P-type silicon substrate.

[0167] The P-type semiconductor region 61p is disposed on the support substrate 61. The P-type semiconductor region 61p contains P-type impurities at a lower concentration than the support substrate 61.

[0168] The P-well 65p is disposed in the P-type semiconductor region 61p. The P-well 65p is lower than the support substrate 61 and contains P-type impurities at a concentration higher than that of the P-type semiconductor region 61p.

[0169] The N-well 65n is disposed in the P-type semiconductor region 61p and contains N-type impurities.

[0170] A P-well is a P-type impurity region, and an N-well is an N-type impurity region.

[0171] 6, an "NMOS Tr. region" is a region where the P-well 65p extends in a plan view, and a "PMOS Tr. region" is a region where the N-well 65n extends in a plan view.

[0172] 7, an insulating layer 70 is provided on a semiconductor substrate 60. Specifically, the insulating layer 70 covers a wide area on the semiconductor substrate 60.

[0173] The reset transistor 400 includes a diffusion region 67n as one of the source and drain. The reset transistor 400 includes a diffusion region 68bn as the other of the source and drain. The reset transistor 400 includes an insulating layer 70 and a gate electrode 400e. The gate electrode 400e is provided on the insulating layer 70.

[0174] The diffusion region 67n also serves as the charge storage unit FD. The diffusion region 67n temporarily stores the signal charge generated by the photoelectric conversion unit 17. In Fig. 6, the electrical connection between the charge storage unit FD and the gate electrode 200e of the amplification transistor 200 is shown by a bold line.

[0175] The feedback transistor 301 includes a diffusion region 68an as one of a source and a drain. The feedback transistor 301 includes a diffusion region 68bn as the other of a source and a drain. The feedback transistor 301 includes an insulating layer 70 and a gate electrode 301e. The gate electrode 301e is provided on the insulating layer 70.

[0176] The inversion transistor 600 includes a diffusion region 72bp as one of the source and drain. The inversion transistor 600 includes a diffusion region 72ap as the other of the source and drain. The inversion transistor 600 includes an insulating layer 70 and a gate electrode 600. The gate electrode 600 is provided on the insulating layer 70.

[0177] The diffusion regions 67n, 68an, and 68bn are N-type impurity regions, and the diffusion regions 72ap and 72bp are P-type impurity regions.

[0178] The diffusion region 67n is disposed within the P-type semiconductor region 61p. The diffusion region 67n includes a first region 67a and a second region 67b. The second region 67b is provided within the first region 67a. The second region 67b has a higher impurity concentration than the first region 67a.

[0179] Diffusion regions 68an and 68bn are disposed in P-well 65p, while diffusion regions 72ap and 72bp are disposed in N-well 65n.

[0180] The inverting transistor 600 is a PMOS. The amplifying transistor 200, the feedback transistor 301, the reset transistor 400 and the selection transistor 503 are NMOS.

[0181] The element isolation region 69a electrically isolates the inversion transistor 600, which is a PMOS, from the amplification transistor 200, feedback transistor 301, reset transistor 400, and selection transistor 503, which are NMOS. In this embodiment, the element isolation region 69a is a region formed by implantation isolation. In this embodiment, the element isolation region 69a is an N-type impurity region. Specifically, in this embodiment, the element isolation region 69a is an N-type impurity region having a higher impurity concentration than the N-well 65n.

[0182] The element isolation region 69b electrically isolates the NMOS amplifier transistor 200, feedback transistor 301, reset transistor 400, and select transistor 503 from the PMOS inversion transistor 600. In this embodiment, the element isolation region 69b is a region formed by implantation isolation. In this embodiment, the element isolation region 69b is a P-type impurity region. Specifically, in this embodiment, the element isolation region 69b is a P-type impurity region having a higher impurity concentration than the P-well 65p.

[0183] The interlayer insulating layer 90 covers the semiconductor substrate 60. The interlayer insulating layer 90 supports the photoelectric conversion section 17. A conductive structure 89 is disposed inside the interlayer insulating layer 90.

[0184] The interlayer insulating layer 90 includes a plurality of insulating layers 90a, 90b, 90c and an insulating layer 90d. The number of insulating layers included in the interlayer insulating layer 90 is not particularly limited.

[0185] The conductive structure 89 includes a plurality of wiring layers 80a, 80b, and 80c. The conductive structure 89 includes a plurality of plugs pa1, pa2, pa3, pa4, pa5, pa6, pa7, pa8, pb, pc, pd, cg1, cg3, and cg5.

[0186] The plug is a component used to connect elements. The material and structure of the plug are not particularly limited.

[0187] The concept of plug includes direct plug, via plug, and contact plug. The materials, structures, etc. of the direct plug, via plug, and contact plug may be the same as or different from one another.

[0188] A direct-connection plug is a plug that is directly connected to a wiring layer and is used to electrically connect the wiring layer to an element located closer to the semiconductor substrate than the wiring layer.

[0189] In one specific example, the direct coupling plug is directly connected to the wiring layer closest to the semiconductor substrate. Specific examples of the "element located closer to the semiconductor substrate than the wiring layer" to which the direct coupling plug is electrically connected include a gate electrode, a contact plug, a diffusion region, or a conductive layer.

[0190] An example of the material of the direct connection plug is a metal such as copper (Cu) or tungsten (W). In the illustrated example, the material of the direct connection plug is tungsten.

[0191] A via plug refers to a plug that electrically connects a wiring layer to another wiring layer, or a plug that is used to electrically connect a wiring layer to an element that is located closer to the photoelectric conversion unit than the wiring layer.

[0192] A specific example of the above-mentioned "via plug used to electrically connect a wiring layer to an element located on the photoelectric conversion unit side of the wiring layer" is to electrically connect the wiring layer closest to the pixel electrode to the pixel electrode.

[0193] An example of the material of the via plug is a metal such as copper (Cu) or tungsten (W). A specific example of the material of the via plug is copper.

[0194] The contact plug is a plug containing impurities of a first conductivity type or a second conductivity type. Here, the first conductivity type and the second conductivity type are mutually different conductivity types. The first conductivity type is N-type or P-type. The second conductivity type is P-type or N-type.

[0195] The contact plug is connected to, for example, a diffusion region or a gate electrode.

[0196] In one embodiment, the contact plug is interposed between the direct contact plug and the diffusion region or between the direct contact plug and the gate electrode in the pixel.

[0197] In one specific example, the contact plug is a plug that is interposed between a first element and a second element to achieve a contact resistance between the first element and the contact plug that is lower than a default resistance, and to achieve a contact resistance between the second element and the contact plug that is lower than the default resistance. Here, the default resistance is the contact resistance between the first element and the second element when the first element and the second element are directly connected. For example, the contact plug achieves low contact resistance by being interposed between a direct-coupled plug as the first element and a diffusion region as the second element.

[0198] An example of the material of the contact plug is polysilicon.

[0199] In the illustrated example, plugs pb, pc, and pd are via plugs. Plugs pa1, pa2, pa3, pa4, pa5, pa6, pa7, and pa8 are direct-coupled plugs. Plugs cg1, cg3, and cg5 are contact plugs. Plugs cg1, cg3, and cg5 have film-shaped portions.

[0200] The plugs pa6, pa8, cg1, cg3 and cg5 penetrate the insulating layer 70.

[0201] There is no particular limitation on the number of wiring layers included in the conductive structure 89. There is no particular limitation on the number of plugs included in the conductive structure 89.

[0202] The multiple wiring layers may include some or all of the band control signal line CON1, the reset control signal line CON2, and the selection control signal line CON3.

[0203] The plugs cg1, cg3, cg5, pa1, pa2, pa3, pa4, pa5, pa6, pa7, and pa8 are disposed in the insulating layer 90a. The wiring layer 80a is disposed in the insulating layer 90a.

[0204] The plug pb and the wiring layer 80b are disposed in an insulating layer 90b. The plug pc and the wiring layer 80c are disposed in an insulating layer 90c. The plug pd is disposed in an insulating layer 90d.

[0205] The interconnect layer 80a is electrically connected to the diffusion region 68an via a plug pa1 and a plug cg1 in this order. The interconnect layer 80a is electrically connected to the diffusion region 68bn via a plug pa3 and a plug cg3 in this order. The interconnect layer 80a is electrically connected to the diffusion region 72ap via a plug pa6. The interconnect layer 80a is electrically connected to the diffusion region 72bp via a plug pa8.

[0206] Specifically, the diffusion region 68an includes a first region 68an1 and a second region 68an2. The second region 68an2 is provided within the first region 68an1. The second region 68an2 has a higher impurity concentration than the first region 68an1. The plug cg1 is connected to the second region 68an2.

[0207] The diffusion region 68bn includes a first region 68bn1 and a second region 68bn2. The second region 68bn2 is provided within the first region 68bn1. The second region 68bn2 has a higher impurity concentration than the first region 68bn1. The plug cg3 is connected to the second region 68bn2.

[0208] The interconnect layer 80a is electrically connected to the gate electrode 301e via a plug pa2. The interconnect layer 80a is electrically connected to the gate electrode 400e via a plug pa4. The interconnect layer 80a is electrically connected to the gate electrode 600e via a plug pa7.

[0209] The pixel electrode 17a is electrically connected to the diffusion region 67n, i.e., the charge storage portion FD, via a conductive structure 89. Specifically, the pixel electrode 17a is electrically connected to the diffusion region 67n via a plug pd, a wiring layer 80c, a plug pc, a wiring layer 80b, a plug pb, a wiring layer 80a, a plug pa5, and a plug cg5, in this order. Specifically, the plug cg5 is connected to the second region 67b of the diffusion region 67n.

[0210] In this embodiment, the wiring layers 80a, 80b, and 80c are formed of a metal such as copper or tungsten, or a metal compound such as a metal nitride or a metal oxide, etc. The same applies to the plugs (specifically, direct coupling plugs) pa1, pa2, pa3, pa4, pa5, pa6, pa7, and pa8 and the plugs (specifically, via plugs) pb, pc, and pd.

[0211] In the illustrated example, there is one electrical path connecting the wiring layer 80a and the diffusion region 72ap, and more specifically, this electrical path is configured by one plug. However, there may be multiple parallel electrical paths connecting the wiring layer 80a and the diffusion region 72ap, and more specifically, such parallel electrical paths may be configured by multiple plugs. In this way, the contact resistance between the electrical path and the diffusion region 72ap can be reduced compared to when there is only one electrical path. This can improve the performance of the characteristic transistor 600. The same applies to the number of electrical paths connecting the wiring layer 80a and the diffusion region 72bp.

[0212] In this embodiment, the plugs (specifically, contact plugs) cg1, cg3, and cg5 are formed of polysilicon. This increases the conductivity of the plugs cg1, cg3, and cg5 and reduces the contact resistance between the plugs cg1, cg3, and cg5 and the diffusion regions 68an, 68bn, and 67n. This can improve the performance of the feedback transistor 301 and the reset transistor 400.

[0213] In this embodiment, the plugs cg1, cg3, and cg5 are N-type polysilicon plugs doped with N-type impurities, such as phosphorus.

[0214] In this embodiment, the plugs cg1, cg3, and cg5, as well as the gate electrodes 301e and 400e, have film-shaped portions. Furthermore, they are formed of the same material. This means that they can be formed using a common film formation process, which is advantageous from the viewpoint of simplifying the manufacturing process. Specifically, the plugs cg1, cg3, and cg5, and the gate electrodes 301e and 400e are formed of polysilicon.

[0215] In this embodiment, the photoelectric conversion unit 17 is a photoelectric conversion unit 17A including a pixel electrode 17a, a counter electrode 17c, and a photoelectric conversion layer 17b. The pixel electrode 17a is provided on an interlayer insulating layer 90. Specifically, the pixel electrode 17a is provided on an insulating layer 90d. The counter electrode 17c is disposed on the light incident side. The photoelectric conversion layer 17b is disposed between the pixel electrode 17a and the counter electrode 17c.

[0216] Although not shown in FIG. 7 , the counter electrode 17c is connected to the aforementioned accumulation control line 130. In one example, during operation of the imaging device 100, the potential of the accumulation control line 130 is controlled to make the potential of the counter electrode 17c higher than the potential of the pixel electrode 17a. This allows the pixel electrode 17a to selectively collect positive charges among the positive and negative charges generated by photoelectric conversion. Because the counter electrode 17c is a single layer that is continuous across multiple pixels 110B, it is possible to collectively apply a predetermined potential to the counter electrodes 17c of multiple pixels 110B.

[0217] The pixel electrode 17a is electrically connected to the diffusion region 67n, i.e., the charge storage portion FD, via the conductive structure 89. Therefore, the charges collected by the pixel electrode 17a are transmitted to the diffusion region 67n via the conductive structure 89. Specifically, the pixel electrode 17a is electrically connected to the diffusion region 67n via the plug pd, the wiring layer 80c, the plug pc, the wiring layer 80b, the plug pb, the wiring layer 80a, the plug pa5, and the plug cg5, in this order. Therefore, the charges collected by the pixel electrode 17a are transmitted to the diffusion region 67n via these in this order.

[0218] The present embodiment will be further described using terms such as first transistor, second transistor, etc.

[0219] The pixel 110B has a photoelectric conversion unit 17, a charge accumulation unit FD, an amplifying transistor 200 as a first transistor, and an inversion transistor 600 as a second transistor. The photoelectric conversion unit 17 converts light into electric charges. The charge accumulation unit FD accumulates the electric charges generated by the photoelectric conversion unit 17. The charge accumulation unit FD is a diffusion region of a first conductivity type. The first transistor includes a source or drain containing impurities of the first conductivity type. The second transistor includes a source or drain containing impurities of a second conductivity type. The second conductivity type is different from the first conductivity type.

[0220] In this embodiment, the charge storage portion FD and the source or drain of the second transistor have different conductivity types. In this case, the source or drain of the second transistor may affect the charge storage portion FD. One example of this effect is the diffusion of impurities of a different conductivity type from the impurities contained in the charge storage portion FD from the second transistor to the charge storage portion FD. Another example of this effect is the inflow of parasitic carriers generated in the second transistor from the second transistor to the charge storage portion FD. This effect is likely to become apparent as pixel size decreases. This effect may cause leakage current and increase noise. The noise may degrade the image.

[0221] However, in this embodiment, as shown in Figure 6, in a plan view, the distance D2 between the charge storage unit FD and the inversion transistor 600, which is the second transistor, is longer than the distance D1 between the charge storage unit FD and the amplification transistor 200, which is the first transistor. This makes it possible to suppress the above-mentioned effects. Therefore, this embodiment is suitable for reducing noise and obtaining high-quality images.

[0222] Here, "plan view" refers to observation in a direction perpendicular to the surface of the semiconductor substrate 60. Fig. 6 shows pixel 110B in plan view.

[0223] In the first example, the distance D2 is the minimum distance, in plan view, between the charge storage unit FD and the source or drain of the inversion transistor 600, which is the second transistor. The distance D1 is the minimum distance, in plan view, between the charge storage unit FD and the gate electrode of the amplification transistor 200, which is the first transistor. Figure 6 shows the distance D2 and the distance D1 in the first example.

[0224] In a typical example, the outer edges of diffusion regions such as the source, drain, and charge storage portion FD are defined by junctions, which are portions where the concentration of the first conductivity type impurity and the concentration of the second conductivity type impurity are equal.

[0225] In the second example, the distance D2 is the center-to-center distance, in plan view, between the charge storage unit FD and the source or drain of the inversion transistor 600, which is the second transistor. The distance D1 is the center-to-center distance, in plan view, between the charge storage unit FD and the gate electrode of the amplification transistor 200, which is the first transistor. In this context, the center refers to the geometric center.

[0226] In the third example, the distance D2 is the distance, in plan view, between the connection point between the charge storage unit FD and the conductive structure 89 and the connection point between the source or drain of the inversion transistor 600, which is the second transistor, and the conductive structure 89. The distance D1 is the distance, in plan view, between the connection point between the charge storage unit FD and the conductive structure 89 and the connection point between the gate electrode of the amplification transistor 200, which is the first transistor, and the conductive structure 89.

[0227] In the fourth example, the distance D2 is the center-to-center distance, in plan view, between the charge storage unit FD and the gate electrode of the inversion transistor 600, which is the second transistor. The distance D1 is the center-to-center distance, in plan view, between the charge storage unit FD and the gate electrode of the amplification transistor 200, which is the first transistor. In this context, the center refers to the geometric center.

[0228] In this embodiment, if distance D2 is greater than distance D1 in a planar view in any of the first, second, third, and fourth examples, distance D2 is treated as being greater than distance D1 in a planar view.

[0229] In this embodiment, the charge storage unit FD, the amplifying transistor 200 serving as the first transistor, and the inverting transistor 600 serving as the second transistor are provided on a single semiconductor substrate 60. In this case, the above-described influence is likely to become apparent. Therefore, in this embodiment, the effect of suppressing the above-described influence is effectively exerted by the magnitude relationship between the distances D2 and D1.

[0230] In this embodiment, the first transistor is an amplifier transistor 200. The amplifier transistor 200 generates a signal according to the charge stored in the charge storage unit FD. The second transistor is an inversion transistor 600.

[0231] In this embodiment, the amplifying transistor 200, which is the first transistor, is electrically connected to the charge storage unit FD. Specifically, the gate of the first transistor is electrically connected to the charge storage unit FD. The inverting transistor 600, which is the second transistor, may also be electrically connected to the charge storage unit FD.

[0232] In this embodiment, the amplification transistor 200, which is the first transistor, is located in a first central region, which is the central region of the pixel 110B, in a planar view. This makes it easier to make the distance D2 greater than the distance D1 in a planar view. Here, the first central region of the pixel in a planar view refers to a region that is similar in shape to the pixel in a planar view, has an area that is 70% of the area of ​​the pixel, and has the same geometric center as the pixel. Specifically, the first transistor being located in the central region in a planar view means that the entire source, drain, and gate electrode of the first transistor are located inside the outer edge that defines the central region in a planar view.

[0233] In a plan view, the amplification transistor 200, which is the first transistor, may be located in a second central region of the pixel 110B. The second central region of the pixel in a plan view means a region that is similar in shape to the pixel in a plan view, has an area that is 40% of the area of ​​the pixel, and has a geometric center that is the same as the geometric center of the pixel.

[0234] In a plan view, the amplification transistor 200, which is the first transistor, may be located in a third central region of the pixel 110B. The third central region of the pixel in a plan view means a region that is similar in shape to the pixel in a plan view, has an area that is 10% of the area of ​​the pixel, and has a geometric center that is the same as the geometric center of the pixel.

[0235] The outer edge of a pixel can be understood from, for example, the repeated arrangement of pixels. A pixel is the smallest unit capable of expressing gradation.

[0236] In this embodiment, in a plan view, the charge storage unit FD and the inversion transistor 600, which is the second transistor, are located on opposite sides of the amplification transistor 200, which is the first transistor, in a direction CD1. In other words, in a plan view, the charge storage unit FD, the first transistor, and the second transistor are arranged in this order in the direction CD1. In this way, it is easy to make the distance D2 greater than the distance D1 in a plan view.

[0237] In the illustrated example, the direction CD1 is the row direction, but the direction CD1 may also be the column direction.

[0238] In this embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0239] Specifically, in this embodiment, the amplifier transistor 200 includes a source or drain containing N-type impurities. In this case, it is easier to ensure the transconductance of the amplifier transistor 200 compared to when the amplifier transistor 200 includes a source or drain containing P-type impurities. This is because electrons have a higher mobility than holes. The ease of ensuring the transconductance is advantageous from the perspective of ensuring the performance of the amplifier transistor 200.

[0240] In this embodiment, the pixel 110B has a first well region 65p and a second well region 65n. The first well region 65p contains impurities of a second conductivity type. An amplifying transistor 200, which is a first transistor, is located in the first well region 65p. The second well region 65n contains impurities of the first conductivity type. An inversion transistor 600, which is a second transistor, is located in the second well region 65n. In a plan view, the area of ​​the first well region 65p is larger than the area of ​​the second well region 65n. Specifically, in a plan view, the area of ​​the first well region 65p belonging to the pixel 110B is larger than the area of ​​the second well region 65n belonging to the pixel 110B.

[0241] In this embodiment, the first well region 65p is a P-well 65p, and the second well region 65n is an N-well region 65n.

[0242] In this embodiment, the imaging device 100 has a semiconductor substrate 60. In a cross section perpendicular to the main surface of the semiconductor substrate 60 (this cross section may be referred to as a first cross section, for example), the source or drain of the amplifying transistor 200, which is a first transistor, and the source or drain of the inversion transistor 600, which is a second transistor, appear. In this context, the source or drain of the first transistor means at least one of the source and drain of the first transistor. The same applies to the source or drain of the second transistor.

[0243] Specifically, the source and drain of the first transistor and the source and drain of the second transistor appear in this cross section, as well as the charge storage portion FD.

[0244] The pixel 110B has an element isolation region 69a and an element isolation region 69b. The element isolation region 69a isolates an inversion transistor 600, which is a second transistor, from other elements. The element isolation region 69b isolates a reset transistor 400, which has an inverted polarity relative to the second transistor, from other elements. The element isolation region 69a and the element isolation region 69b are formed by implantation isolation.

[0245] The arrangement of elements shown in the plan view of Fig. 6 can also be applied to other embodiments. In an embodiment in which an element not present in this embodiment is added, the element can be added to the plan view of Fig. 6. In an embodiment in which an element present in this embodiment is not present, the element can be omitted from the plan view of Fig. 6.

[0246] For example, for the first embodiment, it is possible to eliminate select transistor 503 from the plan view of Figure 6 and use select transistor 502 as inverting transistor 600, among other modifications. Figure 8 shows a plan view applicable to the first embodiment.

[0247] Third Embodiment A pixel 110C according to a third embodiment will now be described with reference to Fig. 9, which is a schematic cross-sectional view of the pixel 110C.

[0248] In pixel 110C, conductive structure 89 includes a plurality of plugs cp1, cp2, cp3, cp4, cp5, cp6, cp7, and cp8. These plugs are disposed in insulating layer 90a. These plugs have bar-shaped portions. Specifically, these plugs are contact plugs.

[0249] The plugs cp1, cp3, cp5, cp6 and cp8 penetrate the insulating layer 70.

[0250] The interconnect layer 80a is electrically connected to the diffusion region 68an via plugs pa1 and cp1 in this order. The interconnect layer 80a is electrically connected to the diffusion region 68bn via plugs pa3 and cp3 in this order. The interconnect layer 80a is electrically connected to the diffusion region 72ap via plugs pa6 and cp6 in this order. The interconnect layer 80a is electrically connected to the diffusion region 72bp via plugs pa8 and cp8 in this order.

[0251] Specifically, the plug cp1 is connected to a second region 68an2 of the diffusion region 68an, and the plug cp3 is connected to a second region 68bn2 of the diffusion region 68bn.

[0252] The diffusion region 72ap includes a first region 72ap1 and a second region 72ap2. The second region 72ap2 is provided within the first region 72ap1. The second region 72ap2 has a higher impurity concentration than the first region 72ap1. The plug cp6 is connected to the second region 72ap2.

[0253] The diffusion region 72bp includes a first region 72bp1 and a second region 72bp2. The second region 72bp2 is provided within the first region 72bp1. The second region 72bp2 has a higher impurity concentration than the first region 72bp1. The plug cp8 is connected to the second region 72bp2.

[0254] The interconnect layer 80a is electrically connected to the gate electrode 301e via plugs pa2 and cp2 in this order. The interconnect layer 80a is electrically connected to the gate electrode 400e via plugs pa4 and cp4 in this order. The interconnect layer 80a is electrically connected to the gate electrode 600e via plugs pa7 and cp7 in this order.

[0255] The pixel electrode 17a is electrically connected to the diffusion region 67n, i.e., the charge storage portion FD, via the conductive structure 89. Specifically, the pixel electrode 17a is electrically connected to the diffusion region 67n via the plug pd, the wiring layer 80c, the plug pc, the wiring layer 80b, the plug pb, the wiring layer 80a, the plug pa5, and the plug cp5, in this order.

[0256] In this embodiment, the plugs (specifically, contact plugs) cp1, cp2, cp3, cp4, cp5, cp6, cp7, and cp8 are formed of polysilicon. This increases the conductivity of the plugs cp1, cp3, cp5, cp6, and cp8, thereby reducing the contact resistance between the plugs cp1, cp3, cp5, cp6, and cp8 and the diffusion regions 68an, 68bn, 67n, 72ap, and 72bp. Furthermore, this increases the conductivity of the plugs cp2, cp4, and cp7, thereby reducing the contact resistance between the plugs cp2, cp4, and cp7 and the gate electrodes 301e, 400e, and 600e. This can improve the performance of the feedback transistor 301, the reset transistor 400, and the inversion transistor 600.

[0257] In this embodiment, the plurality of plugs cp1, cp2, cp3, cp4, and cp5 are N-type polysilicon plugs doped with N-type impurities, such as phosphorus.

[0258] In this embodiment, the plugs cp6, cp7, and cp8 are P-type polysilicon plugs doped with P-type impurities, such as boron.

[0259] Fig. 10 shows an example of a configuration applicable to the pixel 110C. The configuration in Fig. 10 is also applicable to other embodiments.

[0260] 10, some elements such as element isolation regions 69a and 69b are not shown. In addition, in FIG. 10, region xp collectively represents the P-type semiconductor region 61p and the P-well 65p.

[0261] 10, an insulating layer 71 is provided to cover the gate electrodes 400e and 600e. The insulating layer 71 is, for example, a silicon oxide film. The insulating layer 71 may have a stacked structure.

[0262] A sidewall 75 is provided on the insulating layer 71. The sidewall 75 is, for example, a silicon nitride film.

[0263] The sidewall 75 is disposed between the plug cp3 and the gate electrode 400e. The sidewall 75 is disposed between the plug cp5 and the gate electrode 400e. The sidewall 75 is disposed between the plug cp5 and the plug cp6. The sidewall 75 is disposed between the plug cp6 and the gate electrode 600e. The sidewall 75 is disposed between the plug cp8 and the gate electrode 600e.

[0264] In a plan view, the sidewall 75 overlaps with the diffusion region 68bn. In a plan view, the sidewall 75 overlaps with the diffusion region 67n. In a plan view, the sidewall 75 overlaps with the diffusion region 72ap. In a plan view, the sidewall 75 overlaps with the diffusion region 72bp.

[0265] Two elements overlapping in plan view means that the two elements have at least a partial overlap in plan view.

[0266] The overlapping reduces damage to the diffusion regions 68bn, 67n, 72ap, and 72bp and contamination due to metal diffusion. The damage is, for example, damage caused by plasma used in processes after the formation of the diffusion regions. The plasma damage is, for example, physical damage caused by collisions with accelerated ions and defect generation due to light. The light is, for example, ultraviolet light.

[0267] The sidewall may be disposed between another plug and the gate electrode, or may be disposed so as to overlap another diffusion region in plan view.

[0268] The insulating layer 70 and the insulating layer 71 have a plurality of contact holes h3, h5, h6, and h8 that penetrate the insulating layer 70 and the insulating layer 71.

[0269] In plan view, the contact hole h3 overlaps with the diffusion region 68bn. A plug cp3 is disposed in the contact hole h3.

[0270] In plan view, the contact hole h5 overlaps with the diffusion region 67n. A plug cp5 is disposed in the contact hole h5.

[0271] In plan view, the contact hole h6 overlaps with the diffusion region 72ap. A plug cp6 is disposed in the contact hole h6.

[0272] In plan view, the contact hole h8 overlaps with the diffusion region 72bp. A plug cp8 is disposed in the contact hole h8.

[0273] A contact hole may be formed at a position overlapping with another diffusion region in a plan view, and a plug may be disposed in the contact hole.

[0274] Fourth Embodiment A pixel 110D according to a fourth embodiment will now be described with reference to Fig. 11, which is a schematic cross-sectional view of the pixel 110D.

[0275] In pixel 110D, conductive structure 89 includes a plurality of plugs cg6 and cg8, which are disposed in insulating layer 90a.

[0276] In the illustrated example, the plugs cg6 and cg8 have a film-shaped portion and are contact plugs.

[0277] The plugs cg6 and cg8 penetrate the insulating layer 70.

[0278] The interconnect layer 80a is electrically connected to the diffusion region 72ap via a plug pa6 and a plug cg6 in this order. The interconnect layer 80a is electrically connected to the diffusion region 72bp via a plug pa8 and a plug cg8 in this order.

[0279] Specifically, the plug cg6 is connected to the second region 72ap2 of the diffusion region 72ap, and the plug cg8 is connected to the second region 72bp2 of the diffusion region 72bp.

[0280] In this embodiment, the plugs cg6 and cg8 (specifically, contact plugs) are made of polysilicon. This increases the conductivity of the plugs cg6 and cg8 and reduces the contact resistance between the plugs cg6 and cg8 and the diffusion regions 72ap and 72bp. This can improve the performance of the inversion transistor 600.

[0281] In this embodiment, the plugs cg6 and cg8 are P-type polysilicon plugs doped with P-type impurities, such as boron.

[0282] In this embodiment, both the plugs cg6 and cg8 and the gate electrode 600e have film-shaped portions. Furthermore, they are formed of the same material. This means that they can be formed using a common film formation process, which is advantageous from the viewpoint of simplifying the manufacturing process. Specifically, the plugs cg6 and cg8 and the gate electrode 600e are formed of polysilicon.

[0283] The third and fourth embodiments will be further described using terms such as first transistor, second transistor, etc.

[0284] The pixels 110C and 110D each include a reset transistor 400 as a first transistor, an inversion transistor 600 as a second transistor, a first contact plug, and a second contact plug. The first transistor includes a diffusion region 67n or 68bn corresponding to a first diffusion region that is a source or drain, and a gate electrode 400e that is a first gate electrode containing impurities of a first conductivity type. The second transistor includes a diffusion region 72ap or 72bp corresponding to a second diffusion region that is a source or drain, and a second gate electrode 600e containing impurities of a second conductivity type different from the first conductivity type.

[0285] The first contact plug is connected to the diffusion region 67n or 68bn, which is the first diffusion region, and contains impurities of the first conductivity type. The second contact plug is connected to the diffusion region 72ap or 72bp, which is the second diffusion region, and contains impurities of the second conductivity type.

[0286] Both the gate electrode 400e, which is the first gate electrode, and the first contact plug are parts that contribute to the operation of the reset transistor 400, which is the first transistor. In the above configuration, these parts both contain impurities of the first conductivity type. This can contribute to ensuring the stability of the operation of the first transistor. For example, this reduces the occurrence of quality variations during mass production of imaging devices. This leads to the acquisition of high-quality images. The same can be said for the configuration of the inversion transistor 600, which is the second transistor.

[0287] In the third embodiment, the first contact plug is the plug cp3 or cp5, and the second contact plug is the plug cp6 or cp8.

[0288] In the fourth embodiment, the first contact plug is the plug cg3 or cg5, and the second contact plug is the plug cg6 or cg8.

[0289] In the third and fourth embodiments, the diffusion region 67n or 68bn, which is the first diffusion region, contains impurities of the first conductivity type, and the diffusion region 72ap or 72bp, which is the second diffusion region, contains impurities of the second conductivity type.

[0290] As described above, in the third and fourth embodiments, the conductivity type of the impurities in the first contact plug and the first diffusion region, which are connected to each other, is the same, that is, the first conductivity type. The conductivity type of the impurities in the second contact plug and the second diffusion region, which are connected to each other, is the same, that is, the second conductivity type. This is advantageous from the viewpoint of reducing the contact resistance between the first contact plug and the first diffusion region and improving the performance of the first transistor. It is also advantageous from the viewpoint of reducing the contact resistance between the second contact plug and the second diffusion region and improving the performance of the second transistor. These are advantageous from the viewpoint of obtaining high-quality images.

[0291] In the third and fourth embodiments, the first diffusion region has a first region with a relatively low impurity concentration and a second region provided within the first region with a relatively high impurity concentration. A first contact plug is connected to the second region of the first diffusion region. In this case, the effect of reducing the contact resistance based on the first contact plug is easily exerted effectively.

[0292] In the third and fourth embodiments, the second diffusion region has a first region with a relatively low impurity concentration and a second region with a relatively high impurity concentration provided within the first region. A second contact plug is connected to the second region of the second diffusion region. In this case, the effect of reducing the contact resistance based on the second contact plug is easily exerted effectively.

[0293] In the third and fourth embodiments, the first diffusion region is a charge storage portion FD. The charge storage portion FD stores charges. The first transistor is a reset transistor 400. The reset transistor 400 resets the charge storage portion FD. The second transistor is an inversion transistor 600.

[0294] In the third and fourth embodiments, the first region of the first diffusion region is the first region 67a of the charge storage portion FD. The second region of the first diffusion region is the second region 67b of the charge storage portion FD. The first region of the second diffusion region is the first region 72ap1 or 72bp1. The second region of the second diffusion region is the second region 72ap2 or 72bp2.

[0295] In the third and fourth embodiments, the first conductivity type is N-type, and the second conductivity type is P-type.

[0296] Fifth Embodiment A pixel 110E according to a fifth embodiment will now be described with reference to Fig. 12, which is a schematic cross-sectional view of the pixel 110E.

[0297] In the pixel 110E, an element isolation region 69c is used instead of the element isolation region 69a. The element isolation region 69c has an STI (Shallow Trench Isolation) structure. The element isolation region 69c with an STI structure easily ensures element isolation function even when the impurity concentration in the source and drain of the inversion transistor 600 is high. This is advantageous from the perspective of reducing the contact resistance between the plugs cg6 and cg8 and the diffusion regions 72ap and 72bp. This can improve the performance of the inversion transistor 600. Furthermore, the high element isolation function based on the STI structure can also contribute to reducing the pixel size. As described above, the plugs cg6 and cg8 are specifically contact plugs.

[0298] On the other hand, the element isolation region 69b is a region formed by implantation isolation. As in this embodiment, the element isolation region 69c having the STI structure and the element isolation region 69b formed by implantation isolation may be combined.

[0299] The element isolation region 69c having the STI structure is made of, for example, silicon oxide.

[0300] The fifth embodiment will be further described using terms such as first transistor, second transistor, etc.

[0301] The pixel 110E has an element isolation region 69c. The element isolation region 69c isolates the second transistor 600. The element isolation region 69c has an STI structure.

[0302] The STI structure may have crystal defects on its sidewalls, which may cause noise in the charge storage portion FD.

[0303] However, in this embodiment, in a plan view, the distance D3 between the charge storage portion FD and the element isolation region 69c is longer than the distance D1 between the charge storage portion FD and the first transistor, the amplifying transistor 200. This is suitable for suppressing noise resulting from crystal defects from occurring in the charge storage portion FD and obtaining a high-quality image.

[0304] Even when the element isolation region 69c is a region formed by implantation isolation, making the distance D3 longer than the distance D1 can contribute to improving image quality, because this makes it possible to suppress noise resulting from high-concentration impurities in the implantation isolation region from occurring in the charge accumulation portion FD.

[0305] In one example, the distance D3 is the minimum distance between the charge storage unit FD and the element isolation region 69c in a plan view, and the distance D1 is the minimum distance between the charge storage unit FD and the gate electrode of the amplifying transistor 200, which is the first transistor, in a plan view.

[0306] In this embodiment, the isolation region 69c separates the inverting transistor 600, which is the second transistor, from the amplifying transistor 200, which is the first transistor.

[0307] The phrase "an element is isolated from other elements" means that a structure that suppresses leakage current between the element and the other elements is provided between the element and the other elements. In one example, the phrase "an element is isolated from other elements" means that the element is surrounded by the structure in a plan view, and the other elements are disposed outside the structure.

[0308] The pixel 110E has an element isolation region 69b. The element isolation region 69b isolates the reset transistor 400, which has an inverted polarity relative to the inversion transistor 600 serving as the second transistor, from other elements. The element isolation region 69c is formed by implantation isolation.

[0309] In this embodiment, in a plan view, the charge storage unit FD and the element isolation region 69c are located on opposite sides of the first transistor, i.e., the amplifying transistor 200, in a certain direction. This makes it easier to make the distance D3 longer than the distance D1 in a plan view.

[0310] Sixth Embodiment A pixel 110F according to a sixth embodiment will now be described. Fig. 13 is a schematic cross-sectional view of the pixel 110F.

[0311] The pixel 110F has an N-type semiconductor region 62n. The N-type semiconductor region 62n divides the P-type semiconductor region 61p into a first region 61p1 in which the diffusion region 67n is disposed and a second region 61p2 different from the first region 61p1. The N-type semiconductor region 62n can suppress the inflow of minority carriers generated in the inversion transistor 600 or peripheral circuits into the charge storage portion FD. This suppresses leakage current due to the inflow of minority carriers into the charge storage portion FD and is suitable for obtaining high-quality images.

[0312] The support substrate 61, the second region 61p2, the N-type semiconductor region 62n, and the first region 61p1 are arranged in this order, and the support substrate 61, the second region 61p2, the N-type semiconductor region 62n, and the P-well 65p are arranged in this order.

[0313] In plan view, the second region 61p2 overlaps the P-well 65p and the N-well 65n, the charge storage portion FD, and at least one of the diffusion regions 72ap and 72bp, specifically both.

[0314] The pixel 110F has at least one P-type region 64. Specifically, the pixel 110F has a plurality of P-type regions 64. The P-type region 64 has a higher impurity concentration than the support substrate 61 and the P-type semiconductor region 61p. The P-type region 64 electrically connects the support substrate 61, the P-type semiconductor region 61p, and the P-well 65p.

[0315] The sixth embodiment will be further described using terms such as first semiconductor region, second semiconductor region, and the like.

[0316] The pixel 110F has a P-type semiconductor region 61p, which is a first semiconductor region, and an N-type semiconductor region 62n, which is a second semiconductor region. The second semiconductor region divides the first semiconductor region into a first region 61p1 and a second region 61p2, which is different from the first region 61p1. A charge storage unit FD is disposed in the first region 61p1. In a plan view, the second region 61p2 overlaps with an N-well 65n, which is a second well region.

[0317] In this manner, in this embodiment, the second region 61p2 overlapping with the second well region in plan view and the first region 61p1 in which the charge storage portion FD is disposed are separated by the N-type semiconductor region 62n, which is the second semiconductor region. Therefore, this embodiment can suppress the inflow of minority carriers generated in the inversion transistor 600, which is the second transistor, into the charge storage portion FD. This suppresses leakage current due to the inflow of minority carriers into the charge storage portion FD, and is suitable for obtaining high-quality images.

[0318] In this embodiment, the first semiconductor region is a P-type semiconductor region 61p, the second semiconductor region is an N-type semiconductor region 62n, and the second well region is an N-well region 65n. As described above, the charge accumulation portion FD corresponds to the diffusion region 67n.

[0319] Seventh Embodiment A pixel 110G according to a seventh embodiment will be described below.

[0320] Fig. 14 is a schematic plan view of a pixel 110G according to the seventh embodiment, and Fig. 15 is a schematic cross-sectional view of the pixel 110G.

[0321] Fig. 14 schematically shows the arrangement of each element provided on the semiconductor substrate 60 when the pixel 110G shown in Fig. 15 is viewed along the normal direction of the semiconductor substrate 60. The cross section shown in Fig. 15 is obtained by cutting the pixel 110G along the XV-XV dashed line in Fig. 14 and developing it.

[0322] In pixel 110G, conductive structure 89 includes plugs pa0, pa9, cg0, and cg9. Semiconductor substrate 60 includes sub-contact region 66p and well contact region 66n.

[0323] In the illustrated example, the plugs pa0 and pa9 are direct-coupled plugs, the plugs cg0 and cg9 have film-shaped portions, and the plugs cg0 and cg9 are contact plugs.

[0324] The plugs cg0 and cg9 penetrate the insulating layer 70.

[0325] The sub-contact region 66p has P-type impurities. The sub-contact region 66p is disposed in a P-well 65p. The sub-contact region 66p may be formed on a P-type element isolation region. An element isolation region 69b is disposed between the sub-contact region 66p and the diffusion region 68an.

[0326] The well contact region 66n has N-type impurities. The well contact region 66n is disposed in the N-well 65n. An element isolation region 69c is disposed between the well contact region 66n and the diffusion region 72bp.

[0327] The plugs pa0, pa9, cg0 and cg9 are disposed in an insulating layer 90a.

[0328] The interconnect layer 80a is electrically connected to the sub-contact region 66p via a plug pa0 and a plug cg0 in this order. The interconnect layer 80a is electrically connected to the well contact region 66n via a plug pa9 and a plug cg9 in this order.

[0329] Specifically, the sub-contact region 66p includes a first region 66p1 and a second region 66p2. The second region 66p2 is provided within the first region 66p1. The second region 66p2 has a higher impurity concentration than the first region 66p1. The plug cg0 is connected to the second region 66p2.

[0330] The well contact region 66n includes a first region 66n1 and a second region 66n2. The second region 66n2 is provided within the first region 66n1. The second region 66n2 has a higher impurity concentration than the first region 66n1. The plug cg9 is connected to the second region 66n2.

[0331] The plugs (specifically, direct coupling plugs) pa0 and pa9 are made of a metal such as copper or tungsten, or a metal compound such as a metal nitride or a metal oxide.

[0332] The plug (specifically, contact plug) cg0 is made of polysilicon. In this embodiment, the plug cg0 is a P-type polysilicon plug doped with a P-type impurity, such as boron.

[0333] The plug (specifically, contact plug) cg9 is made of polysilicon. In this embodiment, the plug cg9 is an N-type polysilicon plug doped with N-type impurities, such as phosphorus.

[0334] A voltage can be supplied from the wiring layer 80a to the P-well 65p via the plug pa0, plug cg0, and sub-contact region 66p in this order. A voltage can be supplied from the wiring layer 80a to the N-well 65n via the plug pa9, plug cg9, and well contact region 66n in this order. By supplying voltage in this manner, the voltages of the P-well 65p and the N-well 65n are stabilized. This stabilizes the well voltage for each pixel. When a pixel array is formed by multiple pixels 110G, shading in the pixel array can be suppressed. This makes this embodiment suitable for obtaining high-quality images.

[0335] In this embodiment, one sub-contact region 66p and one well contact region 66n are provided for one pixel 110G. However, one sub-contact region 66p and one well contact region 66n may be provided for multiple pixels 110G. The multiple number is, for example, four.

[0336] The seventh embodiment will be further described using terms such as first well region, second well region, etc.

[0337] The pixel 110G has a P-well 65p which is a first well region, an N-well 65n which is a second well region, a sub-contact region 66p which is a first contact region, and a well contact region 66n which is a second contact region. The first well region contains impurities of a second conductivity type. An amplification transistor 200 which is a first transistor is located in the first well region. The second well region contains impurities of the first conductivity type. An inversion transistor 600 which is a second transistor is located in the second well region. The first contact region contains impurities of the second conductivity type. The second contact region contains impurities of the first conductivity type. A voltage is supplied to the first well region via the first contact region. A voltage is supplied to the second well region via the second contact region.

[0338] Specifically, in this embodiment, in each pixel 110G, a voltage is supplied to the first well region via the first contact region, and a voltage is supplied to the second well region via the second contact region.

[0339] In this embodiment, the first well region is a P-well 65p, the second well region is an N-well region 65n, the first contact region is a sub-contact region 66p, and the second contact region is a well contact region 66n.

[0340] 14, the gate 200e of the amplifying transistor 200 is located slightly above the center of the pixel 110G. However, in this embodiment as well, the gate 200e of the amplifying transistor 200 may be located at the center of the pixel 110G in plan view, similar to FIG. 6 and the like.

[0341] (Pixel Arrangement Example) In one specific example, a pixel array is configured from a plurality of pixels in the imaging device 100. An example of the arrangement of pixels in the pixel array will be described below with reference to FIG. 16 . In this specific example, a pixel array AR1 in which a plurality of pixels 110B according to the second embodiment are arranged will be described. However, a similar pixel array may be configured using pixels described in other embodiments.

[0342] Hereinafter, one of the two adjacent pixels 110B will be referred to as a first pixel 210A, and the other of the two adjacent pixels 110B will be referred to as a second pixel 210B.

[0343] 16 , in a plan view, with respect to a certain direction CD1, the charge storage unit FD of the first pixel 210A, the inversion transistor 600 which is the second transistor of the first pixel 210A, the inversion transistor 600 which is the second transistor of the second pixel 210B, and the charge storage unit FD of the second pixel 210B are arranged in this order. This arrangement makes it difficult for the distance between the second transistor of the first pixel 210A and the charge storage unit FD of the second pixel 210B to become short in a plan view. Furthermore, it makes it difficult for the distance between the second transistor of the second pixel 210B and the charge storage unit FD of the first pixel 210A to become short in a plan view. This is suitable for obtaining high-quality images.

[0344] Specifically, in a plan view, the second pixel 210B has a configuration that is line-symmetrically inverted with respect to the first pixel 210A. This inverted configuration can be called a flip configuration.

[0345] 16, the second pixel 210B is horizontally inverted with respect to the first pixel 210A. However, the second pixel 210B may also be vertically inverted with respect to the first pixel 210A. In other words, the axis of line symmetry in a plan view may extend in the column direction or the row direction. Furthermore, the direction CD1 may be the row direction or the column direction.

[0346] 16 , the first pixel 210A and the second pixel 210B share a single first well region, the P-well 65p. This is advantageous from the perspective of miniaturizing the imaging device. Note that the first pixel 210A and the second pixel 210B sharing a single first well region means that at least a portion of the first well region belongs to the first pixel 210A, and at least a portion of the first well region belongs to the second pixel 210B.

[0347] In the example of FIG. 16, the first well region is a P-well 65p.

[0348] The first pixel 210A and the second pixel 210B may share a single second well region, the N-well 65n. This is advantageous from the perspective of miniaturizing the imaging device. Note that the first pixel 210A and the second pixel 210B sharing a single second well region means that at least a portion of the second well region belongs to the first pixel 210A, and at least a portion of the second well region belongs to the second pixel 210B. In the example of FIG. 16 , the second well region is the N-well 65n.

[0349] The pixel array AR1 also includes a third pixel 210C and a fourth pixel 210D. The third pixel 210C and the fourth pixel 210D each correspond to pixel 110B. The second pixel 210B and the third pixel 210C are adjacent to each other. The third pixel 210C and the fourth pixel 210D are adjacent to each other. In the direction CD1, the first pixel 210B, the second pixel 210B, the third pixel 210C, and the fourth pixel 210D are arranged in this order.

[0350] In the example of Figure 16, in a plan view, with respect to a certain direction CD1, the charge storage portion FD of the first pixel 210A, the inversion transistor 600 which is the second transistor of the first pixel 210A, the inversion transistor 600 which is the second transistor of the second pixel 210B, the charge storage portion FD of the second pixel 210B, the charge storage portion FD of the third pixel 210D, the inversion transistor 600 which is the second transistor of the third pixel 210C, the inversion transistor 600 which is the second transistor of the fourth pixel 210D, and the charge storage portion FD of the fourth pixel 210D are arranged in this order.

[0351] Specifically, in a plan view, the third pixel 210C has a configuration that is line-symmetrically inverted with respect to the second pixel 210B. In a plan view, the fourth pixel 210D has a configuration that is line-symmetrically inverted with respect to the third pixel 210C.

[0352] (Example of Supplying Voltage to Pixel Array) In the imaging device 100, a pixel array may be configured with a plurality of pixels. An example of supplying voltage to a pixel array will be described below with reference to FIGS. 17 to 19 . The pixel array AR2 in this specific example is an array of a plurality of pixels 110H. However, the pixel array may also be an array of a plurality of pixels described in other embodiments.

[0353] Fig. 17 is a schematic plan view of the pixel region PR and the peripheral region SA, and Fig. 18 and Fig. 19 are schematic cross-sectional views of the pixel region PR and its peripheral region SA.

[0354] Figure 17 schematically shows the arrangement of each element provided on the semiconductor substrate 60 when the pixel 110H shown in Figures 18 and 19 is viewed along the normal direction of the semiconductor substrate 60. The cross section shown in Figure 18 is an expanded view of the structure cut along the XVIII-XVIII dashed line in Figure 17. The cross section shown in Figure 19 is an expanded view of the structure cut along the XIX-XIX dashed line in Figure 17.

[0355] The pixel region PR includes a pixel array AR2 and a margin region MR. The margin region MR surrounds the pixel array AR2.

[0356] The peripheral area SA surrounds the pixel area PR. Although not shown, in the peripheral area SA, contacts are electrically connected to the support substrate 61. The contacts connect the support substrate 61 to an external circuit.

[0357] The surrounding area SA includes a first portion P1 and a second portion P2.

[0358] The pixel region PR and the peripheral region SA share the interlayer insulating layer 90 and the conductive structure 89. Specifically, the pixel region PR and the peripheral region SA share the wiring layer 80a. The pixel region PR and the peripheral region SA may also share the wiring layer 80b, the wiring layer 80c, the wiring layer 80d, etc.

[0359] The pixel region PR and the peripheral region SA share a support substrate 61, a P-type semiconductor region 61p, an N-type semiconductor region 62n, and a P-well 65p. The pixel region PR and the peripheral region SA each have an N-well 65n. In this example, the N-well 65n in the pixel region PR and the N-well 65n in the peripheral region SA are spaced apart from each other.

[0360] The semiconductor substrate 60 includes a diffusion region 73an and a diffusion region 73bn.

[0361] An element isolation region 69c is disposed between the pixel region PR and the peripheral region SA. In the peripheral region SA, the element isolation region 69c is disposed between the first portion P1 and the second portion P2.

[0362] The pixel region PR and the peripheral region SA each have a P-type region 64. In each of the pixel region PR and the peripheral region SA, the P-type region 64 electrically connects the support substrate 61 and the P-well 65p. Specifically, in each of the pixel 110H and the first portion P1, the P-type region 64 electrically connects the support substrate 61 and the P-well 65p.

[0363] The N-type semiconductor region 62n electrically connects the N-well 65n in the pixel region PR to the N-well 65n in the peripheral region SA. Specifically, the N-type semiconductor region 62n electrically connects the N-well 65n in the pixel 110H to the N-well 65n in the second portion P2.

[0364] In the first portion P1, the conductive structure 89 has a plurality of plugs pa11, pa12, pa13, and pa14. The first portion P1 has conductive layers 81 and 82. The first portion P1 has a plurality of sub-contact regions yp1 and yp2.

[0365] In the illustrated example, plugs pa11, pa12, pa13, and pa14 are direct-connect plugs.

[0366] The plugs pa11, pa12, pa13, and pa14 penetrate the insulating layer 70.

[0367] The plugs pa11 and pa12 are electrically connected to the conductive layer 81. The sub-contact region yp1 is interposed between the conductive layer 81 and the P-well 65p.

[0368] The plugs pa13 and pa14 are electrically connected to the conductive layer 82. The sub-contact region yp2 is interposed between the conductive layer 82 and the P-well 65p.

[0369] In the second portion P2, the conductive structure 89 has a plurality of plugs pa21, pa22, pa23, and pa24. The second portion P2 has conductive layers 83 and 84. The second portion P2 has a plurality of well contact regions zn1 and zn2.

[0370] In the illustrated example, plugs pa21, pa22, pa23, and pa24 are direct-connect plugs.

[0371] The plugs pa21, pa22, pa23, and pa24 penetrate the insulating layer 70.

[0372] The plugs pa21 and pa22 are electrically connected to the conductive layer 83. The well contact region zn1 is interposed between the conductive layer 83 and the N well 65n of the second portion P2.

[0373] The plugs pa23 and pa24 are electrically connected to the conductive layer 84. The well contact region zn2 is interposed between the conductive layer 84 and the N well 65n of the second portion P2.

[0374] In pixel 110H, conductive structure 89 includes plugs pa41, pa42, and cg41.

[0375] In the illustrated example, the plugs pa41 and pa42 are direct-coupled plugs. The plug cg41 has a film-shaped portion. The plug cg41 is also a contact plug.

[0376] The plug cg41 penetrates the insulating layer 70.

[0377] The plugs pa11, pa12, pa13, pa14, pa21, pa22, pa23, pa24, pa41, pa42, and cg41 are disposed in the insulating layer 90a.

[0378] The amplifier transistor 200 includes a diffusion region 73an as one of a source and a drain. The amplifier transistor 200 includes a diffusion region 73bn as the other of the source and the drain. The amplifier transistor 200 includes an insulating layer 70 and a gate electrode 200e. The gate electrode 200 is provided on the insulating layer 70.

[0379] The interconnect layer 80a is electrically connected to the diffusion region 73an via a plug pa41 and a plug cg41 in this order. The interconnect layer 80a is electrically connected to the gate electrode 200e via a plug pa42.

[0380] Unlike the seventh embodiment, the plugs pa0, cg0, and sub-contact region 66p are arranged in the margin region MR, and the plugs pa9, cg9, and well contact region 66n are arranged in the margin region MR.

[0381] The interconnect layer 80a is electrically connected to the sub-contact region 66p via a plug pa0 and a plug cg0 in this order. The interconnect layer 80a is electrically connected to the well contact region 66n via a plug pa9 and a plug cg9 in this order.

[0382] The plugs (specifically, direct-coupled plugs) pa11, pa12, pa13, pa14, pa21, pa22, pa23, pa24, pa41, and pa42 are made of a metal such as copper or tungsten, or a metal compound such as a metal nitride or a metal oxide. The same is true for the conductive layers 81, 82, 83, and 84.

[0383] The conductive layers 81 and 82 are electrically connected to form an integrated conductive layer, and are therefore at the same potential. The same is true for the conductive layers 83 and 84.

[0384] The plug (specifically, contact plug) cg41 is made of polysilicon. In this embodiment, the plug cg41 is an N-type polysilicon plug doped with N-type impurities, such as phosphorus.

[0385] The sub-contact regions yp1 and yp2 have P-type impurities, and the well contact regions zn1 and zn2 have N-type impurities.

[0386] A voltage can be supplied to P-well 65p via interconnection layer 80a, plug pa0, plug cg0, and sub-contact region 66p in this order. A voltage can be supplied to N-well 65n via interconnection layer 80a, plug pa9, plug cg9, and well contact region 66n in this order.

[0387] 17, the pixel region PR is defined with a first column row1, a second column row2, a third column row3, a fourth column row4, etc. In each column, a plurality of transistors are arranged.

[0388] Each of the multiple columns, including the first column row1, the second column row2, the third column row3, and the fourth column row4, has a sub-contact region 66p or a well contact region 66n in the margin region MR. Each column has one continuous P-well 65p or one continuous N-well 65n arranged to extend across both the margin region MR and the pixel array AR2. This allows a stable voltage to be supplied to the P-well 65p or N-well 65n in the pixel array AR2 in each column. This allows leakage current to be suppressed in a pixel array in which multiple transistors of different conductivity types are arranged. This is suitable for obtaining high-quality images.

[0389] 17 , a plurality of columns including a first column row1, a second column row2, a third column row3, and a fourth column row4 share one continuous P-well 65p in the pixel array AR2. A plurality of columns share one continuous N-well 65n in the pixel array AR2. One sub-contact region 66p may be disposed in the margin region MR for one shared P-well 65p. One well contact region 66n may be disposed in the margin region MR for one shared N-well 65n.

[0390] The arrangement of elements in the plan view of Fig. 17 may be rotated by 90 degrees. In the description of Fig. 17, the terms "column" and "row" may be interpreted interchangeably.

[0391] 18 and 19 , a voltage can be supplied to the P-well 65p via the interconnect layer 80a, plugs pa11 and pa12, conductive layer 81, and sub-contact region yp1, in this order. A voltage can be supplied to the P-well 65p via the interconnect layer 80a, plugs pa13 and pa14, conductive layer 82, and sub-contact region yp2, in this order. These voltage supplies can stabilize the voltage of the P-well 65p.

[0392] Furthermore, a voltage can be supplied to the N well 65n in the pixel region PR via the wiring layer 80a, plugs pa21 and pa22, the conductive layer 83, the well contact region zn1, the N well 65n in the second portion P2, and the N-type semiconductor region 62n, in this order. A voltage can be supplied to the N well 65n in the pixel region PR via the wiring layer 80a, plugs pa23 and pa24, the conductive layer 84, the well contact region zn2, the N well 65n in the second portion P2, and the N-type semiconductor region 62n, in this order. These voltage supplies can stabilize the voltage of the N well 65n in the pixel region PR.

[0393] An example of supplying voltages to the pixel array will be further described using terms such as first well region and second well region.

[0394] In this embodiment, the imaging device 100 includes a pixel region PR. The pixel region PR has a pixel array AR2 and a margin region MR. The margin region MR surrounds the pixel array AR2. The pixel array AR2 includes a plurality of pixels 110H aligned in the direction CD2. These pixels 110H share a P-well 65p, which is a single continuous first well region. These pixels 110H share an N-well 65n, which is a single continuous second well region. The margin region MR includes a sub-contact region 66p, which is a first contact region, and a well contact region 66n, which is a second contact region. A voltage is supplied to the single continuous first well region via the first contact region. A voltage is supplied to the single continuous second well region via the second contact region. In this manner, a voltage can be efficiently supplied to the single continuous first well region. Furthermore, this arrangement allows voltage to be efficiently supplied to the single continuous second well region.

[0395] In this embodiment, the first well region is a P-well 65p, the second well region is an N-well region 65n, the first contact region is a sub-contact region 66p, and the second contact region is a well contact region 66n.

[0396] In this embodiment, the direction CD2 is the column direction, which is the vertical direction in Fig. 17, i.e., the up-down direction. However, the direction CD2 may also be the row direction.

[0397] In this embodiment, the imaging device 100 also includes a peripheral area SA. The peripheral area SA surrounds the pixel area PR. The semiconductor substrate 60 is shared by the peripheral area SA and the pixel area PR. A voltage is supplied to at least one of the single continuous first well region and the single continuous second well region from the peripheral area SA via an internal path within the semiconductor substrate 60.

[0398] 17, the gate 200e of the amplifying transistor 200 is located slightly above the center of the pixel 110H. However, in this embodiment as well, the gate 200e of the amplifying transistor 200 may be located at the center of the pixel 110H in plan view, similarly to FIG.

[0399] (Embodiment Using Photodiode) Hereinafter, an embodiment relating to an imaging device 100 in which a photoelectric conversion unit 17B that is a photodiode is used as the photoelectric conversion unit 17 will be described.

[0400] Fig. 20 shows the circuit configuration of a pixel 110I in the imaging device 100 according to this embodiment. Fig. 21 is a plan view of the pixel 110I.

[0401] The pixel 110I includes a photodiode and a transfer transistor 700 .

[0402] The photodiode has an N-type impurity region 85n and a pinning layer.

[0403] The pinning layer is located above the N-type impurity region 85n. The pinning layer is a P-type impurity region. The pinning layer is not shown in FIGS. 20 and 21.

[0404] The photodiode photoelectrically converts the light received during the exposure time to generate electric charges. After the predetermined exposure time has elapsed, a transfer signal is applied to the gate of the transfer transistor 700 via the transfer control signal line CON4. This turns on the transfer transistor 700, and the electric charges generated by the photodiode are transferred to the charge storage unit FD.

[0405] The amplifying transistor 200 outputs a signal corresponding to the charge transferred to the charge storage unit FD to the signal read line 7. The output signal can be subjected to signal processing such as AD conversion.

[0406] The transfer transistor 700 includes a diffusion region 67n, which is a first diffusion region, as one of the source and drain. The transfer transistor 700 includes an N-type impurity region 85n as the other of the source and drain. The transfer transistor 700 also includes a gate electrode 700e. The transfer transistor 700 shares the diffusion region 67n as one of the source and drain with the reset transistor 400. As described above, the diffusion region 67n corresponds to the charge storage unit FD.

[0407] One of the source and drain of the reset transistor 400, the gate of the amplifier transistor 200, and one of the source and drain of the transfer transistor 700 are electrically connected.

[0408] According to an embodiment of the present disclosure, an imaging device capable of capturing high-quality images by suppressing the effects of leakage current is provided. The imaging device of the present disclosure is useful for, for example, image sensors, digital cameras, etc. The imaging device of the present disclosure can be used in medical cameras, robot cameras, security cameras, cameras mounted on vehicles, etc.

[0409] DESCRIPTION OF SYMBOLS 2 Amplifier 3 Bandwidth control section 3A Bandwidth control circuit 4A Reset circuit 5 Output selection section 6, 6A, 6B, 144 Constant current source 7 Signal readout line 9 First capacitance element 10 Second capacitance element 11 First switch element 12 Second switch element 13 Third switch element 14 Fourth switch element 17, 17A, 17B Photoelectric conversion section 17a Pixel electrode 17b Photoelectric conversion layer 17c Counter electrode 20, 40 Switching circuit 30 Feedback circuit 50A, 50B Readout circuit 60 Semiconductor substrate 61 Support substrate 61p P-type semiconductor region 61p1 First region 61p2 Second region 62n N-type semiconductor region 64 P-type region 65p P-well 65n N-well 66n, zn1, zn2 Well contact region 66p, yp1, yp2: sub-contact regions 67a, 68an1, 68bn1, 72ap1, 72bp1, 66p1, 66n1: first region 67b, 68an2, 68bn2, 72ap2, 72bp2, 66p2, 66n2: second region 67n, 68an, 68bn, 72ap, 72bp, 73an, 73bn: diffusion regions 69a, 69b, 69c: element isolation regions 70, 71, 90a, 90b, 90c, 90d: insulating layers 75: sidewalls 80a, 80b, 80c: wiring layers 81, 82, 83, 84: conductive layers 85n: N-type impurity regions 89: conductive structure 90: interlayer insulating layer 99: voltage control circuit 100: imaging device 110A, 110B, 110C, 110D, 110E, 110F, 110G, 110H, 110I, 210A, 210B, 210C, 210D Pixel 120 Power supply wiring 130 Storage control line 141 Vertical scanning circuit 142 Column signal processing circuit 143 Horizontal signal readout circuit 146 Control circuit 148 Voltage supply circuit 170 Vertical signal line 180 Horizontal common signal line 200 Amplifying transistor 200e, 301e, 400e, 600e, 700e Gate electrode 301 Feedback transistor 400 Reset transistor 502, 503 Selection transistor 600 Inversion transistor 700 Transfer transistorcg0, cg1, cg3, cg5, cg6, cg8, cg9, cg41, cp1, cp2, cp3, cp4, cp5, cp6, cp7, cp8, pa0, pa1, pa2, pa3, pa4, pa5, pa6, pa7, pa8, pa9, pa11, pa12, pa13, pa14, pa21, pa22, pa23, pa24, pa41, pa42, pb, pc, pd Plug h3, h5, h6, h8 Contact hole row1, row2, row3, row4 Column xp Group of 61p and 65p AR1, AR2 Pixel array CD1, CD2 Direction CON1 Band control signal line CON2 Reset control signal line CON3 Selection control signal line CON4 Transfer control signal line D1, D2 Distance FD Charge storage section MR Margin area P1 First portion P2 Second portion PR Pixel area RD Node SA Peripheral area Vp, VR1, VR2 Reference voltage VA1, VA2, VB1, VB2 Voltage source V1, V2, V3, V4 Control signal

Claims

1. An imaging device comprising at least one pixel, the at least one pixel comprising: a photoelectric conversion unit that converts light into electric charges; a charge accumulation unit of a first conductivity type that accumulates the electric charges generated in the photoelectric conversion unit; a first transistor including a first gate electrode and a first diffusion region that contains impurities of the first conductivity type and functions as a source or drain; and a second transistor including a second gate electrode and a second diffusion region that contains impurities of a second conductivity type different from the first conductivity type and functions as a source or drain, wherein in a planar view, the distance between the charge accumulation unit and the second transistor is longer than the distance between the charge accumulation unit and the first transistor.

2. The imaging device according to claim 1, wherein the at least one pixel includes an isolation region that isolates the second transistor, and in a planar view, the distance between the charge accumulation section and the isolation region is longer than the distance between the charge accumulation section and the first transistor.

3. The imaging device according to claim 1 or 2, wherein the first transistor is an amplifying transistor that generates a signal according to the charge stored in the charge storage section.

4. The imaging device according to claim 1, wherein the first transistor is located in a central region of the at least one pixel in a plan view.

5. An imaging device according to any one of claims 1 to 4, wherein the charge storage section, the first transistor, and the second transistor are arranged in this order along a certain direction in a plan view.

6. An imaging device according to any one of claims 1 to 5, wherein the first conductivity type is N-type, and the second conductivity type is P-type.

7. An imaging device according to any one of claims 1 to 6, wherein the at least one pixel includes a first well region containing impurities of the second conductivity type and a second well region containing impurities of the first conductivity type, the first transistor being located in the first well region and the second transistor being located in the second well region in a planar view, and the area of ​​the first well region being larger than the area of ​​the second well region in a planar view.

8. An imaging device according to any one of claims 1 to 7, wherein the at least one pixel comprises a plurality of pixels including a first pixel and a second pixel adjacent to each other, and in a plan view, the charge storage section of the first pixel, the second transistor of the first pixel, the second transistor of the second pixel, and the charge storage section of the second pixel are arranged in this order along a certain direction.

9. The imaging device according to claim 7, wherein the at least one pixel comprises a plurality of pixels including a first pixel and a second pixel adjacent to each other, and the first pixel and the second pixel share one of the first well regions.

10. An imaging device according to any one of claims 1 to 9, wherein the photoelectric conversion unit includes a photoelectric conversion layer that converts light into electric charges and a pixel electrode that collects the electric charges generated in the photoelectric conversion layer, and the charge accumulation unit accumulates the electric charges collected by the pixel electrode.

11. The imaging device according to claim 10, wherein the at least one pixel includes a conductive structure connecting the pixel electrode and the charge storage portion.

12. The imaging device according to any one of claims 1 to 9, wherein the photoelectric conversion unit is a photodiode.

13. An imaging device according to any one of claims 1 to 12, further comprising a semiconductor substrate, wherein the first diffusion region of the first transistor and the second diffusion region of the second transistor exist in a cross section perpendicular to a main surface of the semiconductor substrate.

14. The imaging device according to any one of claims 1 to 13, wherein the first diffusion region of the first transistor is different from the charge storage section.

15. An imaging device according to any one of claims 1 to 14, wherein, in a plan view, the distance between the charge accumulation section and the second gate electrode of the second transistor is longer than the distance between the charge accumulation section and the first gate electrode of the first transistor.

16. An imaging device comprising a pixel, the pixel comprising: a first transistor including a first diffusion region which is a source or drain and a first gate electrode containing impurities of a first conductivity type; a second transistor including a second diffusion region which is a source or drain and a second gate electrode containing impurities of a second conductivity type different from the first conductivity type; a first contact plug connected to the first diffusion region and containing impurities of the first conductivity type; and a second contact plug connected to the second diffusion region and containing impurities of the second conductivity type.

17. The imaging device according to claim 16, wherein the first diffusion region contains impurities of the first conductivity type, and the second diffusion region contains impurities of the second conductivity type.

18. An imaging device according to claim 16 or 17, wherein the first diffusion region is a charge storage section that stores charge, and the first transistor is a reset transistor that resets the potential of the first diffusion region.

Images