Semiconductor light receiving element and its manufacturing method

Abstract

To provide a semiconductor light receiving element and a method of manufacturing the same capable of suppressing increase in dark current.SOLUTION: A semiconductor light receiving element comprises: a first semiconductor layer of a first conductivity type provided on a substrate; a light absorption layer provided on the first semiconductor layer; a second semiconductor layer of the first conductivity type provided on the light absorption layer; a third semiconductor layer of a second conductivity type provided on the second semiconductor layer; a first electrode electrically connected with the first semiconductor layer; a second electrode electrically connected with the third semiconductor layer; a third electrode; and an insulating film. The second and third semiconductor layers form a mesa protruded above an upper surface of the second semiconductor layer. The insulating film covers the upper surface of the second semiconductor layer. The third electrode is provided on a surface on the insulating film and on the second semiconductor layer.SELECTED DRAWING: Figure 1B

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor light receiving element and a method for manufacturing the same. [Background technology]

[0002] A semiconductor light receiving element that receives light and outputs an electrical signal is known (for example, Non-Patent Document 1). The semiconductor light receiving element includes a light absorbing layer and has a mesa. For example, an n-type semiconductor layer is provided below the light absorbing layer, and an n-type electrode is connected to the n-type layer. An n-type semiconductor layer and a p-type semiconductor layer are provided above the light absorbing layer, and a p-type electrode is connected to the p-type layer. A negative voltage is applied to the p-type electrode, and a positive voltage is applied to the n-type electrode. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] “Leakage current in GaInAs / InP photodiodes grown by OMVPE” Journal of Crystal Growth, Volume 98, Issues 1-2(1989), p90-97 Summary of the Invention [Problem to be solved by the invention]

[0004] A high electric field is locally applied to a portion of the mesa, which can increase dark current. Therefore, an object of the present invention is to provide a semiconductor light-receiving element capable of suppressing the increase in dark current, and a method for manufacturing the same. [Means for solving the problem]

[0005] The semiconductor light receiving element according to the present disclosure comprises a first semiconductor layer having a first conductivity type and provided on a substrate, a light absorbing layer provided on the first semiconductor layer, a second semiconductor layer having the first conductivity type and provided on the light absorbing layer, a third semiconductor layer having a second conductivity type and provided on the second semiconductor layer, a first electrode electrically connected to the first semiconductor layer, a second electrode electrically connected to the third semiconductor layer, a third electrode, and an insulating film, wherein the second semiconductor layer and the third semiconductor layer form a mesa protruding above an upper surface of the second semiconductor layer, the insulating film covers an upper surface of the second semiconductor layer, and the third electrode is provided on a surface of the insulating film and on the second semiconductor layer.

[0006] A method for manufacturing a semiconductor light-receiving element according to the present disclosure includes the steps of stacking a first semiconductor layer having a first conductivity type, a light absorption layer, a second semiconductor layer having the first conductivity type, and a third semiconductor layer having a second conductivity type on a substrate in this order; etching the second semiconductor layer and the third semiconductor layer to form a mesa that includes the second semiconductor layer and the third semiconductor layer and protrudes above an upper surface of the second semiconductor layer; forming an insulating film covering an upper surface of the second semiconductor layer; forming a first electrode electrically connected to the first semiconductor layer; forming a second electrode electrically connected to the third semiconductor layer; and forming a third electrode provided on a surface of the insulating film and located on the second semiconductor layer. Effect of the Invention

[0007] According to the present disclosure, it is possible to provide a semiconductor light receiving element capable of suppressing an increase in dark current and a method for manufacturing the same. [Brief description of the drawings]

[0008] [Figure 1A] FIG. 1A is a plan view illustrating the semiconductor light receiving element according to the first embodiment. [Figure 1B] FIG. 1B is a cross-sectional view taken along line AA in FIG. 1A. [Figure 2A]FIG. 2A is a plan view illustrating a method for manufacturing a semiconductor light receiving element. [Figure 2B] FIG. 2B is a cross-sectional view taken along line AA in FIG. 2A. [Figure 3A] FIG. 3A is a plan view illustrating a method for manufacturing a semiconductor light receiving element. [Figure 3B] FIG. 3B is a cross-sectional view taken along line AA in FIG. 3A. [Figure 4A] FIG. 4A is a plan view illustrating a method for manufacturing a semiconductor light receiving element. [Figure 4B] FIG. 4B is a cross-sectional view taken along line AA in FIG. 4A. [Figure 5A] FIG. 5A is a plan view illustrating a method for manufacturing a semiconductor light receiving element. [Figure 5B] FIG. 5B is a cross-sectional view taken along line AA in FIG. 5A. [Figure 6A] FIG. 6A is a plan view illustrating a method for manufacturing a semiconductor light receiving element. [Figure 6B] FIG. 6B is a cross-sectional view taken along line AA in FIG. 6A. [Figure 7A] FIG. 7A is a plan view illustrating a method for manufacturing a semiconductor light receiving element. [Figure 7B] FIG. 7B is a cross-sectional view taken along line AA in FIG. 7A. [Figure 8A] FIG. 8A is a cross-sectional view illustrating a semiconductor light receiving element according to a comparative example. [Figure 8B] FIG. 8B is a cross-sectional view illustrating the semiconductor light receiving element. [Figure 9A] FIG. 9A is a plan view illustrating the semiconductor light receiving element according to the second embodiment. [Figure 9B] FIG. 9B is a cross-sectional view taken along line BB in FIG. 9A. [Figure 10A] FIG. 10A is a plan view illustrating the semiconductor light receiving element according to the third embodiment. [Figure 10B] FIG. 10B is a cross-sectional view taken along line CC in FIG. 10A. [Figure 11A] FIG. 11A is a plan view illustrating the semiconductor light receiving element according to the fourth embodiment. [Figure 11B] FIG. 11B is a cross-sectional view taken along line DD in FIG. 11A. [Figure 12A] FIG. 12A is a plan view illustrating the semiconductor light receiving element according to the fifth embodiment. [Figure 12B] FIG. 12B is a cross-sectional view taken along line EE of FIG. 12A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described.

[0010] One embodiment of the present disclosure is a semiconductor light receiving element including: (1) a first semiconductor layer having a first conductivity type provided on a substrate; a light absorbing layer provided on the first semiconductor layer; a second semiconductor layer having the first conductivity type provided on the light absorbing layer; a third semiconductor layer having a second conductivity type provided on the second semiconductor layer; a first electrode electrically connected to the first semiconductor layer; a second electrode electrically connected to the third semiconductor layer; a third electrode; and an insulating film, the second semiconductor layer and the third semiconductor layer forming a mesa protruding above an upper surface of the second semiconductor layer, the insulating film covering an upper surface of the second semiconductor layer, and the third electrode being provided on the surface of the insulating film and on the second semiconductor layer. When a reverse bias voltage is applied to the first electrode and the second electrode, a depletion layer spreads. A part of the electric field lines generated in the depletion layer heads toward the third electrode and terminates at the third electrode. By suppressing the concentration of the electric field lines at the rising portion of the mesa, a change in the interface state is suppressed. An increase in dark current can be suppressed. (2) The third electrode may be spaced apart from an edge of the mesa, which is a portion between the top surface of the second semiconductor layer and a side surface of the mesa. By suppressing the concentration of electric field lines on the edge, an increase in dark current can be suppressed. (3) The third electrode may cover an upper surface of the second semiconductor layer and a side surface of the mesa, thereby suppressing a concentration of electric field lines at an edge, thereby suppressing an increase in dark current. (4) The second electrode may be provided on the upper surface of the mesa, and the third electrode may cover the upper surface of the second semiconductor layer, the side surface of the mesa, and the upper surface of the mesa, and be electrically connected to the second electrode. The third electrode has the same potential as the second electrode. By suppressing the concentration of electric field lines on the edge, an increase in dark current can be suppressed. (5) The third electrode may surround the mesa within a plane of the third semiconductor layer. By suppressing the concentration of electric field lines around the mesa, an increase in dark current can be effectively suppressed. (6) In the plane of the third semiconductor layer, the mesa may have a circular shape, and in the plane of the third semiconductor layer, the third electrode may have a concentric circular shape with the mesa. By suppressing the concentration of electric field lines around the mesa, an increase in dark current can be effectively suppressed. (7) The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer may be formed of indium phosphide. The relative dielectric constant of indium phosphide is higher than that of air. Electric field lines pass through indium phosphide, which has a high relative dielectric constant, more easily than through air, which has a low relative dielectric constant, but they travel toward and terminate at the third electrode, which has a higher relative dielectric constant. An increase in dark current can be suppressed. (8) The light absorbing layer may be made of indium gallium arsenide. The light absorbing layer generates carriers by absorbing light. The semiconductor light receiving element can detect light. (9) The insulating film may be a silicon nitride film. The relative dielectric constant of silicon nitride is higher than that of air. Electric lines of force pass through silicon nitride, which has a higher relative dielectric constant, more easily than through air, which has a lower relative dielectric constant, but they travel toward and terminate at the third electrode, which has a higher relative dielectric constant. This makes it possible to suppress an increase in dark current. (10) A method for manufacturing a semiconductor light receiving element, comprising the steps of stacking a first semiconductor layer having a first conductivity type, a light absorbing layer, a second semiconductor layer having the first conductivity type, and a third semiconductor layer having a second conductivity type on a substrate in this order, etching the second semiconductor layer and the third semiconductor layer to form a mesa including the second semiconductor layer and the third semiconductor layer and projecting above an upper surface of the second semiconductor layer, forming an insulating film covering an upper surface of the second semiconductor layer, forming a first electrode electrically connected to the first semiconductor layer, forming a second electrode electrically connected to the third semiconductor layer, and forming a third electrode provided on a surface of the insulating film and located above the second semiconductor layer. When a reverse bias voltage is applied to the first electrode and the second electrode, a depletion layer spreads. Electric field lines generated in the depletion layer terminate at the third electrode. By suppressing the concentration of electric field lines at the rising portion of the mesa, a change in the interface state is suppressed. An increase in dark current can be suppressed.

[0011] [Details of the embodiment of the present disclosure] Specific examples of semiconductor light receiving elements and manufacturing methods thereof according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0012] First Embodiment (Semiconductor photodetector) Fig. 1A is a plan view illustrating a semiconductor light receiving element 100 according to a first embodiment. Fig. 1B is a cross-sectional view taken along line AA in Fig. 1A.

[0013] 1A, the shape of the semiconductor light receiving element 100 in the XY plane is rectangular. Two sides of the semiconductor light receiving element 100 extend in the X-axis direction. The other two sides extend in the Y-axis direction. The Z-axis direction is the stacking direction of the semiconductor layers of the semiconductor light receiving element 100. The X-axis, Y-axis, and Z-axis directions are perpendicular to each other.

[0014] 1A, the semiconductor light receiving element 100 has one mesa 22 and one recess 25. The shape of the mesa 22 in the XY plane is circular. The shape of the recess 25 is rectangular. The length L1 of one side of the recess 25 is, for example, 100 μm. The mesa 22 and the recess 25 are spaced apart.

[0015] The semiconductor light receiving element 100 has a substrate 10, an n-type semiconductor layer 12 (first semiconductor layer), a light absorbing layer 14, an n-type semiconductor layer 16 (second semiconductor layer), a p-type semiconductor layer 18 (third semiconductor layer), and a contact layer 20. An anti-reflection film 21 is provided on the lower surface of the substrate 10. Along the Z-axis direction, the n-type semiconductor layer 12, the light absorbing layer 14, and the n-type semiconductor layer 16 are stacked in this order on the upper surface of the substrate 10. The n-type semiconductor layer 12 is provided on the entire upper surface of the substrate 10. The recess 25 is a portion recessed from the upper surface of the n-type semiconductor layer 16 in the Z-axis direction. The light absorbing layer 14, the n-type semiconductor layer 16, the p-type semiconductor layer 18, and the contact layer 20 are not provided in the recess 25, and the n-type semiconductor layer 12 is provided.

[0016] The light absorption layer 14 and the n-type semiconductor layer 16 are laminated in the portion other than the recess 25. The p-type semiconductor layer 18 and the contact layer 20 are laminated on a portion of the n-type semiconductor layer 16. More specifically, a portion of the n-type semiconductor layer 16 protrudes upward in the Z-axis direction, and the p-type semiconductor layer 18 and the contact layer 20 are laminated in this order on the protruding portion. The n-type semiconductor layer 16, the p-type semiconductor layer 18, and the contact layer 20 form a mesa 22. The junction interface between the n-type semiconductor layer 16 and the p-type semiconductor layer 18 is included in the mesa 22. The upper surface of the contact layer 20 becomes the upper surface of the mesa 22. The upper surface of the n-type semiconductor layer 16 extends outside the mesa 22. The upper surface of the n-type semiconductor layer 16 becomes the bottom surface of the mesa 22. The side surface of the mesa 22 may extend parallel to the Z-axis direction or may be inclined from the Z-axis direction. The angle θ between the side surface and the X-axis direction is, for example, 60° or more and 90° or less. A portion where mesa 22 rises between the side surface and the bottom surface of mesa 22 is defined as edge 23. More specifically, the boundary between the side surface of mesa 22 and the top surface of n-type semiconductor layer 16 is defined as edge 23.

[0017] 1B has a diameter D1 of 100 μm, for example. The shortest distance D2 from the edge 23 of the mesa 22 to the end of the recess 25 is 200 μm, for example. The height of the mesa 22 with respect to the surface of the insulating film 24 is 0.6 μm, for example.

[0018] The insulating film 24 is continuously provided on and covers the upper surface of the n-type semiconductor layer 12, the side surfaces of the light absorption layer 14 and the n-type semiconductor layer 16, the upper surface of the n-type semiconductor layer 16 (the bottom surface of the mesa 22), and the side and upper surface of the mesa 22. The insulating film 24 has openings on the upper surface of the n-type semiconductor layer 12 and the upper surface of the mesa 22.

[0019] Electrode 26 (first electrode) is located inside recess 25, provided on the upper surface of n-type semiconductor layer 12, and electrically connected to n-type semiconductor layer 12. Electrode 28 (second electrode) is located on mesa 22, provided on the upper surface of contact layer 20, and electrically connected to contact layer 20. Electrodes 26 and 28 are electrically connected to, for example, a readout circuit via bonding wires or the like.

[0020] The electrode 30 (third electrode) is located on the bottom surface of the mesa 22 and is provided in contact with the upper surface of the insulating film 24. The electrode 30 is spaced apart from the side surface and edge 23 of the mesa 22. A distance D3 between an end of the electrode 30 close to the mesa 22 and a portion located on the edge 23 of the insulating film 24 is, for example, 1 μm. A width W1 of the electrode 30 is, for example, 5 μm. The electrode 30 is insulated from the n-type semiconductor layers 12 and 16, the light absorption layer 14, the p-type semiconductor layer 18, and the contact layer 20 by the insulating film 24, and is not electrically connected to these semiconductor layers. The electrodes 26, 28, and 30 are spaced apart from each other.

[0021] 1A, the shape of the mesa 22 and the shape of the electrode 28 in the XY plane are circular. The shape of the electrode 30 in the XY plane is a ring concentric with the mesa 22. The electrode 30 completely surrounds the mesa 22. The pad 32 is provided on the upper surface of the insulating film 24 at a position separated from the mesa 22, and is electrically connected to the electrode 30. An external power supply or the like is connected to the pad 32.

[0022] The substrate 10 and the n-type semiconductor layers 12 and 16 are formed of, for example, n-type indium phosphide (n-InP). The thickness of the n-type semiconductor layer 12 is, for example, 3 μm. The carrier concentration of the n-type semiconductor layer 12 is, for example, 2×10 18 cm -3 The thickness of the n-type semiconductor layer 16 is, for example, 0.5 μm. The carrier concentration of the n-type semiconductor layer 16 is, for example, 1×10 15 cm -3 As an n-type dopant, for example, silicon (Si) is used.

[0023] The light absorption layer 14 is, for example, 3 μm thick and made of undoped indium gallium arsenide (InGaAs). The p-type semiconductor layer 18 is, for example, made of p-InP. The thickness of the p-type semiconductor layer 18 is, for example, 0.3 μm. The carrier concentration of the p-type semiconductor layer 18 is, for example, 1×10 18 cm -3 The contact layer 20 is formed of, for example, p-type indium gallium arsenide (p-InGaAs). The thickness of the contact layer 20 is, for example, 0.3 μm. The carrier concentration of the contact layer 20 is, for example, 1×10 19 cm -3 The p-type dopant may be, for example, zinc (Zn). The semiconductor layers of the semiconductor light receiving element 100 may be formed of compound semiconductors other than those mentioned above.

[0024] The band gap of the substrate 10, the band gap of the n-type semiconductor layers 12 and 16, and the band gap of the p-type semiconductor layer 18 are larger than the band gap of the light absorbing layer 14. The band gap of the light absorbing layer 14 corresponds to the energy of light having a wavelength of, for example, 1.6 μm. The semiconductor light receiving element 100 is sensitive to light having a wavelength of 1.3 μm.

[0025] The insulating film 24 is a passivation film and protects the surface of the semiconductor layer. The insulating film 24 is made of an insulator such as silicon nitride (SiN) having a thickness of 0.3 μm. The electrode 26 is made of a metal such as a gold-germanium alloy, a laminate (Au-Ge / Ni / Au) in which nickel and gold are laminated in this order from above the n-type semiconductor layer 12. The electrode 28 is made of a metal such as a laminate (Ti / Pt / Au) in which titanium, platinum and gold are laminated in this order from above the contact layer 20. The electrode 30 and the pad 32 are made of a metal such as a laminate (Ti / Au) in which titanium and gold are laminated in this order from above the contact layer 20.

[0026] A reverse bias voltage of, for example, 10 V or more and 20 V or less is applied to the semiconductor light receiving element 100. A negative voltage is applied to the electrode 28. A positive voltage is applied to the electrode 26. Light incident from the lower surface of the substrate 10 passes through the substrate 10 and the n-type semiconductor layer 12, which have a large band gap, and is absorbed by the light absorbing layer 14. In the light absorbing layer 14, carriers (hole-electron pairs) are generated in an amount corresponding to the light intensity. A current corresponding to the light intensity is output from the semiconductor light receiving element 100 to an external device.

[0027] When a reverse bias voltage is applied to the semiconductor light receiving element 100, a large electric field is applied to the pn junction interface between the n-type semiconductor layer 16 and the p-type semiconductor layer 18. In general, when carriers are generated in a portion where a large electric field is applied, dark current may be generated through the interface state formed on the side surface (interface with the insulating film). In this embodiment, the band gap of the n-type semiconductor layer 16 and the p-type semiconductor layer 18 is larger than the band gap of the light absorbing layer 14, so that carriers are not easily generated at the pn junction interface. Therefore, leakage current at the interface between the mesa 22 and the insulating film 24 is suppressed. The light absorbing layer 14 has a smaller band gap than the n-type semiconductor layer 16 and the p-type semiconductor layer 18, but extends wider than the mesa 22, and the interface between the insulating film 24 and the light absorbing layer 14 (the side surface of the light absorbing layer 14) is far away from the pn junction interface. Therefore, a large electric field is not easily applied to the interface state formed on the side surface of the light absorbing layer 14. Leak current at the interface between the light absorbing layer 14 and the insulating film 24 is suppressed. An increase in dark current can be suppressed.

[0028] When the semiconductor light receiving element 100 is used, a reverse bias voltage is applied to the electrodes 26 and 28, and a voltage is also applied to the electrode 30. The potential of the electrode 30 may be, for example, within a range of ±1 V with respect to the potential of the electrode 28, or may be approximately the same potential as the potential of the bottom surface of the mesa 22 when the reverse bias voltage is applied. As described below, since the electric field lines terminate at the electrode 30, they are less likely to concentrate near the edge 23. Since the dark current via the interface state formed near the edge 23 is suppressed, an increase in the dark current of the semiconductor light receiving element 100 due to the interface state can be suppressed.

[0029] (Manufacturing method) 2A, 3A, 4A, 5A, 6A, and 7A are plan views illustrating a manufacturing method of the semiconductor light receiving element 100. Figures 2B, 3B, 4B, 5B, 6B, and 7B are cross-sectional views taken along line AA of the corresponding plan views.

[0030] As shown in FIGS. 2A and 2B, an n-type semiconductor layer 12, a light absorption layer 14, an n-type semiconductor layer 16, a p-type semiconductor layer 18, and a contact layer 20 are epitaxially grown in this order on the upper surface of a substrate 10, for example, by metal-organic vapor phase epitaxy (MOVPE).

[0031] As shown in Figures 3A and 3B, a circular mask 33 is provided on the contact layer 20. For example, a 0.3 μm thick SiO2 layer is provided by a plasma CVD (Chemical Vapor Deposition) method or the like, and the mask 33 is formed by performing photolithography and etching with buffered hydrofluoric acid. The diameter of the mask 33 is, for example, 100 μm. The portion of the upper surface of the contact layer 20 that is not covered by the mask 33 is exposed.

[0032] As shown in FIG. 4A and FIG. 4B, for example, dry etching or wet etching using a chemical etching solution is performed to form the mesa 22. The contact layer 20, the p-type semiconductor layer 18, and the n-type semiconductor layer 16 are not etched in the portions covered with the mask 33, and the mesa 22 remains. The contact layer 20 and the p-type semiconductor layer 18 are removed in the portions exposed from the mask 33. The depth of the wet etching may be, for example, up to the middle of the n-type semiconductor layer 16 in the thickness direction, or up to the interface between the n-type semiconductor layer 16 and the p-type semiconductor layer 18. The surface of the n-type semiconductor layer 16 is exposed from the mask 33 and becomes the bottom surface of the mesa 22. After the mesa 22 is formed, the mask 33 is removed by etching with buffered hydrofluoric acid.

[0033] As shown in Figures 5A and 5B, an insulating film such as SiO2 is formed, and a mask 34 is formed by photolithography and etching with buffered hydrofluoric acid. The mask 34 is made of an insulator such as SiO2 with a thickness of, for example, 0.3 µm. The mask 34 has an opening 35 at a position separated from the mesa 22. The shape of the opening 35 in the XY plane is, for example, a rectangle with one side measuring 100 µm. The n-type semiconductor layer 16 is exposed from the opening 35.

[0034] 6A and 6B, dry etching or wet etching using a chemical etching solution is performed to remove the n-type semiconductor layer 16 and the light absorbing layer 14 in the opening 35, forming a recess 25. The upper surface of the n-type semiconductor layer 12 is exposed from the recess 25. The portion covered by the mask 34 is not etched. After the wet etching, the mask 34 is removed by etching with buffered hydrofluoric acid.

[0035] 7A and 7B, an insulating film 24 made of SiN is formed by, for example, plasma CVD, etc. Openings are formed in the insulating film 24 above the mesa 22 and inside the recess 25 by etching with buffered hydrofluoric acid.

[0036] 1A and 1B, an electrode 26 is provided on the upper surface of the n-type semiconductor layer 12 in the recess 25, and an electrode 28 is provided on the upper surface of the mesa 22 by vacuum deposition and lift-off. An electrode 30 is provided on the upper surface of the insulating film 24 at a position spaced from the edge 23 of the mesa 22. A pad 32 connected to the electrode 30 is formed on the upper surface of the insulating film 24. The rear surface of the substrate 10 is polished, and then an anti-reflection film 21 is provided. Through the above steps, the semiconductor light-receiving element 100 is formed.

[0037] 8A is a cross-sectional view illustrating a semiconductor light receiving element 100R according to a comparative example, with some hatching omitted. As shown in FIG. 8A, the semiconductor light receiving element 100R does not have an electrode 30. The other configurations are the same as those of the semiconductor light receiving element 100.

[0038] When a reverse bias voltage is applied to the semiconductor light receiving element 100R, a depletion layer 40 spreads, for example, from the pn junction interface between the n-type semiconductor layer 16 and the p-type semiconductor layer 18 to the n-type semiconductor layer 16 and the light absorbing layer 14 located outside the mesa 22. Negative (-) charges are generated in the depletion layer 40 near the p-type semiconductor layer 18. Positive (+) charges are generated in the depletion layer 40 in a region of the n-type semiconductor layer 16 and the light absorbing layer 14 closer to the n-type semiconductor layer 12 to which a positive voltage is applied. Electric field lines are generated from the positive charges and terminate in negative charges.

[0039] Electric field lines pass easily through a material with a high relative dielectric constant and difficultly through a material with a low relative dielectric constant. The relative dielectric constant of air is about 1. The relative dielectric constant of SiN is about 6 to 7. The relative dielectric constant of InP is about 12 to 14. The electric field lines pass more easily through the n-type semiconductor layer 16 made of InP and the insulating film 24 made of SiN than through the air outside the semiconductor light receiving element 100R. The electric field lines are influenced by the shape of the mesa 22 and extend from the bottom surface of the mesa 22 along the side surface. For this reason, the electric field lines are concentrated near the edge 23 of the mesa 22. The electric field intensity in the surface portion of the n-type semiconductor layer 16 and the insulating film 24 near the edge 23 is locally increased.

[0040] The application of a high electric field locally changes the state of the interface state at the interface between the n-type semiconductor layer 16 and the insulating film 24. For example, under a stress environment such as high temperature and high voltage, the recombination state density and recombination speed increase. A large number of carriers are generated at the interface, and the dark current increases.

[0041] Fig. 8B is a cross-sectional view illustrating the semiconductor light receiving element 100, and some of the hatching is omitted as in Fig. 8A. When a reverse bias voltage is applied to the semiconductor light receiving element 100, the depletion layer 40 also spreads in the semiconductor light receiving element 100.

[0042] According to the first embodiment, the electrode 30 is provided on the surface of the insulating film 24 and is spaced apart from the edge 23 of the mesa 22. In the semiconductor light receiving element 100, a reverse bias voltage is applied to the pn junction interface, and a voltage is also applied to the electrode 30. As shown by the arrows in FIG. 8B, the distribution of the electric field lines changes from that of the comparative example, and some of the electric field lines extend from the positive charge toward the electrode 30 and terminate at the electrode 30. In other words, some of the electric field lines extend toward the electrode 30 without passing through the vicinity of the edge 23 of the n-type semiconductor layer 16 and the insulating film 24. Since the concentration density of the electric field lines in the vicinity of the edge 23 is reduced, the electric field near the edge 23 can be reduced. Even at high temperatures and high voltages, the change in the interface state can be suppressed, and the increase in dark current can be suppressed.

[0043] Since the electrode 30 is spaced apart from the edge 23, the electric field lines terminating at the electrode 30 do not pass near the edge 23. By suppressing the concentration of the electric field lines, it is possible to prevent the dark current of the semiconductor light receiving element 100 from increasing under high voltage. The distribution of the electric field lines is determined according to the range in which the depletion layer 40 spreads and the angle θ of the mesa 22. The range in which the depletion layer 40 spreads depends on the magnitude of the reverse bias voltage, the carrier concentration of the semiconductor layer, etc., and can change. For example, the closer the angle θ is to 90°, the more likely the electric field lines are to concentrate near the edge 23. The position of the electrode 30 is determined according to the magnitude of the reverse bias voltage, the carrier concentration of the semiconductor layer, the angle θ, etc. When the reverse bias voltage is 10V to 20V, the carrier concentration is set to the above value, and the angle θ is, for example, 60° or more and 90° or less, the electrode 30 is spaced apart from the edge 23 by 1 μm. The width W1 of the electrode 30 is 5 μm.

[0044] As shown in FIG. 1A, in the XY plane, the electrode 30 has a circular ring shape concentric with the mesa 22 and surrounds the mesa 22. By having the electrode 30 surround the entire periphery of the mesa 22, the electric field lines are terminated at a position away from the edge 23 of the mesa 22 throughout the entire periphery of the mesa 22. Dark current can be effectively suppressed. The electrode 30 may have a ring shape other than a circular ring. The electrode 30 may surround a portion of the periphery of the mesa 22 (for example, 50% or more, 80% or more, 90% or more of the periphery, etc.) and not the remaining portion.

[0045] The potential applied to the electrode 30 is, for example, the same potential as that of the bottom surface of the mesa 22 when a reverse bias voltage is applied. The magnitude of the voltage applied to the electrode 30 is also changed according to the magnitude of the reverse bias voltage applied between the electrodes 28 and 26.

[0046] The n-type semiconductor layers 12 and 16 are made of n-InP. The p-type semiconductor layer 18 is made of p-InP. The insulating film 24 is a SiN film. The relative dielectric constants of InP and SiN are higher than air. Electric field lines are less likely to escape into the air and more likely to pass through the n-type semiconductor layer 16 and the insulating film 24. The electrode 30 is made of a metal, and the relative dielectric constant of the metal is higher than that of the semiconductor layer and the insulating film. The electric field lines are more likely to head toward the electrode 30, which has a higher relative dielectric constant, and terminate at the electrode 30. According to the first embodiment, the electric field lines terminate at the electrode 30, so that the concentration of the electric field lines at the edge 23 can be suppressed.

[0047] The n-type semiconductor layers 12 and 16 and the p-type semiconductor layer 18 are made of a semiconductor such as InP that has a larger band gap than the light absorbing layer 14. The light absorbing layer 14 is made of InGaAs. Light incident from the lower surface of the substrate 10 passes through the n-type semiconductor layer 12 and is absorbed by the light absorbing layer 14. The semiconductor photodetector 100 can detect the light.

[0048] The n-type semiconductor layer 16 and the p-type semiconductor layer 18, which have a large band gap, form a mesa 22, and the light absorbing layer 14 is not included in the mesa 22. Since a large electric field is unlikely to be applied to the light absorbing layer 14, which has a small band gap, an increase in dark current caused by the interface state between the light absorbing layer 14 and the insulating film 24 can be suppressed. The substrate 10, the n-type semiconductor layers 12 and 16, and the p-type semiconductor layer 18 may be formed of a semiconductor other than InP, as long as they have a larger band gap than the light absorbing layer 14. The n-type and p-type of the semiconductor layers stacked on the substrate 10 may be interchanged. That is, a p-type semiconductor layer may be provided between the light absorbing layer 14 and the substrate 10, and a p-type semiconductor layer and an n-type semiconductor layer may be stacked in order on the light absorbing layer 14.

[0049] <Second embodiment> The second embodiment is an example of an array sensor. Fig. 9A is a plan view illustrating a semiconductor light receiving element 200 according to the second embodiment. Fig. 9B is a cross-sectional view taken along line BB in Fig. 9A. Descriptions of the same configuration as in the first embodiment will be omitted.

[0050] 9A and 9B, the semiconductor light receiving element 200 has, for example, four mesas 22, four electrodes 30, and four pads 32. One electrode 30 is provided around one mesa 22 and is electrically connected to one pad 32. The four mesas 22 are spaced apart from one another. The four electrodes 30 are spaced apart from one another. The four pads 32 are spaced apart from one another. The electrode 26 is an electrode common to the four mesas 22.

[0051] When the semiconductor light receiving element 200 is operated, a reverse bias voltage is applied from the electrodes 28 and 26 on the four mesas 22. A voltage is applied to the four electrodes 30 through the four pads 32.

[0052] According to the second embodiment, the electrodes 30 are provided at positions spaced apart from the edges 23 of the four mesas 22. By suppressing the concentration of electric field lines near the edges 23, an increase in dark current can be suppressed. The number of mesas 22 and the number of electrodes 30 may be four or less, or may be four or more. The number of electrodes 30 is equal to the number of mesas 22. In other words, one electrode 30 is provided for one mesa 22.

[0053] <Third embodiment> FIG. 10A is a plan view illustrating a semiconductor light receiving element 300 according to the third embodiment. FIG. 10B is a cross-sectional view taken along line CC in FIG. 10A. Description of the same configuration as in the first embodiment will be omitted. As shown in FIGS. 10A and 10B, the width of the electrode 30 is larger than that in the first embodiment. As shown in FIG. 10B, the electrode 30 covers a part of the bottom surface of the mesa 22, the edge 23 of the mesa 22, and the side surface.

[0054] The distance from the portion of insulating film 24 covering edge 23 to the end of electrode 30 opposite mesa 22 is, for example, 6 μm. The height of mesa 22 based on the surface of insulating film 24 is, for example, 6 μm. The height of electrode 30 is, for example, 0.3 μm. The upper end of electrode 30 may be located on the side surface of mesa 22 or on the upper surface of mesa 22.

[0055] According to the third embodiment, the electrode 30 is provided on and in contact with the surface of the insulating film 24, and covers a part of the bottom surface of the mesa 22, the edge 23, and a part of the side surface of the mesa 22 via the insulating film 24. Since the electric field lines terminate at the electrode 30, the concentration of the electric field lines in the vicinity of the edge 23 is suppressed. An increase in dark current can be suppressed.

[0056] <Fourth embodiment> FIG. 11A is a plan view illustrating a semiconductor light receiving element 400 according to the fourth embodiment. FIG. 11B is a cross-sectional view taken along line DD in FIG. 11A. The same configuration as in the first embodiment will not be described. As shown in FIGS. 11A and 11B, the electrode 30 extends to a part of the bottom surface of the mesa 22, the edge 23 of the mesa 22, and the side and top surface of the mesa 22, and is electrically connected to the electrode 28. The pad 32 does not need to be provided. When a reverse bias voltage is applied to the semiconductor light receiving element 400, the electrode 30 is given the same potential as the electrode 28.

[0057] According to the fourth embodiment, the electrode 30 is provided on and in contact with the surface of the insulating film 24, covers a part of the bottom surface of the mesa 22, the edge 23, the side surface of the mesa 22, and a part of the top surface thereof via the insulating film 24, and is electrically connected to the electrode 28. Since the electric field lines terminate at the electrode 30, the concentration of the electric field lines in the vicinity of the edge 23 is suppressed. An increase in dark current can be suppressed.

[0058] <Fifth embodiment> FIG. 12A is a plan view illustrating a semiconductor light receiving element 500 according to the fifth embodiment. FIG. 12B is a cross-sectional view taken along the line EE in FIG. 12A. The same configuration as in the first embodiment will not be described. As shown in FIGS. 12A and 12B, the electrode 28 and the contact layer 20 have an opening 29 at the center of the upper surface of the mesa 22. In the XY plane, the opening 29 is, for example, circular and concentric with the mesa 22. The diameter of the opening 29 is smaller than the diameter of the upper surface of the mesa 22, and is, for example, 70 μm. The p-type semiconductor layer 18 is exposed from the opening 29. The electrode 30 is provided on the surface of the insulating film 24, covers a part of the bottom surface of the mesa 22, the edge 23, the side surface of the mesa 22, and a part of the upper surface, and is electrically connected to the electrode 28. The anti-reflection film 21 is not provided.

[0059] Light irradiated from above in the Z-axis direction is incident on the semiconductor light receiving element 500 through the opening 29. The semiconductor light receiving element 500 is a front-illuminated type light receiving element that receives light and outputs an electrical signal.

[0060] According to the fifth embodiment, the electric field lines terminate at the electrode 30, so that the concentration of the electric field lines in the vicinity of the edge 23 is suppressed. An increase in dark current can be suppressed.

[0061] The electrode 30 in the fifth embodiment may be provided on the bottom surface of the mesa 22 and spaced apart from the edge 23 of the mesa 22, for example, as in the first embodiment. The electrode 30 may be provided on the bottom surface and side surfaces of the mesa 22, as in the second embodiment.

[0062] In the third to fifth embodiments, a plurality of mesas 22 and electrodes 30 may be arranged to form an array sensor, similar to the second embodiment.

[0063] Although the embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present disclosure described in the claims. [Explanation of symbols]

[0064] 10 Substrate 12, 16 n-type semiconductor layer 14 Light absorbing layer 18 p-type semiconductor layer 20 Contact layer 21 Anti-reflection coating 24 Insulating film 26, 28, 30 electrodes 22 Mesa 25 Recess 29, 35 Opening 32 Pad 33, 34 Mask 40 Depletion Layer 100, 100R, 200, 300, 400, 500 Semiconductor photodetector

Claims

1. a first semiconductor layer provided on a substrate and having a first conductivity type; a light absorbing layer provided on the first semiconductor layer; a second semiconductor layer provided on the light absorbing layer and having the first conductivity type; a third semiconductor layer provided on the second semiconductor layer and having a second conductivity type; A first electrode electrically connected to the first semiconductor layer; A second electrode electrically connected to the third semiconductor layer; A third electrode; An insulating film; a portion of the second semiconductor layer and the third semiconductor layer form a mesa that protrudes above an upper surface of the second semiconductor layer; the light absorbing layer and a portion of the second semiconductor layer other than the portion extend outside the mesa; a recess recessed from the other portion of the light absorption layer and the second semiconductor layer at a position spaced from the mesa; the insulating film covers an upper surface of the other portion of the second semiconductor layer; the second electrode is provided on an upper surface of the mesa; The third electrode is provided on the surface of the insulating film, on the other portion of the second semiconductor layer, and is located between the mesa and the recess, covers the upper surface of the second semiconductor layer, the side surface of the mesa, and the upper surface of the mesa, and is a semiconductor light-receiving element electrically connected to the second electrode.

2. The semiconductor light-receiving element according to claim 1 , wherein the third electrode surrounds the mesa within a plane of the third semiconductor layer.

3. In a plane of the third semiconductor layer, the mesa has a circular shape; 3. The semiconductor light-receiving element according to claim 1, wherein the third electrode has a shape concentric with the mesa within a plane of the third semiconductor layer.

4. 4. The semiconductor light receiving element according to claim 1, wherein the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are made of indium phosphide.

5. 5. The semiconductor light-receiving element according to claim 1, wherein the light-absorbing layer is made of indium gallium arsenide.

6. 6. The semiconductor light-receiving element according to claim 1, wherein the insulating film is a silicon nitride film.

7. laminating, in this order, a first semiconductor layer having a first conductivity type, a light absorbing layer, a second semiconductor layer having the first conductivity type, and a third semiconductor layer having a second conductivity type on a substrate; forming a mesa including a portion of the second semiconductor layer and the third semiconductor layer by etching the second semiconductor layer and the third semiconductor layer, the mesa protruding above an upper surface of the second semiconductor layer; etching the second semiconductor layer and the light absorbing layer to form a recess at a location spaced from the mesa; forming an insulating film covering an upper surface of the second semiconductor layer; forming a first electrode electrically connected to the first semiconductor layer; forming a second electrode electrically connected to the third semiconductor layer; forming a third electrode on the surface of the insulating film and located above the second semiconductor layer; the light absorbing layer and a portion of the second semiconductor layer other than the portion extend outside the mesa; the recess is recessed from the other portion of the light absorbing layer and the second semiconductor layer, the insulating film covers an upper surface of the other portion of the second semiconductor layer; the second electrode is provided on an upper surface of the mesa; A method for manufacturing a semiconductor light-receiving element, wherein the third electrode is provided on the surface of the insulating film, on the other portion of the second semiconductor layer, and is located between the mesa and the recess, covers the upper surface of the second semiconductor layer, the side surface of the mesa, and the upper surface of the mesa, and is electrically connected to the second electrode.

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