Semiconductor device and method for manufacturing the same

Abstract

Provided is a semiconductor device comprising: a first conductivity type drift region that is disposed on a semiconductor substrate; a first conductivity type buffer region that is disposed further toward the back surface side of the semiconductor substrate than the drift region and that has a first peak of a doping concentration and a second peak which is disposed further toward the front surface side of the semiconductor substrate than the first peak; and a first lifetime control region that is disposed between the first peak and the second peak in the depth direction of the semiconductor substrate. In the depth direction of the semiconductor substrate, the integral concentration from the upper end of the drift region to the second peak may be greater than or equal to a critical integral concentration.

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Patent Document 1 describes that it provides "an insulated gate bipolar transistor having a simple lifetime control structure, small tail loss, and capable of high-speed switching." [Prior art document] [Patent documents] Patent Document 1: JP 2011-086883 A Problem to be Solved

[0003] It is desirable to improve the electrical properties of semiconductor devices.

[0004] In a first aspect of the present invention, there is provided a semiconductor device comprising: a drift region of a first conductivity type provided in a semiconductor substrate; a buffer region of the first conductivity type provided on the back surface side of the semiconductor substrate relative to the drift region and having a first peak of doping concentration and a second peak provided on the front surface side of the semiconductor substrate relative to the first peak; and a first lifetime control region provided between the first peak and the second peak in the depth direction of the semiconductor substrate.

[0005] An integrated concentration obtained by integrating the doping concentration in a direction from an upper end of the drift region to the second peak in a depth direction of a semiconductor substrate of the semiconductor device may be equal to or greater than a critical integrated concentration.

[0006] In any of the semiconductor devices described above, the buffer region may have a third peak located closer to the front surface of the semiconductor substrate than the second peak, and an integrated concentration from an upper end of the drift region to the third peak in a depth direction of the semiconductor substrate may be less than a critical integrated concentration.

[0007] In any of the semiconductor devices described above, the first peak may be a peak that is closest to a rear surface of the semiconductor substrate among a plurality of peaks that the buffer region has.

[0008] In any of the above semiconductor devices, the first lifetime control region may be located 0.5 μm or more away from the second peak on the back surface side in a depth direction of the semiconductor substrate.

[0009] In any of the above semiconductor devices, the first lifetime control region may be located 1.0 μm or more away from the first peak toward the front surface in a depth direction of the semiconductor substrate.

[0010] In any of the above semiconductor devices, the first peak may be provided at a depth of 0.5 μm or more and 2.0 μm or less from the rear surface of the semiconductor substrate.

[0011] In any of the above semiconductor devices, the second peak may be provided at a depth of 2.0 μm or more and 7.0 μm or less from the rear surface of the semiconductor substrate.

[0012] In any of the above semiconductor devices, the distance between the second peak and the peak of the lifetime killer concentration in the first lifetime control region in a depth direction of the semiconductor substrate may be 0.2 μm or more.

[0013] In any of the above semiconductor devices, the semiconductor device may further include a collector region of a second conductivity type provided on a back surface of a semiconductor substrate, and a distance between the second peak and a peak of the doping concentration of the first lifetime control region in a depth direction of the semiconductor substrate may be smaller than a distance between an upper end of the collector region and the peak of the first lifetime control region.

[0014] In any of the above semiconductor devices, the semiconductor device may further include a collector region of a second conductivity type provided on a back surface of a semiconductor substrate, and a distance between the second peak and a peak of the doping concentration of the first lifetime control region in a depth direction of the semiconductor substrate may be greater than a distance between an upper end of the collector region and the peak of the first lifetime control region.

[0015] In any of the above semiconductor devices, the distance between an upper end of the collector region and a peak of the first lifetime control region in a depth direction of the semiconductor substrate may be 0.1 μm or more.

[0016] In any of the semiconductor devices described above, the peak doping concentration of the first lifetime control region may be greater than the first peak doping concentration and less than the peak doping concentration of the collector region.

[0017] In any of the above semiconductor devices, the peak doping concentration of the collector region is 1.0E17 cm -3 Above, 1.0E19cm -3 It may be the following:

[0018] In any of the above semiconductor devices, the peak doping concentration of the first lifetime control region is 1.0E15 cm -3 More than 1.0E17cm -3 It may be the following:

[0019] In any of the above semiconductor devices, the full width at half maximum of the peak of the doping concentration of the first lifetime control region may be 0.5 μm or less.

[0020] In any of the above semiconductor devices, the semiconductor device may include a transistor portion and a diode portion provided on a semiconductor substrate.

[0021] In any of the semiconductor devices described above, the drift region may include a second lifetime control region closer to the front surface of the semiconductor substrate than the first lifetime control region.

[0022] In any of the semiconductor devices described above, a peak doping concentration of the second lifetime control region may be lower than a peak doping concentration of the first lifetime control region.

[0023] In a second aspect of the present invention, there is provided a semiconductor device including a drift region of a first conductivity type provided in a semiconductor substrate, and a buffer region of the first conductivity type provided on the back surface side of the semiconductor substrate relative to the drift region and having a plurality of peaks of doping concentration. The buffer region may have a first peak provided on the most back surface side of the semiconductor substrate among the plurality of peaks of the buffer region, a sub-peak group provided on the front surface side of the semiconductor substrate relative to the first peak and having one or more peaks of doping concentration, and a first lifetime control region provided in the sub-peak group.

[0024] The position where the integral concentration obtained by integrating the doping concentration in a direction from the upper end of the drift region toward the rear surface side in the depth direction of the semiconductor substrate of the semiconductor device becomes the critical integral concentration may be in the sub-peak group.

[0025] In any of the above semiconductor devices, the peak position of the lifetime killer concentration in the first lifetime control region may be 0.1 μm or more away on the back surface side from the position where the integrated concentration becomes the critical integrated concentration.

[0026] In any one of the semiconductor devices described above, one of the sub-peak groups may include, within a full width at half maximum range of the peak, a position where the integrated concentration becomes a critical integrated concentration.

[0027] In any of the above semiconductor devices, the peak position of the lifetime killer concentration in the first lifetime control region may be 0.1 μm or more away on the back surface side from the position of one of the peaks of a group of sub-peaks including the position where the integrated concentration becomes the critical integrated concentration.

[0028] In any of the above semiconductor devices, the peak position of the lifetime killer concentration in the first lifetime control region may be 0.1 μm or more away on the back surface side from the position where the integrated concentration becomes the critical integrated concentration.

[0029] In any one of the above semiconductor devices, the doping concentration of one of the sub-peaks is 3.0E15 cm -3 It may be more than that.

[0030] In any of the semiconductor devices described above, one peak of the group of sub-peaks may be a second peak adjacent to the front surface side of the first peak.

[0031] In any of the semiconductor devices described above, the doping concentration of each peak of the sub-peak group may be lower than the doping concentration of the first peak.

[0032] In any of the above semiconductor devices, the sub-peak group may include a plurality of peaks, and the doping concentrations of the plurality of peaks of the sub-peak group may decrease toward the front surface side.

[0033] In a third aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising the steps of providing a drift region of a first conductivity type in a semiconductor substrate, providing a buffer region of the first conductivity type on a back surface side of the semiconductor substrate relative to the drift region, and providing a first lifetime control region in the buffer region. The buffer region may have a first peak of doping concentration and a second peak provided on a front surface side of the semiconductor substrate relative to the first peak. The first lifetime control region may be provided between the first peak and the second peak in a depth direction of the semiconductor substrate.

[0034] In the method for manufacturing a semiconductor device, a dose of ions for forming the first lifetime control region may be 0.1 to 10 times the dose of ions for forming the first peak.

[0035] In any of the above methods for manufacturing a semiconductor device, the acceleration energy for forming the first lifetime control region may be not less than 50 keV and not more than 2000 keV.

[0036] In any of the above-mentioned methods for manufacturing a semiconductor device, the method may further include a step of forming a collector region of the second conductivity type on the rear surface of the semiconductor substrate. The dose of ions for forming the collector region is 2.3E13 / cm 2Above, 5.0E13 / cm 2 It may be the following:

[0037] In any of the above methods for manufacturing a semiconductor device, the dose of ions for forming the collector region may be 10 times or more and 50 times or less than the dose of ions for forming the first peak.

[0038] In any of the above methods for manufacturing a semiconductor device, the dose of ions for forming the collector region may be 300 times or more and 500 times or less than the dose of ions for forming the first lifetime control region.

[0039] The above summary of the invention does not list all of the features of the present invention. Also, subcombinations of these features may also be inventions. [Brief description of the drawings]

[0040] [Figure 1A] 1 shows an example of a top view of a semiconductor device 100. FIG. [Figure 1B] 1B shows an example of a cross section taken along line aa' in FIG. 1A. [Figure 2A] An example of the doping concentration distribution in the collector region 22, the buffer region 20 and the drift region 18 is shown. [Figure 2B] 1 is an enlarged view of a doping concentration distribution in the vicinity of a first lifetime control region 151. FIG. [Figure 3A] 1 shows a top view of a modified example of the semiconductor device 100. FIG. [Figure 3B] 1 shows a bb' cross section of a modified example of the semiconductor device 100. [Figure 4] 1 shows an example of a doping concentration distribution in a semiconductor substrate 10. [Diagram 5] 3 is a flowchart showing an example of a manufacturing process of the semiconductor device 100. [Figure 6] 1 shows the characteristics of the semiconductor device 100 relative to the peak depth of the first lifetime control region 151. [Figure 7]1 shows an example of a doping concentration distribution in a semiconductor device of a comparative example. [Figure 8] 1 is a graph showing the relationship between leakage current and turn-off loss Eoff. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0041] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0042] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0043] In this specification, technical matters may be explained using orthogonal coordinate axes of X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components, and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without indicating positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.

[0044] In this specification, the orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are the X-axis and the Y-axis. The axis perpendicular to the upper and lower surfaces of the semiconductor substrate is the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. In this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and the Y-axis, may be referred to as the horizontal direction.

[0045] In this specification, when the term "same" or "equal" is used, it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0046] In this specification, the conductivity type of a doped region doped with impurities is described as P type or N type. In this specification, the impurity may particularly mean either an N type donor or a P type acceptor, and may be described as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to make it a semiconductor exhibiting an N type conductivity type or a semiconductor exhibiting a P type conductivity type.

[0047] In this specification, the doping concentration means the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration means the net concentration obtained by adding up the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, including the polarity of the charge. As an example, the donor concentration is N D , acceptor concentration N A Then, the net doping concentration at any position is N D -N A In this specification, the net doping concentration may be simply referred to as the doping concentration.

[0048] A donor has the function of supplying electrons to a semiconductor. An acceptor has the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, a VOH defect, which is a combination of a vacancy (V), oxygen (O), and hydrogen (H) present in a semiconductor, functions as a donor that supplies electrons. In this specification, a VOH defect may be referred to as a hydrogen donor.

[0049] In this specification, when it is described as P+ type or N+ type, it means that the doping concentration is higher than that of P type or N type, and when it is described as P- type or N- type, it means that the doping concentration is lower than that of P type or N type. Also, when it is described as P++ type or N++ type, it means that the doping concentration is higher than that of P+ type or N+ type.

[0050] In this specification, the chemical concentration refers to the atomic density of an impurity measured regardless of the state of electrical activation. The chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The above-mentioned net doping concentration can be measured by voltage-capacitance measurement (CV). The carrier concentration measured by spreading resistance measurement (SR) may be the net doping concentration. The carrier concentration measured by CV or SR may be a value in a thermal equilibrium state. In addition, in an N-type region, since the donor concentration is sufficiently larger than the acceptor concentration, the carrier concentration in that region may be the donor concentration. Similarly, in a P-type region, the carrier concentration in that region may be the acceptor concentration. In this specification, the doping concentration in an N-type region may be referred to as the donor concentration, and the doping concentration in a P-type region may be referred to as the acceptor concentration.

[0051] In addition, when the concentration distribution of the donor, acceptor or net doping has a peak, the peak value may be taken as the concentration of the donor, acceptor or net doping in the region. In cases where the concentration of the donor, acceptor or net doping is almost uniform, the average value of the concentration of the donor, acceptor or net doping in the region may be taken as the concentration of the donor, acceptor or net doping.

[0052] The carrier concentration measured by the SR method may be lower than the concentration of the donor or acceptor. In the range where the current flows when measuring the spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The reduction in carrier mobility occurs when the carriers are scattered due to a disorder in the crystal structure caused by lattice defects, etc.

[0053] The donor or acceptor concentration calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element indicating the donor or acceptor. As an example, the donor concentration of phosphorus or arsenic, which is a donor in a silicon semiconductor, or the acceptor concentration of boron, which is an acceptor, is about 99% of the chemical concentration. On the other hand, the donor concentration of hydrogen, which is a donor in a silicon semiconductor, is about 0.1% to 10% of the chemical concentration of hydrogen. In this specification, the SI system of units is adopted. In this specification, the unit of distance or length may be expressed in cm (centimeter). In this case, various calculations may be performed by converting to m (meter).

[0054] 1A shows an example of a top view of a semiconductor device 100. The semiconductor device 100 of this example is a semiconductor chip including a transistor portion 70.

[0055] The transistor section 70 is a region obtained by projecting a collector region 22 provided on the back surface side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The collector region 22 will be described later. The transistor section 70 includes a transistor such as an IGBT.

[0056] FIG. 1A shows the region around the chip end portion, which is the edge side of the semiconductor device 100, and omits other regions. For example, an edge termination structure may be provided in the region on the negative side in the Y-axis direction of the semiconductor device 100 of this example. The edge termination structure relieves electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure has, for example, a guard ring, a field plate, a resurf, or a structure combining these. Note that, for convenience, in this example, the edge on the negative side in the Y-axis direction will be described, but the same applies to other edges of the semiconductor device 100.

[0057] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, etc. The semiconductor substrate 10 in this example is a silicon substrate.

[0058] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17 on a front surface 21 of a semiconductor substrate 10. The front surface 21 will be described later. The semiconductor device 100 of this example also includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10.

[0059] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the emitter region 12, the base region 14, the contact region 15, and the well region 17. In addition, the gate metal layer 50 is provided above the gate trench portion 40 and the well region 17.

[0060] The emitter electrode 52 and the gate metal layer 50 are formed of a material containing a metal. At least a portion of the emitter electrode 52 may be formed of a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). At least a portion of the gate metal layer 50 may be formed of a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). The emitter electrode 52 and the gate metal layer 50 may have a barrier metal made of titanium, a titanium compound, or the like under the region made of aluminum or the like. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.

[0061] The emitter electrode 52 and the gate metal layer 50 are provided above the semiconductor substrate 10 with an interlayer insulating film 38 therebetween. The interlayer insulating film 38 is omitted in Fig. 1A. A contact hole 54, a contact hole 55, and a contact hole 56 are provided penetrating the interlayer insulating film 38.

[0062] The contact hole 55 connects the gate metal layer 50 and a gate conductive portion in the transistor portion 70. Inside the contact hole 55, a plug made of tungsten or the like may be formed.

[0063] The contact hole 56 connects the emitter electrode 52 and the dummy conductive portion in the dummy trench portion 30. Inside the contact hole 56, a plug made of tungsten or the like may be formed.

[0064] The connection portion 25 electrically connects a front surface electrode, such as the emitter electrode 52 or the gate metal layer 50, to the semiconductor substrate 10. In one example, the connection portion 25 is provided between the gate metal layer 50 and the gate conductive portion. The connection portion 25 is also provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is a conductive material, such as polysilicon doped with impurities. In this example, the connection portion 25 is polysilicon (N+) doped with N-type impurities. The connection portion 25 is provided above the front surface 21 of the semiconductor substrate 10 via an insulating film, such as an oxide film.

[0065] The gate trench portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (the X-axis direction in this example). The gate trench portions 40 in this example may have two extension portions 41 extending along an extension direction (the Y-axis direction in this example) parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction, and a connection portion 43 connecting the two extension portions 41.

[0066] It is preferable that at least a portion of the connection portion 43 is formed in a curved shape. By connecting the ends of the two extension portions 41 of the gate trench portion 40, it is possible to alleviate electric field concentration at the ends of the extension portions 41. At the connection portion 43 of the gate trench portion 40, the gate metal layer 50 may be connected to the gate conductive portion.

[0067] The dummy trench portion 30 is a trench portion electrically connected to the emitter electrode 52. The dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction (the X-axis direction in this example) similar to the gate trench portion 40. The dummy trench portions 30 in this example may have a U-shape on the front surface 21 of the semiconductor substrate 10 similar to the gate trench portion 40. That is, the dummy trench portion 30 may have two extension portions 31 extending along the extension direction and a connection portion 33 connecting the two extension portions 31.

[0068] The transistor section 70 of this example has a structure in which two gate trench sections 40 and three dummy trench sections 30 are repeatedly arranged. That is, the transistor section 70 of this example has the gate trench sections 40 and the dummy trench sections 30 in a ratio of 2:3. For example, the transistor section 70 has one extension section 31 between two extension sections 41. The transistor section 70 also has two extension sections 31 adjacent to the gate trench section 40.

[0069] However, the ratio of the gate trench portions 40 to the dummy trench portions 30 is not limited to this example. The ratio of the gate trench portions 40 to the dummy trench portions 30 may be 1:1 or 2:4. Furthermore, the transistor portion 70 may have all the trench portions as the gate trench portions 40 and may not have the dummy trench portions 30.

[0070] The well region 17 is a second conductive type region provided on the front surface 21 side of the semiconductor substrate 10 relative to the drift region 18 described later. The well region 17 is an example of a well region provided on the edge side of the semiconductor device 100. The well region 17 is, for example, a P+ type. The well region 17 is formed in a predetermined range from the end of the active region on the side where the gate metal layer 50 is provided. The diffusion depth of the well region 17 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. Part of the regions of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side are formed in the well region 17. The bottoms of the ends of the gate trench portion 40 and the dummy trench portion 30 in the extension direction may be covered by the well region 17.

[0071] The contact holes 54 are formed above the emitter region 12 and the contact region 15 in the transistor section 70. The contact holes 54 are not provided above the well regions 17 provided at both ends in the Y-axis direction. In this manner, one or more contact holes 54 are formed in the interlayer insulating film. The one or more contact holes 54 may be provided extending in the extension direction.

[0072] The mesa portion 71 is a mesa portion provided adjacent to a trench portion in a plane parallel to the front surface 21 of the semiconductor substrate 10. The mesa portion is a portion of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and may be a portion from the front surface 21 of the semiconductor substrate 10 to the deepest bottom of each trench portion. The extension portion of each trench portion may be one trench portion. In other words, the region sandwiched between the two extension portions may be the mesa portion.

[0073] The mesa portion 71 is provided in the transistor portion 70 adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40. The mesa portion 71 has a well region 17, an emitter region 12, a base region 14, and a contact region 15 on the front surface 21 of the semiconductor substrate 10. In the mesa portion 71, the emitter regions 12 and the contact regions 15 are provided alternately in the extension direction.

[0074] The base region 14 is a region of a second conductivity type provided on the front surface 21 side of the semiconductor substrate 10. The base region 14 is, for example, a P-type. The base region 14 may be provided on the front surface 21 of the semiconductor substrate 10 at both ends in the Y-axis direction of the mesa portion 71. Note that FIG. 1A shows only one end of the base region 14 in the Y-axis direction.

[0075] The emitter region 12 is a region of a first conductivity type having a higher doping concentration than the drift region 18. In this example, the emitter region 12 is, for example, an N+ type. An example of a dopant for the emitter region 12 is arsenic (As). The emitter region 12 is provided in contact with the gate trench portion 40 on the front surface 21 of the mesa portion 71. The emitter region 12 may be provided extending in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 to the other. The emitter region 12 is also provided below the contact hole 54.

[0076] Moreover, the emitter region 12 may or may not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is in contact with the dummy trench portion 30.

[0077] The contact region 15 is a region of a second conductivity type having a higher doping concentration than the base region 14. The contact region 15 in this example is, for example, a P+ type. The contact region 15 in this example is provided on the front surface 21 of the mesa portion 71. The contact region 15 may be provided in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 to the other. The contact region 15 may or may not be in contact with the gate trench portion 40 or the dummy trench portion 30. The contact region 15 in this example is in contact with the dummy trench portion 30 and the gate trench portion 40. The contact region 15 is also provided below the contact hole 54.

[0078] Fig. 1B shows an example of the a-a' cross section in Fig. 1A. The a-a' cross section is an XZ plane passing through the emitter region 12 in the transistor section 70. In the a-a' cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24. The emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.

[0079] The drift region 18 is a region of a first conductivity type provided in the semiconductor substrate 10. In this example, the drift region 18 is, for example, an N-type. The drift region 18 may be a region remaining in the semiconductor substrate 10 without other doped regions being formed therein. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.

[0080] The buffer region 20 is a region of a first conductivity type provided on the back surface 23 side of the semiconductor substrate 10 relative to the drift region 18. In this example, the buffer region 20 is, for example, an N-type. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer spreading from the lower surface side of the base region 14 from reaching the collector region 22 of the second conductivity type.

[0081] The collector region 22 is provided below the buffer region 20 in the transistor section 70. The collector region 22 has a second conductivity type. In this example, the collector region 22 is, for example, a P+ type.

[0082] The collector electrode 24 is formed on the rear surface 23 of the semiconductor substrate 10. The collector electrode 24 is made of a conductive material such as a metal.

[0083] The base region 14 is a region of the second conductivity type provided above the drift region 18. The base region 14 is provided in contact with the gate trench portion 40. The base region 14 may be provided in contact with the dummy trench portion 30.

[0084] The emitter region 12 is provided between the base region 14 and the front surface 21. The emitter region 12 is provided in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30.

[0085] The accumulation region 16 is a region of a first conductivity type provided on the front surface 21 side of the semiconductor substrate 10 relative to the drift region 18. The accumulation region 16 in this example is an N+ type, for example. However, the accumulation region 16 does not necessarily have to be provided.

[0086] The accumulation region 16 is provided in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18. The dose of ion implantation of the accumulation region 16 is 1.0E12 cm -2 More than 1.0E13cm -2 The ion implantation dose of the accumulation region 16 may be 3.0E12 cm -2 Above, 6.0E12cm -2 By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be enhanced, and the on-voltage of the transistor section 70 can be reduced. Note that E is a power of 10, and may be, for example, 1.0E12 cm -2 is 1.0 × 10 12 cm -2 means.

[0087] One or more gate trench portions 40 and one or more dummy trench portions 30 are provided on the front surface 21. Each trench portion is provided from the front surface 21 to the drift region 18. In a region where at least one of the emitter region 12, the base region 14, the contact region 15, and the accumulation region 16 is provided, each trench portion also penetrates these regions and reaches the drift region 18. The trench portion penetrating the doping region is not limited to a case where the trench portion is formed in the order of forming the doping region and then the trench portion. A case where the trench portion is formed and then the doping region is formed between the trench portions is also included in the case where the trench portion penetrates the doping region.

[0088] The gate trench portion 40 has a gate trench, a gate insulating film 42, and a gate conductive portion 44 formed on the front surface 21. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate insulating film 42 inside the gate trench. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front surface 21 by an interlayer insulating film 38.

[0089] The gate conductive portion 44 includes a region facing the adjacent base region 14 on the mesa portion 71 side, across the gate insulating film 42, in the depth direction of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel due to an electron inversion layer is formed in the surface layer of the interface of the base region 14 that contacts the gate trench.

[0090] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and is formed further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 is covered on the front surface 21 with an interlayer insulating film 38.

[0091] The interlayer insulating film 38 is provided on the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. The interlayer insulating film 38 is provided with one or more contact holes 54 for electrically connecting the emitter electrode 52 to the semiconductor substrate 10. Contact holes 55 and 56 may also be provided penetrating the interlayer insulating film 38.

[0092] The first lifetime control region 151 is a region in which a lifetime killer is intentionally formed by, for example, injecting impurities into the semiconductor substrate 10. In one example, the first lifetime control region 151 is formed by injecting helium into the semiconductor substrate 10. By providing the first lifetime control region 151, it is possible to reduce the turn-off time and suppress the tail current, thereby reducing losses during switching.

[0093] The lifetime killer is a carrier recombination center. The lifetime killer may be a lattice defect. For example, the lifetime killer may be a vacancy, a divacancy, a complex defect of these with an element constituting the semiconductor substrate 10, or a dislocation. The lifetime killer may also be a rare gas element such as helium or neon, or a metal element such as platinum. An electron beam may be used to form the lattice defect.

[0094] The lifetime killer concentration is the concentration of carrier recombination centers. The lifetime killer concentration may be the concentration of lattice defects. For example, the lifetime killer concentration may be the concentration of vacancies such as vacancies and divacancies, the concentration of complex defects between these vacancies and elements constituting the semiconductor substrate 10, or the concentration of dislocations. The lifetime killer concentration may also be the chemical concentration of a rare gas element such as helium or neon, or the chemical concentration of a metal element such as platinum.

[0095] The first lifetime control region 151 is provided on the back surface 23 side of the center of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. The first lifetime control region 151 in this example is provided in the buffer region 20. The first lifetime control region 151 in this example is provided on the entire surface of the semiconductor substrate 10 in the XY plane, and can be formed without using a mask. The first lifetime control region 151 may be provided in a part of the semiconductor substrate 10 in the XY plane. The dose of impurities for forming the first lifetime control region 151 is 0.5E10 cm -2 More than 1.0E13cm -2 Even if it is less than 5.0E10cm -2 Above, 5.0E11cm -2 It may be the following.

[0096] Moreover, first lifetime control region 151 in this example is formed by implantation from the back surface 23 side. This makes it possible to avoid any influence on the front surface 21 side of semiconductor device 100. For example, first lifetime control region 151 is formed by irradiating helium from the back surface 23 side. Here, whether first lifetime control region 151 is formed by implantation from the front surface 21 side or the back surface 23 side can be determined by acquiring the state of the front surface 21 side by the SR method or by measuring a leakage current.

[0097] 2A shows an example of the doping concentration distribution in the collector region 22, the buffer region 20, and the drift region 18. This figure also shows the distribution of the lifetime killer concentration in the first lifetime control region 151. In this example, the lifetime killer concentration in the first lifetime control region 151 is a helium concentration.

[0098] The doping concentration distribution in the collector region 22, the buffer region 20, and the drift region 18 indicates a net doping concentration obtained by combining the concentrations of the impurities other than those in the first lifetime control region 151.

[0099] The buffer region 20 has multiple doping concentration peaks. The buffer region 20 of this example has four peaks, a first peak 61, a second peak 62, a third peak 63, and a fourth peak 64. The lower end of the buffer region 20 may be the boundary between the collector region 22 and the first peak 61. The upper end of the buffer region 20 may be the boundary between the fourth peak 64 and the drift region 18. The thickness of the buffer region 20 in the depth direction may be 10.0 μm or more and 30.0 μm or less. In this specification, the position of each peak is the position where the doping concentration shows a maximum value.

[0100] The first peak 61 is located closer to the front surface 21 than the collector region 22. The first peak 61 is the peak closest to the back surface 23 among the multiple peaks that the buffer region 20 has. The first peak 61 may be located at a depth position of 0.5 μm or more and 2.0 μm or less from the back surface 23. For example, the depth position of the first peak 61 from the back surface 23 is 0.7 μm. The depth position refers to the position from the back surface 23 in the depth direction of the semiconductor substrate 10.

[0101] The first peak 61 may be the peak with the highest doping concentration in the buffer region 20. The doping concentration of the first peak 61 may be 1.0E15 cm -3 It may be 1.0E16cm or more. -3 The doping concentration of the first peak 61 may be 1.0E17 cm-3 May be less than 5.0E16cm -3 For example, the doping concentration of the first peak 61 may be 2.0E16 cm -3 The dopant of the first peak 61 may be phosphorus, arsenic or hydrogen. In this example, the dopant of the first peak 61 is phosphorus.

[0102] The second peak 62 is located closer to the front surface 21 than the first peak 61. The second peak 62 may be located at a depth position of 2.0 μm or more and 7.0 μm or less from the back surface 23. For example, the depth position of the second peak 62 from the back surface 23 is 4.0 μm. The doping concentration of the second peak 62 is 1.0E15 cm -3 It may be 3.0E15cm or more. -3 The doping concentration of the second peak 62 may be 2.0E16 cm -3 It may be less than 1.0E16cm -3 The doping concentration of the second peak 62 in this example may be 5.0E15 cm -3 That's all.

[0103] The third peak 63 is located closer to the front surface 21 than the second peak 62. The third peak 63 may be located at a depth position of 7.0 μm or more and 13.0 μm or less from the back surface 23. For example, the depth position of the third peak 63 from the back surface 23 is 10.0 μm.

[0104] The fourth peak 64 is located closer to the front surface 21 than the third peak 63. The fourth peak 64 may be located at a depth position that is 10% or more and 20% or less of the substrate thickness of the semiconductor substrate 10 from the back surface 23. For example, the depth position of the fourth peak 64 from the back surface 23 is 15.0 μm.

[0105] Each peak of the buffer region 20 may be formed by the same dopant or different dopants. The dopant of each peak of the buffer region 20 may be hydrogen. The first peak 61 may be formed by ion implantation of phosphorus, and the other peaks may be formed by ion implantation of hydrogen ions. The hydrogen ions may be protons, deuthrones, or tritons. In this example, the hydrogen ions are protons. Alternatively, the dopant of the first peak 61 may be phosphorus, and the dopant of the other peaks may be hydrogen.

[0106] The doping concentration of the first peak 61 may be higher than the doping concentrations of peaks other than the first peak 61. The doping concentration of the first peak 61 may be lower than the maximum doping concentration of the collector region 22. The doping concentration of the first peak 61 may be determined to adjust the hole concentration or hole current injected from the collector region 22 when the gate is on.

[0107] The doping concentration of the peaks other than the first peak 61 in the buffer region 20 may decrease toward the front surface 21 side. Alternatively, the doping concentration of the peak closest to the front surface 21 side among the peaks other than the first peak 61 may be higher than or equal to the doping concentration of the peak adjacent to the back surface 23 side of the peak. In this example, the peak closest to the front surface 21 side is the fourth peak 64, and the peak adjacent to the back surface 23 side of the fourth peak 64 is the third peak 63. The doping concentration Dp4 of the fourth peak 64 may be lower than, equal to, or higher than the doping concentration Dp3 of the third peak 63. In this example, the doping concentration Dp4 is lower than the doping concentration Dp3.

[0108] The number of peaks in the buffer region 20 may be four or more. That is, the number of peaks in the buffer region 20 may be five, six, seven or more.

[0109] The first lifetime control region 151 is provided between the first peak 61 and the second peak 62 in the depth direction of the semiconductor substrate 10. This makes it easier to reduce the turn-off loss Eoff while suppressing an increase in leakage current. The first lifetime control region 151 may be provided at a depth position of 1.0 μm or more and 4.0 μm or less from the back surface 23. The first lifetime control region 151 may have one peak or multiple peaks in the lifetime killer concentration distribution. The lifetime killer concentration distribution of the first lifetime control region 151 in this example is a helium chemical concentration distribution having one peak.

[0110] 2B is an enlarged view of the lifetime killer concentration distribution in the vicinity of the first lifetime control region 151. This figure shows the doping concentrations of the collector region 22, the first peak 61, the second peak 62, and the first lifetime control region 151.

[0111] Depth position Pk indicates the depth position from the back surface 23 of the peak of the first lifetime control region 151. Depth position Pa indicates the depth position from the back surface 23 of the second peak 62. Depth position Pb indicates the depth position from the back surface 23 of the upper end of the collector region 22. The upper end of the collector region 22 refers to the surface of the collector region 22 on the front surface 21 side. Depth position Pb indicates the thickness of the collector region 22 in the depth direction. The thickness of the collector region 22 in the depth direction may be 0.2 μm or more and 1.0 μm or less from the back surface 23.

[0112] Distance A is the distance between second peak 62 and the peak of the doping concentration of first lifetime control region 151 in the depth direction of semiconductor substrate 10. That is, distance A is calculated by Pa-Pk. By providing distance A, it is possible to suppress the disappearance of lattice defects in first lifetime control region 151. Distance A may be 0.2 μm or more, or may be 0.5 μm or more.

[0113] Distance B is the distance between the upper end of collector region 22 and the peak of first lifetime control region 151 in the depth direction of semiconductor substrate 10. That is, distance B is calculated by Pk-Pb. By providing distance B, it is possible to suppress the disappearance of lattice defects in first lifetime control region 151. Distance B may be 0.1 μm or more, or may be 1.0 μm or more.

[0114] Here, distance A may be smaller than distance B. In other words, the peak of the first lifetime control region 151 may be located on the side closer to the second peak 62 between depth positions Pa and Pb. Distance A may be ½ or less, or ⅓ or less, of distance B. Distance A may be larger than distance B. Distance A may be twice or more, or three times or more, of distance B.

[0115] The lifetime killer concentration distribution of the first lifetime control region 151 may have a peak concentration Dk1 and a full width at half maximum (FWHM) of the peak concentration Dk1. By reducing the full width at half maximum of the peak concentration Dk1, the influence on the peak of the adjacent buffer region 20 can be reduced. That is, by reducing the full width at half maximum of the first lifetime control region 151, the disappearance of lattice defects in the first lifetime control region 151 can be suppressed. For example, the full width at half maximum of the first lifetime control region 151 is 0.5 μm or less.

[0116] The peak of the lifetime killer concentration in the first lifetime control region 151 may be located at a depth of 0.6 μm or more and 3.8 μm or less from the back surface of the semiconductor substrate 10. By increasing the depth position of the first lifetime control region 151, it becomes easier to reduce the turn-off loss Eoff. However, if the depth position of the first lifetime control region 151 is made too deep, it may be connected to a depletion layer spreading from the lower surface side of the base region 14, increasing the leakage current.

[0117] Furthermore, the peak concentration Dk1 of the lifetime killer concentration of the first lifetime control region 151 may be greater than the peak concentration Dp1 of the doping concentration of the first peak 61. The peak concentration Dk1 of the lifetime killer concentration of the first lifetime control region 151 may be two or more times, five or more times, or ten or more times that of the first peak 61. In one example, the peak concentration Dk1 of the lifetime killer concentration of the first lifetime control region 151 is 1.0E15 cm -3 More than 1.0E17cm -3 The following is the result.

[0118] The following effects are achieved by making the peak concentration Dk1 of the lifetime killer concentration of the first lifetime control region 151 higher than the peak concentration Dp1 of the doping concentration of the first peak 61. Hydrogen for forming the buffer region 20 terminates the dangling bonds of the lattice defects near the peak concentration of the buffer region 20. This may cause the introduced lattice defects to disappear. Even if the lattice defects disappear near the peak concentration of the buffer region 20, the disappearance of the lattice defects is suppressed if the peak concentration Dk1 of the first lifetime control region 151 is higher than the peak concentration of the buffer region 20. This allows the excess carriers on the back surface 23 side during reverse recovery operation to be sufficiently reduced.

[0119] The peak concentration Dk1 of the peak lifetime killer concentration of the first lifetime control region 151 is smaller than the peak concentration Dc of the doping concentration of the collector region 22. The peak doping concentration of the collector region 22 is 1.0E17 cm -3 Above, 1.0E19cm -3 It may be the following:

[0120] 3A shows a top view of a modified example of the semiconductor device 100. The semiconductor device 100 of this example includes a transistor section 70 and a diode section 80. For example, the semiconductor device 100 is a reverse conducting IGBT (RC-IGBT). The transistor section 70 of this example includes a boundary section 90 located at the boundary between the transistor section 70 and the diode section 80.

[0121] The diode section 80 is a region obtained by projecting a cathode region 82 provided on the back surface side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The cathode region 82 has a first conductivity type. In this example, the cathode region 82 is an N+ type, for example. The diode section 80 includes a diode such as a free wheel diode (FWD) provided adjacent to the transistor section 70 on the upper surface of the semiconductor substrate 10.

[0122] The boundary portion 90 is a region provided in the transistor portion 70 and adjacent to the diode portion 80. The boundary portion 90 has a contact region 15. The boundary portion 90 in this example does not have an emitter region 12. In one example, the trench portion of the boundary portion 90 is a dummy trench portion 30. The boundary portion 90 in this example is arranged so that both ends in the X-axis direction are dummy trench portions 30.

[0123] The contact holes 54 are provided above the base region 14 in the diode portion 80. The contact holes 54 are provided above the contact regions 15 in the boundary portion 90. None of the contact holes 54 are provided above the well regions 17 provided at both ends in the Y-axis direction.

[0124] The mesa portion 91 is provided in the boundary portion 90. The mesa portion 91 has a contact region 15 on the front surface 21 of the semiconductor substrate 10. The mesa portion 91 of this example has a base region 14 and a well region 17 on the negative side in the Y-axis direction.

[0125] The mesa portion 81 is provided in a region of the diode portion 80 that is sandwiched between adjacent dummy trench portions 30. The mesa portion 81 has a base region 14 on the front surface 21 of the semiconductor substrate 10. The mesa portion 81 of this example has the base region 14 and a well region 17 on the negative side in the Y-axis direction.

[0126] The emitter region 12 is provided in the mesa portion 71, but may not be provided in the mesa portion 81 and the mesa portion 91. The contact region 15 is provided in the mesa portion 71 and the mesa portion 91, but may not be provided in the mesa portion 81.

[0127] 3B shows a bb' cross section of a modified example of the semiconductor device 100. The semiconductor device 100 of this example includes a first lifetime control region 151 and a second lifetime control region 152.

[0128] The contact region 15 is provided above the base region 14 in the mesa portion 91. The contact region 15 is provided in contact with the dummy trench portion 30 in the mesa portion 91. In another cross section, the contact region 15 may be provided on the front surface 21 of the mesa portion 71.

[0129] The accumulation region 16 is provided in the transistor section 70 and the diode section 80. The accumulation region 16 in this example is provided on the entire surface of the transistor section 70 and the diode section 80. However, the accumulation region 16 does not have to be provided in the diode section 80.

[0130] The cathode region 82 is provided below the buffer region 20 in the diode section 80. The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor section 70 and the diode section 80. That is, the collector region 22 is provided below a boundary section 90 in this example.

[0131] The first lifetime control region 151 is provided in both the transistor portion 70 and the diode portion 80. This enables the semiconductor device 100 of this embodiment to speed up recovery in the diode portion 80 and further improve switching loss. The first lifetime control region 151 may be formed by a method similar to that of the first lifetime control region 151 of the other embodiments.

[0132] The second lifetime control region 152 is provided on the front surface 21 side of the center of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. The second lifetime control region 152 in this example is provided in the drift region 18. The second lifetime control region 152 is provided in both the transistor portion 70 and the diode portion 80. The second lifetime control region 152 may be formed by injecting impurities from the front surface 21 side, or may be formed by injecting impurities from the back surface 23 side. The second lifetime control region 152 is provided in the diode portion 80 and the boundary portion 90, and may not be provided in a part of the transistor portion 70.

[0133] The second lifetime control region 152 may be formed by any method among the methods for forming the first lifetime control region 151. The elements and doses for forming the first lifetime control region 151 and the second lifetime control region 152 may be the same or different.

[0134] 4 shows an example of a doping concentration distribution in the semiconductor substrate 10. This figure also shows the distribution of the doping concentrations of the first lifetime control region 151 and the second lifetime control region 152. This figure also shows the integrated concentration from the upper end of the drift region 18.

[0135] In this specification, the value obtained by integrating the doping concentration along the depth direction of the semiconductor substrate 10 from the lower surface side of the base region 14 to a specific position of the semiconductor substrate 10 is referred to as the integral concentration. In addition, in this specification, when a forward bias is applied between the collector electrode 24 and the emitter electrode 52, the maximum value of the electric field strength reaches the critical electric field strength, causing an avalanche breakdown, and the semiconductor substrate 10 is depleted from the lower surface of the base region 14 to a specific position in the depth direction, the integral concentration is said to reach the critical integral concentration Nc. In the semiconductor device 100, the application of a forward bias between the collector electrode 24 and the emitter electrode 52 means that the potential of the collector electrode 24 is higher than the potential of the emitter electrode 52 when the gate is in an off state. When an avalanche breakdown occurs in the semiconductor device 100, an avalanche current flows between the collector electrode 24 and the emitter electrode 52, and the voltage V between the collector electrode 24 and the emitter electrode 52 increases. CE In this case, the depletion layer reaches the position P where the integral concentration reaches the critical integral concentration Nc. Nc It will not spread further towards the back side than it does.

[0136] The first lifetime control region 151 of this example is provided on the back surface 23 side of the second peak 62. In the depth direction of the semiconductor substrate 10, the integrated concentration from the upper end of the drift region 18 to the second peak 62 may be equal to or greater than the critical integrated concentration Nc. Nc may coincide with the position Pa of the second peak 62. As a result, the depletion layer spreading from the lower surface side of the base region 14 is stopped by the second peak 62, so that the peak of the first lifetime control region 151 can be arranged in a region that is not depleted. Therefore, an increase in leakage current caused by the implantation of the first lifetime control region 151 can also be suppressed. Note that, in the depth direction of the semiconductor substrate 10, the integrated concentration from the upper end of the drift region 18 to the third peak 63 may be less than the critical integrated concentration Nc. That is, the depletion layer spreading from the lower surface side of the base region 14 may be stopped by the second peak 62.

[0137] Position P where the critical integral concentration Nc is reached NcThe position P where the critical integral concentration Nc is reached may not coincide with the peak position of the buffer region 20 (peak Pa in this example). Nc may be located between the position Pa of the second peak 62 and the third peak 63. The position P Nc may be located at the position of the third peak 63. Nc may be located between the fourth peak 64 and the third peak 63. The position P at which the critical integral concentration Nc is reached Nc may be located at the position of the fourth peak 64.

[0138] The peak concentration Dk2 of the lifetime killer concentration of the second lifetime control region 152 may be smaller than, equal to, or larger than the peak concentration Dk1 of the lifetime killer concentration of the first lifetime control region 151. In this example, the peak concentration Dk2 of the second lifetime control region 152 is smaller than the peak concentration Dk1 of the first lifetime control region 151. The peak concentration Dk2 of the second lifetime control region 152 is smaller than the peak concentration Dk1 of the doping concentration of the accumulation region 16. acc In this example, the peak concentration Dk2 in the second lifetime control region 152 is smaller than, equal to, or larger than the peak concentration D acc The peak concentration Dk2 of the second lifetime control region 152 may be greater than, equal to, or smaller than the peak concentration Dp4 of the doping concentration of the fourth peak 64. In this example, the peak concentration Dk2 of the second lifetime control region 152 is greater than the peak concentration Dp4 of the doping concentration of the fourth peak 64.

[0139] 5 is a flowchart showing an example of a manufacturing process of the semiconductor device 100. In step S100, a structure is formed on the front surface side of the semiconductor device 100. Also, in step S100, after the structure on the front surface side is formed, the back surface 23 side of the semiconductor substrate 10 is ground to adjust the thickness of the semiconductor substrate 10 according to the required withstand voltage.

[0140] In step S102, the first peak 61 is formed by ion implantation from the back surface 23 side of the semiconductor substrate 10. In one example, the dopant of the first peak 61 is phosphorus. For example, the dose of the dopant of the first peak 61 is 1.0E12 cm -2 It may be more than 2.0E12cm -2 The dose of the dopant in the first peak 61 may be 1.0E13 cm -2 May be less than 5.0E12cm -2 In this example, it is 3.0E12 cm. -2 The acceleration energy of the dopant of the first peak 61 may be 500 keV or more, or 700 keV or more. The acceleration energy of the dopant of the first peak 61 may be 4000 keV or less, or 3000 keV or less. In this example, it is 2000 keV.

[0141] In step S104, the collector region 22 is formed. The collector region 22 may be formed on the entire back surface 23 of the semiconductor substrate 10. The dose of ions for forming the collector region 22 is 2.0E13 / cm 2 or more, 5.0E13 / cm 2 The dose of ions for forming the collector region 22 may be 10 times or more and 50 times or less of the dose of ions for forming the first peak 61.

[0142] In step S106, the cathode region 82 is formed. It is to be noted that the collector region 22 may be formed after the cathode region 82 is formed. If the semiconductor device 100 does not have the diode portion 80, step S106 may be omitted. In step S108, the region into which the impurities have been implanted from the back surface 23 side of the semiconductor substrate 10 is heated by laser annealing.

[0143] In step S110, hydrogen ions are implanted to form the buffer region 20. When multiple peaks are to be formed in the buffer region 20, hydrogen ions are implanted multiple times with different acceleration energies. For example, in step S110, a second peak 62, a third peak 63, and a fourth peak 64 are formed.

[0144] As an example, the dose of hydrogen ions corresponding to the second peak 62 is 7.0×10 12 / cm 2 The acceleration energy is 1100 keV. The dose of hydrogen ions corresponding to the third peak 63 is 1.0×10 13 / cm 2 The acceleration energy is 820 keV. The dose of hydrogen ions corresponding to the fourth peak 64 is 3.0 × 10 14 / cm 2 The acceleration energy is 400 keV. In step S112, the semiconductor substrate 10 is heated in an annealing furnace in a nitrogen atmosphere or the like. As an example, the annealing temperature is 370 degrees and the annealing time is 5 hours.

[0145] In step S114, helium is ion-implanted from the rear surface 23 side of the semiconductor substrate 10 to form the first lifetime control region 151. The ion dose for forming the first lifetime control region 151 is 1.0E11 cm -2 It may be 3.0E11cm or more. -2 The dose of ions for forming the first lifetime control region 151 may be 5.0E12 cm -2 It may be less than 2.0E12cm -2 or less. By making the dose of the first lifetime control region 151 larger than a predetermined lower limit, the turn-off loss Eoff can be reduced. However, if the dose of the first lifetime control region 151 is made larger than a predetermined upper limit, the characteristics may vary due to lattice defects.

[0146] The dose of ions for forming the collector region 22 may be 300 times or more and 500 times or less than the dose of ions for forming the first lifetime control region 151. The acceleration energy for forming the first lifetime control region 151 may be 50 keV or more and 2000 keV or less. As an example, He 2+ , dose amount 2×10 12 / cm 2 The ions are implanted at an acceleration energy of 700 keV. In step S116, the semiconductor substrate 10 is heated in an annealing furnace in a nitrogen atmosphere or the like.

[0147] The dose of ions to form the first lifetime control region 151 may be 0.1 times or more and 10 times or less, or 0.5 times or more and 5 times or less, or 0.7 times or more and 3 times or less, of the dose of ions to form the first peak 61.

[0148] In step S118, the collector electrode 24 is formed. For example, the collector electrode 24 is formed by a sputtering method. The collector electrode 24 may be a laminated electrode in which an aluminum layer, a titanium layer, a nickel layer, and the like are laminated. Through such a process, the semiconductor device 100 can be manufactured.

[0149] 6 shows the characteristics of the semiconductor device 100 with respect to the peak depth of the first lifetime control region 151. This figure shows the change in turn-off loss Eoff and the change in leakage current when the IGBT rated voltage is applied with respect to the peak depth of the first lifetime control region 151. As the peak depth of the first lifetime control region 151 is increased, the turn-off loss Eoff tends to decrease. On the other hand, if the peak depth of the first lifetime control region 151 is made too large, the first lifetime control region 151 may be connected to a depletion layer spreading from the lower surface side of the base region 14, increasing the leakage current.

[0150] 6, 2A, 2B, or 4, when the peak position Pk of the lifetime killer concentration in the first lifetime control region 151 is 4.0 μm from the back surface 23, the turn-off loss Eoff increases specifically. When the peak position Pk is 4.0 μm, the peak position Pk coincides with the position Pa of the second peak 62 in the buffer region 20. Therefore, the lifetime killer concentration distribution in the first lifetime control region 151 and the doping concentration distribution of the second peak 62 overlap. Due to the overlap of the distributions, the dangling bonds in the vacancies in the first lifetime control region 151 are terminated by hydrogen in the second peak 62 in the buffer region 20. As a result, the peak concentration Dk of the lifetime killer concentration in the first lifetime control region 151 decreases, and the turn-off loss Eoff increases.

[0151] The buffer region 20 may have a first peak 61 and a group of sub-peaks 600. The group of sub-peaks 600 is one or more peaks other than the first peak 61 and located closer to the front surface 21 of the semiconductor substrate 10 than the first peak 61. In this example, the group of sub-peaks 600 has a second peak 62, a third peak 63, and a fourth peak 64. The position P at which the critical integral concentration Nc is reached Nc may be in the minor peak group 600. The minor peak group 600 may be provided with a first lifetime control region 151.

[0152] The peak position Pk of the first lifetime control region 151 is the position P where the critical integral concentration Nc is reached. Nc The peak position Pk may be at least 0.1 μm away, at least 0.5 μm away, or at least 1.0 μm away from the position P Nc From the position P toward the rear surface 23, the position may be located at a depth of 3.0 μm or less, or may be located at a depth of 2.0 μm or less. Nc is the position Pa, and the peak position Pk is the position P Nc Alternatively, it is located at a depth of 1 μm away from the position Pa on the rear surface 23 side.

[0153] position P Ncmay be located in the range of the full width at half maximum FWHM of the peak concentration Dpx of one peak x in the sub-peak group 600. In this example, the peak x is the second peak 62. The second peak 62 is adjacent to the first peak 61 on the front surface 21 side of the semiconductor substrate 10. Furthermore, the full width at 30% of the peak concentration Dpx of the peak x is referred to as the 30% full width (FW30%M), and the position P Nc may be located in the range of 30% full width. Furthermore, the full width at 20% of the peak concentration Dpx of the peak x is called the 20% full width (FW20%M), and the position P Nc may be located in the range of 20% full width. Furthermore, the full width at 10% of the peak concentration Dpx of the peak x is called the 10% full width (FW10%M), and the position P Nc may lie within a range of 10% full width.

[0154] That is, a position P where one of the sub-peaks 600 has an integral concentration of a critical integral concentration Nc within a range of the full width at half maximum, 30% full width, 20% full width, or 10% full width of the peak x. Nc In these cases, the peak density Dpx of peak x is 3.0E15 cm -3 It may be more than 4.0E15cm -3 It may be more than 5.0E15cm -3 The peak density Dpx may be 1.0E16 cm or more. -3 May be less than 8.0E15cm -3 It may be less than 6.0E15cm -3 In this example, peak x is the second peak 62, Dpx is Dp2, and Dp is 7.0E15 cm -3 The doping concentration of each peak x of the group of sub-peaks 600 may be less than the doping concentration of the first peak 61.

[0155] Furthermore, the position Pk of the first lifetime control region 151 is the position P Nc The peak position Pk may be 0.1 μm or more, 0.5 μm or more, or 1.0 μm or more away from the position Px of the peak x included in FWHM, FW30%M, FW20%M, or FW10%M toward the rear surface 23 side. NcFrom the above, it may be located at a depth of 3.0 μm or less toward the rear surface 23 side, or may be located at a depth of 2.0 μm or less.

[0156] Furthermore, the position Pk of the first lifetime control region 151 is the position P Nc Position P of peak x that is included in FWHM, FW30%M, FW20%M or FW10%M Nc The peak position Pk may be at least 0.1 μm away, at least 0.5 μm away, or at least 1.0 μm away from the position P Nc From the above, it may be located at a depth of 3.0 μm or less toward the rear surface 23 side, or may be located at a depth of 2.0 μm or less.

[0157] As a result, the turn-off loss Eoff can be reduced and the leakage current can also be reduced, improving the trade-off between the turn-off loss Eoff and the leakage current.

[0158] 7 shows an example of the doping concentration distribution of a semiconductor device of a comparative example, in which the doping concentration distribution of the lifetime control region 550 is also shown.

[0159] The buffer region 520 has a plurality of doping concentration peaks. In this example, the buffer region 520 has four peaks: a first peak 61, a second peak 62, a third peak 63, and a fourth peak 64.

[0160] The lifetime control region 550 is provided closer to the front surface 21 than the second peak 62 in the depth direction of the semiconductor substrate 10. That is, the lifetime control region 550 may be connected to a depletion layer spreading from the lower surface side of the base region 14. The doping concentration of the peak of the lifetime control region 550 is smaller than the doping concentration of the first peak 61. Although the lifetime control region 550 can further reduce energy loss by increasing the amount of light ion irradiation, leakage current may increase starting from the generated lattice defects.

[0161] 8 is a graph showing the relationship between the leakage current and the turn-off loss Eoff. The vertical axis shows the turn-off loss Eoff, and the horizontal axis shows the leakage current. In this example, the results of both the example and the comparative example are shown.

[0162] In the semiconductor device 100 of the embodiment, the turn-off loss Eoff can be reduced while suppressing an increase in leakage current even if the light ion irradiation dose for forming the first lifetime control region 151 is increased. On the other hand, in the semiconductor device of the comparative example, when the light ion irradiation dose for forming the lifetime control region 550 is increased, the leakage current increases starting from the generated lattice defects.

[0163] In this way, in the semiconductor device 100 of this example, by setting the peak of the lifetime killer concentration of the first lifetime control region 151 between the first peak 61 and the second peak 62, the leakage current can be suppressed even if the doping concentration is increased.

[0164] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included in the technical scope of the present invention.

[0165] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically indicated as "before," "prior to," etc., and may be realized in any order unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is explained using "first," "next," etc. for convenience, it does not mean that it is essential to perform the process in this order. [Explanation of symbols]

[0166] 10 semiconductor substrate, 12 emitter region, 14 base region, 15 contact region, 16 accumulation region, 17 well region, 18 drift region, 20 buffer region, 21 front surface, 22 collector region, 23 back surface, 24 collector electrode, 25 connection portion, 30 dummy trench portion, 31 extension portion, 32 dummy insulating film, 33 connection portion, 34 dummy conductive portion, 38 interlayer insulating film, 40 gate trench portion, 41 extension portion, 42 gate insulating film, 43 connection portion, 44 gate conductive portion, 50 52···gate metal layer, 52···emitter electrode, 54···contact hole, 55···contact hole, 56···contact hole, 61···first peak, 62···second peak, 63···third peak, 64···fourth peak, 70···transistor portion, 71···mesa portion, 80···diode portion, 81···mesa portion, 82···cathode region, 90···boundary portion, 91···mesa portion, 100···semiconductor device, 151···first lifetime control region, 152···second lifetime control region, 520···buffer region, 550···lifetime control region, 600···sub-peak group

Claims

1. a drift region of a first conductivity type provided in a semiconductor substrate; a first conductivity type buffer region provided closer to the back surface of the semiconductor substrate than the drift region and having two or more peaks in a doping concentration distribution, the two or more peaks including a first peak provided closest to the back surface and a second peak provided adjacent to and closer to the front surface of the semiconductor substrate than the first peak; a first lifetime control region provided between the first peak and the second peak in a depth direction of the semiconductor substrate; Equipped with an integral concentration obtained by integrating a doping concentration in a direction from an upper end of the drift region to the second peak in a depth direction of the semiconductor substrate is equal to or greater than a critical integral concentration; A peak concentration of a lifetime killer concentration of the first lifetime control region is greater than a doping concentration of the first peak and a doping concentration of the second peak. Semiconductor device.

2. the buffer region has a third peak provided closer to the front surface of the semiconductor substrate than the second peak; In the depth direction of the semiconductor substrate, an integrated concentration from an upper end of the drift region to the third peak is less than a critical integrated concentration. The semiconductor device according to claim 1 .

3. The first peak is the peak closest to the back surface of the semiconductor substrate among a plurality of peaks that the buffer region has. The semiconductor device according to claim 1 .

4. The first lifetime control region is located 0.5 μm or more away from the second peak toward the rear surface in the depth direction of the semiconductor substrate. The semiconductor device according to claim 1 .

5. The first lifetime control region is located 1.0 μm or more away from the first peak toward the front surface in the depth direction of the semiconductor substrate. The semiconductor device according to claim 1 .

6. The first peak is provided at a depth of 0.5 μm or more and 2.0 μm or less from the rear surface of the semiconductor substrate. The semiconductor device according to claim 1 .

7. The second peak is provided at a depth of 2.0 μm or more and 7.0 μm or less from the rear surface of the semiconductor substrate. The semiconductor device according to claim 1 .

8. In the depth direction of the semiconductor substrate, the distance between the second peak and the peak of the lifetime killer concentration of the first lifetime control region is 0.2 μm or more. The semiconductor device according to claim 1 .

9. a collector region of a second conductivity type provided on a rear surface of the semiconductor substrate; In the depth direction of the semiconductor substrate, the distance between the second peak and the peak of the lifetime killer concentration in the first lifetime control region is smaller than the distance between the upper end of the collector region and the peak in the first lifetime control region. The semiconductor device according to claim 1 .

10. a collector region of a second conductivity type provided on a rear surface of the semiconductor substrate; In a depth direction of the semiconductor substrate, a distance between the second peak and a peak of the lifetime killer concentration in the first lifetime control region is greater than a distance between an upper end of the collector region and the peak of the lifetime killer concentration in the first lifetime control region. The semiconductor device according to claim 1 .

11. In the depth direction of the semiconductor substrate, the distance between the upper end of the collector region and the peak of the lifetime killer concentration of the first lifetime control region is 0.1 μm or more. The semiconductor device according to claim 9.

12. The peak concentration of the lifetime killer concentration of the first lifetime control region is greater than the first peak doping concentration and less than the peak doping concentration of the collector region. The semiconductor device according to claim 9.

13. The peak doping concentration of the collector region is 1.0E17 cm －３ Above, 1.0E19cm －３ is less than or equal to The semiconductor device according to claim 9.

14. a drift region of a first conductivity type provided in a semiconductor substrate; a buffer region of a first conductivity type provided closer to the back surface of the semiconductor substrate than the drift region and having a first peak of doping concentration and a second peak provided closer to the front surface of the semiconductor substrate than the first peak; a first lifetime control region provided between the first peak and the second peak in a depth direction of the semiconductor substrate; a collector region of a second conductivity type provided on a rear surface of the semiconductor substrate; Equipped with an integral concentration obtained by integrating a doping concentration in a direction from an upper end of the drift region to the second peak in a depth direction of the semiconductor substrate is equal to or greater than a critical integral concentration; In a depth direction of the semiconductor substrate, a distance between the second peak and a peak of the lifetime killer concentration in the first lifetime control region is greater than a distance between an upper end of the collector region and the peak of the lifetime killer concentration in the first lifetime control region. Semiconductor device.

15. a drift region of a first conductivity type provided in a semiconductor substrate; a buffer region of a first conductivity type provided closer to the back surface of the semiconductor substrate than the drift region and having a first peak of doping concentration and a second peak provided closer to the front surface of the semiconductor substrate than the first peak; a first lifetime control region provided between the first peak and the second peak in a depth direction of the semiconductor substrate; a collector region of a second conductivity type provided on a rear surface of the semiconductor substrate; Equipped with an integral concentration obtained by integrating a doping concentration in a direction from an upper end of the drift region to the second peak in a depth direction of the semiconductor substrate is equal to or greater than a critical integral concentration; The peak concentration of the lifetime killer concentration of the first lifetime control region is greater than the first peak doping concentration and less than the peak doping concentration of the collector region. Semiconductor device.

16. a drift region of a first conductivity type provided in a semiconductor substrate; a buffer region of a first conductivity type provided closer to the back surface of the semiconductor substrate than the drift region and having a first peak of doping concentration and a second peak provided closer to the front surface of the semiconductor substrate than the first peak; a first lifetime control region provided between the first peak and the second peak in a depth direction of the semiconductor substrate; Equipped with an integral concentration obtained by integrating a doping concentration in a direction from an upper end of the drift region to the second peak in a depth direction of the semiconductor substrate is equal to or greater than a critical integral concentration; The full width at half maximum of the peak of the lifetime killer concentration in the first lifetime control region is 0.5 μm or less. Semiconductor device.

17. The peak concentration of the lifetime killer concentration in the first lifetime control region is 1.0E15 cm －３ Above, 1.0E17cm －３ is less than or equal to The semiconductor device according to claim 1 .

18. A transistor section and a diode section are provided on the semiconductor substrate. The semiconductor device according to claim 1 .

19. The drift region includes a second lifetime control region located closer to the front surface of the semiconductor substrate than the first lifetime control region. The semiconductor device according to claim 1 .

20. The peak concentration of the lifetime killer in the second lifetime control region is smaller than the peak concentration of the lifetime killer in the first lifetime control region.

20. The semiconductor device according to claim 19.

21. a drift region of a first conductivity type provided in a semiconductor substrate; a first conductivity type buffer region provided on a back surface side of the semiconductor substrate relative to the drift region and having a plurality of peaks of doping concentration; Equipped with The buffer area is Among the multiple peaks of the buffer region, a first peak is provided on the back surface side of the semiconductor substrate; a sub-peak group that is located closer to the front surface side of the semiconductor substrate than the first peak and has one or more peaks of doping concentration; a first lifetime control region provided in the sub-peak group; having a position where an integral concentration obtained by integrating a doping concentration in a direction from an upper end of the drift region toward the rear surface side in a depth direction of the semiconductor substrate becomes a critical integral concentration is in the sub-peak group; One of the sub-peaks includes a position where the integrated concentration becomes a critical integrated concentration within a full width at half maximum range of the peak. Semiconductor device.

22. The peak position of the lifetime killer concentration in the first lifetime control region is 0.1 μm or more away from the position where the integral concentration becomes a critical integral concentration on the rear surface side. The semiconductor device according to claim 21.

23. The peak position of the lifetime killer concentration in the first lifetime control region is away from one peak position of the sub-peak group including the position where the integral concentration becomes a critical integral concentration by 0.1 μm or more on the back surface side. The semiconductor device according to claim 21.

24. The doping concentration of one of the sub-peaks is 3.0E15 cm －３ That's all. The semiconductor device according to claim 21.

25. One peak of the group of minor peaks is a second peak adjacent to the first peak on the front surface side. The semiconductor device according to claim 21.

26. The doping concentration of each of the sub-peaks is less than the doping concentration of the first peak.

26. The semiconductor device according to claim 21 .

27. The sub-peak group comprises a plurality of peaks, The doping concentration of the plurality of peaks of the sub-peak group decreases toward the front surface side. The semiconductor device according to claim 26.

28. providing a drift region of a first conductivity type in a semiconductor substrate; providing a buffer region of a first conductivity type on a back surface side of the semiconductor substrate relative to the drift region; providing a first lifetime control region in the buffer region; Equipped with the buffer region has a first peak of doping concentration and a second peak located closer to the front surface of the semiconductor substrate than the first peak; the first lifetime control region is provided between the first peak and the second peak in a depth direction of the semiconductor substrate, The dose of ions for forming the first lifetime control region is 0.1 to 10 times the dose of ions for forming the first peak. A method for manufacturing a semiconductor device.

29. The acceleration energy for forming the first lifetime control region is 50 keV or more and 2000 keV or less. The method for manufacturing a semiconductor device according to claim 28.

30. forming a collector region of a second conductivity type on a back surface of the semiconductor substrate; The dose of ions for forming the collector region is 2.0E13 / cm ２ Above, 5.0E13 / cm ２ is less than or equal to 30. The method for manufacturing a semiconductor device according to claim 28 or 29.

31. The dose of ions for forming the collector region is 10 times or more and 50 times or less than the dose of ions for forming the first peak. The method for manufacturing a semiconductor device according to claim 30.

32. The dose of ions for forming the collector region is 300 times or more and 500 times or less than the dose of ions for forming the first lifetime control region. The method for manufacturing a semiconductor device according to claim 30.

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