Image sensor and method of operation thereof

Abstract

To provide an image sensor and an operation method for the image sensor.SOLUTION: An image sensor includes a first pixel and a second pixel, each including at least one light sensing element and a switching element configured to transfer a charge generated in the light sensing element to a floating diffusion node. The first pixel and the second pixel include a pixel array connected to the same column line, and a row driver configured to provide a clamping control signal shifting from a first level to a second level lower than the first level to the switching element of the first pixel in a reading period of the second pixel.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an image sensor and a method for operating the image sensor, and more particularly to an image sensor for generating a pixel signal based on a plurality of pixels and a method for operating the image sensor. [Background technology]

[0002] Image sensors create two-dimensional or three-dimensional images of an object. Image sensors create images of the object using light-sensing elements that respond to the intensity of light reflected from the object. Complementary Metal-Oxide Semiconductor (CMOS) image sensors contain multiple light-sensitive pixels. The charge from each pixel is converted into a voltage to represent the image of the object. Summary of the Invention [Problem to be solved by the invention]

[0003] An object of the present disclosure is to provide an image sensor and an operating method of the image sensor that prevent a pixel signal output from a pixel from becoming excessively low. [Means for solving the problem]

[0004] In order to achieve the above-mentioned object, an image sensor according to the technical idea of ​​the present disclosure includes a pixel array including a first pixel and a second pixel, each including at least one photo-sensing element and a switching element configured to transfer a charge generated in the photo-sensing element to a floating diffusion node, the first pixel and the second pixel being connected to the same column line; and a row driver configured to provide a clamping control signal that transitions from a first level to a second level lower than the first level to the switching element of the first pixel during a read period of the second pixel.

[0005] In order to achieve the above object, an image sensor according to the technical idea of ​​the present disclosure includes a pixel array including a first pixel and a second pixel connected to the same column line, a row driver providing a control signal to the pixel array, a voltage generating circuit providing a driving voltage to the row driver to be used for driving the first pixel and the second pixel, a ramp signal generator generating a ramp signal, an analog-to-digital conversion circuit converting a pixel voltage received from the column line into a pixel data value based on the ramp signal, and a timing generator controlling operation points of the row driver, the ramp signal generator, and the analog-to-digital conversion circuit, wherein a clamping control signal of a first level and a clamping control signal of a second level lower than the first level are sequentially applied to a switching element of the first pixel during a read operation of the second pixel. Effect of the Invention

[0006] According to an image sensor and pixel array according to an exemplary embodiment of the present disclosure, pixel noise can be reduced by adjusting pixel signals output from column lines using the same pixels. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram illustrating an image sensor according to an exemplary embodiment of the present disclosure. [Diagram 2] 1 is a diagram illustrating a pixel array and an ADC according to an exemplary embodiment of the present disclosure. [Diagram 3] 11 is a graph illustrating a pixel reading operation. [Figure 4] 4 is a diagram illustrating a reading operation of an image sensor according to an exemplary embodiment of the present disclosure. [Figure 5A] FIG. 2 is a timing diagram illustrating signals in a pixel array during a read operation of an image sensor according to an exemplary embodiment of the present disclosure. [Figure 5B]FIG. 2 is a timing diagram illustrating signals in a pixel array during a read operation of an image sensor according to an exemplary embodiment of the present disclosure. [Figure 6] 1 is a diagram showing a WTA circuit. [Figure 7A] 4 is a diagram illustrating a reading operation of an image sensor according to an exemplary embodiment of the present disclosure. [Figure 7B] 4 is a diagram illustrating a reading operation of an image sensor according to an exemplary embodiment of the present disclosure. [Figure 7C] 4 is a diagram illustrating a reading operation of an image sensor according to an exemplary embodiment of the present disclosure. [Figure 8A] 1 is a diagram illustrating a pixel array according to an exemplary embodiment of the present disclosure. [Figure 8B] 4 is a diagram illustrating a reading operation of an image sensor according to an exemplary embodiment of the present disclosure. [Figure 9] 4 is a diagram illustrating a reading operation of an image sensor according to an exemplary embodiment of the present disclosure. [Figure 10A] 1 is a diagram illustrating clamping levels according to an exemplary embodiment of the present disclosure. [Figure 10B] FIG. 2 is a circuit diagram illustrating an implementation of a current source according to an exemplary embodiment of the present disclosure. [Figure 11] 1 illustrates an image sensor and a read operation of the image sensor according to an exemplary embodiment of the present disclosure. [Figure 12] 12 is a timing diagram illustrating signals in the pixel array during a read operation of the image sensor of FIG. 11. [Figure 13] 4 is a flowchart illustrating a method of operating an image sensor according to an exemplary embodiment of the present disclosure. [Figure 14] 1 is a block diagram illustrating an image processing system according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0009] FIG. 1 is a block diagram illustrating an image sensor according to an exemplary embodiment of the present disclosure.

[0010] The image sensor 100 is mounted on an electronic device having an image or light sensing function. For example, the image sensor 100 is mounted on electronic devices such as cameras, smartphones, wearable devices, Internet of Things (IoT) devices, home appliances, tablet PCs (Personal Computers), PDAs (Personal Digital Assistants), PMPs (Portable Multimedia Players), navigation systems, drones, and Advanced Driver Assistance Systems (ADAS). The image sensor 100 is also mounted on electronic devices provided as components in vehicles, furniture, manufacturing equipment, doors, various measuring instruments, and the like.

[0011] 1, the image sensor 100 includes a pixel array 110, a row driver 120 (e.g., a driving circuit), an analog-to-digital converter (ADC) 130 (e.g., an ADC conversion circuit), a ramp signal generator 160, a timing generator 170 (e.g., a signal generator), and a buffer 180 (e.g., a buffer circuit). The ADC 130 includes a comparison block 140 and a counter block 150 (e.g., a counter circuit).

[0012] The pixel array 110 includes a plurality of row lines ROW, a plurality of column lines COL, and a plurality of pixels 111 connected to the plurality of row lines ROW and column lines COL and arranged in a matrix form. Although FIG. 1 illustrates the pixel array 110 as including 16 pixels 111 arranged in 4 rows and 4 columns, this is for convenience of explanation, and the pixel array 110 may include a greater number of pixels.

[0013] Each of the row lines ROW extends in the row direction and is connected to the pixels 111 arranged in the same row. For example, three row lines ROW are connected to the pixels 111 arranged in the same row, and each row line ROW transmits a control signal output from the row driver 120 to a reset transistor, a transfer transistor, and a selection transistor, respectively, as described later with reference to FIG. 2. Each of the column lines COL extends in the column direction and is connected to the pixels 111 arranged in the same column. Each of the column lines COL outputs a pixel signal PXS to the ADC 130.

[0014] Each of the pixels 111 includes a light-sensing element (or photoelectric conversion element). For example, the light-sensing element includes a photodiode, a phototransistor, a photogate, or a buried photodiode. Each of the pixels 111 includes at least one light-sensing element, and in an embodiment, each of the pixels 111 may include multiple light-sensing elements. The multiple light-sensing elements may be disposed in the same layer or stacked in a perpendicular direction to each other.

[0015] A microlens for collecting light may be disposed on each of the pixels 111 or on each of pixel groups consisting of adjacent pixels 111. Each of the pixels 111 senses light of a specific spectral region from light received through the microlens. For example, the pixel array 110 includes a red pixel for converting light of a red spectral region into an electrical signal, a green pixel for converting light of a green spectral region into an electrical signal, and a blue pixel for converting light of a blue spectral region into an electrical signal. A color filter for transmitting light of a specific spectral region may be disposed on each of the pixels 111. However, the present invention is not limited thereto, and the pixel array 110 may include pixels for converting light of other spectral regions into electrical signals in addition to red, green, and blue.

[0016] In an embodiment, the pixels 111 may have a multi-layer structure, which includes stacked light-sensing elements that convert light in different spectral regions into electrical signals, and the electrical signals corresponding to different hues are generated from the light-sensing elements. In other words, electrical signals corresponding to multiple colors are output from one pixel 111.

[0017] The pixels 111 detect light using a light sensing element and convert it into a pixel signal PSX (e.g., a pixel voltage), which is an electrical signal. For example, when bright light is applied to the pixels 111, many electrons (photocharges) are emitted. The brighter the light, the lower the voltage value output from the light sensing element. If the output voltage value becomes too low, various noises such as band noise are generated.

[0018] The row driver 120 selects at least one row line ROW of the pixel array 110 according to a control signal (e.g., a row address signal) received from the timing generator 170. The pixels 111 connected to the selected row line ROW output a pixel signal PXS. For example, the pixel signal PXS may have any one of a voltage corresponding to a reset state, a voltage corresponding to a photocharge, and a clamping voltage.

[0019] The row driver 120 drives the pixel array 110 row by row to control the read operation of the pixels 111. Hereinafter, the read operation means an operation of resetting a pixel and outputting a pixel signal PXS having a magnitude corresponding to the amount of photocharge from the pixel. The row driver 120 controls the read operation of the pixel array 110 by outputting control signals to the multiple pixels 111 via multiple row lines ROW. A selected row in which a read operation is performed is designated as a read row, and the remaining rows are designated as non-read rows, the pixel in which a read operation is performed is designated as a read pixel, and the remaining pixels are designated as non-read pixels.

[0020] In this embodiment, when a read operation is performed on a pixel 111 of a read row, the row driver 120 controls the pixel 111 of an adjacent non-read row to operate as a clamping circuit. The clamping circuit can prevent the voltage of the column line COL, i.e., the level of the pixel signal PXS (e.g., pixel voltage) from dropping below a predetermined level. For example, when a read operation is performed on a pixel 111 of a third row R3 among the first to fourth rows R1 to R4 of the pixel array 110, the row driver 120 controls the pixel 111 of an adjacent non-read row, for example, the second row R2, to operate as a clamping circuit. In an embodiment, the pixel 111 of a row in which reading has been completed within one frame or a dummy row may operate as a clamping circuit. Hereinafter, in this disclosure, a pixel operating as a clamping circuit is referred to as a clamping pixel, and a row including a clamping pixel is referred to as a clamping row.

[0021] In an embodiment, the row driver 120 may provide a clamping control signal to the pixels 111 of a non-reading row. The row driver 120 provides the clamping control signal via a row line ROW coupled to the pixels 111 of a non-reading row. The clamping control signal may transition from a first level to a second level at a point in time when a read operation is performed on the pixels 111 of a selected row. At that time, the second level is lower than the first level, and the clamping control signal transitions from the first level to the second level in a reset counting period or before a charge transfer period among a plurality of sub-periods included in a read period.

[0022] When a read operation is performed on the pixels 111 of a selected row, the row driver 120 provides a transfer control signal to each of the pixels 111 of the selected row via a row line ROW connected to the pixels 111 of the selected row, and provides a clamping control signal to each of the pixels 111 of a non-read row via a row line connected to the pixels 111 of an adjacent non-read row.

[0023] In an embodiment, the transfer control signal and the clamping control signal may be input to a drive terminal of a charge transfer element, such as a gate terminal of a charge transfer transistor, in the pixel 111. For example, the transfer control signal may be input to a gate terminal of a transfer transistor in the pixel 111 of a selected row, and the clamping control signal may be input to a gate terminal of a transfer transistor in the pixel 111 of at least one non-reading row adjacent to the selected row.

[0024] The ramp signal generator 160 generates a ramp signal RAMP. The ramp signal RAMP may be a signal having a voltage that increases or decreases with a certain slope. The ramp signal generator 160 operates based on a ramp control signal provided by the timing generator 170. The ramp control signal includes a ramp enable signal, a mode signal, etc. When the ramp enable signal is activated, the ramp signal generator 160 generates a ramp signal having a slope that is set based on the mode signal.

[0025] The ADC 130 converts the pixel signal PXS received from the pixel array 110, i.e., an analog signal, into a digital signal. For example, the ADC 130 generates a result of comparing the pixel signal PXS with a ramp signal RAMP to effectively detect the difference between a reset signal and an image signal. The ADC 130 counts the signal output as the comparison result and converts it into a digital signal.

[0026] The comparison block 140 includes a plurality of comparison circuits 141, each of which compares a pixel signal PXS received via a corresponding column line COL with a ramp signal RAMP, and outputs a comparison result.

[0027] The comparison circuit 141 generates a comparison result signal to which a correlated double sampling technique is applied, and is called a correlated double sampling circuit. The pixel signals PXS output from the multiple pixels 111 have deviations due to pixel-specific characteristics (e.g., FPN (Fixed Pattern Noise) etc.) that each pixel has, and / or deviations due to differences in characteristics of logic for outputting pixel signals from the pixels 111. In order to compensate for such deviations between the pixel signals PXS, a reset component (or reset signal) and an image component (or image signal) are obtained for each pixel signal, and the difference between them is extracted as a valid signal component, which is called correlated double sampling. The comparison circuit 141 outputs a comparison result signal to which a correlated double sampling technique is applied.

[0028] The counter block 150 includes a plurality of counters 151. Each of the plurality of counters 151 is connected to an output terminal of the comparison circuit 141, and counts based on the output of the comparison circuit 141. The counter control signals received from the timing generator 170 include a counter clock signal, a counter reset signal for controlling a reset operation of the plurality of counters 151, and an inversion signal for inverting an internal bit of each of the plurality of counters 151. The counter block 150 counts the comparison result signal according to the counter clock signal, and outputs it as a digital value.

[0029] The buffer 180 includes a column memory block 181 and a sense amplifier 182, and the column memory block 181 includes a plurality of memories 183. Each of the plurality of memories 183 temporarily stores a digital signal, e.g., pixel data, output from each of the plurality of counters 151, and then outputs the digital signal to a sense amplifier 182, which senses and amplifies the digital signal output from the plurality of memories 183. The sense amplifier 182 outputs the amplified digital signal as image data IDTA.

[0030] The timing generator 170 generally controls the image sensor 100. For example, the timing generator 170 transmits control signals or clock signals to the row driver 120 and the ADC 130, respectively, to control the operations or timings of the row driver 120 and the ADC 130.

[0031] When excessive light is applied to the pixel array 110 and the output value of the pixel 111, i.e., the level of the pixel signal PXS, becomes too low, a phenomenon occurs in which a current source sinking a current from the column line COL to which the pixel 111 is connected disappears. When multiple current sources disappear in the same row, a change in current consumption and a resulting fluctuation in the power supply voltage occur, which causes band noise. However, as described above, the image sensor 100 according to the exemplary embodiment of the present disclosure can prevent the level of the pixel signal PXS from becoming too low because the row driver 120 operates the pixels of the non-read row as a clamping circuit. Therefore, the image sensor 100 according to the exemplary embodiment of the present disclosure can suppress the occurrence of band noise.

[0032] Also, without adding wiring or circuitry on the pixel array 110, when a read operation is performed on a selected pixel, a pixel in at least one unselected row can be utilized as a clamping pixel, so no additional circuit area or power consumption is required.

[0033] FIG. 2 is a diagram illustrating a pixel array and an ADC according to an exemplary embodiment of the present disclosure.

[0034] 2, the pixel array 110 includes a first pixel PX1 and a second pixel PX2 connected to the same column line COL. The first pixel PX1 and the second pixel PX2 may be located in different rows. For example, the first pixel PX1 and the second pixel PX2 may be located in adjacent rows. However, the present invention is not limited thereto, and at least one other pixel may be located between the first pixel PX1 and the second pixel PX2. For convenience of explanation, only one pixel is shown in each row, but as shown in FIG. 1, each row may include a plurality of other pixels. The pixel array 110 is driven in row units, and the operation of the other pixels is similar to the operation of the first pixel PX1 and the second pixel PX2.

[0035] 2, the first pixel PX1 and the second pixel PX2 each include reset transistors RX1, RX2, transfer transistors TX1, TX2, drive transistors DX1, DX2, selection transistors SX1, SX2, and photodiodes PD1, PD2. The reset transistors RX1, RX2, transfer transistors TX1, TX2, and selection transistors SX1, SX2 are turned on or off in response to a control signal received, and thus operate as switching elements. The photodiodes PD1, PD2 can be replaced with other light-sensing elements. A control signal is transmitted to the reset transistors RX1, RX2, transfer transistors TX1, TX2, and selection transistors SX1, SX2 of the first pixel PX1 and the second pixel PX2, respectively, through a plurality of row lines ROW (FIG. 1), where the plurality of row lines extend in the row direction on the pixel array 110 and are connected to pixels arranged in the same row.

[0036] The operation of the pixels PX1 and PX2 will be described with reference to the first pixel PX1 as an example. When a read operation is performed on the first pixel PX1, the photodiode PD1 generates photocharges that vary depending on the intensity of incident light. The transfer transistor TX1 transfers the photocharges to the floating diffusion node FD1 in response to a transfer control signal TG1 output from the row driver 120 (FIG. 1). For example, the transfer control signal TG1 may be applied to the gate terminal of the transfer transistor TX1. The drive transistor DX1 amplifies and transmits the photocharges to the selection transistor SX1 in response to a potential due to the photocharges accumulated in the floating diffusion node FD1. For example, the gate terminal of the drive transistor DX1 may receive a signal from the floating diffusion node FD1 having a voltage corresponding to the potential. The drain node of the selection transistor SX1 is connected to the source node of the drive transistor DX1. When the selection transistor SX1 is turned on in response to a selection signal SEL1 output from the row driver 120, an output signal V out is output. For example, the selection signal SEL1 may be output to the gate terminal of the selection transistor SX1. The reset transistor RX1 resets the floating diffusion node FD1 based on the power supply voltage VDD by the reset signal RS1 provided from the row driver 120. For example, the reset signal RS1 may be applied to the gate terminal of the reset transistor RX1 to apply the power supply voltage VDD to the floating diffusion node FD1.

[0037] Meanwhile, when the first pixel PX1 operates as a clamping pixel, a clamping control signal CG is applied to the transfer transistor TX1, and the voltage level of the floating diffusion node FD1 of the first pixel PX1 changes in response to the clamping control signal CG. For example, the clamping control signal may be applied to the gate terminal of the transfer transistor TX1. At that time, the voltage level of the floating diffusion node FD1 is determined based on the change in the level (voltage level) of the clamping control signal CG, regardless of the photocharges generated in the photodiode PD1. The selection transistor SX1 outputs an output signal VV1 having a level corresponding to the voltage level of the floating diffusion node FD1 in response to the selection signal SEL1. out Output.

[0038] A current source PL is connected to one end of the column line COL. The current source PL outputs a load current I L The current source PL is called the pixel load.

[0039] A pixel signal PXS output from the first pixel PX1 or the second pixel PX2 is provided to the ADC 130 via a column line COL. The ADC 130 includes a comparison circuit 141 (e.g., an operational amplifier) ​​and a counter 151 (e.g., a counting circuit). For convenience of explanation, one comparison circuit 141 and counter 151 connected to one column line COL are shown, but as described with reference to FIG. 1, the ADC 130 may include a plurality of comparison circuits 141 and a plurality of counters 151 connected to a plurality of column lines COL.

[0040] The comparison circuit 141 is implemented by at least one comparator. For example, the comparator may include a differential amplifier, an OTA (Operational Transconductance Amplifier), a source follower, etc. In an embodiment, a capacitor may be connected to two input terminals of the comparison circuit 141. The comparison circuit 141 compares the received pixel signal PXS and the ramp signal RAMP to generate a comparison result, and outputs the comparison result. The counter 151 counts the output V of the comparison circuit 141 based on a counting clock signal CCLK and an inverted signal CONV. comp to generate a counting result, and output the counting result as pixel data PXD. The pixel data PXD has an image component obtained by removing the reset component from the pixel signal PXS, that is, a digital value corresponding to the image signal.

[0041] FIG. 3 is a graph illustrating the read operation performed on a pixel.

[0042] The selection signal SEL, the reset signal RS, and the transfer control signal TG shown in Fig. 3 represent control signals applied to the pixels from which reading is to be performed. For example, it is assumed that a reading operation is to be performed from the first pixel PX1 in Fig. 2.

[0043] 2 and 3, before time t0, a high-level reset signal RS is applied to the reset transistor RX1, and the floating diffusion node FD1 is reset based on the power supply voltage VDD. For example, the voltage level of the floating diffusion node FD1 may be the same as the level of the power supply voltage VDD.

[0044] A read operation is performed from time t0 to time t10. When the read operation is performed, the selection signal SEL maintains a high level that turns on the selection transistor SX1, and the reset signal RS maintains a low level that turns off the reset transistor RX1.

[0045] The period from time t0 to time t1 is defined as an auto-zero period, and the period from time t1 to time t10 is defined as a comparison operation period. From time t0 to time t1, an auto-zero signal AZS is activated, and the comparison circuit 141 is initialized in response to the auto-zero signal AZS. For example, the input terminal and / or the output terminal of the comparator included in the comparison circuit 141 may have the same level. For reset counting, for example, counting the reset signals of the pixels, an offset is added to the ramp signal RAMP at time t2, and then the ramp signal RAMP is decreased from time t3. The counter 151 counts the output V of the comparison circuit 141 from time t3. comp Until the time t4 when the polarity of the output V comp From time t3 to time t4, the counting value CV increases.

[0046] When the reset counting is completed, an offset is added again to the ramp signal RAMP at time t5 for signal counting, e.g., counting the image signal of the pixel, and then the bit of the counting value CV is inverted at time t6 in response to the inversion signal CONV. At time t7, the transfer control signal TG transitions to a high level, and the transfer transistor TX1 is turned on in response to the transfer control signal TG to transfer the photocharge accumulated in the photo-sensing element PD to the floating diffusion node FD1. As a result, the pixel signal PXS representing the voltage level of the floating diffusion node FD1 drops.

[0047] From time t8, the ramp signal RAMP starts decreasing. From time t8, the voltage level of the ramp signal RAMP becomes the same as the voltage level of the pixel signal PXS, and the counter 151 starts decreasing the output V comp Until the time t9 when the polarity of the output V comp The counting value CV is output as pixel data PXD. When the signal counting is completed, the ADC 130 is initialized.

[0048] Meanwhile, in the present disclosure, an example in which a digital correlated double sampling technique is applied to the ADC 130 has been described, but the present invention is not limited thereto, and an analog correlated double sampling technique may also be applied.

[0049] 4 is a diagram illustrating a read operation of an image sensor according to an exemplary embodiment of the present disclosure. Figures 5A and 5B are timing diagrams illustrating signals of a pixel array during a read operation of an image sensor according to an exemplary embodiment of the present disclosure.

[0050] 4, a first pixel PX1 and a second pixel PX2 are arranged in different rows and connected to the same column line COL. When a read operation is performed on the second pixel PX2, the first pixel PX1 in the row adjacent to the row in which the second pixel PX2 is arranged operates as a clamping pixel, as described above with reference to FIG 1. At that time, the first pixel PX1 is a pixel that has been read or a dummy pixel.

[0051] The row driver 120 provides control signals to the first pixel PX1 and the second pixel PX2 through a plurality of row lines. For example, the row driver 120 may provide select signals SEL1, SEL2 and reset signals RS1, RS2 to the first pixel PX1 and the second pixel PX2, respectively. At that time, the same select signal SEL and reset signal RS may be provided to the first pixel PX1 and the second pixel PX2. The row driver 120 may provide a transfer control signal TG to the second pixel PX2 and a clamping control signal CG to the first pixel PX1.

[0052] The row driver 120 includes a first transmission driver TXD1 and a second transmission driver TXD2. The first transmission driver TXD1 and the second transmission driver TXD2 are realized by an amplifier, a buffer, an inverter, and the like.

[0053] The first transmission driver TXD1 generates a clamping control signal CG and transmits the clamping control signal CG to the first pixel PX1. The first transmission driver TXD1 generates a clamping reference signal S CLP is buffered or level converted to generate the clamping control signal CG.

[0054] The second transmission driver TXD2 generates a transfer control signal TG and transmits the transfer control signal TG to the second pixel PX2. The second transmission driver TXD2 generates a transfer reference signal S TX is buffered or level-converted to generate the transfer control signal TG.

[0055] Meanwhile, for convenience of explanation, the row driver 120 is illustrated as including a first transmission driver TXD1 and a second transmission driver TXD2, but is not limited thereto, and the row driver 120 may further include other transmission drivers for transmitting a selection signal SEL and a reset signal RS to the first pixel PX1 and the second pixel PX2, respectively.

[0056] 5A and 5B, the read section HP for one row includes an auto-zero section, a reset counting section, a signal transmission section, and a signal counting section.

[0057] At the beginning of the read period HP, the reset transistors RX1 and RX2 are turned on in response to the reset signal RS at an active level, for example, a high level, so that the power supply voltage VDD is applied to the floating diffusion nodes FD1 and FD2 of the first pixel PX1 and the second pixel PX2. As a result, the voltages VFD1 and VFD2 (hereinafter referred to as floating diffusion node voltages) of the floating diffusion nodes FD1 and FD2 are equal to the power supply voltage VDD. Thereafter, the reset signal RS transitions to an inactive level, for example, a low level, and the selection signal SEL transitions to an active level, for example, a high level. At that time, the clamping control signal CG is at a high level, for example, a first voltage level V1, and thereafter, the clamping control signal CG transitions to a low level, for example, a second voltage level V2.

[0058] The floating diffusion node FD1 of the first pixel PX1 has a parasitic capacitor C FD is formed, and a coupling capacitor Cc is formed between the floating diffusion node FD1 and the gate terminal of the transfer transistor TX1. When the clamping control signal CG applied to the gate terminal of the transfer transistor TX1 transitions from high level to low level, the floating diffusion node voltage VFD1 drops due to the coupling capacitor Cc. At that time, the floating diffusion node voltage VFD1 is determined based on the voltage change of the clamping control signal CG. The voltage change amount ΔVFD1 of the floating diffusion node voltage VFD1 is proportional to the voltage change amount ΔVCLP of the clamping control signal CG, for example, the difference between the first voltage level V1 and the second voltage level V2, and the parasitic capacitor C FD and the capacitance of the coupling capacitor Cc. The voltage change amount ΔVFD1 of the floating diffusion node voltage VFD1 is expressed by the following formula (1).

[0059]

number

[0060] Meanwhile, during the signal transmission period, the transfer control signal TG is at an active level, for example, a high level, and the transfer transistor TX2 of the second pixel PX2 is turned on in response to the transfer control signal TG to transfer the photocharges generated in the photodiode PD2 to the floating diffusion node FD2. As a result, the floating diffusion node voltage VFD2 of the second pixel PX2 is lowered. Since the selection transistors SX1 and SX2 of the first pixel PX1 and the second pixel PX2 are both turned on, the floating diffusion node voltages VFD1 and VFD2 of the first pixel PX1 and the second pixel PX2 are output to the column line COL. At that time, the output voltage V out That is, the pixel signal PXS (FIG. 2) is determined based on the higher voltage of the floating diffusion node voltages VFD1 and VFD2. This will be described with reference to FIG.

[0061] Figure 6 shows the winner takes all circuit (WTA) circuit.

[0062] 6, the two transistors TR1 and TR2 shown in the figure correspond to the drive transistor DX included in the pixel of the present disclosure. For example, the first transistor TR1 and the second transistor TR2 correspond to the first drive transistor DX1 included in the first pixel PX1 and the second drive transistor DX2 included in the second pixel PX2, respectively. For convenience of explanation, the following description will be given assuming that the first transistor TR1 and the second transistor TR2 are implemented using NMOS.

[0063] When the first gate voltage VG1 is higher than the second gate voltage VG2, the voltage applied to the common node CN is equal to the first gate voltage VG1 minus the gate-source voltage Vgs. That is, VG1-Vgs=VCN. When the first gate voltage VG1 is higher than the second gate voltage VG2, the bias current Io is based on the first current I1 and is not related to the second current I2. Therefore, only the transistor with a high gate voltage level operates, and the transistor with a low gate voltage level does not operate. This is also called a WTA circuit (winner takes all circuit). For example, referring to FIG. 6 and FIG. 4, the principle of applying a voltage to the common node CN in FIG. 6 is similar to the principle of applying a voltage to the column line COL in FIG. 4. In that case, the first gate voltage VG1 and the second gate voltage VG2 in FIG. 6 correspond to the voltage VFD1 of the first floating diffusion node FD1 and the voltage VFD2 of the second floating diffusion node FD2 in FIG. 4, respectively. Therefore, the higher of the floating diffusion node voltages VFD1 and VFD2 is output to the column line COL. out corresponds to the higher of the floating diffusion node voltages VFD1 and VFD2.

[0064] 5A and 5B, before the signal transmission section, the floating diffusion node voltage VFD1 of the first pixel PX1 is equal to or lower than the floating diffusion node voltage VFD2 of the second pixel PX2. Therefore, the floating diffusion node voltage VFD2 of the second pixel PX2 is equal to or lower than the output voltage V out will be output as:

[0065] Thereafter, as shown in FIG. 5A, if the floating diffusion node voltage VFD2 of the second pixel PX2 becomes too low (e.g., close to 0V) during the signal transmission period, and the floating diffusion node voltage VFD1 of the first pixel PX1 is higher than the floating diffusion node voltage VFD2 of the second pixel PX2 during the signal counting period, the floating diffusion node voltage VFD1 of the first pixel PX1 becomes lower than the output voltage V out Therefore, the output voltage V out is prevented from becoming excessively low.

[0066] Meanwhile, as shown in FIG. 5B, during the signal counting period, if the floating diffusion node voltage VFD2 of the second pixel PX2 is higher than the floating diffusion node voltage VFD1 of the first pixel PX1, the floating diffusion node voltage VFD2 of the second pixel PX2 becomes the output voltage V out will be output as:

[0067] On the other hand, the floating diffusion node voltage VFD1 of the first pixel PX1 is lower than the lower limit of the input range of the comparison circuit 141 (FIG. 2). Therefore, when the floating diffusion node voltage VFD2 of the second pixel PX2 is within the input range of the comparison circuit 141 (FIG. 2) (e.g., FIG. 5B), the floating diffusion node voltage VFD2 of the second pixel PX2 is provided to the comparison circuit 141 (FIG. 2) as the pixel signal PXS, and the pixel data value of the second pixel PX2 is read.

[0068] If the floating diffusion node voltage VFD2 of the second pixel PX2 becomes too low and deviates from the input range of the comparison circuit 141 (FIG. 2), the pixel data value of the second pixel PX2 is output as the highest value. At that time, if the floating diffusion node voltage VFD2 of the second pixel PX2 does not operate normally, band noise will occur. However, as described above, even if the floating diffusion node voltage VFD2 of the second pixel PX2 becomes too low, the first pixel PX1 operates as a clamping circuit (e.g., FIG. 5A), and the output voltage V out This prevents the output voltage V from becoming too low, thus blocking noise generation. out The lower limit value of V FD1 is set as a clamping level, and the clamping level can be determined by the floating diffusion node voltage VFD1 of the first pixel PX1.

[0069] In this manner, when a read operation is performed on a read pixel of a read row, the image sensor according to the exemplary embodiment of the present disclosure can use the adjacent pixels of the non-read row as a clamping circuit by providing a clamping control signal to the gate terminal of the transfer transistor included in each of the pixels of the non-read row, thereby using the adjacent pixels of the non-read row as a clamping circuit without additional wiring or circuitry, thereby suppressing noise generation without additional circuit area or power consumption.

[0070] 7A, 7B, and 7C are diagrams illustrating a read operation of an image sensor according to an exemplary embodiment of the present disclosure. In FIG. 7A, 7B, and 7C, it is assumed that the n-th row Rn is a read row. Although FIG. 7A, 7B, and 7C show that one pixel is arranged in each of rows Rn-2 to Rn+2, this is for convenience of explanation, and as shown in FIG. 1, multiple pixels may be arranged in each of rows Rn-2 to Rn+2, and the same control signal may be applied to multiple pixels arranged in the same row.

[0071] 7A, 7B and 7C, when a read operation is performed on pixels in a read row, i.e., the nth row Rn, pixels in a non-read row connected to the same column line COL as the read pixel act as a clamping pixel. In an embodiment, the clamping row may be a row where reading has been completed.

[0072] 7A, the non-read row closest to the read row may act as the clamping row. For example, when the nth row Rn is the read row, the n-1th row Rn-1, which is the non-read row closest to the nth row Rn and has been read, may act as the clamping row.

[0073] The n-th transmission driver TXDn in the row driver 120 transmits a transfer control signal TG to the pixel PX of the n-th row Rn, and the n-1-th transmission driver TXDn-1 transmits a clamping control signal CG to the pixel PX of the n-1-th row Rn-1. As described with reference to Figures 5A and 5B, the clamping control signal CG transitions from a high level to a low level before the signal transmission period, and the transfer control signal TG is at a high level during the signal transmission period of the read period HP and at a low level during the remaining period.

[0074] 7B, at least one of the non-read rows adjacent to the read row may act as a clamping row. In some embodiments, as shown in FIG. 7B, another non-read row may be disposed between the read row and the clamping row. For example, when the nth row Rn is a read row, the n-2th row Rn-2 may act as a clamping row.

[0075] The n-th transmission driver TXDn in the row driver 120 transmits a transfer control signal TG to the pixels PX in the n-th row Rn, and the n-2-th transmission driver TXDn-2 transmits a clamping control signal CG to the pixels PX in the n-2-th row Rn-2.

[0076] 7C, multiple non-read rows may act as clamping rows. For example, the n-2th row Rn-2 and the n-1st row Rn-1 before the nth row Rn, which is a read row, may act as clamping rows. However, the present invention is not limited thereto, and three or more rows may act as clamping rows.

[0077] The nth transmission driver TXDn provided in the row driver 120 transmits a transfer control signal TG to the pixels PX of the nth row Rn, and the n-2th transmission driver TXDn-2 and the n-1st transmission driver TXDn-1 transmit a clamping control signal CG to the pixels PX of the n-2th row Rn-2 and the n-1st row Rn-1, respectively.

[0078] FIG. 8A shows a pixel array according to an exemplary embodiment of the present disclosure, and FIG. 8B is a diagram illustrating a read operation of an image sensor according to an exemplary embodiment of the present disclosure.

[0079] 8A, the pixel array 110a includes an effective pixel area VPA and a non-effective pixel area NVPA. Each of the effective pixel area VPA and the non-effective pixel area NVPA includes a plurality of rows. Although FIG. 8A illustrates the non-effective pixel area NVPA being located at the top and bottom of the pixel array 110a, the non-effective pixel area NVPA may be located at the top or bottom, or between a plurality of effective pixel areas VPA.

[0080] The image sensor generates image data based on pixel signals output from the pixels in the effective pixel area VPA, and pixel signals output from the pixels in the non-effective pixel area NVPA are used for various purposes such as characteristic analysis of the pixel array 110a, noise removal, and data correction.

[0081] 8B, a row of the non-effective pixel area NVPA, for example, a dummy row Rdm, may be used as a clamping row. When a read operation is performed on the pixels PX of the n-th row Rn, the dummy row Rdm may be used as a clamping row. Also, when a read operation is performed on other rows of the effective pixel area VPA, for example, the n-1th row Rn-1, the n+1th row Rn+1, and the n+2th row Rn+2, at least one dummy row Rdm may be used as a clamping row.

[0082] In an embodiment, as shown in FIG. 8A, when non-effective pixel areas NVPA are located at the top and bottom of pixel array 110a and a read operation is performed on a row of effective pixel area VPA, among a plurality of dummy rows Rdm included in the non-effective pixel areas NVPA at the top and bottom, a dummy row that is closest to the read row may operate as a clamping row. The dummy row Rdm may include a dummy pixel PXdm. In an exemplary embodiment, the dummy pixel PXdm does not output a pixel signal PXS.

[0083] FIG. 9 is a diagram illustrating a read operation of an image sensor according to an exemplary embodiment of the present disclosure.

[0084] 9, when a read operation is performed on the second pixel PX2, the first pixel PX1 operates as a clamping pixel. The first transmission driver TXD1 included in the row driver 120 transmits a clamping control signal CG to the first pixel PX1. At that time, the first transmission driver TXD1 transmits a first clamping voltage VH CLP and the second clamping voltage VL CLP It operates based on the first clamping voltage VH CLP is the second clamping voltage VL CLP The first transmission driver TXD1 receives the clamping reference signal S CLP , the first clamping voltage VH CLP or the second clamping voltage VL CLPThe clamping control signal CG is generated by amplifying (buffering or level converting) the clamping control signal CG based on the first clamping voltage VH CLP The low level is the same as or similar to the voltage level of the second clamping voltage VL CLP The voltage level is the same as or similar to that of

[0085] The second transmission driver TXD2 is connected to the first transmission voltage VH TX and the second transfer voltage VL TX The first transfer voltage VH TX is the second transfer voltage VL TX The second transmission driver TXD2 is connected to the transmission reference signal S TX , the first transfer voltage VH TX or the second transfer voltage VL TX Therefore, the high level of the transfer control signal TG is amplified (buffered or level converted) based on the first transfer voltage VH TX The low level is the same as or similar to the voltage level of the second transfer voltage VL TX The voltage level is the same as or similar to that of

[0086] On the other hand, when a read operation is performed on the first pixel PX1, the first transmission driver TXD1 supplies the first transfer voltage VH TX and the second transfer voltage VL TX and transmits the transfer control signal TG to the first pixel PX1. When the second pixel PX2 operates as a clamping pixel, the second transmission driver TXD2 generates the transfer control signal TG based on the first clamping voltage VH CLP and the second clamping voltage VL CLP and transmits the clamping control signal CG to the second pixel PX2.

[0087] In an embodiment, the image sensor may include a voltage generator 190, which generates a first clamping voltage VH CLP , the second clamping voltage VL CLP, first transfer voltage VH TX and the second transfer voltage VL TX and provides these voltages to the row driver 120. The voltage generator 190 generates a first clamping voltage VH CLP , the second clamping voltage VL CLP , first transfer voltage VH TX and the second transfer voltage VL TX , and based on the received voltage control signal, generate a first clamping voltage VH CLP , the second clamping voltage VL CLP , first transfer voltage VH TX and the second transfer voltage VL TX The voltage level may be varied.

[0088] In the embodiment, the first clamping voltage VH CLP and the first transfer voltage VH TX is the same, and the second clamping voltage VL CLP and the second transfer voltage VL TX For example, the first clamping voltage VH CLP and the first transfer voltage VH TX is the analog power supply voltage of the image sensor, and the second clamping voltage VL CLP and the second transfer voltage VL TX is the ground voltage.

[0089] In another embodiment, the first clamping voltage VH CLP and the first transfer voltage VH TX are different, or the second clamping voltage VL CLP and the second transfer voltage VL TX may be different.

[0090] On the other hand, the first clamping voltage VH CLP and the second clamping voltage VL CLPThe voltage difference between this corresponds to the voltage change amount ΔVCLP of the clamping control signal CG, and as described with reference to Equation (1), the voltage change amount ΔVFD1 of the floating diffusion node voltage VFD1 of the first pixel PX1 is proportional to the voltage change amount ΔVCLP of the clamping control signal CG, and the voltage change amount ΔVFD1 of the floating diffusion node voltage VFD1 of the first pixel PX1 determines the clamping level. Therefore, if the voltage change amount ΔVCLP of the clamping control signal CG increases, the clamping level decreases, and if the voltage change amount ΔVCLP of the clamping control signal CG decreases, the clamping level increases. The voltage generator 190 controls the first clamping voltage VH to generate a target clamping level based on the received voltage control signal. CLP and the second clamping voltage VL CLP Adjust the voltage level of

[0091] 10A is a diagram illustrating clamping levels according to an exemplary embodiment of the present disclosure, and FIG 10B is a circuit diagram illustrating an example of a current source according to an exemplary embodiment of the present disclosure.

[0092] Referring to FIG. 10A, the lowest value of the column line COL, i.e., the clamping level V CLP may be determined taking into consideration the input range of the comparison circuit 141 and the operating range of the current source PL. The input range of the comparison circuit 141 may be between the first input voltage VinH and the second input voltage VinL. At that time, the clamping level V CLP is set lower than the input range of the comparison circuit 141, the comparison circuit 141 receives the pixel signal PXS from the read pixel.

[0093] Meanwhile, the current source PL may be realized by a bias transistor TRb and an enable transistor TRen connected in series. When the enable transistor TRen is turned on in response to an enable signal Ven, the bias transistor TRb sinks a current based on a bias voltage Vb. For example, the enable signal Ven is applied to the gate terminal of the enable transistor TRen, and the bias voltage Vb is applied to the gate terminal of the bias transistor TRb. At that time, if the voltage of the column line COL is lower than the minimum operating voltage of the current source PL, i.e., the voltage required for the current source PL to operate normally, the current source PL cannot operate normally. The minimum operating voltage of the current source PL is also the voltage Vds between the drain and source of the bias transistor TRb. At that time, the voltage between the drain and source of the enable transistor TRen is approximately close to 0V. Therefore, the clamping level V, which is the minimum voltage level of the column line COL, CLP is set higher than Vds.

[0094] In an embodiment, the current source PLa may be realized by at least two bias transistors TRb1 and TRb2 and an enable transistor TRen connected in series, as shown in FIG. 10B. The minimum operating voltage of the current source PLa may be 2*Vds′, which is the sum of the drain-source voltages of the two bias transistors TRb1 and TRb2. Therefore, the clamping level V, which is the minimum voltage level of the column line COL, may be 2*Vds′. CLP is set higher than 2*Vds'.

[0095] As described with reference to FIGS. 10A and 10B, the clamping level V CLP is set lower than the input range of the comparison circuit 141 and higher than the operating voltage of the current source PL.

[0096] 11 is a diagram illustrating an image sensor and a read operation of the image sensor according to an exemplary embodiment of the present disclosure, and FIG 12 is a timing diagram illustrating signals of a pixel array during a read operation of the image sensor of FIG 11.

[0097] 11, the image sensor 100c includes a pixel array 110c, a row driver 120c, and a signal generator 171. In the embodiment, the signal generator 171 is included in the timing generator 170. However, the present invention is not limited thereto, and the signal generator 171 may be realized as a circuit separate from the timing generator 170. The image sensor may further include other components described with reference to FIG.

[0098] A pixel 111c, for example, a first pixel PX1, included in the pixel array 110c includes a plurality of photo-sensing elements PD11, PD12, PD13, and PD14, a plurality of transfer transistors TX11, TX12, TX13, and TX14, a reset transistor RX1, a driving transistor DX1, and a selection transistor SX1. The plurality of transfer transistors TX11, TX12, TX13, and TX14 are respectively connected to the plurality of photo-sensing elements PD11, PD12, PD13, and PD14, and are commonly connected to the driving transistor DX1. Such a structure in which the plurality of photo-sensing elements PD11, PD12, PD13, and PD14 are connected to one driving transistor is called a multi-share structure.

[0099] FIG. 11 illustrates pixel 111c as having four photo-sensing elements PD11, PD12, PD13, and PD14 and four transfer transistors TX11, TX12, TX13, and TX14, but is not limited thereto and the number of photo-sensing elements and transfer transistors may vary.

[0100] When the second pixel PX2 is read, the first pixel PX1 operates as a clamping pixel. A reset signal RS is applied to the reset transistors RX1 and RX2 of the first pixel PX1 and the second pixel PX2, respectively, and a selection signal SEL is applied to the selection transistors SX1 and SX2. A transfer control signal TG is applied to the multiple transfer transistors TX21, TX22, TX23, and TX24 of the second pixel PX2. In an embodiment, the transfer control signal TG may be applied to some of the multiple transfer transistors TX21, TX22, TX23, and TX24 of the second pixel PX2.

[0101] A clamping control signal CG is applied to at least one of the transfer transistors TX11, TX12, TX13, and TX14 of the first pixel PX1, and a blocking control signal OFF is applied to the other transfer transistors. In FIG. 11, the clamping control signal CG is applied to the first and second transfer transistors TX11 and TX12 of the first pixel PX1, and the blocking control signal OFF is applied to the third and fourth transfer transistors TX13 and TX14 of the first pixel PX1, but the present invention is not limited thereto. The clamping signal CG may be applied to at least one transfer transistor, and the clamping control signal CG may be applied to all of the transfer transistors TX21, TX22, TX23, and TX24, for example. The blocking control signal OFF may have a certain level when a read operation is performed for the first pixel PX1. In an embodiment, the level of the blocking control signal OFF may be the same as the low level of the clamping control signal CG.

[0102] The multiple transfer transistors TX11, TX12, TX13, and TX14 share the floating diffusion node FD1. Therefore, when the first pixel PX1 is used as a clamping pixel, the voltage change amount of the floating diffusion node voltage VFD1 varies based on the number of transfer transistors to which the clamping control signal CG is applied among the multiple transfer transistors TX11, TX12, TX13, and TX14. In other words, the low level of the floating diffusion node voltage VFD1 varies.

[0103] 12, the voltage change amount of the floating diffusion node voltage VFD1 is proportional to the number of transfer transistors to which the clamping control signal CG is applied. For example, when the clamping control signal CG is applied to one transfer transistor and the cutoff control signal OFF is applied to the other transfer transistor, in other words, when one transfer transistor is used for clamping, the voltage change amount of the floating diffusion node voltage VFD1 is represented as ΔVFD11. When two transfer transistors are used for clamping, the voltage change amount of the floating diffusion node voltage VFD1 is 2*ΔVFD11, when three transfer transistors are used for clamping, the voltage change amount of the floating diffusion node voltage VFD1 is 3*ΔVFD11, and when four transfer transistors are used for clamping, the voltage change amount of the floating diffusion node voltage VFD1 is 4*ΔVFD11. In other words, as the number of transfer transistors used for clamping in the clamping pixel, for example, the first pixel PX1, increases, the voltage change amount of the floating diffusion node voltage VFD1 also increases. out The lower limit value, for example the clamping level, becomes lower.

[0104] 11, the row driver 120c includes a first driver 121 for driving the row in which the first pixel PX1 is located, i.e., the clamping row, and a second driver 122 for driving the row in which the second pixel PX2 is located, i.e., the read row. The first driver 121 includes first through fourth transmission drivers TXD11, TXD12, TXD13, and TXD14 for driving the first through fourth transfer transistors TX11, TX12, TXD13, and TXD14, respectively. For example, each of the driving first through fourth transmission drivers TXD11, TXD12, TXD13, and TXD14 may be realized by an operational amplifier. The first through fourth transmission drivers TXD11, TXD12, TXD13, and TXD14 are driven by a clamping reference signal S provided from a signal generator 171. CLP or the cutoff reference signal S OFF is buffered or level converted to generate the clamping control signal CG and the cutoff control signal OFF.

[0105] The signal generator 171 generates input signals, such as a clamping reference signal S, provided to the first through fourth transmission drivers TXD11, TXD12, TXD13, and TXD14. CLP or the cutoff reference signal S OFF and generates a clamping reference signal S CLP This adjusts the number of transfer transistors used for clamping in the clamping pixel, for example, the first pixel PX1.

[0106] In this embodiment, when a pixel has a multi-share structure, the image sensor can adjust the clamping level by adjusting the number of transfer transistors used for clamping. Also, this embodiment may be combined with a method of adjusting the clamping level by adjusting the first and second levels of the clamping control signal CG, as described above with reference to FIG.

[0107] 13 is a flowchart showing a method of operating an image sensor according to an exemplary embodiment of the present disclosure. The method of operating an image sensor in FIG. 13 is performed in the image sensor 100, 100c in FIG. 1 or FIG. 12, and therefore the above-described method of operating an image sensor is applied to this embodiment.

[0108] 13 shows a method of using a first pixel connected to the same column line as the second pixel as a clamping pixel when the image sensor performs a read operation on the second pixel, where the first pixel and the second pixel are disposed in different rows, and in an embodiment, the first pixel is a pixel that has been read and is adjacent to the second pixel or a dummy pixel.

[0109] 13, a plurality of pixels in a pixel array are reset in response to a reset signal (S110), and then a read operation is performed on the pixel array row by row.

[0110] During the reset counting period, a clamping control signal decreasing from a first level to a second level is applied to the first pixel via a first row line (S120). The clamping control signal may be applied to a gate terminal of a transfer transistor of the first pixel. A parasitic capacitor between the gate terminal of the transfer transistor and the floating diffusion node decreases the voltage level of the floating diffusion node of the first pixel. The voltage change amount of the floating diffusion node voltage varies based on the difference between the first level and the second level. For example, as the difference between the first level and the second level increases, the voltage change amount of the floating diffusion node voltage increases, and thus the floating diffusion node voltage becomes lower. The floating diffusion node voltage of the first pixel is lower than the input range of the comparator 141 (FIG. 2) of the ADC and higher than a voltage (e.g., the sum of the voltages between the source and drain of the transistors included in the current source) for the current source PL (FIG. 2) connected to the column line to operate normally.

[0111] Thereafter, during a signal transmission period, a transfer control signal of an active level is applied to the second pixel via the second row line, and the transfer transistor of the second pixel is turned on in response to the transfer control signal (S130). At this time, the active level of the transfer control signal may be the same as or different from the first level of the clamping control signal.

[0112] The higher of the output voltage of the first pixel and the output voltage of the second pixel is output as a pixel signal through the column line (S140). The output voltage of the pixel means the floating diffusion node voltage of the pixel. Thus, the pixel signal is determined based on the higher of the floating diffusion node voltage of the first pixel and the floating diffusion node voltage of the second pixel. Before the signal transmission section, the floating diffusion node voltage of the second pixel is higher than or equal to the floating diffusion node voltage of the first pixel. Thus, the floating diffusion node voltage of the second pixel is output as a pixel signal. Thereafter, during the signal transmission section, photocharges generated in the photo-sensing element flow into the floating diffusion node of the second pixel, thereby decreasing the floating diffusion node voltage of the second pixel. When the floating diffusion node voltage of the second pixel becomes excessively low and is lower than the floating diffusion node voltage of the first pixel, the floating diffusion node voltage of the first pixel is output as a pixel signal, thereby blocking band noise that occurs when the pixel signal becomes excessively low.

[0113] FIG. 14 is a block diagram illustrating an image processing system according to an exemplary embodiment of the present disclosure.

[0114] Referring to FIG. 14, an image processing system 400 according to an exemplary embodiment of the present disclosure includes an image sensor 100, an image processor 200, a display unit 500, and a lens 320.

[0115] The image sensor 100 includes a pixel array 110, a row driver 120, an ADC 130, a ramp signal generator 160, a timing generator 170, a control register block 195, and a buffer 180.

[0116] The image sensor 100 senses an object 310 captured through a lens 320 under the control of the image processor 200, and the image processor 200 outputs an image sensed and output by the image sensor 100 to the display unit 500. In this case, the display unit 500 includes all devices capable of outputting an image. For example, the display unit 500 may include a computer, a mobile phone, and other image output terminals.

[0117] The image processor 200 includes a camera controller 201, an image signal processor 202, and a PC I / F 203. The camera controller 201 controls the control register block 195. For example, the camera controller 201 may control the image sensor 100, i.e., the control register block 195, using an I2C (Inter-Integrated Circuit). However, the present invention is not limited thereto, and various interfaces may be applied between the camera controller 201 and the control register block 195.

[0118] The image signal processor 202 receives the image data IDTA, which is the output signal of the buffer 180, processes the image so that it looks good, and outputs the processed image to the display unit 500. Alternatively, the image signal processor 202 receives a control signal from an external host via the PC I / F 203, and provides the processed image to the external host.

[0119] 1 and 12 is applied as the image sensor 100. The control register block 195 outputs control signals to the ramp signal generator 160, the timing generator 170, the buffer 180, and the voltage generator 190 to control their operations. At this time, the control register block 195 may operate under the control of the camera controller 201.

[0120] The pixel array 110, the row driver 120, the ADC 130, the timing generator 170, the buffer 180, the ramp signal generator 160, and the voltage generator 190 have been described in detail with reference to the drawings, and therefore will not be described again. When a read operation is performed in the pixel array 110, a pixel in a non-read row adjacent to a read row is used as a clamping pixel, i.e., a clamping circuit. Also, before a signal transmission section, a clamping signal that decreases from a first level to a second level is applied to a gate terminal of a transfer transistor of the clamping pixel, and the floating diffusion node voltage decreases with the decrease in the clamping signal due to a parasitic capacitor between the gate terminal of the transfer transistor and the floating diffusion node. The voltage level of the floating diffusion node voltage is used as a clamping level. If the plotting diffusion node voltage of the read pixel becomes too low, the floating diffusion node voltage of the clamping pixel is output as a pixel signal. This prevents the pixel signal from becoming excessively low, and suppresses the occurrence of band noise.

[0121] As above, exemplary embodiments have been disclosed in the drawings and the specification. In this specification, the embodiments have been described using specific terms, but these terms are merely used for the purpose of describing the technical ideas of the present disclosure, and are not used to limit the meaning or the scope of the present disclosure described in the claims. Therefore, a person having ordinary skill in the art can understand that various modifications and equivalent other embodiments are possible. Therefore, the true technical scope of protection of the present disclosure must be determined by the technical ideas of the claims. [Industrial Applicability]

[0122] The present invention is applicable, for example, to image generation related technical fields. [Explanation of symbols]

[0123] 100 Image Sensor 110 pixel array 111 pixels 120 Row Driver 130 ADC 140 Comparison Block 141 Comparison circuit 150 Counter Block 151 Counter 160 Ramp Signal Generator 170 Timing Generator 180 buffers 181 column memory block 182 Sense Amplifier 183 Memory COL Column Line IDTA Image Data PXS Pixel signal RAMP Ramp signal ROW

Claims

1. a pixel array including a first pixel and a second pixel, each pixel including at least one light sensing element and a charge transfer transistor configured to transfer a charge generated in the light sensing element to a floating diffusion node, the first pixel and the second pixel being connected to the same column line; a row driver configured to provide a clamping control signal that transitions from a first level to a second level lower than the first level to a first charge transfer transistor that is the charge transfer transistor of the first pixel during a reset counting period of a read period of the second pixel; the read section includes, in this order, a reset counting section for counting a reset signal, a signal transmission section for transferring the charge from the light sensing element to the floating diffusion node, and a signal counting section for counting an image signal; The image sensor according to claim 1, wherein the row driver is configured to provide a transfer control signal of an active level to a second charge transfer transistor, which is the charge transfer transistor of the second pixel, during the signal transmission period.

2. 2. The image sensor of claim 1, wherein the pixel voltage output from the column line is determined based on a relatively higher voltage among a voltage of a first floating diffusion node which is the floating diffusion node of the first pixel and a voltage of a second floating diffusion node which is the floating diffusion node of the second pixel.

3. The image sensor described in Claim 2, characterized in that the second charge transfer transistor is turned on in response to the transfer control signal of a third level after the clamping control signal transitions to the second level, and transfers the charge generated in the photo-sensing element to the second floating diffusion node of the second pixel.

4. 4. The image sensor of claim 3, wherein the first level and the third level are the same.

5. The row driver includes: a first transmission driver that generates the clamping control signal based on the first voltage of the first level and the second voltage of the second level, and outputs the clamping control signal to a first row line connected to the first pixel; a second transmission driver that generates the transfer control signal based on a third voltage of the third level and a fourth voltage of a fourth level lower than the third level, and outputs the transfer control signal to a second row line connected to the second pixel; 4. The image sensor of claim 3, wherein the first level and the third level are different from each other.

6. 2. The image sensor of claim 1, wherein a voltage of a first floating diffusion node, which is the floating diffusion node of the first pixel, is decreased based on a difference between the first level and the second level of the clamping control signal.

7. Each of the first pixel and the second pixel is a plurality of light-sensing elements; and a plurality of charge transfer transistors configured to transfer charge generated by each of the plurality of light-sensing elements to the floating diffusion node; The row driver includes:

2. The image sensor of claim 1, further comprising: a clamping control signal provided to at least one of the plurality of charge transfer transistors of the first pixel.

8. The row driver includes:

8. The image sensor of claim 7, further comprising: a blocking control signal having a constant level being transmitted to at least one other switching element of the plurality of charge transfer transistors of the first pixel.

9. 2. The image sensor of claim 1, wherein the first pixel and the second pixel are arranged in different rows, and the first pixel is arranged in a row closest to the row in which the second pixel is arranged.

10. The image sensor of claim 1 , wherein the first pixel is a dummy pixel provided in a non-effective pixel area of ​​the pixel array.

11. The pixel array comprises: a third pixel connected to the same column line as the first pixel and the second pixel, 2. The image sensor of claim 1, wherein the row driver provides the clamping control signal to the first charge transfer transistor of the first pixel and a third charge transfer transistor which is a charge transfer transistor of the third pixel during the reset counting period of the read period of the second pixel.

12. a current source coupled to the column line for sinking a load current from the column line; a comparator for comparing a pixel voltage output from the column line with a ramp signal and outputting a comparison result; 2. The image sensor of claim 1, wherein a voltage of a first floating diffusion node of the first pixel is lowered to a clamping level in response to the clamping control signal, the clamping level being lower than a lower limit of an input range of the comparator and higher than an operating voltage of the current source.

13. a pixel array including a first pixel and a second pixel coupled to a same column line, each of the first pixel and the second pixel including a charge transfer transistor configured to transfer a charge generated in a photo-sensing element to a floating diffusion node; a row driver for providing control signals to the pixel array; a voltage generating circuit for providing the row driver with a driving voltage used to drive the first pixel and the second pixel; a ramp signal generator for generating a ramp signal; an analog-to-digital conversion circuit that converts pixel voltages received from the column lines into pixel data values ​​based on the ramp signal; a timing generator for controlling the operation points of the row driver, the ramp signal generator, and the analog-to-digital conversion circuit; During a read operation of the second pixel, a clamping control signal of a first level and a clamping control signal of a second level lower than the first level are sequentially applied to the charge transfer transistor of the first pixel; the clamping control signal drops from the first level to the second level before a signal transmission section in which a charge transfer signal of an active level is applied to the charge transfer transistor of the second pixel.

14. 14. The image sensor of claim 13, wherein the charge transfer transistor of the first pixel is connected to gate terminals of the photo-sensing element and the driving transistor of the first pixel, and the clamping control signal is applied to the gate terminal of the charge transfer transistor of the first pixel.

15. Each of the first pixel and the second pixel is the light-sensing element generating a photocharge corresponding to a received optical signal; a reset transistor that resets the floating diffusion node; the charge transfer transistor for transferring the photo-induced charge to the floating diffusion node; a driving transistor for outputting a voltage corresponding to the voltage of the floating diffusion node; 14. The image sensor according to claim 13, further comprising: a selection transistor for outputting an output of the driving transistor to the column line in response to a selection signal.

16. The row driver includes:

14. The image sensor of claim 13, further comprising: a first voltage having the first level, a second voltage having the second level, a third voltage having a third level, and a fourth voltage having a fourth level from a voltage generator; generating the clamping control signal based on the first voltage and the second voltage; and generating the charge transfer signal based on the third voltage and the fourth voltage, wherein the third level is higher than the fourth level, and the first level and the third level are different from each other.

17. 14. The image sensor of claim 13, wherein a minimum value of the pixel voltage is determined based on a difference between the first level and the second level.

18. Each of the first pixel and the second pixel is a plurality of light-sensing elements; and a plurality of charge transfer transistors configured to transfer charges generated by each of the plurality of light-sensing elements to the floating diffusion node; The row driver includes:

16. The image sensor of claim 15, further comprising: providing the clamping control signal to at least one of the plurality of charge transfer transistors of the first pixel.

19. 1. A method of operating an image sensor including a pixel array including first and second pixels arranged in different rows and coupled to a same column line, each of the first and second pixels including a charge transfer transistor configured to transfer charge generated in a photo-sensing element to a floating diffusion node, the method comprising: resetting the pixel array; applying a clamp control signal that falls from a first level to a second level to a charge transfer transistor of the first pixel during a reset counting period in a read period for the second pixel; applying a transfer control signal of an active level to the charge transfer transistor of the second pixel during a signal transmission period after the reset counting period; The method, wherein the read section includes, in this order, the reset counting section for counting a reset signal, the signal transmission section for transferring charges from a photo-sensing element to a floating diffusion node, and a signal counting section for counting an image signal.

Images